1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 21 ********************************************************************************/ 22 /*******************************************************************************/ 23 /*! \file sainit.c 24 * \brief The file implements the functions to initialize the LL layer 25 * 26 */ 27 /******************************************************************************/ 28 #include <sys/cdefs.h> 29 #include <dev/pms/config.h> 30 31 #include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 32 #ifdef SA_ENABLE_TRACE_FUNCTIONS 33 #ifdef siTraceFileID 34 #undef siTraceFileID 35 #endif 36 #define siTraceFileID 'F' 37 #endif 38 39 bit32 gLLDebugLevel = 3; 40 41 #if defined(SALLSDK_DEBUG) 42 bit32 gLLDebugLevelSet = 0; // block reinitialize from updating 43 bit32 gLLLogFuncDebugLevel = 0; 44 bit32 gLLSoftResetCounter = 0; 45 #endif 46 47 bit32 gPollForMissingInt; 48 49 #ifdef FW_EVT_LOG_TST 50 void *eventLogAddress = NULL; 51 #endif 52 53 extern bit32 gWait_3; 54 extern bit32 gWait_2; 55 bit32 gFPGA_TEST = 0; // If set unblock fpga functions 56 57 /******************************************************************************/ 58 /*! \brief Get the memory and lock requirement from LL layer 59 * 60 * Get the memory and lock requirement from LL layer 61 * 62 * \param agRoot Handles for this instance of SAS/SATA hardware 63 * \param swConfig Pointer to the software configuration 64 * \param memoryRequirement Point to the data structure that holds the different 65 * chunks of memory that are required 66 * \param usecsPerTick micro-seconds per tick for the LL layer 67 * \param maxNumLocks maximum number of locks for the LL layer 68 * 69 * \return -void- 70 * 71 */ 72 /*******************************************************************************/ 73 GLOBAL void saGetRequirements( 74 agsaRoot_t *agRoot, 75 agsaSwConfig_t *swConfig, 76 agsaMemoryRequirement_t *memoryRequirement, 77 bit32 *usecsPerTick, 78 bit32 *maxNumLocks 79 ) 80 { 81 bit32 memoryReqCount = 0; 82 bit32 i; 83 static mpiConfig_t mpiConfig; 84 static mpiMemReq_t mpiMemoryRequirement; 85 86 87 /* sanity check */ 88 SA_ASSERT((agNULL != swConfig), ""); 89 SA_ASSERT((agNULL != memoryRequirement), ""); 90 SA_ASSERT((agNULL != usecsPerTick), ""); 91 SA_ASSERT((agNULL != maxNumLocks), ""); 92 93 si_memset(&mpiMemoryRequirement, 0, sizeof(mpiMemReq_t)); 94 si_memset(&mpiConfig, 0, sizeof(mpiConfig_t)); 95 96 SA_DBG1(("saGetRequirements:agRoot %p swConfig %p memoryRequirement %p usecsPerTick %p maxNumLocks %p\n",agRoot, swConfig,memoryRequirement,usecsPerTick,maxNumLocks)); 97 SA_DBG1(("saGetRequirements: usecsPerTick 0x%x (%d)\n",*usecsPerTick,*usecsPerTick)); 98 99 /* Get Resource Requirements for SPC MPI */ 100 /* Set the default/specified requirements swConfig from TD layer */ 101 siConfiguration(agRoot, &mpiConfig, agNULL, swConfig); 102 mpiRequirementsGet(&mpiConfig, &mpiMemoryRequirement); 103 104 /* memory requirement for saRoot, CACHE memory */ 105 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength = sizeof(agsaLLRoot_t); 106 memoryRequirement->agMemory[LLROOT_MEM_INDEX].numElements = 1; 107 memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength = sizeof(agsaLLRoot_t); 108 memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment = sizeof(void *); 109 memoryRequirement->agMemory[LLROOT_MEM_INDEX].type = AGSA_CACHED_MEM; 110 memoryReqCount ++; 111 112 SA_DBG1(("saGetRequirements: agMemory[LLROOT_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 113 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength, 114 memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength, 115 memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment, 116 memoryRequirement->agMemory[LLROOT_MEM_INDEX].type )); 117 118 /* memory requirement for Device Links, CACHE memory */ 119 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength = sizeof(agsaDeviceDesc_t); 120 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].numElements = swConfig->numDevHandles; 121 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength = sizeof(agsaDeviceDesc_t) 122 * swConfig->numDevHandles; 123 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment = sizeof(void *); 124 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type = AGSA_CACHED_MEM; 125 memoryReqCount ++; 126 SA_DBG1(("saGetRequirements: agMemory[DEVICELINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 127 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength, 128 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength, 129 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment, 130 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type )); 131 132 /* memory requirement for IORequest Links, CACHE memory */ 133 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength = sizeof(agsaIORequestDesc_t); 134 /* 135 Add SA_RESERVED_REQUEST_COUNT to guarantee quality of service 136 */ 137 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements = swConfig->maxActiveIOs + SA_RESERVED_REQUEST_COUNT; 138 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength = sizeof(agsaIORequestDesc_t) * 139 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements; 140 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment = sizeof(void *); 141 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type = AGSA_CACHED_MEM; 142 memoryReqCount ++; 143 144 SA_DBG1(("saGetRequirements: agMemory[IOREQLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 145 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength, 146 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength, 147 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment, 148 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type )); 149 150 /* memory requirement for Timer Links, CACHE memory */ 151 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength = sizeof(agsaTimerDesc_t); 152 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].numElements = NUM_TIMERS; 153 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength = sizeof(agsaTimerDesc_t) * NUM_TIMERS; 154 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment = sizeof(void *); 155 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type = AGSA_CACHED_MEM; 156 memoryReqCount ++; 157 SA_DBG1(("saGetRequirements: agMemory[TIMERLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 158 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength, 159 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength, 160 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment, 161 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type )); 162 163 #ifdef SA_ENABLE_TRACE_FUNCTIONS 164 165 /* memory requirement for LL trace memory */ 166 memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength = 1; 167 memoryRequirement->agMemory[LL_FUNCTION_TRACE].numElements = swConfig->TraceBufferSize; 168 memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength = swConfig->TraceBufferSize; 169 memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment = sizeof(void *); 170 memoryRequirement->agMemory[LL_FUNCTION_TRACE].type = AGSA_CACHED_MEM; 171 memoryReqCount ++; 172 173 SA_DBG1(("saGetRequirements: agMemory[LL_FUNCTION_TRACE] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 174 memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength, 175 memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength, 176 memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment, 177 memoryRequirement->agMemory[LL_FUNCTION_TRACE].type )); 178 179 #endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 180 181 #ifdef FAST_IO_TEST 182 { 183 agsaMem_t *agMemory = memoryRequirement->agMemory; 184 185 /* memory requirement for Super IO CACHE memory */ 186 agMemory[LL_FAST_IO].singleElementLength = sizeof(saFastRequest_t); 187 agMemory[LL_FAST_IO].numElements = LL_FAST_IO_SIZE; 188 agMemory[LL_FAST_IO].totalLength = LL_FAST_IO_SIZE * 189 agMemory[LL_FAST_IO].singleElementLength; 190 agMemory[LL_FAST_IO].alignment = sizeof(void*); 191 agMemory[LL_FAST_IO].type = AGSA_CACHED_MEM; 192 memoryReqCount ++; 193 194 SA_DBG1(("saGetRequirements: agMemory[LL_FAST_IO] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 195 memoryRequirement->agMemory[LL_FAST_IO].singleElementLength, 196 memoryRequirement->agMemory[LL_FAST_IO].totalLength, 197 memoryRequirement->agMemory[LL_FAST_IO].alignment, 198 memoryRequirement->agMemory[LL_FAST_IO].type )); 199 200 } 201 #endif 202 203 #ifdef SA_ENABLE_HDA_FUNCTIONS 204 { 205 agsaMem_t *agMemory = memoryRequirement->agMemory; 206 207 /* memory requirement for HDA FW image */ 208 agMemory[HDA_DMA_BUFFER].singleElementLength = (1024 * 1024); /* must be greater than size of aap1 fw image */ 209 agMemory[HDA_DMA_BUFFER].numElements = 1; 210 agMemory[HDA_DMA_BUFFER].totalLength = agMemory[HDA_DMA_BUFFER].numElements * 211 agMemory[HDA_DMA_BUFFER].singleElementLength; 212 agMemory[HDA_DMA_BUFFER].alignment = 32; 213 agMemory[HDA_DMA_BUFFER].type = AGSA_DMA_MEM; 214 memoryReqCount ++; 215 SA_DBG1(("saGetRequirements: agMemory[HDA_DMA_BUFFER] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 216 memoryRequirement->agMemory[HDA_DMA_BUFFER].singleElementLength, 217 memoryRequirement->agMemory[HDA_DMA_BUFFER].totalLength, 218 memoryRequirement->agMemory[HDA_DMA_BUFFER].alignment, 219 memoryRequirement->agMemory[HDA_DMA_BUFFER].type )); 220 } 221 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 222 223 /* memory requirement for MPI MSGU layer, DMA memory */ 224 for ( i = 0; i < mpiMemoryRequirement.count; i ++ ) 225 { 226 memoryRequirement->agMemory[memoryReqCount].singleElementLength = mpiMemoryRequirement.region[i].elementSize; 227 memoryRequirement->agMemory[memoryReqCount].numElements = mpiMemoryRequirement.region[i].numElements; 228 memoryRequirement->agMemory[memoryReqCount].totalLength = mpiMemoryRequirement.region[i].totalLength; 229 memoryRequirement->agMemory[memoryReqCount].alignment = mpiMemoryRequirement.region[i].alignment; 230 memoryRequirement->agMemory[memoryReqCount].type = mpiMemoryRequirement.region[i].type; 231 SA_DBG1(("saGetRequirements:MPI agMemory[%d] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 232 memoryReqCount, 233 memoryRequirement->agMemory[memoryReqCount].singleElementLength, 234 memoryRequirement->agMemory[memoryReqCount].totalLength, 235 memoryRequirement->agMemory[memoryReqCount].alignment, 236 memoryRequirement->agMemory[memoryReqCount].type )); 237 memoryReqCount ++; 238 } 239 240 241 /* requirement for locks */ 242 if (swConfig->param3 == agNULL) 243 { 244 *maxNumLocks = (LL_IOREQ_IBQ_LOCK + AGSA_MAX_INBOUND_Q ); 245 SA_DBG1(("saGetRequirements: param3 == agNULL maxNumLocks %d\n", *maxNumLocks )); 246 } 247 else 248 { 249 agsaQueueConfig_t *queueConfig; 250 queueConfig = (agsaQueueConfig_t *)swConfig->param3; 251 *maxNumLocks = (LL_IOREQ_IBQ_LOCK_PARM + queueConfig->numInboundQueues ); 252 SA_DBG1(("saGetRequirements: maxNumLocks %d\n", *maxNumLocks )); 253 } 254 255 256 /* setup the time tick */ 257 *usecsPerTick = SA_USECS_PER_TICK; 258 259 SA_ASSERT(memoryReqCount < AGSA_NUM_MEM_CHUNKS, "saGetRequirements: Exceed max number of memory place holder"); 260 261 /* set up memory requirement count */ 262 memoryRequirement->count = memoryReqCount; 263 264 swConfig->legacyInt_X = 1; 265 swConfig->max_MSI_InterruptVectors = 32; 266 swConfig->max_MSIX_InterruptVectors = 64;//16; 267 268 SA_DBG1(("saGetRequirements: swConfig->stallUsec %d\n",swConfig->stallUsec )); 269 270 #ifdef SA_CONFIG_MDFD_REGISTRY 271 SA_DBG1(("saGetRequirements: swConfig->disableMDF %d\n",swConfig->disableMDF)); 272 #endif /*SA_CONFIG_MDFD_REGISTRY*/ 273 /*SA_DBG1(("saGetRequirements: swConfig->enableDIF %d\n",swConfig->enableDIF ));*/ 274 /*SA_DBG1(("saGetRequirements: swConfig->enableEncryption %d\n",swConfig->enableEncryption ));*/ 275 #ifdef SA_ENABLE_HDA_FUNCTIONS 276 swConfig->hostDirectAccessSupport = 1; 277 swConfig->hostDirectAccessMode = 0; 278 #else 279 swConfig->hostDirectAccessSupport = 0; 280 swConfig->hostDirectAccessMode = 0; 281 #endif 282 283 } 284 285 /******************************************************************************/ 286 /*! \brief Initialize the Hardware 287 * 288 * Initialize the Hardware 289 * 290 * \param agRoot Handles for this instance of SAS/SATA hardware 291 * \param memoryAllocated Point to the data structure that holds the different 292 chunks of memory that are required 293 * \param hwConfig Pointer to the hardware configuration 294 * \param swConfig Pointer to the software configuration 295 * \param usecsPerTick micro-seconds per tick for the LL layer 296 * 297 * \return If initialization is successful 298 * - \e AGSA_RC_SUCCESS initialization is successful 299 * - \e AGSA_RC_FAILURE initialization is not successful 300 */ 301 /*******************************************************************************/ 302 GLOBAL bit32 saInitialize( 303 agsaRoot_t *agRoot, 304 agsaMemoryRequirement_t *memoryAllocated, 305 agsaHwConfig_t *hwConfig, 306 agsaSwConfig_t *swConfig, 307 bit32 usecsPerTick 308 ) 309 { 310 agsaLLRoot_t *saRoot; 311 agsaDeviceDesc_t *pDeviceDesc; 312 agsaIORequestDesc_t *pRequestDesc; 313 agsaTimerDesc_t *pTimerDesc; 314 agsaPort_t *pPort; 315 agsaPortMap_t *pPortMap; 316 agsaDeviceMap_t *pDeviceMap; 317 agsaIOMap_t *pIOMap; 318 bit32 maxNumIODevices; 319 bit32 i, j; 320 static mpiMemReq_t mpiMemoryAllocated; 321 bit32 Tried_NO_HDA = agFALSE; 322 bit32 Double_Reset_HDA = agFALSE; 323 bit32 ret = AGSA_RC_SUCCESS; 324 #ifdef FAST_IO_TEST 325 void *fr; /* saFastRequest_t */ 326 bit32 size; 327 bit32 alignment; 328 #endif 329 330 /* sanity check */ 331 SA_ASSERT((agNULL != agRoot), ""); 332 SA_ASSERT((agNULL != memoryAllocated), ""); 333 SA_ASSERT((agNULL != hwConfig), ""); 334 SA_ASSERT((agNULL != swConfig), ""); 335 SA_ASSERT((LLROOT_MEM_INDEX < memoryAllocated->count), ""); 336 SA_ASSERT((DEVICELINK_MEM_INDEX < memoryAllocated->count), ""); 337 SA_ASSERT((IOREQLINK_MEM_INDEX < memoryAllocated->count), ""); 338 SA_ASSERT((TIMERLINK_MEM_INDEX < memoryAllocated->count), ""); 339 340 si_memset(&mpiMemoryAllocated, 0, sizeof(mpiMemReq_t)); 341 342 si_macro_check(agRoot); 343 344 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n", WAIT_INCREMENT )); 345 SA_DBG1(("saInitialize: usecsPerTick %d\n", usecsPerTick )); 346 if(! smIS_SPC(agRoot)) 347 { 348 if(! smIS_SPCV(agRoot)) 349 { 350 SA_DBG1(("saInitialize: ossaHwRegReadConfig32 ID reads as %08X\n", ossaHwRegReadConfig32(agRoot,0 ) )); 351 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCV, VEN_DEV_SPCVE)); 352 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCVP, VEN_DEV_SPCVEP)); 353 SA_DBG1(("saInitialize: expect %08X or %08X\n", VEN_DEV_ADAPVEP, VEN_DEV_ADAPVP)); 354 return AGSA_RC_FAILURE; 355 } 356 } 357 358 if( smIS_SPC(agRoot) && smIS_SPCV(agRoot)) 359 { 360 SA_DBG1(("saInitialize: Macro error !smIS_SPC %d smIS_SPCv %d smIS_SFC %d\n",smIS_SPC(agRoot),smIS_SPCV(agRoot), smIS_SFC(agRoot) )); 361 return AGSA_RC_FAILURE; 362 } 363 364 /* Check the memory allocated */ 365 for ( i = 0; i < memoryAllocated->count; i ++ ) 366 { 367 /* If memory allocation failed */ 368 if (memoryAllocated->agMemory[i].singleElementLength && 369 memoryAllocated->agMemory[i].numElements) 370 { 371 if ( (0 != memoryAllocated->agMemory[i].numElements) 372 && (0 == memoryAllocated->agMemory[i].totalLength) ) 373 { 374 /* return failure */ 375 SA_DBG1(("saInitialize:AGSA_RC_FAILURE Memory[%d] singleElementLength = 0x%x numElements = 0x%x NOT allocated\n", 376 i, 377 memoryAllocated->agMemory[i].singleElementLength, 378 memoryAllocated->agMemory[i].numElements)); 379 ret = AGSA_RC_FAILURE; 380 return ret; 381 } 382 else 383 { 384 SA_DBG1(("saInitialize: Memory[%d] singleElementLength = 0x%x numElements = 0x%x allocated %p\n", 385 i, 386 memoryAllocated->agMemory[i].singleElementLength, 387 memoryAllocated->agMemory[i].numElements, 388 memoryAllocated->agMemory[i].virtPtr)); 389 } 390 } 391 } 392 393 /* Get the saRoot memory address */ 394 saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); 395 SA_ASSERT((agNULL != saRoot), "saRoot"); 396 if(agNULL == saRoot) 397 { 398 SA_DBG1(("saInitialize:AGSA_RC_FAILURE saRoot\n")); 399 return AGSA_RC_FAILURE; 400 } 401 402 agRoot->sdkData = (void *) saRoot; 403 404 SA_DBG1(("saInitialize: saRoot %p\n",saRoot)); 405 406 if ( (memoryAllocated != &saRoot->memoryAllocated) || 407 (hwConfig != &saRoot->hwConfig) || 408 (swConfig != &saRoot->swConfig) ) 409 { 410 agsaMemoryRequirement_t *memA = &saRoot->memoryAllocated; 411 agsaHwConfig_t *hwC = &saRoot->hwConfig; 412 agsaSwConfig_t *swC = &saRoot->swConfig; 413 414 /* Copy data here */ 415 416 *memA = *memoryAllocated; 417 *hwC = *hwConfig; 418 *swC = *swConfig; 419 } 420 421 422 #if defined(SALLSDK_DEBUG) 423 if(gLLDebugLevelSet == 0) 424 { 425 gLLDebugLevelSet = 1; 426 gLLDebugLevel = swConfig->sallDebugLevel & 0xF; 427 SA_DBG1(("saInitialize: gLLDebugLevel %x\n",gLLDebugLevel)); 428 } 429 #endif /* SALLSDK_DEBUG */ 430 431 #ifdef SA_ENABLE_TRACE_FUNCTIONS 432 433 saRoot->TraceBufferLength = memoryAllocated->agMemory[LL_FUNCTION_TRACE].totalLength; 434 saRoot->TraceBuffer = memoryAllocated->agMemory[LL_FUNCTION_TRACE].virtPtr; 435 436 siEnableTracing ( agRoot ); 437 /* 438 */ 439 440 #endif /* SA_ENABLE_TRACE_FUNCTIONS */ 441 442 #ifdef FAST_IO_TEST 443 { 444 agsaMem_t *agMemory = memoryAllocated->agMemory; 445 446 /* memory requirement for Super IO CACHE memory */ 447 size = sizeof(saRoot->freeFastReq) / sizeof(saRoot->freeFastReq[0]); 448 449 SA_ASSERT(size == agMemory[LL_FAST_IO].numElements, ""); 450 SA_ASSERT(agMemory[LL_FAST_IO].virtPtr, ""); 451 SA_ASSERT((agMemory[LL_FAST_IO].singleElementLength == 452 sizeof(saFastRequest_t)) && 453 (agMemory[LL_FAST_IO].numElements == LL_FAST_IO_SIZE) && 454 (agMemory[LL_FAST_IO].totalLength == agMemory[LL_FAST_IO].numElements * 455 agMemory[LL_FAST_IO].singleElementLength), ""); 456 457 for (i = 0, alignment = agMemory[LL_FAST_IO].alignment, 458 fr = agMemory[LL_FAST_IO].virtPtr; 459 i < size; i++, 460 fr = (void*)((bitptr)fr + (bitptr)(((bit32)sizeof(saFastRequest_t) + 461 alignment - 1) & ~(alignment - 1)))) 462 { 463 saRoot->freeFastReq[i] = fr; 464 } 465 saRoot->freeFastIdx = size; 466 } 467 #endif /* FAST_IO_TEST*/ 468 469 smTraceFuncEnter(hpDBG_VERY_LOUD, "m1"); 470 471 SA_DBG1(("saInitialize: swConfig->PortRecoveryResetTimer %x\n",swConfig->PortRecoveryResetTimer )); 472 473 SA_DBG1(("saInitialize: hwDEVICE_ID_VENDID 0x%08x\n", ossaHwRegReadConfig32(agRoot,0))); 474 SA_DBG1(("saInitialize: CFGSTAT CFGCMD 0x%08x\n", ossaHwRegReadConfig32(agRoot,4))); 475 SA_DBG1(("saInitialize: CLSCODE REVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,8))); 476 SA_DBG1(("saInitialize: BIST DT HDRTYPE LATTIM CLSIZE 0x%08x\n", ossaHwRegReadConfig32(agRoot,12))); 477 SA_DBG1(("saInitialize: hwSVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,44))); 478 479 480 #ifdef SA_ENABLE_PCI_TRIGGER 481 482 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER a 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); 483 484 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_INIT_TEST ) 485 { 486 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); 487 saRoot->swConfig.PCI_trigger &= ~PCI_TRIGGER_INIT_TEST; 488 siPCITriger(agRoot); 489 } 490 #endif /* SA_ENABLE_PCI_TRIGGER */ 491 492 493 saRoot->ChipId = (ossaHwRegReadConfig32(agRoot,0) & 0xFFFF0000); 494 495 SA_DBG1(("saInitialize: saRoot->ChipId 0x%08x\n", saRoot->ChipId)); 496 siUpdateBarOffsetTable(agRoot,saRoot->ChipId); 497 498 if(saRoot->ChipId == VEN_DEV_SPC) 499 { 500 if(! smIS_SPC(agRoot)) 501 { 502 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); 503 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m1"); 504 return AGSA_RC_FAILURE; 505 } 506 507 SA_DBG1(("saInitialize: SPC \n" )); 508 } 509 else if(saRoot->ChipId == VEN_DEV_HIL ) 510 { 511 SA_DBG1(("saInitialize: SPC HIL\n" )); 512 if(! smIS_SPC(agRoot)) 513 { 514 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); 515 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m1"); 516 return AGSA_RC_FAILURE; 517 } 518 } 519 else if(saRoot->ChipId == VEN_DEV_SPCV) 520 { 521 SA_DBG1(("saInitialize: SPC V\n" )); 522 if(! smIS_SPCV(agRoot)) 523 { 524 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 525 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m1"); 526 return AGSA_RC_FAILURE; 527 } 528 } 529 else if(saRoot->ChipId == VEN_DEV_SPCVE) 530 { 531 SA_DBG1(("saInitialize: SPC VE\n" )); 532 if(! smIS_SPCV(agRoot)) 533 { 534 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 535 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m1"); 536 return AGSA_RC_FAILURE; 537 } 538 } 539 else if(saRoot->ChipId == VEN_DEV_SPCVP) 540 { 541 SA_DBG1(("saInitialize: SPC VP\n" )); 542 if(! smIS_SPCV(agRoot)) 543 { 544 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 545 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m1"); 546 return AGSA_RC_FAILURE; 547 } 548 } 549 else if(saRoot->ChipId == VEN_DEV_SPCVEP) 550 { 551 SA_DBG1(("saInitialize: SPC VEP\n" )); 552 if(! smIS_SPCV(agRoot)) 553 { 554 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 555 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m1"); 556 return AGSA_RC_FAILURE; 557 } 558 } 559 else if(saRoot->ChipId == VEN_DEV_ADAPVP) 560 { 561 SA_DBG1(("saInitialize: Adaptec 8088\n" )); 562 } 563 else if(saRoot->ChipId == VEN_DEV_ADAPVEP) 564 { 565 SA_DBG1(("saInitialize: Adaptec 8089\n" )); 566 } 567 else if(saRoot->ChipId == VEN_DEV_SPC12V) 568 { 569 SA_DBG1(("saInitialize: SPC 12V\n" )); 570 if(! smIS_SPCV(agRoot)) 571 { 572 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 573 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m1"); 574 return AGSA_RC_FAILURE; 575 } 576 } 577 else if(saRoot->ChipId == VEN_DEV_SPC12VE) 578 { 579 SA_DBG1(("saInitialize: SPC 12VE\n" )); 580 if(! smIS_SPCV(agRoot)) 581 { 582 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 583 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m1"); 584 return AGSA_RC_FAILURE; 585 } 586 } 587 else if(saRoot->ChipId == VEN_DEV_SPC12VP) 588 { 589 SA_DBG1(("saInitialize: SPC 12VP\n" )); 590 if(! smIS_SPCV(agRoot)) 591 { 592 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 593 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m1"); 594 return AGSA_RC_FAILURE; 595 } 596 } 597 else if(saRoot->ChipId == VEN_DEV_SPC12VEP) 598 { 599 SA_DBG1(("saInitialize: SPC 12VEP\n" )); 600 if(! smIS_SPCV(agRoot)) 601 { 602 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 603 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m1"); 604 return AGSA_RC_FAILURE; 605 } 606 } 607 else if(saRoot->ChipId == VEN_DEV_SPC12ADP) 608 { 609 SA_DBG1(("saInitialize: SPC 12ADP\n" )); 610 if(! smIS_SPCV(agRoot)) 611 { 612 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 613 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m1"); 614 return AGSA_RC_FAILURE; 615 } 616 } 617 else if(saRoot->ChipId == VEN_DEV_SPC12ADPE) 618 { 619 SA_DBG1(("saInitialize: SPC 12ADPE\n" )); 620 if(! smIS_SPCV(agRoot)) 621 { 622 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 623 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m1"); 624 return AGSA_RC_FAILURE; 625 } 626 } 627 else if(saRoot->ChipId == VEN_DEV_SPC12ADPP) 628 { 629 SA_DBG1(("saInitialize: SPC 12ADPP\n" )); 630 if(! smIS_SPCV(agRoot)) 631 { 632 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 633 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m1"); 634 return AGSA_RC_FAILURE; 635 } 636 } 637 else if(saRoot->ChipId == VEN_DEV_SPC12ADPEP) 638 { 639 SA_DBG1(("saInitialize: SPC 12ADPEP\n" )); 640 if(! smIS_SPCV(agRoot)) 641 { 642 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 643 smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m1"); 644 return AGSA_RC_FAILURE; 645 } 646 } 647 else if(saRoot->ChipId == VEN_DEV_SPC12SATA) 648 { 649 SA_DBG1(("saInitialize: SPC12SATA\n" )); 650 if(! smIS_SPCV(agRoot)) 651 { 652 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 653 smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m1"); 654 return AGSA_RC_FAILURE; 655 } 656 } 657 else if(saRoot->ChipId == VEN_DEV_9015) 658 { 659 SA_DBG1(("saInitialize: SPC 12V FPGA\n" )); 660 if(! smIS_SPCV(agRoot)) 661 { 662 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 663 smTraceFuncExit(hpDBG_VERY_LOUD, 'p', "m1"); 664 return AGSA_RC_FAILURE; 665 } 666 } 667 else if(saRoot->ChipId == VEN_DEV_9060) 668 { 669 SA_DBG1(("saInitialize: SPC 12V FPGA B\n" )); 670 if(! smIS_SPCV(agRoot)) 671 { 672 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 673 smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); 674 return AGSA_RC_FAILURE; 675 } 676 } 677 else if(saRoot->ChipId == VEN_DEV_SFC) 678 { 679 SA_DBG1(("saInitialize: SFC \n" )); 680 } 681 else 682 { 683 SA_DBG1(("saInitialize saRoot->ChipId %8X expect %8X or %8X\n", saRoot->ChipId,VEN_DEV_SPC, VEN_DEV_SPCV)); 684 SA_ASSERT(0, "ChipId"); 685 smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); 686 return AGSA_RC_FAILURE; 687 } 688 689 if( smIS_SPC(agRoot)) 690 { 691 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgSpcREV_A(agRoot),smIsCfgSpcREV_B(agRoot),smIsCfgSpcREV_C(agRoot))); 692 } 693 else 694 { 695 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgVREV_A(agRoot),smIsCfgVREV_B(agRoot),smIsCfgVREV_C(agRoot))); 696 } 697 698 if( smIS_SPC(agRoot)) 699 { 700 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,128), 701 ((ossaHwRegReadConfig32(agRoot,128) & 0x000F0000) >> 16), 702 ((ossaHwRegReadConfig32(agRoot,128) & 0x0FF00000) >> 20) )); 703 } 704 else 705 { 706 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,208), 707 ((ossaHwRegReadConfig32(agRoot,208) & 0x000F0000) >> 16), 708 ((ossaHwRegReadConfig32(agRoot,208) & 0x0FF00000) >> 20) )); 709 } 710 711 SA_DBG1(("saInitialize: V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ))); 712 713 /* 714 SA_DBG1(("saInitialize:TOP_BOOT_STRAP STRAP_BIT %X\n", ossaHwRegReadExt(agRoot, PCIBAR1, 0) )); 715 716 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_DEVICE_ID), SPC_TOP_DEVICE_ID)); 717 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", siHalRegReadExt( agRoot, GEN_SPC_REG_TOP_DEVICE_ID,SPC_REG_TOP_DEVICE_ID ) , SPC_TOP_DEVICE_ID)); 718 719 SA_DBG1(("SPC_REG_TOP_BOOT_STRAP %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_BOOT_STRAP), SPC_TOP_BOOT_STRAP)); 720 721 SA_DBG1(("swConfig->numSASDevHandles =%d\n", swConfig->numDevHandles)); 722 */ 723 smTrace(hpDBG_VERY_LOUD,"29",swConfig->numDevHandles); 724 /* TP:29 swConfig->numDevHandles */ 725 726 /* Setup Device link */ 727 /* Save the information of allocated device Link memory */ 728 saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; 729 if(agNULL == saRoot->deviceLinkMem.virtPtr) 730 { 731 SA_ASSERT(0, "deviceLinkMem"); 732 smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); 733 return AGSA_RC_FAILURE; 734 } 735 736 si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); 737 SA_DBG2(("saInitialize: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 738 DEVICELINK_MEM_INDEX, 739 saRoot->deviceLinkMem.virtPtr, 740 saRoot->deviceLinkMem.phyAddrLower, 741 saRoot->deviceLinkMem.numElements, 742 saRoot->deviceLinkMem.totalLength, 743 saRoot->deviceLinkMem.type)); 744 745 maxNumIODevices = swConfig->numDevHandles; 746 SA_DBG2(("saInitialize: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", 747 maxNumIODevices, 748 swConfig->numDevHandles)); 749 750 #ifdef SA_ENABLE_PCI_TRIGGER 751 SA_DBG1(("saInitialize: swConfig->PCI_trigger= 0x%x\n", swConfig->PCI_trigger)); 752 #endif /* SA_ENABLE_PCI_TRIGGER */ 753 754 /* Setup free IO Devices link list */ 755 saLlistInitialize(&(saRoot->freeDevicesList)); 756 for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) 757 { 758 /* get the pointer to the device descriptor */ 759 pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); 760 /* Initialize device descriptor */ 761 saLlinkInitialize(&(pDeviceDesc->linkNode)); 762 763 pDeviceDesc->initiatorDevHandle.osData = agNULL; 764 pDeviceDesc->initiatorDevHandle.sdkData = agNULL; 765 pDeviceDesc->targetDevHandle.osData = agNULL; 766 pDeviceDesc->targetDevHandle.sdkData = agNULL; 767 pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; 768 pDeviceDesc->pPort = agNULL; 769 pDeviceDesc->DeviceMapIndex = 0; 770 771 saLlistInitialize(&(pDeviceDesc->pendingIORequests)); 772 773 /* Add the device descriptor to the free IO device link list */ 774 saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); 775 } 776 777 /* Setup IO Request link */ 778 /* Save the information of allocated IO Request Link memory */ 779 saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; 780 si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); 781 782 SA_DBG2(("saInitialize: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 783 IOREQLINK_MEM_INDEX, 784 saRoot->IORequestMem.virtPtr, 785 saRoot->IORequestMem.phyAddrLower, 786 saRoot->IORequestMem.numElements, 787 saRoot->IORequestMem.totalLength, 788 saRoot->IORequestMem.type)); 789 790 /* Setup free IO Request link list */ 791 saLlistIOInitialize(&(saRoot->freeIORequests)); 792 saLlistIOInitialize(&(saRoot->freeReservedRequests)); 793 for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) 794 { 795 /* get the pointer to the request descriptor */ 796 pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); 797 /* Initialize request descriptor */ 798 saLlinkInitialize(&(pRequestDesc->linkNode)); 799 800 pRequestDesc->valid = agFALSE; 801 pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; 802 pRequestDesc->pIORequestContext = agNULL; 803 pRequestDesc->HTag = i; 804 pRequestDesc->pDevice = agNULL; 805 pRequestDesc->pPort = agNULL; 806 807 /* Add the request descriptor to the free Reserved Request link list */ 808 /* SMP request must get service so reserve one request when first SMP completes */ 809 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 810 { 811 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); 812 } 813 else 814 { 815 /* Add the request descriptor to the free IO Request link list */ 816 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); 817 } 818 819 } 820 821 /* Setup timer link */ 822 /* Save the information of allocated timer Link memory */ 823 saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; 824 si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); 825 SA_DBG2(("saInitialize: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 826 TIMERLINK_MEM_INDEX, 827 saRoot->timerLinkMem.virtPtr, 828 saRoot->timerLinkMem.phyAddrLower, 829 saRoot->timerLinkMem.numElements, 830 saRoot->timerLinkMem.totalLength, 831 saRoot->timerLinkMem.type )); 832 833 /* Setup free timer link list */ 834 saLlistInitialize(&(saRoot->freeTimers)); 835 for ( i = 0; i < NUM_TIMERS; i ++ ) 836 { 837 /* get the pointer to the timer descriptor */ 838 pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); 839 /* Initialize timer descriptor */ 840 saLlinkInitialize(&(pTimerDesc->linkNode)); 841 842 pTimerDesc->valid = agFALSE; 843 pTimerDesc->timeoutTick = 0; 844 pTimerDesc->pfnTimeout = agNULL; 845 pTimerDesc->Event = 0; 846 pTimerDesc->pParm = agNULL; 847 848 /* Add the timer descriptor to the free timer link list */ 849 saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); 850 } 851 /* Setup valid timer link list */ 852 saLlistInitialize(&(saRoot->validTimers)); 853 854 /* Setup Phys */ 855 /* Setup PhyCount */ 856 saRoot->phyCount = (bit8) hwConfig->phyCount; 857 /* Init Phy data structure */ 858 for ( i = 0; i < saRoot->phyCount; i ++ ) 859 { 860 saRoot->phys[i].pPort = agNULL; 861 saRoot->phys[i].phyId = (bit8) i; 862 863 /* setup phy status is PHY_STOPPED */ 864 PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); 865 } 866 867 /* Setup Ports */ 868 /* Setup PortCount */ 869 saRoot->portCount = saRoot->phyCount; 870 /* Setup free port link list */ 871 saLlistInitialize(&(saRoot->freePorts)); 872 for ( i = 0; i < saRoot->portCount; i ++ ) 873 { 874 /* get the pointer to the port */ 875 pPort = &(saRoot->ports[i]); 876 /* Initialize port */ 877 saLlinkInitialize(&(pPort->linkNode)); 878 879 pPort->portContext.osData = agNULL; 880 pPort->portContext.sdkData = pPort; 881 pPort->portId = 0; 882 pPort->portIdx = (bit8) i; 883 pPort->status = PORT_NORMAL; 884 885 for ( j = 0; j < saRoot->phyCount; j ++ ) 886 { 887 pPort->phyMap[j] = agFALSE; 888 } 889 890 saLlistInitialize(&(pPort->listSASATADevices)); 891 892 /* Add the port to the free port link list */ 893 saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); 894 } 895 /* Setup valid port link list */ 896 saLlistInitialize(&(saRoot->validPorts)); 897 898 /* Init sysIntsActive - default is interrupt enable */ 899 saRoot->sysIntsActive = agFALSE; 900 901 /* setup timer tick granunarity */ 902 saRoot->usecsPerTick = usecsPerTick; 903 904 /* setup smallest timer increment for stall */ 905 saRoot->minStallusecs = swConfig->stallUsec; 906 907 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n" ,WAIT_INCREMENT )); 908 if (0 == WAIT_INCREMENT) 909 { 910 saRoot->minStallusecs = WAIT_INCREMENT_DEFAULT; 911 } 912 913 /* initialize LL timer tick */ 914 saRoot->timeTick = 0; 915 916 /* initialize device (de)registration callback fns */ 917 saRoot->DeviceRegistrationCB = agNULL; 918 saRoot->DeviceDeregistrationCB = agNULL; 919 920 /* Initialize the PortMap for port context */ 921 for ( i = 0; i < saRoot->portCount; i ++ ) 922 { 923 pPortMap = &(saRoot->PortMap[i]); 924 925 pPortMap->PortContext = agNULL; 926 pPortMap->PortID = PORT_MARK_OFF; 927 pPortMap->PortStatus = PORT_NORMAL; 928 saRoot->autoDeregDeviceflag[i] = 0; 929 } 930 931 /* Initialize the DeviceMap for device handle */ 932 for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) 933 { 934 pDeviceMap = &(saRoot->DeviceMap[i]); 935 936 pDeviceMap->DeviceHandle = agNULL; 937 pDeviceMap->DeviceIdFromFW = i; 938 } 939 940 /* Initialize the IOMap for IOrequest */ 941 for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) 942 { 943 pIOMap = &(saRoot->IOMap[i]); 944 945 pIOMap->IORequest = agNULL; 946 pIOMap->Tag = MARK_OFF; 947 } 948 949 /* setup mpi configuration */ 950 if (!swConfig->param3) 951 { 952 /* default configuration */ 953 siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); 954 } 955 else 956 { 957 /* get from TD layer and save it */ 958 agsaQueueConfig_t *dCFG = &saRoot->QueueConfig; 959 agsaQueueConfig_t *sCFG = (agsaQueueConfig_t *)swConfig->param3; 960 961 if (dCFG != sCFG) 962 { 963 *dCFG = *sCFG; 964 965 if ((hwConfig->hwInterruptCoalescingTimer) || (hwConfig->hwInterruptCoalescingControl)) 966 { 967 for ( i = 0; i < sCFG->numOutboundQueues; i ++ ) 968 { 969 /* disable FW assisted coalescing */ 970 sCFG->outboundQueues[i].interruptDelay = 0; 971 sCFG->outboundQueues[i].interruptCount = 0; 972 } 973 974 if(smIS_SPC(agRoot)) 975 { 976 if (hwConfig->hwInterruptCoalescingTimer == 0) 977 { 978 hwConfig->hwInterruptCoalescingTimer = 1; 979 SA_DBG1(("saInitialize:InterruptCoalescingTimer should not be zero. Force to 1\n")); 980 } 981 } 982 } 983 ret = siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); 984 if (AGSA_RC_FAILURE == ret) 985 { 986 SA_DBG1(("saInitialize failure queue number=%d\n", saRoot->QueueConfig.numInboundQueues)); 987 agRoot->sdkData = agNULL; 988 smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); 989 return ret; 990 } 991 } 992 } 993 994 995 saRoot->swConfig.param3 = &saRoot->QueueConfig; 996 997 mpiMemoryAllocated.count = memoryAllocated->count - MPI_MEM_INDEX; 998 for ( i = 0; i < mpiMemoryAllocated.count; i ++ ) 999 { 1000 mpiMemoryAllocated.region[i].virtPtr = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr; 1001 mpiMemoryAllocated.region[i].appHandle = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].osHandle; 1002 mpiMemoryAllocated.region[i].physAddrUpper = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrUpper; 1003 mpiMemoryAllocated.region[i].physAddrLower = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower; 1004 mpiMemoryAllocated.region[i].totalLength = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength; 1005 mpiMemoryAllocated.region[i].numElements = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements; 1006 mpiMemoryAllocated.region[i].elementSize = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].singleElementLength; 1007 mpiMemoryAllocated.region[i].alignment = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].alignment; 1008 mpiMemoryAllocated.region[i].type = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type; 1009 SA_DBG2(("saInitialize: memoryAllocated->agMemory[%d] VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 1010 (MPI_IBQ_OBQ_INDEX + i), 1011 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr, 1012 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower, 1013 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements, 1014 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength, 1015 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type)); 1016 1017 /* set to zeros */ 1018 SA_DBG1(("saInitialize: Zero memory region %d virt %p allocated %d\n", 1019 i,mpiMemoryAllocated.region[i].virtPtr, mpiMemoryAllocated.region[i].totalLength)); 1020 si_memset(mpiMemoryAllocated.region[i].virtPtr , 0,mpiMemoryAllocated.region[i].totalLength); 1021 1022 } 1023 1024 if ((!swConfig->max_MSI_InterruptVectors) && 1025 (!swConfig->max_MSIX_InterruptVectors) && 1026 (!swConfig->legacyInt_X)) 1027 { 1028 /* polling mode */ 1029 SA_DBG1(("saInitialize: configured as polling mode\n")); 1030 } 1031 else 1032 { 1033 1034 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %d\n",swConfig->max_MSI_InterruptVectors)); 1035 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %d\n",swConfig->max_MSIX_InterruptVectors)); 1036 1037 if ((swConfig->legacyInt_X > 1) || (swConfig->max_MSI_InterruptVectors > 32) || 1038 (swConfig->max_MSIX_InterruptVectors > 64)) 1039 { 1040 /* error */ 1041 agRoot->sdkData = agNULL; 1042 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors A\n")); 1043 smTraceFuncExit(hpDBG_VERY_LOUD, 's', "m1"); 1044 return AGSA_RC_FAILURE; 1045 } 1046 if ((swConfig->legacyInt_X) && (swConfig->max_MSI_InterruptVectors)) 1047 { 1048 /* error */ 1049 agRoot->sdkData = agNULL; 1050 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors B\n")); 1051 smTraceFuncExit(hpDBG_VERY_LOUD, 't', "m1"); 1052 return AGSA_RC_FAILURE; 1053 } 1054 else if ((swConfig->legacyInt_X) && (swConfig->max_MSIX_InterruptVectors)) 1055 { 1056 /* error */ 1057 agRoot->sdkData = agNULL; 1058 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors C\n")); 1059 smTraceFuncExit(hpDBG_VERY_LOUD, 'u', "m1"); 1060 return AGSA_RC_FAILURE; 1061 } 1062 else if ((swConfig->max_MSI_InterruptVectors) && (swConfig->max_MSIX_InterruptVectors)) 1063 { 1064 /* error */ 1065 agRoot->sdkData = agNULL; 1066 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors D\n")); 1067 smTraceFuncExit(hpDBG_VERY_LOUD, 'v', "m1"); 1068 return AGSA_RC_FAILURE; 1069 } 1070 } 1071 1072 /* This section sets common interrupt for Legacy(IRQ) and MSI and MSIX types */ 1073 if(smIS_SPC(agRoot)) 1074 { 1075 SA_DBG1(("saInitialize: SPC interrupts\n" )); 1076 1077 if (swConfig->legacyInt_X) 1078 { 1079 saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ 1080 saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ 1081 saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ 1082 } 1083 else if (swConfig->max_MSIX_InterruptVectors) 1084 { 1085 saRoot->OurInterrupt = siOurMSIXInterrupt; 1086 saRoot->DisableInterrupts = siDisableMSIXInterrupts; 1087 saRoot->ReEnableInterrupts = siReenableMSIXInterrupts; 1088 } 1089 else if (swConfig->max_MSI_InterruptVectors) 1090 { 1091 saRoot->OurInterrupt = siOurMSIInterrupt; 1092 saRoot->DisableInterrupts = siDisableMSIInterrupts; 1093 saRoot->ReEnableInterrupts = siReenableMSIInterrupts; 1094 } 1095 else 1096 { 1097 /* polling mode */ 1098 saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ 1099 saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ 1100 saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ 1101 } 1102 } 1103 else 1104 { 1105 SA_DBG1(("saInitialize: SPC V interrupts\n" )); 1106 if (swConfig->legacyInt_X ) 1107 { 1108 SA_DBG1(("saInitialize: SPC V legacyInt_X\n" )); 1109 saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ 1110 saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ 1111 saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ 1112 } 1113 else if (swConfig->max_MSIX_InterruptVectors) 1114 { 1115 SA_DBG1(("saInitialize: SPC V max_MSIX_InterruptVectors %X\n", swConfig->max_MSIX_InterruptVectors)); 1116 saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ 1117 saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; 1118 saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; 1119 } 1120 else if (swConfig->max_MSI_InterruptVectors) 1121 { 1122 SA_DBG1(("saInitialize: SPC V max_MSI_InterruptVectors\n" )); 1123 saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ 1124 saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; 1125 saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; 1126 } 1127 else 1128 { 1129 /* polling mode */ 1130 SA_DBG1(("saInitialize: SPC V polling mode\n" )); 1131 saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ 1132 saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ 1133 saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ 1134 } 1135 SA_DBG1(("saInitialize: SPC V\n" )); 1136 } 1137 1138 saRoot->Use64bit = (saRoot->QueueConfig.numOutboundQueues > 32 ) ? 1 : 0; 1139 if( smIS64bInt(agRoot)) 1140 { 1141 SA_DBG1(("saInitialize: Use 64 bits for interrupts %d %d\n" ,saRoot->Use64bit, saRoot->QueueConfig.numOutboundQueues )); 1142 } 1143 else 1144 { 1145 SA_DBG1(("saInitialize: Use 32 bits for interrupts %d %d\n",saRoot->Use64bit , saRoot->QueueConfig.numOutboundQueues )); 1146 } 1147 1148 #ifdef SA_LL_IBQ_PROTECT 1149 SA_DBG1(("saInitialize: Inbound locking defined since LL_IOREQ_IBQ0_LOCK %d\n",LL_IOREQ_IBQ0_LOCK)); 1150 #endif /* SA_LL_IBQ_PROTECT */ 1151 1152 /* Disable interrupt */ 1153 saRoot->DisableInterrupts(agRoot, 0); 1154 SA_DBG1(("saInitialize: DisableInterrupts sysIntsActive %X\n" ,saRoot->sysIntsActive)); 1155 1156 #ifdef SA_FW_TEST_BUNCH_STARTS 1157 saRoot->BunchStarts_Enable = FALSE; 1158 saRoot->BunchStarts_Threshold = 5; 1159 saRoot->BunchStarts_Pending = 0; 1160 saRoot->BunchStarts_TimeoutTicks = 10; // N x 100 ms 1161 #endif /* SA_FW_TEST_BUNCH_STARTS */ 1162 1163 /* clear the interrupt vector bitmap */ 1164 for ( i = 0; i < MAX_NUM_VECTOR; i ++ ) 1165 { 1166 saRoot->interruptVecIndexBitMap[i] = 0; 1167 saRoot->interruptVecIndexBitMap1[i] = 0; 1168 } 1169 1170 #if defined(SALLSDK_DEBUG) 1171 smTrace(hpDBG_VERY_LOUD,"2Y",0); 1172 /* TP:2Y SCRATCH_PAD */ 1173 1174 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); 1175 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 1176 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); 1177 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 1178 #endif /* SALLSDK_DEBUG */ 1179 1180 if(smIS_SPCV(agRoot)) 1181 { 1182 bit32 ScratchPad1 =0; 1183 bit32 ScratchPad3 =0; 1184 1185 ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); 1186 ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); 1187 if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) 1188 { 1189 if(((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR ) || 1190 ((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR ) ) 1191 { 1192 SA_DBG1(("saInitialize:Warning Encryption Issue SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 1193 } 1194 } 1195 } 1196 1197 if( smIS_SPC(agRoot)) 1198 { 1199 #ifdef SA_ENABLE_HDA_FUNCTIONS 1200 TryWithHDA_ON: 1201 Double_Reset_HDA = TRUE; 1202 1203 if (swConfig->hostDirectAccessSupport) 1204 { 1205 if (AGSA_RC_FAILURE == siHDAMode(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) 1206 { 1207 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode\n")); 1208 agRoot->sdkData = agNULL; 1209 smTraceFuncExit(hpDBG_VERY_LOUD, 'w', "m1"); 1210 return AGSA_RC_FAILURE; 1211 } 1212 else 1213 { 1214 SA_DBG1(("saInitialize:1 Going to HDA mode HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1215 if(Double_Reset_HDA == agFALSE) 1216 { 1217 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1218 SA_DBG1(("saInitialize: Double_Reset_HDA HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1219 Double_Reset_HDA = TRUE; 1220 goto TryWithHDA_ON; 1221 } 1222 } 1223 } 1224 else 1225 { 1226 /* check FW is running */ 1227 if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS)) 1228 { 1229 /* HDA mode */ 1230 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); 1231 if(Tried_NO_HDA != agTRUE ) 1232 { 1233 1234 Tried_NO_HDA = TRUE; 1235 swConfig->hostDirectAccessSupport = 1; 1236 swConfig->hostDirectAccessMode = 1; 1237 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1238 SA_DBG1(("saInitialize: 2 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1239 goto TryWithHDA_ON; 1240 } 1241 else 1242 { 1243 SA_DBG1(("saInitialize: could not start HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1244 smTraceFuncExit(hpDBG_VERY_LOUD, 'x', "m1"); 1245 1246 return AGSA_RC_FAILURE; 1247 } 1248 smTraceFuncExit(hpDBG_VERY_LOUD, 'y', "m1"); 1249 return AGSA_RC_FAILURE; 1250 } 1251 } 1252 #else /* SA_ENABLE_HDA_FUNCTIONS */ 1253 /* check FW is running */ 1254 if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS) ) 1255 { 1256 /* HDA mode */ 1257 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); 1258 smTraceFuncExit(hpDBG_VERY_LOUD, 'z', "m1"); 1259 return AGSA_RC_FAILURE; 1260 } 1261 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 1262 } 1263 else 1264 { 1265 SA_DBG1(("saInitialize: SPCv swConfig->hostDirectAccessMode %d swConfig->hostDirectAccessSupport %d\n",swConfig->hostDirectAccessMode,swConfig->hostDirectAccessSupport)); 1266 if (swConfig->hostDirectAccessSupport) 1267 { 1268 bit32 hda_status; 1269 bit32 soft_reset_status = AGSA_RC_SUCCESS; 1270 1271 SA_DBG1(("saInitialize: SPCv load HDA\n")); 1272 1273 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1274 1275 SA_DBG1(("saInitialize: hda_status 0x%x\n",hda_status)); 1276 1277 siScratchDump(agRoot); 1278 1279 if( swConfig->hostDirectAccessMode == 0) 1280 { 1281 soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1282 if(soft_reset_status != AGSA_RC_SUCCESS) 1283 { 1284 agRoot->sdkData = agNULL; 1285 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status\n")); 1286 1287 smTraceFuncExit(hpDBG_VERY_LOUD, 'A', "m1"); 1288 return AGSA_RC_FAILURE; 1289 } 1290 } 1291 1292 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 1293 { 1294 SA_DBG1(("saInitialize: hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); 1295 soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1296 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1297 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 1298 { 1299 SA_DBG1(("saInitialize: 2 reset hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); 1300 } 1301 } 1302 if(soft_reset_status != AGSA_RC_SUCCESS) 1303 { 1304 agRoot->sdkData = agNULL; 1305 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status A\n")); 1306 smTraceFuncExit(hpDBG_VERY_LOUD, 'B', "m1"); 1307 return AGSA_RC_FAILURE; 1308 } 1309 1310 #ifdef SA_ENABLE_HDA_FUNCTIONS 1311 if (AGSA_RC_FAILURE == siHDAMode_V(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) 1312 { 1313 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode_V\n")); 1314 1315 siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1316 agRoot->sdkData = agNULL; 1317 smTraceFuncExit(hpDBG_VERY_LOUD, 'C', "m1"); 1318 return AGSA_RC_FAILURE; 1319 } 1320 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 1321 1322 } 1323 else 1324 { 1325 SA_DBG1(("saInitialize: SPCv normal\n")); 1326 } 1327 1328 } 1329 1330 /* copy the table to the LL layer */ 1331 si_memcpy(&saRoot->mpiConfig.phyAnalogConfig, &hwConfig->phyAnalogConfig, sizeof(agsaPhyAnalogSetupTable_t)); 1332 1333 #ifdef SALL_API_TEST 1334 /* Initialize the LL IO counter */ 1335 si_memset(&saRoot->LLCounters, 0, sizeof(agsaIOCountInfo_t)); 1336 #endif 1337 1338 si_memset(&saRoot->IoErrorCount, 0, sizeof(agsaIOErrorEventStats_t)); 1339 si_memset(&saRoot->IoEventCount, 0, sizeof(agsaIOErrorEventStats_t)); 1340 if(smIS_SPC(agRoot)) 1341 { 1342 if( smIS_spc8081(agRoot)) 1343 { 1344 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) 1345 { 1346 SA_DBG1(("saInitialize: siBar4Shift FAILED ******************************************\n")); 1347 } 1348 } 1349 siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 1350 } 1351 if(smIS_SPCV(agRoot)) 1352 { 1353 SA_DBG1(("saInitialize: saRoot->ChipId == VEN_DEV_SPCV\n")); 1354 siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 1355 } 1356 1357 /* MPI Initialization */ 1358 ret = mpiInitialize(agRoot, &mpiMemoryAllocated, &saRoot->mpiConfig); 1359 SA_DBG1(("saInitialize: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", saRoot->ControllerInfo.maxPendingIO,saRoot->swConfig.maxActiveIOs )); 1360 1361 #ifdef SA_ENABLE_HDA_FUNCTIONS 1362 if( ret == AGSA_RC_FAILURE && Tried_NO_HDA == agFALSE && smIS_SPC(agRoot)) 1363 { /* FW not flashed */ 1364 Tried_NO_HDA=agTRUE; 1365 swConfig->hostDirectAccessSupport = 1; 1366 swConfig->hostDirectAccessMode = 1; 1367 siSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 1368 SA_DBG1(("saInitialize: 3 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1369 goto TryWithHDA_ON; 1370 } 1371 1372 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 1373 1374 if( ret == AGSA_RC_FAILURE) 1375 { 1376 SA_DBG1(("saInitialize: AGSA_RC_FAILURE mpiInitialize\n")); 1377 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register))); 1378 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register))); 1379 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register))); 1380 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register))); 1381 1382 if(saRoot->swConfig.fatalErrorInterruptEnable) 1383 { 1384 ossaDisableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1385 } 1386 1387 agRoot->sdkData = agNULL; 1388 smTraceFuncExit(hpDBG_VERY_LOUD, 'D', "m1"); 1389 return ret; 1390 } 1391 1392 /* setup hardware interrupt coalescing control and timer registers */ 1393 if(smIS_SPCV(agRoot)) 1394 { 1395 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingTimer\n" )); 1396 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingControl\n" )); 1397 } 1398 else 1399 { 1400 ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICTIMER,hwConfig->hwInterruptCoalescingTimer ); 1401 ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICCONTROL, hwConfig->hwInterruptCoalescingControl); 1402 } 1403 1404 1405 SA_DBG1(("saInitialize: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); 1406 1407 SA_DBG1(("saInitialize: saRoot->swConfig.fatalErrorInterruptVector %X\n",saRoot->swConfig.fatalErrorInterruptVector)); 1408 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %X\n",swConfig->max_MSI_InterruptVectors)); 1409 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); 1410 SA_DBG1(("saInitialize: swConfig->legacyInt_X %X\n",swConfig->legacyInt_X)); 1411 SA_DBG1(("saInitialize: swConfig->hostDirectAccessSupport %X\n",swConfig->hostDirectAccessSupport)); 1412 SA_DBG1(("saInitialize: swConfig->hostDirectAccessMode %X\n",swConfig->hostDirectAccessMode)); 1413 1414 #ifdef SA_CONFIG_MDFD_REGISTRY 1415 SA_DBG1(("saInitialize: swConfig->disableMDF %X\n",swConfig->disableMDF)); 1416 #endif /*SA_CONFIG_MDFD_REGISTRY*/ 1417 /*SA_DBG1(("saInitialize: swConfig->enableDIF %X\n",swConfig->enableDIF));*/ 1418 /*SA_DBG1(("saInitialize: swConfig->enableEncryption %X\n",swConfig->enableEncryption));*/ 1419 1420 1421 /* log message if failure */ 1422 if (AGSA_RC_FAILURE == ret) 1423 { 1424 SA_DBG1(("saInitialize:AGSA_RC_FAILURE mpiInitialize\n")); 1425 /* Assign chip status */ 1426 saRoot->chipStatus = CHIP_FATAL_ERROR; 1427 } 1428 else 1429 { 1430 /* Assign chip status */ 1431 saRoot->chipStatus = CHIP_NORMAL; 1432 #ifdef SA_FW_TIMER_READS_STATUS 1433 siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,0,agNULL ); 1434 #endif /* SA_FW_TIMER_READS_STATUS */ 1435 } 1436 1437 1438 if( ret == AGSA_RC_SUCCESS || ret == AGSA_RC_VERSION_UNTESTED) 1439 { 1440 if(gPollForMissingInt) 1441 { 1442 mpiOCQueue_t *circularQ; 1443 SA_DBG1(("saInitialize: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1444 1445 circularQ = &saRoot->outboundQueue[0]; 1446 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1447 SA_DBG1(("saInitialize: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); 1448 } 1449 } 1450 1451 /* If fatal error interrupt enable we need checking it during the interrupt */ 1452 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptEnable %d\n",saRoot->swConfig.fatalErrorInterruptEnable)); 1453 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptVector %d\n",saRoot->swConfig.fatalErrorInterruptVector)); 1454 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); 1455 1456 if(saRoot->swConfig.fatalErrorInterruptEnable) 1457 { 1458 1459 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", 1460 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1461 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1462 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", 1463 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1464 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1465 1466 ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1467 1468 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", 1469 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1470 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1471 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", 1472 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1473 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1474 } 1475 1476 1477 SA_DBG1(("saInitialize: siDumpActiveIORequests\n")); 1478 siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); 1479 1480 smTraceFuncExit(hpDBG_VERY_LOUD, 'E', "m1"); 1481 /* return */ 1482 return ret; 1483 } 1484 1485 1486 1487 #ifdef SA_FW_TIMER_READS_STATUS 1488 1489 bit32 siReadControllerStatus( 1490 agsaRoot_t *agRoot, 1491 bit32 Event, 1492 void * pParm 1493 ) 1494 { 1495 bit32 to_ret =0; 1496 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1497 mpiReadGSTable(agRoot, &saRoot->mpiGSTable); 1498 1499 if(smIS_SPCV_2_IOP(agRoot)) 1500 { 1501 if(saRoot->Iop1Tcnt_last == saRoot->mpiGSTable.Iop1Tcnt ) 1502 SA_DBG2(("siReadControllerStatus: Iop1 %d STUCK\n", saRoot->mpiGSTable.Iop1Tcnt)); 1503 } 1504 1505 if( saRoot->MsguTcnt_last == saRoot->mpiGSTable.MsguTcnt || saRoot->IopTcnt_last == saRoot->mpiGSTable.IopTcnt ) 1506 { 1507 SA_DBG1(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); 1508 saFatalInterruptHandler(agRoot, saRoot->swConfig.fatalErrorInterruptVector ); 1509 } 1510 SA_DBG2(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); 1511 1512 saRoot->MsguTcnt_last = saRoot->mpiGSTable.MsguTcnt; 1513 saRoot->IopTcnt_last = saRoot->mpiGSTable.IopTcnt; 1514 saRoot->Iop1Tcnt_last = saRoot->mpiGSTable.Iop1Tcnt; 1515 1516 1517 if(gPollForMissingInt) 1518 { 1519 mpiOCQueue_t *circularQ; 1520 SA_DBG4(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1521 1522 circularQ = &saRoot->outboundQueue[0]; 1523 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1524 if(circularQ->producerIdx != circularQ->consumerIdx) 1525 { 1526 SA_DBG1(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1527 SA_DBG1(("siReadControllerStatus: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); 1528 1529 SA_DBG1(("siReadControllerStatus:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1530 SA_DBG1(("siReadControllerStatus:MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 1531 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF ); 1532 1533 } 1534 } 1535 1536 siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,Event,pParm ); 1537 1538 return(to_ret); 1539 } 1540 1541 #endif /* SA_FW_TIMER_READS_STATUS */ 1542 1543 /******************************************************************************/ 1544 /*! \brief Routine to do SPC configuration with default or specified values 1545 * 1546 * Set up configuration table in LL Layer 1547 * 1548 * \param agRoot handles for this instance of SAS/SATA hardware 1549 * \param mpiConfig MPI Configuration 1550 * \param swConfig Pointer to the software configuration 1551 * 1552 * \return -void- 1553 */ 1554 /*******************************************************************************/ 1555 GLOBAL bit32 siConfiguration( 1556 agsaRoot_t *agRoot, 1557 mpiConfig_t *mpiConfig, 1558 agsaHwConfig_t *hwConfig, 1559 agsaSwConfig_t *swConfig 1560 ) 1561 { 1562 agsaQueueConfig_t *queueConfig; 1563 bit32 intOption, enable64 = 0; 1564 bit8 i; 1565 1566 1567 /* sanity check */ 1568 SA_ASSERT( (agNULL != agRoot), ""); 1569 1570 smTraceFuncEnter(hpDBG_VERY_LOUD,"m2"); 1571 1572 si_memset(mpiConfig, 0, sizeof(mpiConfig_t)); 1573 SA_DBG1(("siConfiguration: si_memset mpiConfig\n")); 1574 1575 #if defined(SALLSDK_DEBUG) 1576 sidump_swConfig(swConfig); 1577 #endif 1578 mpiConfig->mainConfig.custset = swConfig->FWConfig; 1579 1580 SA_DBG1(("siConfiguration:custset %8X %8X\n",mpiConfig->mainConfig.custset,swConfig->FWConfig)); 1581 1582 if (swConfig->param3 == agNULL) 1583 { 1584 SA_DBG1(("siConfiguration: swConfig->param3 == agNULL\n")); 1585 /* initialize the mpiConfig */ 1586 /* We configure the Host main part of configuration table */ 1587 mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = 0; 1588 mpiConfig->mainConfig.outboundHWEventPID0_3 = 0; 1589 mpiConfig->mainConfig.outboundHWEventPID4_7 = 0; 1590 mpiConfig->mainConfig.outboundNCQEventPID0_3 = 0; 1591 mpiConfig->mainConfig.outboundNCQEventPID4_7 = 0; 1592 mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; 1593 mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; 1594 mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; 1595 mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; 1596 1597 mpiConfig->mainConfig.ioAbortDelay = 0; 1598 1599 mpiConfig->mainConfig.upperEventLogAddress = 0; 1600 mpiConfig->mainConfig.lowerEventLogAddress = 0; 1601 mpiConfig->mainConfig.eventLogSize = MPI_LOGSIZE; 1602 mpiConfig->mainConfig.eventLogOption = 0; 1603 mpiConfig->mainConfig.upperIOPeventLogAddress = 0; 1604 mpiConfig->mainConfig.lowerIOPeventLogAddress = 0; 1605 mpiConfig->mainConfig.IOPeventLogSize = MPI_LOGSIZE; 1606 mpiConfig->mainConfig.IOPeventLogOption = 0; 1607 mpiConfig->mainConfig.FatalErrorInterrupt = 0; 1608 1609 /* save the default value */ 1610 mpiConfig->numInboundQueues = AGSA_MAX_INBOUND_Q; 1611 mpiConfig->numOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1612 mpiConfig->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; 1613 mpiConfig->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1614 1615 /* configure inbound queues */ 1616 for ( i = 0; i < AGSA_MAX_INBOUND_Q; i ++ ) 1617 { 1618 mpiConfig->inboundQueues[i].numElements = INBOUND_DEPTH_SIZE; 1619 mpiConfig->inboundQueues[i].elementSize = IOMB_SIZE64; 1620 mpiConfig->inboundQueues[i].priority = MPI_QUEUE_NORMAL; 1621 } 1622 1623 /* configure outbound queues */ 1624 for ( i = 0; i < AGSA_MAX_OUTBOUND_Q; i ++ ) 1625 { 1626 mpiConfig->outboundQueues[i].numElements = OUTBOUND_DEPTH_SIZE; 1627 mpiConfig->outboundQueues[i].elementSize = IOMB_SIZE64; 1628 mpiConfig->outboundQueues[i].interruptVector = 0; 1629 mpiConfig->outboundQueues[i].interruptDelay = 0; 1630 mpiConfig->outboundQueues[i].interruptThreshold = 0; 1631 /* always enable OQ interrupt */ 1632 mpiConfig->outboundQueues[i].interruptEnable = 1; 1633 } 1634 } 1635 else 1636 { /* Parm3 is not null */ 1637 queueConfig = (agsaQueueConfig_t *)swConfig->param3; 1638 1639 #if defined(SALLSDK_DEBUG) 1640 sidump_Q_config( queueConfig ); 1641 #endif 1642 1643 SA_DBG1(("siConfiguration: swConfig->param3 == %p\n",queueConfig)); 1644 1645 if ((queueConfig->numInboundQueues > AGSA_MAX_INBOUND_Q) || 1646 (queueConfig->numOutboundQueues > AGSA_MAX_OUTBOUND_Q)) 1647 { 1648 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m2"); 1649 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE MAX_Q\n")); 1650 1651 return AGSA_RC_FAILURE; 1652 } 1653 1654 if ((queueConfig->numInboundQueues == 0 || 1655 queueConfig->numOutboundQueues == 0 )) 1656 { 1657 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m2"); 1658 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE NO_Q\n")); 1659 return AGSA_RC_FAILURE; 1660 } 1661 mpiConfig->mainConfig.eventLogSize = swConfig->sizefEventLog1 * KBYTES; 1662 mpiConfig->mainConfig.eventLogOption = swConfig->eventLog1Option; 1663 mpiConfig->mainConfig.IOPeventLogSize = swConfig->sizefEventLog2 * KBYTES; 1664 mpiConfig->mainConfig.IOPeventLogOption = swConfig->eventLog2Option; 1665 1666 if ((queueConfig->numInboundQueues > IQ_NUM_32) || (queueConfig->numOutboundQueues > OQ_NUM_32)) 1667 { 1668 enable64 = 1; 1669 } 1670 1671 if (agNULL == hwConfig) 1672 { 1673 intOption = 0; 1674 } 1675 else 1676 { 1677 1678 #if defined(SALLSDK_DEBUG) 1679 sidump_hwConfig(hwConfig); 1680 #endif 1681 1682 1683 if(smIS_SPCV(agRoot)) 1684 { 1685 intOption = 0; 1686 } 1687 else 1688 { 1689 intOption = hwConfig->intReassertionOption & INT_OPTION; 1690 } 1691 1692 } 1693 1694 /* Enable SGPIO */ 1695 swConfig->sgpioSupportEnable = 1; 1696 1697 /* set bit for normal priority or high priority path */ 1698 /* set fatal error interrupt enable and vector */ 1699 /* set Interrupt Reassertion enable and 64 IQ/OQ enable */ 1700 mpiConfig->mainConfig.FatalErrorInterrupt = 1701 (swConfig->fatalErrorInterruptEnable) /* bit 0*/ | 1702 (hwConfig == agNULL ? 0: (hwConfig->hwOption & HW_CFG_PICI_EFFECTIVE_ADDRESS ? (0x1 << SHIFT1): 0))| 1703 (swConfig->sgpioSupportEnable ? (0x1 << SHIFT2): 0) | 1704 /* compile option SA_ENABLE_POISION_TLP */(SA_PTNFE_POISION_TLP << SHIFT3) | 1705 #ifdef SA_CONFIG_MDFD_REGISTRY 1706 (swConfig->disableMDF ? (0x1 << SHIFT4): 0) | 1707 #else 1708 /* compile option SA_DISABLE_MDFD */ (SA_MDFD_MULTI_DATA_FETCH << SHIFT4) | 1709 #endif /*SA_CONFIG_MDFD_REGISTRY*/ 1710 /* compile option SA_DISABLE_OB_COAL */(SA_OUTBOUND_COALESCE << SHIFT5) | 1711 /* compile option SA_ENABLE_ARBTE */(SA_ARBTE << SHIFT6) | 1712 ((swConfig->fatalErrorInterruptVector & FATAL_ERROR_INT_BITS) << SHIFT8) | 1713 (enable64 << SHIFT16) | 1714 (intOption << SHIFT17); 1715 1716 1717 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); 1718 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptVector %X\n",swConfig->fatalErrorInterruptVector)); 1719 1720 1721 1722 /* initialize the mpiConfig */ 1723 /* We configure the Host main part of configuration table */ 1724 mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; 1725 mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; 1726 mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; 1727 mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; 1728 mpiConfig->mainConfig.ioAbortDelay = 0; 1729 mpiConfig->mainConfig.PortRecoveryTimerPortResetTimer = swConfig->PortRecoveryResetTimer; 1730 1731 /* get parameter from queueConfig */ 1732 mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = queueConfig->iqNormalPriorityProcessingDepth | 1733 (queueConfig->iqHighPriorityProcessingDepth << SHIFT8) | 1734 (queueConfig->generalEventQueue << SHIFT16) | 1735 (queueConfig->tgtDeviceRemovedEventQueue << SHIFT24); 1736 1737 mpiConfig->mainConfig.outboundHWEventPID0_3 = queueConfig->sasHwEventQueue[0] | 1738 (queueConfig->sasHwEventQueue[1] << SHIFT8) | 1739 (queueConfig->sasHwEventQueue[2] << SHIFT16) | 1740 (queueConfig->sasHwEventQueue[3] << SHIFT24); 1741 mpiConfig->mainConfig.outboundHWEventPID4_7 = queueConfig->sasHwEventQueue[4] | 1742 (queueConfig->sasHwEventQueue[5] << SHIFT8) | 1743 (queueConfig->sasHwEventQueue[6] << SHIFT16) | 1744 (queueConfig->sasHwEventQueue[7] << SHIFT24); 1745 mpiConfig->mainConfig.outboundNCQEventPID0_3 = queueConfig->sataNCQErrorEventQueue[0] | 1746 (queueConfig->sataNCQErrorEventQueue[1] << SHIFT8) | 1747 (queueConfig->sataNCQErrorEventQueue[2] << SHIFT16) | 1748 (queueConfig->sataNCQErrorEventQueue[3] << SHIFT24); 1749 mpiConfig->mainConfig.outboundNCQEventPID4_7 = queueConfig->sataNCQErrorEventQueue[4] | 1750 (queueConfig->sataNCQErrorEventQueue[5] << SHIFT8) | 1751 (queueConfig->sataNCQErrorEventQueue[6] << SHIFT16) | 1752 (queueConfig->sataNCQErrorEventQueue[7] << SHIFT24); 1753 /* save it */ 1754 mpiConfig->numInboundQueues = queueConfig->numInboundQueues; 1755 mpiConfig->numOutboundQueues = queueConfig->numOutboundQueues; 1756 mpiConfig->queueOption = queueConfig->queueOption; 1757 1758 SA_DBG2(("siConfiguration: numInboundQueues=%d numOutboundQueues=%d\n", 1759 queueConfig->numInboundQueues, 1760 queueConfig->numOutboundQueues)); 1761 1762 /* configure inbound queues */ 1763 /* We configure the size of queue based on swConfig */ 1764 for( i = 0; i < queueConfig->numInboundQueues; i ++ ) 1765 { 1766 mpiConfig->inboundQueues[i].numElements = (bit16)queueConfig->inboundQueues[i].elementCount; 1767 mpiConfig->inboundQueues[i].elementSize = (bit16)queueConfig->inboundQueues[i].elementSize; 1768 mpiConfig->inboundQueues[i].priority = queueConfig->inboundQueues[i].priority; 1769 1770 SA_DBG2(("siConfiguration: IBQ%d:elementCount=%d elementSize=%d priority=%d Total Size 0x%X\n", 1771 i, 1772 queueConfig->inboundQueues[i].elementCount, 1773 queueConfig->inboundQueues[i].elementSize, 1774 queueConfig->inboundQueues[i].priority, 1775 queueConfig->inboundQueues[i].elementCount * queueConfig->inboundQueues[i].elementSize )); 1776 } 1777 1778 /* configura outbound queues */ 1779 /* We configure the size of queue based on swConfig */ 1780 for( i = 0; i < queueConfig->numOutboundQueues; i ++ ) 1781 { 1782 mpiConfig->outboundQueues[i].numElements = (bit16)queueConfig->outboundQueues[i].elementCount; 1783 mpiConfig->outboundQueues[i].elementSize = (bit16)queueConfig->outboundQueues[i].elementSize; 1784 mpiConfig->outboundQueues[i].interruptVector = (bit8)queueConfig->outboundQueues[i].interruptVectorIndex; 1785 mpiConfig->outboundQueues[i].interruptDelay = (bit16)queueConfig->outboundQueues[i].interruptDelay; 1786 mpiConfig->outboundQueues[i].interruptThreshold = (bit8)queueConfig->outboundQueues[i].interruptCount; 1787 mpiConfig->outboundQueues[i].interruptEnable = (bit32)queueConfig->outboundQueues[i].interruptEnable; 1788 1789 SA_DBG2(("siConfiguration: OBQ%d:elementCount=%d elementSize=%d interruptCount=%d interruptEnable=%d\n", 1790 i, 1791 queueConfig->outboundQueues[i].elementCount, 1792 queueConfig->outboundQueues[i].elementSize, 1793 queueConfig->outboundQueues[i].interruptCount, 1794 queueConfig->outboundQueues[i].interruptEnable)); 1795 } 1796 } 1797 1798 SA_DBG1(("siConfiguration:mpiConfig->mainConfig.FatalErrorInterrupt 0x%X\n",mpiConfig->mainConfig.FatalErrorInterrupt)); 1799 SA_DBG1(("siConfiguration:swConfig->fatalErrorInterruptVector 0x%X\n",swConfig->fatalErrorInterruptVector)); 1800 SA_DBG1(("siConfiguration:enable64 0x%X\n",enable64)); 1801 SA_DBG1(("siConfiguration:PortRecoveryResetTimer 0x%X\n",swConfig->PortRecoveryResetTimer)); 1802 1803 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m2"); 1804 1805 /* return */ 1806 return AGSA_RC_SUCCESS; 1807 } 1808 1809 #ifdef FW_EVT_LOG_TST 1810 void saLogDump(agsaRoot_t *agRoot, 1811 U32 *eventLogSize, 1812 U32 **eventLogAddress_) 1813 { 1814 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1815 //mpiConfig_t *mpiConfig = &saRoot->mpiConfig; 1816 mpiHostLLConfigDescriptor_t *mpiConfig = &saRoot->mainConfigTable; 1817 1818 *eventLogAddress_ = (U32*)eventLogAddress; 1819 *eventLogSize = (U32)mpiConfig->eventLogSize; 1820 } 1821 #endif 1822 1823 /*******************************************************************************/ 1824 /** \fn mpiInitialize(agsaRoot *agRoot, mpiMemReq_t* memoryAllocated, mpiConfig_t* config) 1825 * \brief Initializes the MPI Message Unit 1826 * \param agRoot Pointer to a data structure containing LL layer context handles 1827 * \param memoryAllocated Data structure that holds the different chunks of memory that are allocated 1828 * \param config MPI configuration 1829 * 1830 * This function is called to initialize SPC_HOST_MPI internal data structures and the SPC hardware. 1831 * This function is competed synch->ronously (there is no callback) 1832 * 1833 * Return: 1834 * AGSA_RC_SUCCESS if initialization succeeded. 1835 * AGSA_RC_FAILURE if initialization failed. 1836 */ 1837 /*******************************************************************************/ 1838 GLOBAL bit32 mpiInitialize(agsaRoot_t *agRoot, 1839 mpiMemReq_t* memoryAllocated, 1840 mpiConfig_t* config) 1841 { 1842 static spc_configMainDescriptor_t mainCfg; /* main part of MPI configuration */ 1843 static spc_inboundQueueDescriptor_t inQueueCfg; /* Inbound queue HW configuration structure */ 1844 static spc_outboundQueueDescriptor_t outQueueCfg; /* Outbound queue HW configuration structure */ 1845 bit16 qIdx, i, indexoffset; /* Queue index */ 1846 bit16 mIdx = 0; /* Memory region index */ 1847 bit32 MSGUCfgTblDWIdx, GSTLenMPIS; 1848 bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; 1849 bit32 value, togglevalue; 1850 bit32 saveOffset; 1851 bit32 inboundoffset, outboundoffset; 1852 bit8 pcibar; 1853 bit16 maxinbound = AGSA_MAX_INBOUND_Q; 1854 bit16 maxoutbound = AGSA_MAX_OUTBOUND_Q; 1855 bit32 OB_CIPCIBar; 1856 bit32 IB_PIPCIBar; 1857 bit32 max_wait_time; 1858 bit32 max_wait_count; 1859 bit32 memOffset; 1860 agsaLLRoot_t *saRoot; 1861 mpiICQueue_t *circularIQ = agNULL; 1862 mpiOCQueue_t *circularOQ; 1863 1864 bit32 mpiUnInitFailed = 0; 1865 bit32 mpiStartToggleFailed = 0; 1866 1867 1868 #if defined(SALLSDK_DEBUG) 1869 bit8 phycount = AGSA_MAX_VALID_PHYS; 1870 #endif /* SALLSDK_DEBUG */ 1871 1872 SA_DBG1(("mpiInitialize: Entering\n")); 1873 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 1874 SA_ASSERT(NULL != memoryAllocated, "memoryAllocated argument cannot be null"); 1875 SA_ASSERT(NULL != config, "config argument cannot be null"); 1876 SA_ASSERT(0 == (sizeof(spc_inboundQueueDescriptor_t) % 4), "spc_inboundQueueDescriptor_t type size has to be divisible by 4"); 1877 1878 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1879 1880 si_memset(&mainCfg,0,sizeof(spc_configMainDescriptor_t)); 1881 si_memset(&inQueueCfg,0,sizeof(spc_inboundQueueDescriptor_t)); 1882 si_memset(&outQueueCfg,0,sizeof(spc_outboundQueueDescriptor_t)); 1883 1884 SA_ASSERT((agNULL !=saRoot ), ""); 1885 if(saRoot == agNULL) 1886 { 1887 SA_DBG1(("mpiInitialize: saRoot == agNULL\n")); 1888 return(AGSA_RC_FAILURE); 1889 } 1890 smTraceFuncEnter(hpDBG_VERY_LOUD,"m3"); 1891 1892 /*Shift BAR 4 for SPC HAILEAH*/ 1893 if(smIS_SPC(agRoot)) 1894 { 1895 if( smIS_HIL(agRoot)) 1896 { 1897 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) 1898 { 1899 SA_DBG1(("mpiInitialize: siBar4Shift FAILED ******************************************\n")); 1900 return AGSA_RC_FAILURE; 1901 } 1902 } 1903 } 1904 1905 /* Wait for the SPC Configuration Table to be ready */ 1906 ret = mpiWaitForConfigTable(agRoot, &mainCfg); 1907 if (AGSA_RC_FAILURE == ret) 1908 { 1909 /* return error if MPI Configuration Table not ready */ 1910 SA_DBG1(("mpiInitialize: mpiWaitForConfigTable FAILED ******************************************\n")); 1911 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m3"); 1912 return ret; 1913 } 1914 1915 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 1916 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 1917 /* get PCI BAR */ 1918 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 1919 /* get pci Bar index */ 1920 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 1921 1922 SA_DBG1(("mpiInitialize: MSGUCfgTblBase = 0x%x\n", MSGUCfgTblBase)); 1923 #if defined(SALLSDK_DEBUG) 1924 /* get Phy count from configuration table */ 1925 phycount = (bit8)((mainCfg.ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); 1926 1927 SA_DBG1(("mpiInitialize: Number of PHYs = 0x%x\n", phycount)); 1928 1929 smTrace(hpDBG_VERY_LOUD,"70",phycount); 1930 /* TP:70 phycount */ 1931 #endif /* SALLSDK_DEBUG */ 1932 1933 /* get High Priority IQ support flag */ 1934 if (mainCfg.ContrlCapFlag & HP_SUPPORT_BIT) 1935 { 1936 SA_DBG1(("mpiInitialize: High Priority IQ support from SPC\n")); 1937 } 1938 /* get Interrupt Coalescing Support flag */ 1939 if (mainCfg.ContrlCapFlag & INT_COL_BIT) 1940 { 1941 SA_DBG1(("mpiInitialize: Interrupt Coalescing support from SPC\n")); 1942 } 1943 1944 /* get configured the number of inbound/outbound queues */ 1945 if (memoryAllocated->count == TOTAL_MPI_MEM_CHUNKS) 1946 { 1947 config->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; 1948 config->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1949 } 1950 else 1951 { 1952 config->maxNumInboundQueues = config->numInboundQueues; 1953 config->maxNumOutboundQueues = config->numOutboundQueues; 1954 maxinbound = config->numInboundQueues; 1955 maxoutbound = config->numOutboundQueues; 1956 } 1957 1958 SA_DBG1(("mpiInitialize: Number of IQ %d\n", maxinbound)); 1959 SA_DBG1(("mpiInitialize: Number of OQ %d\n", maxoutbound)); 1960 1961 /* get inbound queue offset */ 1962 inboundoffset = mainCfg.inboundQueueOffset; 1963 /* get outbound queue offset */ 1964 outboundoffset = mainCfg.outboundQueueOffset; 1965 1966 if(smIS_SPCV(agRoot)) 1967 { 1968 SA_DBG2(("mpiInitialize: Offset of IQ %d\n", (inboundoffset & 0xFF000000) >> 24)); 1969 SA_DBG2(("mpiInitialize: Offset of OQ %d\n", (outboundoffset & 0xFF000000) >> 24)); 1970 inboundoffset &= 0x00FFFFFF; 1971 outboundoffset &= 0x00FFFFFF; 1972 } 1973 /* get offset of the configuration table */ 1974 MSGUCfgTblDWIdx = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 1975 MSGUCfgTblDWIdx = MSGUCfgTblDWIdx & SCRATCH_PAD0_OFFSET_MASK; 1976 1977 saveOffset = MSGUCfgTblDWIdx; 1978 1979 /* Checks if the configuration memory region size is the same as the mpiConfigMain */ 1980 if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.eventLogSize) 1981 { 1982 SA_DBG1(("ERROR: The memory region [%d] 0x%X != 0x%X does not have the size of the MSGU event log ******************************************\n", 1983 mIdx,memoryAllocated->region[mIdx].totalLength,config->mainConfig.eventLogSize)); 1984 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m3"); 1985 return AGSA_RC_FAILURE; 1986 } 1987 1988 mainCfg.iQNPPD_HPPD_GEvent = config->mainConfig.iQNPPD_HPPD_GEvent; 1989 1990 if(smIS_SPCV(agRoot)) 1991 { 1992 mainCfg.outboundHWEventPID0_3 = 0; 1993 mainCfg.outboundHWEventPID4_7 = 0; 1994 mainCfg.outboundNCQEventPID0_3 = 0; 1995 mainCfg.outboundNCQEventPID4_7 = 0; 1996 mainCfg.outboundTargetITNexusEventPID0_3 = 0; 1997 mainCfg.outboundTargetITNexusEventPID4_7 = 0; 1998 mainCfg.outboundTargetSSPEventPID0_3 = 0; 1999 mainCfg.outboundTargetSSPEventPID4_7 = 0; 2000 mainCfg.ioAbortDelay = 0; /* SPCV reserved */ 2001 mainCfg.custset = 0; 2002 mainCfg.portRecoveryResetTimer = config->mainConfig.PortRecoveryTimerPortResetTimer; 2003 SA_DBG1(("mpiInitialize:custset V %8X\n",mainCfg.custset)); 2004 SA_DBG1(("mpiInitialize:portRecoveryResetTimer V %8X\n",mainCfg.portRecoveryResetTimer)); 2005 2006 mainCfg.interruptReassertionDelay = saRoot->hwConfig.intReassertionOption; 2007 SA_DBG1(("mpiInitialize:interruptReassertionDelay V %8X\n", mainCfg.interruptReassertionDelay)); 2008 2009 2010 } 2011 else 2012 { 2013 mainCfg.outboundHWEventPID0_3 = config->mainConfig.outboundHWEventPID0_3; 2014 mainCfg.outboundHWEventPID4_7 = config->mainConfig.outboundHWEventPID4_7; 2015 mainCfg.outboundNCQEventPID0_3 = config->mainConfig.outboundNCQEventPID0_3; 2016 mainCfg.outboundNCQEventPID4_7 = config->mainConfig.outboundNCQEventPID4_7; 2017 mainCfg.outboundTargetITNexusEventPID0_3 = config->mainConfig.outboundTargetITNexusEventPID0_3; 2018 mainCfg.outboundTargetITNexusEventPID4_7 = config->mainConfig.outboundTargetITNexusEventPID4_7; 2019 mainCfg.outboundTargetSSPEventPID0_3 = config->mainConfig.outboundTargetSSPEventPID0_3; 2020 mainCfg.outboundTargetSSPEventPID4_7 = config->mainConfig.outboundTargetSSPEventPID4_7; 2021 mainCfg.ioAbortDelay = config->mainConfig.ioAbortDelay; 2022 mainCfg.custset = config->mainConfig.custset; 2023 2024 SA_DBG1(("mpiInitialize:custset spc %8X\n",mainCfg.custset)); 2025 2026 } 2027 #ifdef FW_EVT_LOG_TST 2028 eventLogAddress = memoryAllocated->region[mIdx].virtPtr; 2029 #endif 2030 mainCfg.upperEventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; 2031 mainCfg.lowerEventLogAddress = memoryAllocated->region[mIdx].physAddrLower; 2032 mainCfg.eventLogSize = config->mainConfig.eventLogSize; 2033 mainCfg.eventLogOption = config->mainConfig.eventLogOption; 2034 2035 mIdx++; 2036 2037 /* Checks if the configuration memory region size is the same as the mpiConfigMain */ 2038 if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.IOPeventLogSize) 2039 { 2040 SA_DBG1(("ERROR: The memory region does not have the size of the IOP event log\n")); 2041 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m3"); 2042 return AGSA_RC_FAILURE; 2043 } 2044 2045 mainCfg.upperIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; 2046 mainCfg.lowerIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrLower; 2047 mainCfg.IOPeventLogSize = config->mainConfig.IOPeventLogSize; 2048 mainCfg.IOPeventLogOption = config->mainConfig.IOPeventLogOption; 2049 mainCfg.FatalErrorInterrupt = config->mainConfig.FatalErrorInterrupt; 2050 2051 SA_DBG1(("mpiInitialize: iQNPPD_HPPD_GEvent 0x%x\n", mainCfg.iQNPPD_HPPD_GEvent)); 2052 if(smIS_SPCV(agRoot)) 2053 { 2054 } 2055 else 2056 { 2057 SA_DBG3(("mpiInitialize: outboundHWEventPID0_3 0x%x\n", mainCfg.outboundHWEventPID0_3)); 2058 SA_DBG3(("mpiInitialize: outboundHWEventPID4_7 0x%x\n", mainCfg.outboundHWEventPID4_7)); 2059 SA_DBG3(("mpiInitialize: outboundNCQEventPID0_3 0x%x\n", mainCfg.outboundNCQEventPID0_3)); 2060 SA_DBG3(("mpiInitialize: outboundNCQEventPID4_7 0x%x\n", mainCfg.outboundNCQEventPID4_7)); 2061 SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID0_3 0x%x\n", mainCfg.outboundTargetITNexusEventPID0_3)); 2062 SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID4_7 0x%x\n", mainCfg.outboundTargetITNexusEventPID4_7)); 2063 SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID0_3 0x%x\n", mainCfg.outboundTargetSSPEventPID0_3)); 2064 SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID4_7 0x%x\n", mainCfg.outboundTargetSSPEventPID4_7)); 2065 } 2066 2067 SA_DBG3(("mpiInitialize: upperEventLogAddress 0x%x\n", mainCfg.upperEventLogAddress)); 2068 SA_DBG3(("mpiInitialize: lowerEventLogAddress 0x%x\n", mainCfg.lowerEventLogAddress)); 2069 SA_DBG3(("mpiInitialize: eventLogSize 0x%x\n", mainCfg.eventLogSize)); 2070 SA_DBG3(("mpiInitialize: eventLogOption 0x%x\n", mainCfg.eventLogOption)); 2071 #ifdef FW_EVT_LOG_TST 2072 SA_DBG3(("mpiInitialize: eventLogAddress 0x%p\n", eventLogAddress)); 2073 #endif 2074 SA_DBG3(("mpiInitialize: upperIOPLogAddress 0x%x\n", mainCfg.upperIOPeventLogAddress)); 2075 SA_DBG3(("mpiInitialize: lowerIOPLogAddress 0x%x\n", mainCfg.lowerIOPeventLogAddress)); 2076 SA_DBG3(("mpiInitialize: IOPeventLogSize 0x%x\n", mainCfg.IOPeventLogSize)); 2077 SA_DBG3(("mpiInitialize: IOPeventLogOption 0x%x\n", mainCfg.IOPeventLogOption)); 2078 SA_DBG3(("mpiInitialize: FatalErrorInterrupt 0x%x\n", mainCfg.FatalErrorInterrupt)); 2079 SA_DBG3(("mpiInitialize: HDAModeFlags 0x%x\n", mainCfg.HDAModeFlags)); 2080 SA_DBG3(("mpiInitialize: analogSetupTblOffset 0x%08x\n", mainCfg.analogSetupTblOffset)); 2081 2082 saRoot->mainConfigTable.iQNPPD_HPPD_GEvent = mainCfg.iQNPPD_HPPD_GEvent; 2083 2084 if(smIS_SPCV(agRoot)) 2085 { 2086 /* SPCV - reserved fields */ 2087 saRoot->mainConfigTable.outboundHWEventPID0_3 = 0; 2088 saRoot->mainConfigTable.outboundHWEventPID4_7 = 0; 2089 saRoot->mainConfigTable.outboundNCQEventPID0_3 = 0; 2090 saRoot->mainConfigTable.outboundNCQEventPID4_7 = 0; 2091 saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = 0; 2092 saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = 0; 2093 saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = 0; 2094 saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = 0; 2095 saRoot->mainConfigTable.ioAbortDelay = 0; 2096 saRoot->mainConfigTable.custset = 0; 2097 2098 } 2099 else 2100 { 2101 saRoot->mainConfigTable.outboundHWEventPID0_3 = mainCfg.outboundHWEventPID0_3; 2102 saRoot->mainConfigTable.outboundHWEventPID4_7 = mainCfg.outboundHWEventPID4_7; 2103 saRoot->mainConfigTable.outboundNCQEventPID0_3 = mainCfg.outboundNCQEventPID0_3; 2104 saRoot->mainConfigTable.outboundNCQEventPID4_7 = mainCfg.outboundNCQEventPID4_7; 2105 saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = mainCfg.outboundTargetITNexusEventPID0_3; 2106 saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = mainCfg.outboundTargetITNexusEventPID4_7; 2107 saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = mainCfg.outboundTargetSSPEventPID0_3; 2108 saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = mainCfg.outboundTargetSSPEventPID4_7; 2109 saRoot->mainConfigTable.ioAbortDelay = mainCfg.ioAbortDelay; 2110 saRoot->mainConfigTable.custset = mainCfg.custset; 2111 2112 } 2113 2114 saRoot->mainConfigTable.upperEventLogAddress = mainCfg.upperEventLogAddress; 2115 saRoot->mainConfigTable.lowerEventLogAddress = mainCfg.lowerEventLogAddress; 2116 saRoot->mainConfigTable.eventLogSize = mainCfg.eventLogSize; 2117 saRoot->mainConfigTable.eventLogOption = mainCfg.eventLogOption; 2118 saRoot->mainConfigTable.upperIOPeventLogAddress = mainCfg.upperIOPeventLogAddress; 2119 saRoot->mainConfigTable.lowerIOPeventLogAddress = mainCfg.lowerIOPeventLogAddress; 2120 saRoot->mainConfigTable.IOPeventLogSize = mainCfg.IOPeventLogSize; 2121 saRoot->mainConfigTable.IOPeventLogOption = mainCfg.IOPeventLogOption; 2122 saRoot->mainConfigTable.FatalErrorInterrupt = mainCfg.FatalErrorInterrupt; 2123 2124 2125 if(smIS_SPCV(agRoot)) 2126 { 2127 ;/* SPCV - reserved fields */ 2128 } 2129 else 2130 { 2131 saRoot->mainConfigTable.HDAModeFlags = mainCfg.HDAModeFlags; 2132 } 2133 2134 saRoot->mainConfigTable.analogSetupTblOffset = mainCfg.analogSetupTblOffset; 2135 2136 smTrace(hpDBG_VERY_LOUD,"71",mIdx); 2137 /* TP:71 71 mIdx */ 2138 2139 2140 2141 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), 2142 mainCfg.iQNPPD_HPPD_GEvent); 2143 2144 SA_DBG3(("mpiInitialize: Offset 0x%08x mainCfg.iQNPPD_HPPD_GEvent 0x%x\n", (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), mainCfg.iQNPPD_HPPD_GEvent)); 2145 2146 if(smIS_SPC6V(agRoot)) 2147 { 2148 if(smIsCfgVREV_B(agRoot)) 2149 { 2150 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2151 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2152 2153 SA_DBG1(("mpiInitialize:SPCV - MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE\n" )); 2154 } 2155 if(smIsCfgVREV_C(agRoot)) 2156 { 2157 SA_DBG1(("mpiInitialize:SPCV - END_TO_END_CRC On\n" )); 2158 } 2159 SA_DBG3(("mpiInitialize:SPCV - rest reserved field \n" )); 2160 ;/* SPCV - reserved field */ 2161 } 2162 else if(smIS_SPC(agRoot)) 2163 { 2164 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID03_OFFSET), 2165 mainCfg.outboundHWEventPID0_3); 2166 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID47_OFFSET), 2167 mainCfg.outboundHWEventPID4_7); 2168 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID03_OFFSET), 2169 mainCfg.outboundNCQEventPID0_3); 2170 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID47_OFFSET), 2171 mainCfg.outboundNCQEventPID4_7); 2172 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID03_OFFSET), 2173 mainCfg.outboundTargetITNexusEventPID0_3); 2174 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID47_OFFSET), 2175 mainCfg.outboundTargetITNexusEventPID4_7); 2176 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID03_OFFSET), 2177 mainCfg.outboundTargetSSPEventPID0_3); 2178 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID47_OFFSET), 2179 mainCfg.outboundTargetSSPEventPID4_7); 2180 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_CUSTOMER_SETTING), 2181 mainCfg.custset); 2182 }else 2183 { 2184 if(smIsCfgVREV_A(agRoot)) 2185 { 2186 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2187 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); /* */ 2188 SA_DBG1(("mpiInitialize:SPCV12G - offset MAIN_IO_ABORT_DELAY 0x%x value MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x%x\n",MAIN_IO_ABORT_DELAY ,MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE)); 2189 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC OFF for rev A %d\n",smIsCfgVREV_A(agRoot) )); 2190 } 2191 else if(smIsCfgVREV_B(agRoot)) 2192 { 2193 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC ON rev B %d ****************************\n",smIsCfgVREV_B(agRoot) )); 2194 /*ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2195 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2196 */ 2197 } 2198 else if(smIsCfgVREV_C(agRoot)) 2199 { 2200 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC on rev C %d\n",smIsCfgVREV_C(agRoot) )); 2201 } 2202 else 2203 { 2204 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2205 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2206 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC Off unknown rev 0x%x\n", ossaHwRegReadConfig32((agRoot), 8 ))); 2207 } 2208 } 2209 2210 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress); 2211 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress); 2212 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize); 2213 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption); 2214 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress); 2215 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress); 2216 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize); 2217 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption); 2218 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt); 2219 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer); 2220 2221 SA_DBG3(("mpiInitialize: Offset 0x%08x upperEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress )); 2222 SA_DBG3(("mpiInitialize: Offset 0x%08x lowerEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress )); 2223 SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize )); 2224 SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption )); 2225 SA_DBG3(("mpiInitialize: Offset 0x%08x upperIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress )); 2226 SA_DBG3(("mpiInitialize: Offset 0x%08x lowerIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress )); 2227 SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize )); 2228 SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption )); 2229 SA_DBG3(("mpiInitialize: Offset 0x%08x FatalErrorInterrupt 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt )); 2230 SA_DBG3(("mpiInitialize: Offset 0x%08x PortRecoveryResetTimer 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer )); 2231 2232 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay); 2233 SA_DBG3(("mpiInitialize: Offset 0x%08x InterruptReassertionDelay 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay )); 2234 2235 mIdx++; 2236 2237 /* skip the ci and pi memory region */ 2238 mIdx++; 2239 mIdx++; 2240 2241 smTrace(hpDBG_VERY_LOUD,"72",mIdx); 2242 /* TP:72 mIdx */ 2243 smTrace(hpDBG_VERY_LOUD,"Bc",maxinbound); 2244 /* TP:Bc maxinbound */ 2245 smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); 2246 /* TP:Bd pcibar */ 2247 2248 /* index offset */ 2249 indexoffset = 0; 2250 memOffset = 0; 2251 2252 /* Memory regions for the inbound queues */ 2253 for(qIdx = 0; qIdx < maxinbound; qIdx++) 2254 { 2255 /* point back to the begin then plus offset to next queue */ 2256 smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); 2257 /* TP:Bd pcibar */ 2258 MSGUCfgTblDWIdx = saveOffset; 2259 MSGUCfgTblDWIdx += inboundoffset; 2260 MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); 2261 SA_DBG1(("mpiInitialize: A saveOffset 0x%x MSGUCfgTblDWIdx 0x%x\n",saveOffset ,MSGUCfgTblDWIdx)); 2262 2263 /* if the MPI configuration says that this queue is disabled ... */ 2264 if(0 == config->inboundQueues[qIdx].numElements) 2265 { 2266 /* ... Clears the configuration table for this queue */ 2267 2268 inQueueCfg.elementPriSizeCount= 0; 2269 inQueueCfg.upperBaseAddress = 0; 2270 inQueueCfg.lowerBaseAddress = 0; 2271 inQueueCfg.ciUpperBaseAddress = 0; 2272 inQueueCfg.ciLowerBaseAddress = 0; 2273 /* skip inQueueCfg.PIPCIBar (PM8000 write access) */ 2274 /* skip inQueueCfg.PIOffset (PM8000 write access) */ 2275 2276 /* Update the inbound configuration table in SPC GSM */ 2277 mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); 2278 } 2279 2280 /* If the queue is enabled, then ... */ 2281 else 2282 { 2283 bit32 memSize = config->inboundQueues[qIdx].numElements * config->inboundQueues[qIdx].elementSize; 2284 bit32 remainder = memSize & 127; 2285 2286 /* Calculate the size of this queue padded to 128 bytes */ 2287 if (remainder > 0) 2288 { 2289 memSize += (128 - remainder); 2290 } 2291 2292 /* ... first checks that the memory region has the right size */ 2293 if( (memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || 2294 (NULL == memoryAllocated->region[mIdx].virtPtr) || 2295 (0 == memoryAllocated->region[mIdx].totalLength)) 2296 { 2297 SA_DBG1(("mpiInitialize: ERROR The memory region does not have the right size for this inbound queue")); 2298 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m3"); 2299 return AGSA_RC_FAILURE; 2300 } 2301 else 2302 { 2303 /* Then, using the MPI configuration argument, initializes the corresponding element on the saRoot */ 2304 saRoot->inboundQueue[qIdx].numElements = config->inboundQueues[qIdx].numElements; 2305 saRoot->inboundQueue[qIdx].elementSize = config->inboundQueues[qIdx].elementSize; 2306 saRoot->inboundQueue[qIdx].priority = config->inboundQueues[qIdx].priority; 2307 si_memcpy(&saRoot->inboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); 2308 saRoot->inboundQueue[qIdx].memoryRegion.virtPtr = 2309 (bit8 *)saRoot->inboundQueue[qIdx].memoryRegion.virtPtr + memOffset; 2310 saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; 2311 saRoot->inboundQueue[qIdx].memoryRegion.elementSize = memSize; 2312 saRoot->inboundQueue[qIdx].memoryRegion.totalLength = memSize; 2313 saRoot->inboundQueue[qIdx].memoryRegion.numElements = 1; 2314 2315 /* Initialize the local copy of PIs, CIs */ 2316 SA_DBG1(("mpiInitialize: queue %d PI CI zero\n",qIdx)); 2317 saRoot->inboundQueue[qIdx].producerIdx = 0; 2318 saRoot->inboundQueue[qIdx].consumerIdx = 0; 2319 saRoot->inboundQueue[qIdx].agRoot = agRoot; 2320 2321 /* MPI memory region for inbound CIs are 2 */ 2322 saRoot->inboundQueue[qIdx].ciPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX].virtPtr)) + qIdx * 4); 2323 /* ... and in the local structure we will use to copy to the HW configuration table */ 2324 2325 /* CI base address */ 2326 inQueueCfg.elementPriSizeCount= config->inboundQueues[qIdx].numElements | 2327 (config->inboundQueues[qIdx].elementSize << SHIFT16) | 2328 (config->inboundQueues[qIdx].priority << SHIFT30); 2329 inQueueCfg.upperBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrUpper; 2330 inQueueCfg.lowerBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower; 2331 inQueueCfg.ciUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrUpper; 2332 inQueueCfg.ciLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrLower + qIdx * 4; 2333 2334 /* write the configured data of inbound queue to SPC GSM */ 2335 mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); 2336 /* get inbound PI PCI Bar and Offset */ 2337 /* get the PI PCI Bar offset and convert it to logical BAR */ 2338 IB_PIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR)); 2339 saRoot->inboundQueue[qIdx].PIPCIBar = mpiGetPCIBarIndex(agRoot, IB_PIPCIBar); 2340 saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); 2341 saRoot->inboundQueue[qIdx].qNumber = qIdx; 2342 2343 memOffset += memSize; 2344 2345 if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || 2346 (qIdx == (maxinbound - 1))) 2347 { 2348 mIdx++; 2349 indexoffset += MAX_QUEUE_EACH_MEM; 2350 memOffset = 0; 2351 } 2352 2353 } /* else for memeory ok */ 2354 } /* queue enable */ 2355 } /* loop for inbound queue */ 2356 2357 smTrace(hpDBG_VERY_LOUD,"73",0); 2358 /* TP:73 outbound queues */ 2359 2360 /* index offset */ 2361 indexoffset = 0; 2362 memOffset = 0; 2363 /* Let's process the memory regions for the outbound queues */ 2364 for(qIdx = 0; qIdx < maxoutbound; qIdx++) 2365 { 2366 /* point back to the begin then plus offset to next queue */ 2367 MSGUCfgTblDWIdx = saveOffset; 2368 MSGUCfgTblDWIdx += outboundoffset; 2369 MSGUCfgTblDWIdx += (sizeof(spc_outboundQueueDescriptor_t) * qIdx); 2370 2371 /* if the MPI configuration says that this queue is disabled ... */ 2372 if(0 == config->outboundQueues[qIdx].numElements) 2373 { 2374 /* ... Clears the configuration table for this queue */ 2375 outQueueCfg.upperBaseAddress = 0; 2376 outQueueCfg.lowerBaseAddress = 0; 2377 outQueueCfg.piUpperBaseAddress = 0; 2378 outQueueCfg.piLowerBaseAddress = 0; 2379 /* skip outQueueCfg.CIPCIBar = 0; read access only */ 2380 /* skip outQueueCfg.CIOffset = 0; read access only */ 2381 outQueueCfg.elementSizeCount = 0; 2382 outQueueCfg.interruptVecCntDelay = 0; 2383 2384 /* Updated the configuration table in SPC GSM */ 2385 mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); 2386 } 2387 2388 /* If the outbound queue is enabled, then ... */ 2389 else 2390 { 2391 bit32 memSize = config->outboundQueues[qIdx].numElements * config->outboundQueues[qIdx].elementSize; 2392 bit32 remainder = memSize & 127; 2393 2394 /* Calculate the size of this queue padded to 128 bytes */ 2395 if (remainder > 0) 2396 { 2397 memSize += (128 - remainder); 2398 } 2399 2400 /* ... first checks that the memory region has the right size */ 2401 if((memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || 2402 (NULL == memoryAllocated->region[mIdx].virtPtr) || 2403 (0 == memoryAllocated->region[mIdx].totalLength)) 2404 { 2405 SA_DBG1(("ERROR: The memory region does not have the right size for this outbound queue")); 2406 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m3"); 2407 return AGSA_RC_FAILURE; 2408 } 2409 else 2410 { 2411 /* Then, using the MPI configuration argument, initializes the corresponding element on the MPI context ... */ 2412 saRoot->outboundQueue[qIdx].numElements = config->outboundQueues[qIdx].numElements; 2413 saRoot->outboundQueue[qIdx].elementSize = config->outboundQueues[qIdx].elementSize; 2414 si_memcpy(&saRoot->outboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); 2415 saRoot->outboundQueue[qIdx].memoryRegion.virtPtr = 2416 (bit8 *)saRoot->outboundQueue[qIdx].memoryRegion.virtPtr + memOffset; 2417 saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; 2418 saRoot->outboundQueue[qIdx].memoryRegion.elementSize = memSize; 2419 saRoot->outboundQueue[qIdx].memoryRegion.totalLength = memSize; 2420 saRoot->outboundQueue[qIdx].memoryRegion.numElements = 1; 2421 saRoot->outboundQueue[qIdx].producerIdx = 0; 2422 saRoot->outboundQueue[qIdx].consumerIdx = 0; 2423 saRoot->outboundQueue[qIdx].agRoot = agRoot; 2424 2425 /* MPI memory region for outbound PIs are 3 */ 2426 saRoot->outboundQueue[qIdx].piPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX + 1].virtPtr))+ qIdx * 4); 2427 /* ... and in the local structure we will use to copy to the HW configuration table */ 2428 outQueueCfg.upperBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrUpper; 2429 outQueueCfg.lowerBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower; 2430 2431 /* PI base address */ 2432 outQueueCfg.piUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrUpper; 2433 outQueueCfg.piLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrLower + qIdx * 4; 2434 outQueueCfg.elementSizeCount = config->outboundQueues[qIdx].numElements | 2435 (config->outboundQueues[qIdx].elementSize << SHIFT16); 2436 2437 /* enable/disable interrupt - use saSystemInterruptsActive() API */ 2438 /* instead of ossaHwRegWrite(agRoot, MSGU_ODMR, 0); */ 2439 /* Outbound Doorbell Auto disable */ 2440 /* LL does not use ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ODAR, 0xffffffff); */ 2441 if (config->outboundQueues[qIdx].interruptEnable) 2442 { 2443 /* enable interrupt flag bit30 of outbound table */ 2444 outQueueCfg.elementSizeCount |= OB_PROPERTY_INT_ENABLE; 2445 } 2446 if(smIS_SPCV(agRoot)) 2447 { 2448 outQueueCfg.interruptVecCntDelay = ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); 2449 } 2450 else 2451 { 2452 outQueueCfg.interruptVecCntDelay = (config->outboundQueues[qIdx].interruptDelay & INT_DELAY_BITS) | 2453 ((config->outboundQueues[qIdx].interruptThreshold & INT_THR_BITS ) << SHIFT16) | 2454 ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); 2455 } 2456 2457 /* create a VectorIndex Bit Map */ 2458 if (qIdx < OQ_NUM_32) 2459 { 2460 saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] |= (1 << qIdx); 2461 SA_DBG2(("mpiInitialize:below 32 saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector])); 2462 } 2463 else 2464 { 2465 saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] |= (1 << (qIdx - OQ_NUM_32)); 2466 SA_DBG2(("mpiInitialize:Above 32 saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector])); 2467 } 2468 /* Update the outbound configuration table */ 2469 mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); 2470 2471 /* read the CI PCIBar offset and convert it to logical bar */ 2472 OB_CIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR)); 2473 saRoot->outboundQueue[qIdx].CIPCIBar = mpiGetPCIBarIndex(agRoot, OB_CIPCIBar); 2474 saRoot->outboundQueue[qIdx].CIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR_OFFSET)); 2475 saRoot->outboundQueue[qIdx].DIntTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_DYNAMIC_COALES_OFFSET)); 2476 saRoot->outboundQueue[qIdx].qNumber = qIdx; 2477 2478 memOffset += memSize; 2479 2480 if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || 2481 (qIdx == (maxoutbound - 1))) 2482 { 2483 mIdx++; 2484 indexoffset += MAX_QUEUE_EACH_MEM; 2485 memOffset =0; 2486 } 2487 } 2488 } 2489 } 2490 2491 /* calculate number of vectors */ 2492 saRoot->numInterruptVectors = 0; 2493 for (qIdx = 0; qIdx < MAX_NUM_VECTOR; qIdx++) 2494 { 2495 if ((saRoot->interruptVecIndexBitMap[qIdx]) || (saRoot->interruptVecIndexBitMap1[qIdx])) 2496 { 2497 (saRoot->numInterruptVectors)++; 2498 } 2499 } 2500 2501 SA_DBG2(("mpiInitialize:(saRoot->numInterruptVectors) 0x%x\n",(saRoot->numInterruptVectors))); 2502 2503 if(smIS_SPCV(agRoot)) 2504 { 2505 /* setup interrupt vector table */ 2506 mpiWrIntVecTable(agRoot,config); 2507 } 2508 2509 if(smIS_SPCV(agRoot)) 2510 { 2511 mpiWrAnalogSetupTable(agRoot,config); 2512 } 2513 2514 /* setup phy analog registers */ 2515 mpiWriteCALAll(agRoot, &config->phyAnalogConfig); 2516 2517 { 2518 bit32 pcibar = 0; 2519 bit32 TableOffset; 2520 pcibar = siGetPciBar(agRoot); 2521 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2522 TableOffset &= SCRATCH_PAD0_OFFSET_MASK; 2523 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); 2524 2525 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); 2526 2527 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE 0x%08X\n", 0)); 2528 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET) & 0xFFFF ))); 2529 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET) & 0xFFFF))); 2530 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET) & 0xFFFF))); 2531 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF ))); 2532 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF))); 2533 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET) & 0xFFFF))); 2534 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES) & 0xFFFF))); 2535 2536 } 2537 2538 if(agNULL != saRoot->swConfig.mpiContextTable ) 2539 { 2540 agsaMPIContext_t * context = (agsaMPIContext_t * )saRoot->swConfig.mpiContextTable; 2541 bit32 length = saRoot->swConfig.mpiContextTablelen; 2542 bit32 pcibar = 0; 2543 bit32 TableOffset; 2544 pcibar = siGetPciBar(agRoot); 2545 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2546 TableOffset &= SCRATCH_PAD0_OFFSET_MASK; 2547 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); 2548 2549 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); 2550 if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) 2551 { 2552 SA_DBG1(("mpiInitialize: TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); 2553 } 2554 2555 if(context ) 2556 { 2557 SA_DBG1(("mpiInitialize: MPITableType 0x%x context->offset 0x%x context->value 0x%x\n",context->MPITableType,context->offset,context->value)); 2558 while( length != 0) 2559 { 2560 switch(context->MPITableType) 2561 { 2562 2563 bit32 OffsetInMain; 2564 case AGSA_MPI_MAIN_CONFIGURATION_TABLE: 2565 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE %d 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset, context->offset, context->value)); 2566 OffsetInMain = TableOffset; 2567 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4) , context->value); 2568 break; 2569 case AGSA_MPI_GENERAL_STATUS_TABLE: 2570 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType ,TableOffset+MAIN_GST_OFFSET, context->offset, context->value )); 2571 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET ) & 0xFFFF) + TableOffset; 2572 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2573 break; 2574 case AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE: 2575 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_IBQ_OFFSET, context->offset, context->value)); 2576 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET ) & 0xFFFF) + TableOffset; 2577 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2578 break; 2579 case AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE: 2580 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_OBQ_OFFSET, context->offset, context->value)); 2581 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET ) & 0xFFFF) + TableOffset; 2582 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2583 break; 2584 case AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE: 2585 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_ANALOG_SETUP_OFFSET, context->offset, context->value)); 2586 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF) + TableOffset; 2587 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2588 break; 2589 case AGSA_MPI_INTERRUPT_VECTOR_TABLE: 2590 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_INT_VEC_TABLE_OFFSET, context->offset, context->value)); 2591 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF) + TableOffset; 2592 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2593 break; 2594 case AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE: 2595 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET, context->offset, context->value)); 2596 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET ) & 0xFFFF) + TableOffset; 2597 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2598 break; 2599 case AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE: 2600 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_MOQFOT_MOQFOES, context->offset, context->value)); 2601 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES ) & 0xFFFF) + TableOffset; 2602 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2603 break; 2604 default: 2605 SA_DBG1(("mpiInitialize: error MPITableType unknown %d offset 0x%x value 0x%x\n",context->MPITableType, context->offset, context->value)); 2606 break; 2607 } 2608 if(smIS_SPC12V(agRoot)) 2609 { 2610 if (saRoot->ControllerInfo.fwInterfaceRev > 0x301 ) 2611 { 2612 SA_DBG1(("mpiInitialize: MAIN_AWT_MIDRANGE 0x%08X\n", 2613 ossaHwRegReadExt(agRoot, pcibar, TableOffset + MAIN_AWT_MIDRANGE) 2614 )); 2615 } 2616 } 2617 if(length >= sizeof(agsaMPIContext_t)) 2618 { 2619 length -= sizeof(agsaMPIContext_t); 2620 context++; 2621 2622 } 2623 else 2624 { 2625 length = 0; 2626 } 2627 } 2628 2629 } 2630 2631 SA_DBG1(("mpiInitialize: context %p saRoot->swConfig.mpiContextTable %p %d\n",context,saRoot->swConfig.mpiContextTable,context == saRoot->swConfig.mpiContextTable ? 1 : 0)); 2632 2633 if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) 2634 { 2635 SA_DBG1(("mpiInitialize:TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); 2636 } 2637 2638 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture After"); 2639 } 2640 /* At this point the Message Unit configuration table is set up. Now we need to ring the doorbell */ 2641 togglevalue = 0; 2642 2643 smTrace(hpDBG_VERY_LOUD,"74", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); 2644 /* TP:74 Doorbell */ 2645 2646 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the table is updated */ 2647 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 2648 2649 if(siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET ) & SPC_MSGU_CFG_TABLE_UPDATE) 2650 { 2651 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE (0x%X) \n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); 2652 } 2653 else 2654 { 2655 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE not set (0x%X)\n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); 2656 ossaStallThread(agRoot, WAIT_INCREMENT); 2657 } 2658 2659 smTrace(hpDBG_VERY_LOUD,"A5", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); 2660 /* TP:A5 Doorbell */ 2661 2662 /* 2663 // ossaHwRegWrite(agRoot, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 2664 MSGU_WRITE_IDR(SPC_MSGU_CFG_TABLE_UPDATE); 2665 */ 2666 2667 2668 /* wait until Inbound DoorBell Clear Register toggled */ 2669 WaitLonger: 2670 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 2671 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 2672 do 2673 { 2674 ossaStallThread(agRoot, WAIT_INCREMENT); 2675 value = MSGU_READ_IDR; 2676 value &= SPC_MSGU_CFG_TABLE_UPDATE; 2677 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 2678 2679 smTrace(hpDBG_VERY_LOUD,"80", max_wait_count); 2680 /* TP:80 TP max_wait_count */ 2681 if (!max_wait_count && mpiStartToggleFailed < 5 ) 2682 { 2683 SA_DBG1(("mpiInitialize: mpiStartToggleFailed count %d\n", mpiStartToggleFailed)); 2684 mpiStartToggleFailed++; 2685 goto WaitLonger; 2686 } 2687 2688 if (!max_wait_count ) 2689 { 2690 2691 SA_DBG1(("mpiInitialize: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 2692 MSGUCfgTblDWIdx = saveOffset; 2693 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 2694 SA_DBG1(("mpiInitialize: MPI State = 0x%x\n", GSTLenMPIS)); 2695 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m3"); 2696 return AGSA_RC_FAILURE; 2697 } 2698 smTrace(hpDBG_VERY_LOUD,"81", mpiStartToggleFailed ); 2699 /* TP:81 TP */ 2700 2701 /* check the MPI-State for initialization */ 2702 MSGUCfgTblDWIdx = saveOffset; 2703 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 2704 if ( (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) && ( mpiUnInitFailed < 5 ) ) 2705 { 2706 SA_DBG1(("mpiInitialize: MPI State = 0x%x mpiUnInitFailed count %d\n", GSTLenMPIS & GST_MPI_STATE_MASK,mpiUnInitFailed)); 2707 ossaStallThread(agRoot, (20 * 1000)); 2708 2709 mpiUnInitFailed++; 2710 goto WaitLonger; 2711 } 2712 2713 if (GST_MPI_STATE_INIT != (GSTLenMPIS & GST_MPI_STATE_MASK)) 2714 { 2715 SA_DBG1(("mpiInitialize: Error Not GST_MPI_STATE_INIT MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); 2716 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m3"); 2717 return AGSA_RC_FAILURE; 2718 } 2719 smTrace(hpDBG_VERY_LOUD,"82", 0); 2720 /* TP:82 TP */ 2721 2722 /* check MPI Initialization error */ 2723 GSTLenMPIS = GSTLenMPIS >> SHIFT16; 2724 if (0x0000 != GSTLenMPIS) 2725 { 2726 SA_DBG1(("mpiInitialize: MPI Error = 0x%x\n", GSTLenMPIS)); 2727 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m3"); 2728 return AGSA_RC_FAILURE; 2729 } 2730 smTrace(hpDBG_VERY_LOUD,"83", 0); 2731 /* TP:83 TP */ 2732 2733 /* reread IQ PI offset from SPC if IQ/OQ > 32 */ 2734 if ((maxinbound > IQ_NUM_32) || (maxoutbound > OQ_NUM_32)) 2735 { 2736 for(qIdx = 0; qIdx < maxinbound; qIdx++) 2737 { 2738 /* point back to the begin then plus offset to next queue */ 2739 MSGUCfgTblDWIdx = saveOffset; 2740 MSGUCfgTblDWIdx += inboundoffset; 2741 MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); 2742 saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); 2743 } 2744 } 2745 smTrace(hpDBG_VERY_LOUD,"84", 0); 2746 /* TP:84 TP */ 2747 2748 /* at least one inbound queue and one outbound queue enabled */ 2749 if ((0 == config->inboundQueues[0].numElements) || (0 == config->outboundQueues[0].numElements)) 2750 { 2751 SA_DBG1(("mpiInitialize: Error,IQ0 or OQ0 have to enable\n")); 2752 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m3"); 2753 return AGSA_RC_FAILURE; 2754 } 2755 smTrace(hpDBG_VERY_LOUD,"85", 0); 2756 /* TP:85 TP */ 2757 2758 /* clean the inbound queues */ 2759 for (i = 0; i < config->numInboundQueues; i ++) 2760 { 2761 if(0 != config->inboundQueues[i].numElements) 2762 { 2763 circularIQ = &saRoot->inboundQueue[i]; 2764 si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); 2765 si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); 2766 2767 if(smIS_SPCV(agRoot)) 2768 { 2769 ossaHwRegWriteExt(circularIQ->agRoot, circularIQ->PIPCIBar, circularIQ->PIPCIOffset, 0); 2770 SA_DBG1(("mpiInitialize: SPC V writes IQ %2d offset 0x%x\n",i ,circularIQ->PIPCIOffset)); 2771 } 2772 } 2773 } 2774 smTrace(hpDBG_VERY_LOUD,"86", 0); 2775 /* TP:86 TP */ 2776 2777 /* clean the outbound queues */ 2778 for (i = 0; i < config->numOutboundQueues; i ++) 2779 { 2780 if(0 != config->outboundQueues[i].numElements) 2781 { 2782 circularOQ = &saRoot->outboundQueue[i]; 2783 si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); 2784 si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); 2785 if(smIS_SPCV(agRoot)) 2786 { 2787 ossaHwRegWriteExt(circularOQ->agRoot, circularOQ->CIPCIBar, circularOQ->CIPCIOffset, 0); 2788 SA_DBG2(("mpiInitialize: SPC V writes OQ %2d offset 0x%x\n",i ,circularOQ->CIPCIOffset)); 2789 } 2790 2791 } 2792 } 2793 2794 2795 smTrace(hpDBG_VERY_LOUD,"75",0); 2796 /* TP:75 AAP1 IOP */ 2797 2798 /* read back AAP1 and IOP event log address and size */ 2799 MSGUCfgTblDWIdx = saveOffset; 2800 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI)); 2801 saRoot->mainConfigTable.upperEventLogAddress = value; 2802 SA_DBG1(("mpiInitialize: upperEventLogAddress 0x%x\n", value)); 2803 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO)); 2804 saRoot->mainConfigTable.lowerEventLogAddress = value; 2805 SA_DBG1(("mpiInitialize: lowerEventLogAddress 0x%x\n", value)); 2806 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE)); 2807 saRoot->mainConfigTable.eventLogSize = value; 2808 SA_DBG1(("mpiInitialize: eventLogSize 0x%x\n", value)); 2809 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION)); 2810 saRoot->mainConfigTable.eventLogOption = value; 2811 SA_DBG1(("mpiInitialize: eventLogOption 0x%x\n", value)); 2812 SA_DBG1(("mpiInitialize: EventLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperEventLogAddress,saRoot->mainConfigTable.lowerEventLogAddress,saRoot->mainConfigTable.eventLogSize/4 )); 2813 2814 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI)); 2815 saRoot->mainConfigTable.upperIOPeventLogAddress = value; 2816 SA_DBG1(("mpiInitialize: upperIOPLogAddress 0x%x\n", value)); 2817 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO)); 2818 saRoot->mainConfigTable.lowerIOPeventLogAddress = value; 2819 SA_DBG1(("mpiInitialize: lowerIOPLogAddress 0x%x\n", value)); 2820 SA_DBG1(("mpiInitialize: IOPLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperIOPeventLogAddress,saRoot->mainConfigTable.lowerIOPeventLogAddress,saRoot->mainConfigTable.IOPeventLogSize/4 )); 2821 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE)); 2822 saRoot->mainConfigTable.IOPeventLogSize = value; 2823 SA_DBG1(("mpiInitialize: IOPeventLogSize 0x%x\n", value)); 2824 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION)); 2825 saRoot->mainConfigTable.IOPeventLogOption = value; 2826 SA_DBG1(("mpiInitialize: IOPeventLogOption 0x%x\n", value)); 2827 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT)); 2828 2829 #ifdef SA_PRINTOUT_IN_WINDBG 2830 #ifndef DBG 2831 DbgPrint("mpiInitialize: EventLog (%d) dd /p %08X`%08X L %x\n", 2832 saRoot->mainConfigTable.eventLogOption, 2833 saRoot->mainConfigTable.upperEventLogAddress, 2834 saRoot->mainConfigTable.lowerEventLogAddress, 2835 saRoot->mainConfigTable.eventLogSize/4 ); 2836 DbgPrint("mpiInitialize: IOPLog (%d) dd /p %08X`%08X L %x\n", 2837 saRoot->mainConfigTable.IOPeventLogOption, 2838 saRoot->mainConfigTable.upperIOPeventLogAddress, 2839 saRoot->mainConfigTable.lowerIOPeventLogAddress, 2840 saRoot->mainConfigTable.IOPeventLogSize/4 ); 2841 #endif /* DBG */ 2842 #endif /* SA_PRINTOUT_IN_WINDBG */ 2843 2844 saRoot->mainConfigTable.FatalErrorInterrupt = value; 2845 smTrace(hpDBG_VERY_LOUD,"76",value); 2846 /* TP:76 FatalErrorInterrupt */ 2847 2848 SA_DBG1(("mpiInitialize: hwConfig->hwOption %X\n", saRoot->hwConfig.hwOption )); 2849 2850 SA_DBG1(("mpiInitialize: FatalErrorInterrupt 0x%x\n", value)); 2851 2852 /* read back Register Dump offset and length */ 2853 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET)); 2854 saRoot->mainConfigTable.FatalErrorDumpOffset0 = value; 2855 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset0 0x%x\n", value)); 2856 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH)); 2857 saRoot->mainConfigTable.FatalErrorDumpLength0 = value; 2858 SA_DBG1(("mpiInitialize: FatalErrorDumpLength0 0x%x\n", value)); 2859 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET)); 2860 saRoot->mainConfigTable.FatalErrorDumpOffset1 = value; 2861 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset1 0x%x\n", value)); 2862 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH)); 2863 saRoot->mainConfigTable.FatalErrorDumpLength1 = value; 2864 SA_DBG1(("mpiInitialize: FatalErrorDumpLength1 0x%x\n", value)); 2865 2866 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD)); 2867 saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = value; 2868 2869 SA_DBG1(("mpiInitialize: PortRecoveryTimerPortResetTimer 0x%x\n", value)); 2870 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED)); 2871 saRoot->mainConfigTable.InterruptReassertionDelay = value; 2872 2873 SA_DBG1(("mpiInitialize: InterruptReassertionDelay 0x%x\n", value)); 2874 2875 2876 if(smIS_SPCV(agRoot)) 2877 { 2878 bit32 sp1; 2879 sp1= ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); 2880 if(SCRATCH_PAD1_V_ERROR_STATE(sp1)) 2881 { 2882 SA_DBG1(("mpiInitialize: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 )); 2883 ret = AGSA_RC_FAILURE; 2884 } 2885 2886 } 2887 2888 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m3"); 2889 return ret; 2890 } 2891 2892 /*******************************************************************************/ 2893 /** \fn mpiWaitForConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) 2894 * \brief Reading and Writing the Configuration Table 2895 * \param agsaRoot Pointer to a data structure containing LL layer context handles 2896 * \param config Pointer to Configuration Table 2897 * 2898 * Return: 2899 * AGSA_RC_SUCCESS if read the configuration table from SPC sucessful 2900 * AGSA_RC_FAILURE if read the configuration table from SPC failed 2901 */ 2902 /*******************************************************************************/ 2903 GLOBAL bit32 mpiWaitForConfigTable(agsaRoot_t *agRoot, 2904 spc_configMainDescriptor_t *config) 2905 { 2906 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2907 bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; 2908 bit32 CfgTblDWIdx; 2909 bit32 value, value1; 2910 bit32 max_wait_time; 2911 bit32 max_wait_count; 2912 bit32 Signature, ExpSignature; 2913 bit8 pcibar; 2914 2915 SA_DBG2(("mpiWaitForConfigTable: Entering\n")); 2916 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 2917 2918 smTraceFuncEnter(hpDBG_VERY_LOUD,"m4"); 2919 2920 2921 /* check error state */ 2922 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 2923 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 2924 2925 if( smIS_SPC(agRoot) ) 2926 { 2927 SA_DBG1(("mpiWaitForConfigTable: Waiting for SPC FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); 2928 2929 /* check AAP error */ 2930 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) 2931 { 2932 /* error state */ 2933 SA_DBG1(("mpiWaitForConfigTable: AAP error state and code 0x%x, ScratchPad2=0x%x\n", value, value1)); 2934 #if defined(SALLSDK_DEBUG) 2935 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2936 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2937 #endif 2938 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m4"); 2939 return AGSA_RC_FAILURE; 2940 } 2941 2942 /* check IOP error */ 2943 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) 2944 { 2945 /* error state */ 2946 SA_DBG1(("mpiWaitForConfigTable: IOP error state and code 0x%x, ScratchPad1=0x%x\n", value1, value)); 2947 #if defined(SALLSDK_DEBUG) 2948 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2949 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2950 #endif 2951 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m4"); 2952 return AGSA_RC_FAILURE; 2953 } 2954 2955 /* bit 4-31 of scratch pad1 should be zeros if it is not in error state */ 2956 #ifdef DONT_DO /* */ 2957 if (value & SCRATCH_PAD1_STATE_MASK) 2958 { 2959 /* error case */ 2960 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad1 0x%x\n", value)); 2961 SA_DBG1(("mpiWaitForConfigTable: ScratchPad0 AAP error code 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2962 #if defined(SALLSDK_DEBUG) 2963 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_0))); 2964 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2965 #endif 2966 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m4"); 2967 return AGSA_RC_FAILURE; 2968 } 2969 2970 /* bit 4-31 of scratch pad2 should be zeros if it is not in error state */ 2971 if (value1 & SCRATCH_PAD2_STATE_MASK) 2972 { 2973 /* error case */ 2974 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad2 0x%x\n", value1)); 2975 SA_DBG1(("mpiWaitForConfigTable: ScratchPad3 IOP error code 0x%x\n",siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3) )); 2976 #if defined(SALLSDK_DEBUG) 2977 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2978 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1))); 2979 #endif 2980 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m4"); 2981 2982 return AGSA_RC_FAILURE; 2983 } 2984 #endif /* DONT_DO */ 2985 2986 /* checking the fw and IOP in ready state */ 2987 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ 2988 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 2989 /* wait until scratch pad 1 and 2 registers in ready state */ 2990 do 2991 { 2992 ossaStallThread(agRoot, WAIT_INCREMENT); 2993 value =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RDY; 2994 value1 =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_RDY; 2995 if(smIS_SPCV(agRoot)) 2996 { 2997 SA_DBG1(("mpiWaitForConfigTable:VEN_DEV_SPCV force SCRATCH_PAD2 RDY 1 %08X 2 %08X\n" ,value,value1)); 2998 value1 =3; 2999 } 3000 3001 if ((max_wait_count -= WAIT_INCREMENT) == 0) 3002 { 3003 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3004 break; 3005 } 3006 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 3007 3008 if (!max_wait_count) 3009 { 3010 SA_DBG1(("mpiWaitForConfigTable: timeout failure\n")); 3011 #if defined(SALLSDK_DEBUG) 3012 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 3013 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 3014 #endif 3015 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m4"); 3016 return AGSA_RC_FAILURE; 3017 } 3018 3019 }else 3020 { 3021 3022 if(((value & SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM)) 3023 { 3024 SA_DBG1(("mpiWaitForConfigTable: HDA mode set in SEEPROM SP1 0x%X\n",value)); 3025 } 3026 if(((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || 3027 (value == 0xffffffff)) 3028 { 3029 SA_DBG1(("mpiWaitForConfigTable: Waiting for _V_ FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); 3030 3031 /* checking the fw and IOP in ready state */ 3032 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ 3033 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3034 /* wait until scratch pad 1 and 2 registers in ready state */ 3035 do 3036 { 3037 ossaStallThread(agRoot, WAIT_INCREMENT); 3038 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 3039 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 3040 3041 if ((max_wait_count -= WAIT_INCREMENT) == 0) 3042 { 3043 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3044 return AGSA_RC_FAILURE; 3045 } 3046 } while (((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || 3047 (value == 0xffffffff)); 3048 } 3049 } 3050 3051 3052 SA_DBG1(("mpiWaitForConfigTable: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3053 3054 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 3055 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3056 /* get offset */ 3057 CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; 3058 /* get PCI BAR */ 3059 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3060 3061 if(smIS_SPC(agRoot)) 3062 { 3063 if( smIS_spc8081(agRoot)) 3064 { 3065 if (BAR4 != MSGUCfgTblBase) 3066 { 3067 SA_DBG1(("mpiWaitForConfigTable: smIS_spc8081 PCI BAR is not BAR4, bar=0x%x - failure\n", MSGUCfgTblBase)); 3068 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m4"); 3069 return AGSA_RC_FAILURE; 3070 } 3071 } 3072 else 3073 { 3074 if (BAR5 != MSGUCfgTblBase) 3075 { 3076 SA_DBG1(("mpiWaitForConfigTable: PCI BAR is not BAR5, bar=0x%x - failure\n", MSGUCfgTblBase)); 3077 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m4"); 3078 return AGSA_RC_FAILURE; 3079 } 3080 } 3081 } 3082 3083 /* convert the PCI BAR to logical bar number */ 3084 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 3085 3086 /* read signature from the configuration table */ 3087 Signature = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx); 3088 3089 /* Error return if the signature is not "PMCS" */ 3090 ExpSignature = ('P') | ('M' << SHIFT8) | ('C' << SHIFT16) | ('S' << SHIFT24); 3091 3092 if (Signature != ExpSignature) 3093 { 3094 SA_DBG1(("mpiWaitForConfigTable: Signature value = 0x%x\n", Signature)); 3095 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m4"); 3096 return AGSA_RC_FAILURE; 3097 } 3098 3099 /* save Signature */ 3100 si_memcpy(&config->Signature, &Signature, sizeof(Signature)); 3101 3102 /* read Interface Revsion from the configuration table */ 3103 config->InterfaceRev = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INTERFACE_REVISION); 3104 3105 /* read FW Revsion from the configuration table */ 3106 config->FWRevision = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FW_REVISION); 3107 3108 /* read Max Outstanding IO from the configuration table */ 3109 config->MaxOutstandingIO = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_OUTSTANDING_IO_OFFSET); 3110 3111 /* read Max SGL and Max Devices from the configuration table */ 3112 config->MDevMaxSGL = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_SGL_OFFSET); 3113 3114 /* read Controller Cap Flags from the configuration table */ 3115 config->ContrlCapFlag = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_CNTRL_CAP_OFFSET); 3116 3117 /* read GST Table Offset from the configuration table */ 3118 config->GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); 3119 3120 /* read Inbound Queue Offset from the configuration table */ 3121 config->inboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_IBQ_OFFSET); 3122 3123 /* read Outbound Queue Offset from the configuration table */ 3124 config->outboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_OBQ_OFFSET); 3125 3126 3127 if(smIS_SPCV(agRoot)) 3128 { 3129 ;/* SPCV - reserved field */ 3130 } 3131 else 3132 { 3133 /* read HDA Flags from the configuration table */ 3134 config->HDAModeFlags = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_HDA_FLAGS_OFFSET); 3135 } 3136 3137 /* read analog Setting offset from the configuration table */ 3138 config->analogSetupTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ANALOG_SETUP_OFFSET); 3139 3140 if(smIS_SPCV(agRoot)) 3141 { 3142 ;/* SPCV - reserved field */ 3143 /* read interrupt vector table offset */ 3144 config->InterruptVecTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INT_VEC_TABLE_OFFSET); 3145 /* read phy attribute table offset */ 3146 config->phyAttributeTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_PHY_ATTRIBUTE_OFFSET); 3147 SA_DBG1(("mpiWaitForConfigTable: INT Vector Tble Offset = 0x%x\n", config->InterruptVecTblOffset)); 3148 SA_DBG1(("mpiWaitForConfigTable: Phy Attribute Tble Offset = 0x%x\n", config->phyAttributeTblOffset)); 3149 } 3150 else 3151 { 3152 ;/* SPC - Not used */ 3153 } 3154 3155 /* read Error Dump Offset and Length */ 3156 config->FatalErrorDumpOffset0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET); 3157 config->FatalErrorDumpLength0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH); 3158 config->FatalErrorDumpOffset1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET); 3159 config->FatalErrorDumpLength1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH); 3160 3161 SA_DBG1(("mpiWaitForConfigTable: Interface Revision value = 0x%08x\n", config->InterfaceRev)); 3162 SA_DBG1(("mpiWaitForConfigTable: FW Revision value = 0x%08x\n", config->FWRevision)); 3163 3164 if(smIS_SPC(agRoot)) 3165 { 3166 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n", STSDK_LL_SPC_VERSION)); 3167 } 3168 if(smIS_SPC6V(agRoot)) 3169 { 3170 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_VERSION )); 3171 } 3172 if(smIS_SPC12V(agRoot)) 3173 { 3174 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_12G_VERSION )); 3175 } 3176 3177 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO value = 0x%08x\n", config->MaxOutstandingIO)); 3178 SA_DBG1(("mpiWaitForConfigTable: MDevMaxSGL value = 0x%08x\n", config->MDevMaxSGL)); 3179 SA_DBG1(("mpiWaitForConfigTable: ContrlCapFlag value = 0x%08x\n", config->ContrlCapFlag)); 3180 SA_DBG1(("mpiWaitForConfigTable: GSTOffset value = 0x%08x\n", config->GSTOffset)); 3181 SA_DBG1(("mpiWaitForConfigTable: inboundQueueOffset value = 0x%08x\n", config->inboundQueueOffset)); 3182 SA_DBG1(("mpiWaitForConfigTable: outboundQueueOffset value = 0x%08x\n", config->outboundQueueOffset)); 3183 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset0 value = 0x%08x\n", config->FatalErrorDumpOffset0)); 3184 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength0 value = 0x%08x\n", config->FatalErrorDumpLength0)); 3185 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset1 value = 0x%08x\n", config->FatalErrorDumpOffset1)); 3186 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength1 value = 0x%08x\n", config->FatalErrorDumpLength1)); 3187 3188 3189 SA_DBG1(("mpiWaitForConfigTable: HDAModeFlags value = 0x%08x\n", config->HDAModeFlags)); 3190 SA_DBG1(("mpiWaitForConfigTable: analogSetupTblOffset value = 0x%08x\n", config->analogSetupTblOffset)); 3191 3192 /* check interface version */ 3193 3194 if(smIS_SPC6V(agRoot)) 3195 { 3196 if (config->InterfaceRev != STSDK_LL_INTERFACE_VERSION) 3197 { 3198 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3199 ret = AGSA_RC_VERSION_UNTESTED; 3200 if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) 3201 { 3202 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3203 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3204 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m4"); 3205 return ret; 3206 } 3207 } 3208 } 3209 else if(smIS_SPC12V(agRoot)) 3210 { 3211 if (config->InterfaceRev != STSDK_LL_12G_INTERFACE_VERSION) 3212 { 3213 SA_DBG1(("mpiWaitForConfigTable: 12g V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); 3214 ret = AGSA_RC_VERSION_UNTESTED; 3215 if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_12G_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) 3216 { 3217 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); 3218 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3219 ret = AGSA_RC_VERSION_UNTESTED; 3220 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m4"); 3221 return ret; 3222 } 3223 } 3224 } 3225 else 3226 { 3227 if (config->InterfaceRev != STSDK_LL_OLD_INTERFACE_VERSION) 3228 { 3229 SA_DBG1(("mpiWaitForConfigTable: SPC sTSDK interface ver. 0x%08x not compatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3230 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3231 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m4"); 3232 return ret; 3233 } 3234 3235 } 3236 3237 3238 /* Check FW versions */ 3239 if(smIS_SPC6V(agRoot)) 3240 { 3241 SA_DBG1(("mpiWaitForConfigTable:6 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_VERSION, config->FWRevision)); 3242 /* check FW and LL sTSDK version */ 3243 if (config->FWRevision != MATCHING_V_FW_VERSION ) 3244 { 3245 if (config->FWRevision > MATCHING_V_FW_VERSION) 3246 { 3247 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); 3248 ret = AGSA_RC_VERSION_UNTESTED; 3249 } 3250 3251 else if (config->FWRevision < MIN_FW_SPCVE_VERSION_SUPPORTED) 3252 { 3253 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); 3254 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3255 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m4"); 3256 return ret; 3257 } 3258 else 3259 { 3260 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_VERSION , config->FWRevision)); 3261 ret = AGSA_RC_VERSION_UNTESTED; 3262 } 3263 } 3264 }else if(smIS_SPC12V(agRoot)) 3265 { 3266 SA_DBG1(("mpiWaitForConfigTable:12 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3267 /* check FW and LL sTSDK version */ 3268 if (config->FWRevision != MATCHING_12G_V_FW_VERSION ) 3269 { 3270 if (config->FWRevision > MATCHING_12G_V_FW_VERSION) 3271 { 3272 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3273 ret = AGSA_RC_VERSION_UNTESTED; 3274 } 3275 3276 else if (config->FWRevision < MIN_FW_12G_SPCVE_VERSION_SUPPORTED) 3277 { 3278 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3279 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3280 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m4"); 3281 return ret; 3282 } 3283 else 3284 { 3285 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_12G_VERSION , config->FWRevision)); 3286 ret = AGSA_RC_VERSION_UNTESTED; 3287 } 3288 } 3289 } 3290 else 3291 { 3292 if (config->FWRevision != MATCHING_SPC_FW_VERSION ) 3293 { 3294 if (config->FWRevision > MATCHING_SPC_FW_VERSION) 3295 { 3296 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); 3297 ret = AGSA_RC_VERSION_UNTESTED; 3298 } 3299 else if (config->FWRevision < MIN_FW_SPC_VERSION_SUPPORTED) 3300 { 3301 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); 3302 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3303 smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m4"); 3304 return ret; 3305 } 3306 else 3307 { 3308 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_SPC_VERSION , config->FWRevision)); 3309 ret = AGSA_RC_VERSION_UNTESTED; 3310 } 3311 } 3312 } 3313 SA_DBG1(("mpiWaitForConfigTable: ILA version 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN) )); 3314 3315 3316 if(smIS_SPC12V(agRoot)) 3317 { 3318 if (config->InterfaceRev > 0x301 ) 3319 { 3320 SA_DBG1(("mpiWaitForConfigTable: MAIN_INACTIVE_ILA_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INACTIVE_ILA_REVSION) )); 3321 SA_DBG1(("mpiWaitForConfigTable: MAIN_SEEPROM_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_SEEPROM_REVSION) )); 3322 } 3323 } 3324 3325 if(smIS_SPC12V(agRoot)) 3326 { 3327 if (config->InterfaceRev > 0x301 ) 3328 { 3329 SA_DBG1(("mpiWaitForConfigTable: MAIN_AWT_MIDRANGE 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_AWT_MIDRANGE) )); 3330 } 3331 } 3332 3333 3334 if(smIS_SFC(agRoot)) 3335 { 3336 /* always success for SFC*/ 3337 ret = AGSA_RC_SUCCESS; 3338 } 3339 3340 if (agNULL != saRoot) 3341 { 3342 /* save the information */ 3343 saRoot->ControllerInfo.signature = Signature; 3344 saRoot->ControllerInfo.fwInterfaceRev = config->InterfaceRev; 3345 3346 if(smIS_SPCV(agRoot)) 3347 { 3348 saRoot->ControllerInfo.hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); 3349 SA_DBG1(("mpiWaitForConfigTable: hwRevision 0x%x\n",saRoot->ControllerInfo.hwRevision )); 3350 } 3351 else 3352 { 3353 saRoot->ControllerInfo.hwRevision = SPC_READ_DEV_REV; 3354 } 3355 3356 saRoot->ControllerInfo.fwRevision = config->FWRevision; 3357 saRoot->ControllerInfo.ilaRevision = config->ilaRevision; 3358 saRoot->ControllerInfo.maxPendingIO = config->MaxOutstandingIO; 3359 saRoot->ControllerInfo.maxSgElements = config->MDevMaxSGL & 0xFFFF; 3360 saRoot->ControllerInfo.maxDevices = (config->MDevMaxSGL & MAX_DEV_BITS) >> SHIFT16; 3361 saRoot->ControllerInfo.queueSupport = config->ContrlCapFlag & Q_SUPPORT_BITS; 3362 saRoot->ControllerInfo.phyCount = (bit8)((config->ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); 3363 saRoot->ControllerInfo.sasSpecsSupport = (config->ContrlCapFlag & SAS_SPEC_BITS) >> SHIFT25; 3364 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", config->MaxOutstandingIO,saRoot->swConfig.maxActiveIOs )); 3365 3366 if(smIS_SPCV(agRoot)) 3367 { 3368 ;/* SPCV - reserved field */ 3369 } 3370 else 3371 { 3372 saRoot->ControllerInfo.controllerSetting = (bit8)config->HDAModeFlags; 3373 } 3374 3375 saRoot->ControllerInfo.sdkInterfaceRev = STSDK_LL_INTERFACE_VERSION; 3376 saRoot->ControllerInfo.sdkRevision = STSDK_LL_VERSION; 3377 saRoot->mainConfigTable.regDumpPCIBAR = pcibar; 3378 saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; 3379 saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; 3380 saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; 3381 saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; 3382 3383 if(smIS_SPCV(agRoot)) 3384 { 3385 ;/* SPCV - reserved field */ 3386 } 3387 else 3388 { 3389 saRoot->mainConfigTable.HDAModeFlags = config->HDAModeFlags; 3390 } 3391 3392 saRoot->mainConfigTable.analogSetupTblOffset = config->analogSetupTblOffset; 3393 3394 if(smIS_SPCV(agRoot)) 3395 { 3396 saRoot->mainConfigTable.InterruptVecTblOffset = config->InterruptVecTblOffset; 3397 saRoot->mainConfigTable.phyAttributeTblOffset = config->phyAttributeTblOffset; 3398 saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = config->portRecoveryResetTimer; 3399 } 3400 3401 SA_DBG1(("mpiWaitForConfigTable: Signature = 0x%x\n", Signature)); 3402 SA_DBG1(("mpiWaitForConfigTable: hwRevision = 0x%x\n", saRoot->ControllerInfo.hwRevision)); 3403 SA_DBG1(("mpiWaitForConfigTable: FW Revision = 0x%x\n", config->FWRevision)); 3404 SA_DBG1(("mpiWaitForConfigTable: Max Sgl = 0x%x\n", saRoot->ControllerInfo.maxSgElements)); 3405 SA_DBG1(("mpiWaitForConfigTable: Max Device = 0x%x\n", saRoot->ControllerInfo.maxDevices)); 3406 SA_DBG1(("mpiWaitForConfigTable: Queue Support = 0x%x\n", saRoot->ControllerInfo.queueSupport)); 3407 SA_DBG1(("mpiWaitForConfigTable: Phy Count = 0x%x\n", saRoot->ControllerInfo.phyCount)); 3408 SA_DBG1(("mpiWaitForConfigTable: sas Specs Support = 0x%x\n", saRoot->ControllerInfo.sasSpecsSupport)); 3409 3410 } 3411 3412 3413 if(ret != AGSA_RC_SUCCESS ) 3414 { 3415 SA_DBG1(("mpiWaitForConfigTable: return 0x%x not AGSA_RC_SUCCESS warning!\n", ret)); 3416 } 3417 3418 3419 smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m4"); 3420 return ret; 3421 } 3422 3423 /*******************************************************************************/ 3424 /** \fn mpiUnInitConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) 3425 * \brief UnInitialization Configuration Table 3426 * \param agsaRoot Pointer to a data structure containing LL layer context handles 3427 * 3428 * Return: 3429 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 3430 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 3431 */ 3432 /*******************************************************************************/ 3433 GLOBAL bit32 mpiUnInitConfigTable(agsaRoot_t *agRoot) 3434 { 3435 bit32 MSGUCfgTblBase; 3436 bit32 CfgTblDWIdx, GSTOffset, GSTLenMPIS; 3437 bit32 value, togglevalue; 3438 bit32 max_wait_time; 3439 bit32 max_wait_count; 3440 bit8 pcibar; 3441 3442 smTraceFuncEnter(hpDBG_VERY_LOUD,"m7"); 3443 SA_DBG1(("mpiUnInitConfigTable: agRoot %p\n",agRoot)); 3444 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 3445 3446 togglevalue = 0; 3447 3448 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 3449 MSGUCfgTblBase =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3450 3451 if(MSGUCfgTblBase == 0xFFFFFFFF) 3452 { 3453 SA_DBG1(("mpiUnInitConfigTable: MSGUCfgTblBase = 0x%x AGSA_RC_FAILURE\n",MSGUCfgTblBase)); 3454 return AGSA_RC_FAILURE; 3455 } 3456 3457 /* get offset */ 3458 CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; 3459 /* get PCI BAR */ 3460 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3461 3462 /* convert the PCI BAR to logical bar number */ 3463 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 3464 3465 /* Write bit 1 to Inbound DoorBell Register */ 3466 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 3467 3468 /* wait until Inbound DoorBell Clear Register toggled */ 3469 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 3470 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3471 do 3472 { 3473 ossaStallThread(agRoot, WAIT_INCREMENT); 3474 value = MSGU_READ_IDR; 3475 value &= SPC_MSGU_CFG_TABLE_RESET; 3476 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 3477 3478 if (!max_wait_count) 3479 { 3480 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 3481 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m7"); 3482 3483 if(smIS_SPC(agRoot) ) 3484 { 3485 return AGSA_RC_FAILURE; 3486 } 3487 3488 } 3489 3490 /* check the MPI-State for termination in progress */ 3491 /* wait until Inbound DoorBell Clear Register toggled */ 3492 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 3493 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3494 GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); 3495 do 3496 { 3497 ossaStallThread(agRoot, WAIT_INCREMENT); 3498 3499 if(GSTOffset == 0xFFFFFFFF) 3500 { 3501 SA_DBG1(("mpiUnInitConfigTable:AGSA_RC_FAILURE GSTOffset = 0x%x\n",GSTOffset)); 3502 return AGSA_RC_FAILURE; 3503 } 3504 3505 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + (bit32)(GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 3506 if (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) 3507 { 3508 break; 3509 } 3510 } while (max_wait_count -= WAIT_INCREMENT); 3511 3512 if (!max_wait_count) 3513 { 3514 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT, MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); 3515 #if defined(SALLSDK_DEBUG) 3516 3517 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); 3518 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 3519 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); 3520 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 3521 #endif 3522 3523 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m7"); 3524 return AGSA_RC_FAILURE; 3525 } 3526 3527 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m7"); 3528 return AGSA_RC_SUCCESS; 3529 } 3530 3531 /*******************************************************************************/ 3532 /** \fn void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, spc_inboundQueueDescriptor_t *outQueueCfg, 3533 * bit32 QueueTableOffset,bit8 pcibar) 3534 * \brief Writing to the inbound queue of the Configuration Table 3535 * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles 3536 * \param outQueueCfg Pointer to inbuond configuration area 3537 * \param QueueTableOffset Queue configuration table offset 3538 * \param pcibar PCI BAR 3539 * 3540 * Return: 3541 * None 3542 */ 3543 /*******************************************************************************/ 3544 GLOBAL void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, 3545 spc_inboundQueueDescriptor_t *inQueueCfg, 3546 bit32 QueueTableOffset, 3547 bit8 pcibar) 3548 { 3549 smTraceFuncEnter(hpDBG_VERY_LOUD,"m5"); 3550 3551 smTrace(hpDBG_VERY_LOUD,"Ba",QueueTableOffset); 3552 /* TP:Ba QueueTableOffset */ 3553 smTrace(hpDBG_VERY_LOUD,"Bb",pcibar); 3554 /* TP:Bb pcibar */ 3555 3556 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount); 3557 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress); 3558 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress); 3559 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress); 3560 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress); 3561 3562 3563 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x elementPriSizeCount 0x%x\n",(bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount)); 3564 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress)); 3565 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress)); 3566 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress)); 3567 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress)); 3568 3569 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m5"); 3570 } 3571 3572 /*******************************************************************************/ 3573 /** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, 3574 * bit32 QueueTableOffset,bit8 pcibar) 3575 * \brief Writing to the inbound queue of the Configuration Table 3576 * \param agsaRoot Pointer to a data structure containing both application 3577 * and LL layer context handles 3578 * \param outQueueCfg Pointer to outbuond configuration area 3579 * \param QueueTableOffset Queue configuration table offset 3580 * \param pcibar PCI BAR 3581 * 3582 * Return: 3583 * None 3584 */ 3585 /*******************************************************************************/ 3586 GLOBAL void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, 3587 spc_outboundQueueDescriptor_t *outQueueCfg, 3588 bit32 QueueTableOffset, 3589 bit8 pcibar) 3590 { 3591 3592 smTraceFuncEnter(hpDBG_VERY_LOUD,"m8"); 3593 3594 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount); 3595 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress); 3596 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress); 3597 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress); 3598 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress); 3599 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay); 3600 3601 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x elementSizeCount 0x%x\n",(bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount)); 3602 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress)); 3603 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress)); 3604 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress)); 3605 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress)); 3606 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x interruptVecCntDelay 0x%x\n",(bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay)); 3607 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m8"); 3608 } 3609 3610 3611 3612 /*******************************************************************************/ 3613 /** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, 3614 * bit32 QueueTableOffset,bit8 pcibar) 3615 * \brief Writing to the inbound queue of the Configuration Table 3616 * \param agsaRoot Pointer to a data structure containing both application 3617 * and LL layer context handles 3618 * \param outQueueCfg Pointer to outbuond configuration area 3619 * \param QueueTableOffset Queue configuration table offset 3620 * \param pcibar PCI BAR 3621 * 3622 * Return: 3623 * None 3624 */ 3625 /*******************************************************************************/ 3626 GLOBAL void mpiUpdateFatalErrorTable(agsaRoot_t *agRoot, 3627 bit32 FerrTableOffset, 3628 bit32 lowerBaseAddress, 3629 bit32 upperBaseAddress, 3630 bit32 length, 3631 bit8 pcibar) 3632 { 3633 3634 smTraceFuncEnter(hpDBG_VERY_LOUD,"2U"); 3635 3636 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET), lowerBaseAddress); 3637 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET), upperBaseAddress); 3638 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH), length); 3639 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE), 0); 3640 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS), 0); 3641 3642 3643 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET, lowerBaseAddress)); 3644 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET,upperBaseAddress )); 3645 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LENGTH 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH, length)); 3646 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE,0 )); 3647 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_STATUS 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS,0 )); 3648 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2U"); 3649 } 3650 3651 3652 /*******************************************************************************/ 3653 /** \fn bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, pciBar) 3654 * \brief Get PCI BAR Index from PCI BAR 3655 * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles 3656 * \param pciBar - PCI BAR 3657 * 3658 * Return: 3659 * PCI BAR Index 3660 */ 3661 /*******************************************************************************/ 3662 GLOBAL bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, bit32 pciBar) 3663 { 3664 switch(pciBar) 3665 { 3666 case BAR0: 3667 case BAR1: 3668 pciBar = PCIBAR0; 3669 break; 3670 case BAR2: 3671 case BAR3: 3672 pciBar = PCIBAR1; 3673 break; 3674 case BAR4: 3675 pciBar = PCIBAR2; 3676 break; 3677 case BAR5: 3678 pciBar = PCIBAR3; 3679 break; 3680 default: 3681 pciBar = PCIBAR0; 3682 break; 3683 } 3684 3685 return pciBar; 3686 } 3687 3688 /*******************************************************************************/ 3689 /** \fn void mpiReadGSTTable(agsaRoot_t *agRoot, spc_GSTableDescriptor_t *mpiGSTable) 3690 * \brief Reading the General Status Table 3691 * 3692 * \param agsaRoot Handles for this instance of SAS/SATA LLL 3693 * \param mpiGSTable Pointer of General Status Table 3694 * 3695 * Return: 3696 * None 3697 */ 3698 /*******************************************************************************/ 3699 GLOBAL void mpiReadGSTable(agsaRoot_t *agRoot, 3700 spc_GSTableDescriptor_t *mpiGSTable) 3701 { 3702 bit32 CFGTableOffset, TableOffset; 3703 bit32 GSTableOffset; 3704 bit8 i, pcibar; 3705 3706 smTraceFuncEnter(hpDBG_VERY_LOUD,"m9"); 3707 3708 /* get offset of the configuration table */ 3709 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3710 3711 if(0xFFFFFFFF == TableOffset) 3712 { 3713 SA_ASSERT(0xFFFFFFFF == TableOffset, "Chip PCI dead"); 3714 3715 SA_DBG1(("mpiReadGSTable: Chip PCI dead TableOffset 0x%x\n", TableOffset)); 3716 return; 3717 } 3718 3719 // SA_DBG1(("mpiReadGSTable: TableOffset 0x%x\n", TableOffset)); 3720 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 3721 3722 /* get PCI BAR */ 3723 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3724 /* convert the PCI BAR to logical bar number */ 3725 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 3726 3727 /* read GST Table Offset from the configuration table */ 3728 GSTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_GST_OFFSET); 3729 // SA_DBG1(("mpiReadGSTable: GSTableOffset 0x%x\n",GSTableOffset )); 3730 3731 GSTableOffset = CFGTableOffset + GSTableOffset; 3732 3733 mpiGSTable->GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GSTLEN_MPIS_OFFSET)); 3734 mpiGSTable->IQFreezeState0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE0_OFFSET)); 3735 mpiGSTable->IQFreezeState1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE1_OFFSET)); 3736 mpiGSTable->MsguTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_MSGUTCNT_OFFSET)); 3737 mpiGSTable->IopTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOPTCNT_OFFSET)); 3738 mpiGSTable->Iop1Tcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOP1TCNT_OFFSET)); 3739 3740 SA_DBG4(("mpiReadGSTable: GSTLenMPIS 0x%x\n", mpiGSTable->GSTLenMPIS)); 3741 SA_DBG4(("mpiReadGSTable: GSTLen 0x%x\n", (mpiGSTable->GSTLenMPIS & 0xfff8) >> SHIFT3)); 3742 SA_DBG4(("mpiReadGSTable: IQFreezeState0 0x%x\n", mpiGSTable->IQFreezeState0)); 3743 SA_DBG4(("mpiReadGSTable: IQFreezeState1 0x%x\n", mpiGSTable->IQFreezeState1)); 3744 SA_DBG4(("mpiReadGSTable: MsguTcnt 0x%x\n", mpiGSTable->MsguTcnt)); 3745 SA_DBG4(("mpiReadGSTable: IopTcnt 0x%x\n", mpiGSTable->IopTcnt)); 3746 SA_DBG4(("mpiReadGSTable: Iop1Tcnt 0x%x\n", mpiGSTable->Iop1Tcnt)); 3747 3748 3749 if(smIS_SPCV(agRoot)) 3750 { 3751 /***** read Phy State from SAS Phy Attribute Table */ 3752 TableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); 3753 TableOffset &= 0x00FFFFFF; 3754 TableOffset = TableOffset + CFGTableOffset; 3755 for (i = 0; i < 8; i++) 3756 { 3757 mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(TableOffset + i * sizeof(phyAttrb_t))); 3758 SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); 3759 } 3760 } 3761 else 3762 { 3763 for (i = 0; i < 8; i++) 3764 { 3765 mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_PHYSTATE_OFFSET + i * 4)); 3766 SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); 3767 } 3768 } 3769 3770 mpiGSTable->GPIOpins = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GPIO_PINS_OFFSET)); 3771 SA_DBG4(("mpiReadGSTable: GPIOpins 0x%x\n", mpiGSTable->GPIOpins)); 3772 3773 for (i = 0; i < 8; i++) 3774 { 3775 mpiGSTable->recoverErrInfo[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_RERRINFO_OFFSET)); 3776 SA_DBG4(("mpiReadGSTable: recoverErrInfo[0x%x] 0x%x\n", i, mpiGSTable->recoverErrInfo[i])); 3777 } 3778 3779 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m9"); 3780 3781 } 3782 3783 /*******************************************************************************/ 3784 /** \fn void siInitResources(agsaRoot_t *agRoot) 3785 * Initialization of LL resources 3786 * 3787 * \param agsaRoot Handles for this instance of SAS/SATA LLL 3788 * \param memoryAllocated Point to the data structure that holds the different 3789 * chunks of memory that are required 3790 * 3791 * Return: 3792 * None 3793 */ 3794 /*******************************************************************************/ 3795 GLOBAL void siInitResources(agsaRoot_t *agRoot, 3796 agsaMemoryRequirement_t *memoryAllocated, 3797 agsaHwConfig_t *hwConfig, 3798 agsaSwConfig_t *swConfig, 3799 bit32 usecsPerTick) 3800 { 3801 agsaLLRoot_t *saRoot; 3802 agsaDeviceDesc_t *pDeviceDesc; 3803 agsaIORequestDesc_t *pRequestDesc; 3804 agsaTimerDesc_t *pTimerDesc; 3805 agsaPort_t *pPort; 3806 agsaPortMap_t *pPortMap; 3807 agsaDeviceMap_t *pDeviceMap; 3808 agsaIOMap_t *pIOMap; 3809 bit32 maxNumIODevices; 3810 bit32 i, j; 3811 mpiICQueue_t *circularIQ; 3812 mpiOCQueue_t *circularOQ; 3813 3814 if (agNULL == agRoot) 3815 { 3816 return; 3817 } 3818 3819 /* Get the saRoot memory address */ 3820 saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); 3821 agRoot->sdkData = (void *) saRoot; 3822 3823 /* Setup Device link */ 3824 /* Save the information of allocated device Link memory */ 3825 saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; 3826 si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); 3827 SA_DBG2(("siInitResources: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n" , 3828 DEVICELINK_MEM_INDEX, 3829 saRoot->deviceLinkMem.virtPtr, 3830 saRoot->deviceLinkMem.phyAddrLower, 3831 saRoot->deviceLinkMem.numElements, 3832 saRoot->deviceLinkMem.totalLength, 3833 saRoot->deviceLinkMem.type)); 3834 3835 maxNumIODevices = swConfig->numDevHandles; 3836 SA_DBG2(("siInitResources: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", 3837 maxNumIODevices, 3838 swConfig->numDevHandles)); 3839 3840 /* Setup free IO Devices link list */ 3841 saLlistInitialize(&(saRoot->freeDevicesList)); 3842 for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) 3843 { 3844 /* get the pointer to the device descriptor */ 3845 pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); 3846 /* Initialize device descriptor */ 3847 saLlinkInitialize(&(pDeviceDesc->linkNode)); 3848 3849 pDeviceDesc->initiatorDevHandle.osData = agNULL; 3850 pDeviceDesc->initiatorDevHandle.sdkData = agNULL; 3851 pDeviceDesc->targetDevHandle.osData = agNULL; 3852 pDeviceDesc->targetDevHandle.sdkData = agNULL; 3853 pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; 3854 pDeviceDesc->pPort = agNULL; 3855 pDeviceDesc->DeviceMapIndex = 0; 3856 3857 saLlistInitialize(&(pDeviceDesc->pendingIORequests)); 3858 3859 /* Add the device descriptor to the free IO device link list */ 3860 saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); 3861 } 3862 3863 /* Setup IO Request link */ 3864 /* Save the information of allocated IO Request Link memory */ 3865 saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; 3866 si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); 3867 3868 SA_DBG2(("siInitResources: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 3869 IOREQLINK_MEM_INDEX, 3870 saRoot->IORequestMem.virtPtr, 3871 saRoot->IORequestMem.phyAddrLower, 3872 saRoot->IORequestMem.numElements, 3873 saRoot->IORequestMem.totalLength, 3874 saRoot->IORequestMem.type)); 3875 3876 /* Setup free IO Request link list */ 3877 saLlistIOInitialize(&(saRoot->freeIORequests)); 3878 saLlistIOInitialize(&(saRoot->freeReservedRequests)); 3879 for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) 3880 { 3881 /* get the pointer to the request descriptor */ 3882 pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); 3883 /* Initialize request descriptor */ 3884 saLlinkIOInitialize(&(pRequestDesc->linkNode)); 3885 3886 pRequestDesc->valid = agFALSE; 3887 pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; 3888 pRequestDesc->pIORequestContext = agNULL; 3889 pRequestDesc->HTag = i; 3890 pRequestDesc->pDevice = agNULL; 3891 pRequestDesc->pPort = agNULL; 3892 3893 /* Add the request descriptor to the free IO Request link list */ 3894 /* Add the request descriptor to the free Reserved Request link list */ 3895 /* SMP request must get service so reserve one request when first SMP completes */ 3896 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 3897 { 3898 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); 3899 } 3900 else 3901 { 3902 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); 3903 } 3904 } 3905 3906 3907 /* Setup timer link */ 3908 /* Save the information of allocated timer Link memory */ 3909 saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; 3910 si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); 3911 SA_DBG2(("siInitResources: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 3912 TIMERLINK_MEM_INDEX, 3913 saRoot->timerLinkMem.virtPtr, 3914 saRoot->timerLinkMem.phyAddrLower, 3915 saRoot->timerLinkMem.numElements, 3916 saRoot->timerLinkMem.totalLength, 3917 saRoot->timerLinkMem.type)); 3918 3919 /* Setup free timer link list */ 3920 saLlistInitialize(&(saRoot->freeTimers)); 3921 for ( i = 0; i < NUM_TIMERS; i ++ ) 3922 { 3923 /* get the pointer to the timer descriptor */ 3924 pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); 3925 /* Initialize timer descriptor */ 3926 saLlinkInitialize(&(pTimerDesc->linkNode)); 3927 3928 pTimerDesc->valid = agFALSE; 3929 pTimerDesc->timeoutTick = 0; 3930 pTimerDesc->pfnTimeout = agNULL; 3931 pTimerDesc->Event = 0; 3932 pTimerDesc->pParm = agNULL; 3933 3934 /* Add the timer descriptor to the free timer link list */ 3935 saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); 3936 } 3937 /* Setup valid timer link list */ 3938 saLlistInitialize(&(saRoot->validTimers)); 3939 3940 /* Setup Phys */ 3941 /* Setup PhyCount */ 3942 saRoot->phyCount = (bit8) hwConfig->phyCount; 3943 /* Init Phy data structure */ 3944 for ( i = 0; i < saRoot->phyCount; i ++ ) 3945 { 3946 saRoot->phys[i].pPort = agNULL; 3947 saRoot->phys[i].phyId = (bit8) i; 3948 3949 /* setup phy status is PHY_STOPPED */ 3950 PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); 3951 } 3952 3953 /* Setup Ports */ 3954 /* Setup PortCount */ 3955 saRoot->portCount = saRoot->phyCount; 3956 /* Setup free port link list */ 3957 saLlistInitialize(&(saRoot->freePorts)); 3958 for ( i = 0; i < saRoot->portCount; i ++ ) 3959 { 3960 /* get the pointer to the port */ 3961 pPort = &(saRoot->ports[i]); 3962 /* Initialize port */ 3963 saLlinkInitialize(&(pPort->linkNode)); 3964 3965 pPort->portContext.osData = agNULL; 3966 pPort->portContext.sdkData = pPort; 3967 pPort->portId = 0; 3968 pPort->portIdx = (bit8) i; 3969 pPort->status = PORT_NORMAL; 3970 3971 for ( j = 0; j < saRoot->phyCount; j ++ ) 3972 { 3973 pPort->phyMap[j] = agFALSE; 3974 } 3975 3976 saLlistInitialize(&(pPort->listSASATADevices)); 3977 3978 /* Add the port to the free port link list */ 3979 saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); 3980 } 3981 /* Setup valid port link list */ 3982 saLlistInitialize(&(saRoot->validPorts)); 3983 3984 /* Init sysIntsActive */ 3985 saRoot->sysIntsActive = agFALSE; 3986 3987 /* setup timer tick granunarity */ 3988 saRoot->usecsPerTick = usecsPerTick; 3989 3990 /* initialize LL timer tick */ 3991 saRoot->timeTick = 0; 3992 3993 /* initialize device (de)registration callback fns */ 3994 saRoot->DeviceRegistrationCB = agNULL; 3995 saRoot->DeviceDeregistrationCB = agNULL; 3996 3997 /* Initialize the PortMap for port context */ 3998 for ( i = 0; i < saRoot->portCount; i ++ ) 3999 { 4000 pPortMap = &(saRoot->PortMap[i]); 4001 4002 pPortMap->PortContext = agNULL; 4003 pPortMap->PortID = PORT_MARK_OFF; 4004 pPortMap->PortStatus = PORT_NORMAL; 4005 saRoot->autoDeregDeviceflag[i] = 0; 4006 } 4007 4008 /* Initialize the DeviceMap for device handle */ 4009 for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) 4010 { 4011 pDeviceMap = &(saRoot->DeviceMap[i]); 4012 4013 pDeviceMap->DeviceHandle = agNULL; 4014 pDeviceMap->DeviceIdFromFW = i; 4015 } 4016 4017 /* Initialize the IOMap for IOrequest */ 4018 for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) 4019 { 4020 pIOMap = &(saRoot->IOMap[i]); 4021 4022 pIOMap->IORequest = agNULL; 4023 pIOMap->Tag = MARK_OFF; 4024 } 4025 4026 /* clean the inbound queues */ 4027 for (i = 0; i < saRoot->QueueConfig.numInboundQueues; i ++) 4028 { 4029 if(0 != saRoot->inboundQueue[i].numElements) 4030 { 4031 circularIQ = &saRoot->inboundQueue[i]; 4032 si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); 4033 si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); 4034 } 4035 } 4036 /* clean the outbound queues */ 4037 for (i = 0; i < saRoot->QueueConfig.numOutboundQueues; i ++) 4038 { 4039 if(0 != saRoot->outboundQueue[i].numElements) 4040 { 4041 circularOQ = &saRoot->outboundQueue[i]; 4042 si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); 4043 si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); 4044 circularOQ->producerIdx = 0; 4045 circularOQ->consumerIdx = 0; 4046 SA_DBG3(("siInitResource: Q %d Clean PI 0x%03x CI 0x%03x\n", i,circularOQ->producerIdx, circularOQ->consumerIdx)); 4047 } 4048 } 4049 4050 return; 4051 } 4052 4053 /*******************************************************************************/ 4054 /** \fn void mpiReadCALTable(agsaRoot_t *agRoot, 4055 * spc_SPASTable_t *mpiCALTable, bit32 index) 4056 * \brief Reading the Phy Analog Setup Register Table 4057 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4058 * \param mpiCALTable Pointer of Phy Calibration Table 4059 * 4060 * Return: 4061 * None 4062 */ 4063 /*******************************************************************************/ 4064 GLOBAL void mpiReadCALTable(agsaRoot_t *agRoot, 4065 spc_SPASTable_t *mpiCALTable, 4066 bit32 index) 4067 { 4068 bit32 CFGTableOffset, TableOffset; 4069 bit32 CALTableOffset; 4070 bit8 pcibar; 4071 4072 /* get offset of the configuration table */ 4073 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4074 4075 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 4076 4077 /* get PCI BAR */ 4078 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4079 /* convert the PCI BAR to logical bar number */ 4080 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 4081 4082 /* read Calibration Table Offset from the configuration table */ 4083 CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4084 if(smIS_SPCV(agRoot)) 4085 { 4086 CALTableOffset &= 0x00FFFFFF; 4087 } 4088 CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); 4089 4090 mpiCALTable->spaReg0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET)); 4091 mpiCALTable->spaReg1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET)); 4092 mpiCALTable->spaReg2 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET)); 4093 mpiCALTable->spaReg3 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET)); 4094 mpiCALTable->spaReg4 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET)); 4095 mpiCALTable->spaReg5 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET)); 4096 mpiCALTable->spaReg6 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET)); 4097 mpiCALTable->spaReg7 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET)); 4098 4099 SA_DBG3(("mpiReadCALTable: spaReg0 0x%x\n", mpiCALTable->spaReg0)); 4100 SA_DBG3(("mpiReadCALTable: spaReg1 0x%x\n", mpiCALTable->spaReg1)); 4101 SA_DBG3(("mpiReadCALTable: spaReg2 0x%x\n", mpiCALTable->spaReg2)); 4102 SA_DBG3(("mpiReadCALTable: spaReg3 0x%x\n", mpiCALTable->spaReg3)); 4103 SA_DBG3(("mpiReadCALTable: spaReg4 0x%x\n", mpiCALTable->spaReg4)); 4104 SA_DBG3(("mpiReadCALTable: spaReg5 0x%x\n", mpiCALTable->spaReg5)); 4105 SA_DBG3(("mpiReadCALTable: spaReg6 0x%x\n", mpiCALTable->spaReg6)); 4106 SA_DBG3(("mpiReadCALTable: spaReg7 0x%x\n", mpiCALTable->spaReg7)); 4107 } 4108 4109 /*******************************************************************************/ 4110 /** \fn void mpiWriteCALTable(agsaRoot_t *agRoot, 4111 * spc_SPASTable_t *mpiCALTable, index) 4112 * \brief Writing the Phy Analog Setup Register Table 4113 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4114 * \param mpiCALTable Pointer of Phy Calibration Table 4115 * 4116 * Return: 4117 * None 4118 */ 4119 /*******************************************************************************/ 4120 GLOBAL void mpiWriteCALTable(agsaRoot_t *agRoot, 4121 spc_SPASTable_t *mpiCALTable, 4122 bit32 index) 4123 { 4124 bit32 CFGTableOffset, TableOffset; 4125 bit32 CALTableOffset; 4126 bit8 pcibar; 4127 4128 smTraceFuncEnter(hpDBG_VERY_LOUD,"m6"); 4129 4130 /* get offset of the configuration table */ 4131 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4132 4133 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 4134 4135 /* get PCI BAR */ 4136 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4137 /* convert the PCI BAR to logical bar number */ 4138 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 4139 4140 /* read Calibration Table Offset from the configuration table */ 4141 CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4142 if(smIS_SPCV(agRoot)) 4143 { 4144 CALTableOffset &= 0x00FFFFFF; 4145 } 4146 CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); 4147 4148 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0); 4149 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET), mpiCALTable->spaReg1); 4150 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET), mpiCALTable->spaReg2); 4151 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET), mpiCALTable->spaReg3); 4152 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4); 4153 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET), mpiCALTable->spaReg5); 4154 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET), mpiCALTable->spaReg6); 4155 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET), mpiCALTable->spaReg7); 4156 4157 SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg0 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0, mpiCALTable->spaReg1, mpiCALTable->spaReg2, mpiCALTable->spaReg3)); 4158 SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg4 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4, mpiCALTable->spaReg5, mpiCALTable->spaReg6, mpiCALTable->spaReg7)); 4159 4160 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m6"); 4161 } 4162 4163 /*******************************************************************************/ 4164 /** \fn void mpiWriteCALAll(agsaRoot_t *agRoot, 4165 * agsaPhyAnalogSetupTable_t *mpiCALTable) 4166 * \brief Writing the Phy Analog Setup Register Table 4167 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4168 * \param mpiCALTable Pointer of Phy Calibration Table 4169 * 4170 * Return: 4171 * None 4172 */ 4173 /*******************************************************************************/ 4174 GLOBAL void mpiWriteCALAll(agsaRoot_t *agRoot, 4175 agsaPhyAnalogSetupTable_t *mpiCALTable) 4176 { 4177 bit8 i; 4178 smTraceFuncEnter(hpDBG_VERY_LOUD,"mz"); 4179 4180 if(smIS_SPCV(agRoot)) 4181 { 4182 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mz"); 4183 return; 4184 } 4185 4186 for (i = 0; i < MAX_INDEX; i++) 4187 { 4188 mpiWriteCALTable(agRoot, (spc_SPASTable_t *)&mpiCALTable->phyAnalogSetupRegisters[i], i); 4189 } 4190 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "mz"); 4191 } 4192 4193 GLOBAL void mpiWrAnalogSetupTable(agsaRoot_t *agRoot, 4194 mpiConfig_t *config 4195 ) 4196 { 4197 4198 bit32 AnalogTableBase,CFGTableOffset, value,phy; 4199 bit32 AnalogtableSize; 4200 bit8 pcibar; 4201 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4202 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4203 4204 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4205 AnalogtableSize = AnalogTableBase = ossaHwRegReadExt(agRoot,pcibar , (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4206 AnalogtableSize &= 0xFF000000; 4207 AnalogtableSize >>= SHIFT24; 4208 AnalogTableBase &= 0x00FFFFFF; 4209 4210 AnalogTableBase = CFGTableOffset + AnalogTableBase; 4211 4212 // config->phyAnalogConfig.phyAnalogSetupRegisters[0].spaRegister0 = 0; 4213 SA_DBG1(("mpiWrAnalogSetupTable:Analogtable Base Offset %08X pcibar %d\n",AnalogTableBase, pcibar )); 4214 4215 SA_DBG1(("mpiWrAnalogSetupTable:%d %d\n",(int)sizeof(agsaPhyAnalogSetupRegisters_t), AnalogtableSize)); 4216 4217 for(phy = 0; phy < 10; phy++) /* upto 10 phys See PM*/ 4218 { 4219 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 0 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ); 4220 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 4 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ); 4221 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 8 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 ); 4222 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 12),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 ); 4223 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 16),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 ); 4224 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 20),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 ); 4225 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 24),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 ); 4226 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 28),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 ); 4227 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 32),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 ); 4228 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 36),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 ); 4229 4230 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister0 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 0,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 0 ))); 4231 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister1 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 4,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 4 ))); 4232 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister2 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 8,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 )); 4233 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister3 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +12,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 )); 4234 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister4 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +16,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 )); 4235 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister5 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +20,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 )); 4236 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister6 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +24,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 )); 4237 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister7 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +28,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 )); 4238 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister8 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +32,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 )); 4239 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister9 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +36,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 )); 4240 } 4241 4242 } 4243 4244 4245 GLOBAL void mpiWrIntVecTable(agsaRoot_t *agRoot, 4246 mpiConfig_t* config 4247 ) 4248 { 4249 bit32 CFGTableOffset, value; 4250 bit32 INTVTableOffset; 4251 bit32 ValuetoWrite; 4252 bit8 pcibar, i,obq; 4253 4254 /* get offset of the configuration table */ 4255 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4256 4257 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4258 4259 /* get PCI BAR */ 4260 value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4261 /* convert the PCI BAR to logical bar number */ 4262 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4263 4264 /* read Interrupt Table Offset from the main configuration table */ 4265 INTVTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_INT_VEC_TABLE_OFFSET); 4266 INTVTableOffset &= 0x00FFFFFF; 4267 INTVTableOffset = CFGTableOffset + INTVTableOffset; 4268 SA_DBG1(("mpiWrIntVecTable: Base Offset %08X\n",(bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO ) )); 4269 4270 for (i = 0; i < MAX_NUM_VECTOR; i ++) 4271 { 4272 bit32 found=0; 4273 for (obq = 0; obq < MAX_NUM_VECTOR; obq++) 4274 { /* find OBQ for vector i */ 4275 if( config->outboundQueues[obq].interruptVector == i ) 4276 { 4277 found=1; 4278 break; 4279 } 4280 } 4281 4282 if(!found ) 4283 { 4284 continue; 4285 } 4286 4287 ValuetoWrite = (( config->outboundQueues[obq].interruptDelay << SHIFT15) | config->outboundQueues[obq].interruptThreshold ); 4288 4289 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), ValuetoWrite ); 4290 4291 SA_DBG3(("mpiWrIntVecTable: Q %d interruptDelay 0x%X interruptThreshold 0x%X \n",i, 4292 config->outboundQueues[i].interruptDelay, config->outboundQueues[i].interruptThreshold )); 4293 4294 SA_DBG3(("mpiWrIntVecTable: %d INT_VT_Coal_CNT_TO Bar %d Offset %3X Writing 0x%08x\n",i, 4295 pcibar, 4296 (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), 4297 ValuetoWrite)); 4298 4299 } 4300 4301 for (i = 0; i < MAX_NUM_VECTOR; i++) 4302 { 4303 /* read interrupt colescing control and timer */ 4304 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t))); 4305 SA_DBG4(("mpiWrIntVecTable: Offset 0x%08x Interrupt Colescing iccict[%02d] 0x%x\n", (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), i, value)); 4306 } 4307 } 4308 4309 GLOBAL void mpiWrPhyAttrbTable(agsaRoot_t *agRoot, sasPhyAttribute_t *phyAttrib) 4310 { 4311 bit32 CFGTableOffset, value; 4312 bit32 PHYTableOffset; 4313 bit8 pcibar, i; 4314 4315 /* get offset of the configuration table */ 4316 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4317 4318 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4319 4320 /* get PCI BAR */ 4321 value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4322 /* convert the PCI BAR to logical bar number */ 4323 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4324 4325 /* read Phy Attribute Table Offset from the configuration table */ 4326 PHYTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); 4327 4328 PHYTableOffset &=0x00FFFFFF; 4329 4330 PHYTableOffset = CFGTableOffset + PHYTableOffset + PHY_EVENT_OQ; 4331 4332 SA_DBG1(("mpiWrPhyAttrbTable: PHYTableOffset 0x%08x\n", PHYTableOffset)); 4333 4334 /* write OQ event per phy */ 4335 for (i = 0; i < MAX_VALID_PHYS; i ++) 4336 { 4337 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ); 4338 4339 SA_DBG3(("mpiWrPhyAttrbTable:%d Offset 0x%08x phyAttribute 0x%x\n",i,(bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ )); 4340 4341 4342 } 4343 4344 for (i = 0; i < MAX_VALID_PHYS; i ++) 4345 { 4346 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t))); 4347 SA_DBG1(("mpiWrPhyAttrbTable: OQ Event per phy[%x] 0x%x\n", i, value)); 4348 } 4349 } 4350 4351 4352 #ifdef TEST /******************************************************************/ 4353 /*******************************************************************************/ 4354 /** \fn mpiFreezeInboundQueue(agsaRoot_t *agRoot) 4355 * \brief Freeze the inbound queue 4356 * 4357 * \param agRoot Handles for this instance of SAS/SATA hardware 4358 * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze 4359 * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze 4360 * 4361 * Return: 4362 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 4363 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 4364 */ 4365 /*******************************************************************************/ 4366 GLOBAL bit32 mpiFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) 4367 { 4368 bit32 value, togglevalue; 4369 bit32 max_wait_time; 4370 bit32 max_wait_count; 4371 4372 SA_DBG2(("Entering function:mpiFreezeInboundQueue\n")); 4373 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 4374 4375 togglevalue = 0; 4376 4377 if (bitMapQueueNum0) 4378 { 4379 /* update the inbound queue number to HOST_SCRATCH_PAD1 register for queue 0 to 31 */ 4380 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 4381 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 4382 4383 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_1); 4384 value |= bitMapQueueNum0; 4385 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); 4386 } 4387 4388 if (bitMapQueueNum1) 4389 { 4390 /* update the inbound queue number to HOST_SCRATCH_PAD2 register for queue 32 to 63 */ 4391 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 4392 value |= bitMapQueueNum1; 4393 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); 4394 } 4395 4396 /* Write bit 2 to Inbound DoorBell Register */ 4397 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_FREEZE); 4398 4399 /* wait until Inbound DoorBell Clear Register toggled */ 4400 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 4401 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4402 do 4403 { 4404 ossaStallThread(agRoot, WAIT_INCREMENT); 4405 /* Read Inbound DoorBell Register - for RevB */ 4406 // value = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_IBDB_SET); 4407 value = MSGU_READ_IDR; 4408 value &= IBDB_IBQ_FREEZE; 4409 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 4410 4411 if (!max_wait_count) 4412 { 4413 SA_DBG1(("mpiFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 4414 return AGSA_RC_FAILURE; 4415 } 4416 4417 return AGSA_RC_SUCCESS; 4418 } 4419 4420 /******************************************************************************/ 4421 /** \fn mpiUnFreezeInboundQueue(agsaRoot_t *agRoot) 4422 * \brief Freeze the inbound queue 4423 * 4424 * \param agRoot Handles for this instance of SAS/SATA hardware 4425 * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze 4426 * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze 4427 * 4428 * Return: 4429 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 4430 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 4431 */ 4432 /******************************************************************************/ 4433 GLOBAL bit32 mpiUnFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) 4434 { 4435 bit32 value, togglevalue; 4436 bit32 max_wait_time; 4437 bit32 max_wait_count; 4438 4439 SA_DBG2(("Entering function:mpiUnFreezeInboundQueue\n")); 4440 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 4441 4442 togglevalue = 0; 4443 4444 if (bitMapQueueNum0) 4445 { 4446 /* update the inbound queue number to HOST_SCRATCH_PAD1 register - for queue 0 to 31 */ 4447 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 4448 value |= bitMapQueueNum0; 4449 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); 4450 } 4451 4452 if (bitMapQueueNum1) 4453 { 4454 /* update the inbound queue number to HOST_SCRATCH_PAD2 register - for queue 32 to 63 */ 4455 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 4456 value |= bitMapQueueNum1; 4457 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); 4458 } 4459 4460 /* Write bit 2 to Inbound DoorBell Register */ 4461 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_UNFREEZE); 4462 4463 /* wait until Inbound DoorBell Clear Register toggled */ 4464 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 4465 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4466 do 4467 { 4468 ossaStallThread(agRoot, WAIT_INCREMENT); 4469 /* Read Inbound DoorBell Register - for RevB */ 4470 value = MSGU_READ_IDR; 4471 value &= IBDB_IBQ_UNFREEZE; 4472 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 4473 4474 if (!max_wait_count) 4475 { 4476 SA_DBG1(("mpiUnFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 4477 return AGSA_RC_FAILURE; 4478 } 4479 4480 return AGSA_RC_SUCCESS; 4481 } 4482 4483 #endif /* TEST ****************************************************************/ 4484 4485 GLOBAL bit32 si_check_V_HDA(agsaRoot_t *agRoot) 4486 { 4487 bit32 ret = AGSA_RC_SUCCESS; 4488 bit32 hda_status = 0; 4489 4490 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 4491 4492 SA_DBG1(("si_check_V_HDA: hda_status 0x%08X\n",hda_status )); 4493 4494 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) 4495 { 4496 /* HDA mode */ 4497 SA_DBG1(("si_check_V_HDA: HDA mode, value = 0x%x\n", hda_status)); 4498 ret = AGSA_RC_HDA_NO_FW_RUNNING; 4499 } 4500 4501 4502 return(ret); 4503 } 4504 GLOBAL bit32 si_check_V_Ready(agsaRoot_t *agRoot) 4505 { 4506 bit32 ret = AGSA_RC_SUCCESS; 4507 bit32 SCRATCH_PAD1; 4508 bit32 max_wait_time; 4509 bit32 max_wait_count; 4510 /* ILA */ 4511 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4512 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4513 do 4514 { 4515 ossaStallThread(agRoot, WAIT_INCREMENT); 4516 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4517 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4518 4519 if (!max_wait_count) 4520 { 4521 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 4522 return( AGSA_RC_FAILURE); 4523 } 4524 /* RAAE */ 4525 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4526 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4527 do 4528 { 4529 ossaStallThread(agRoot, WAIT_INCREMENT); 4530 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4531 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4532 4533 if (!max_wait_count) 4534 { 4535 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 4536 return( AGSA_RC_FAILURE); 4537 4538 } 4539 /* IOP0 */ 4540 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4541 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4542 do 4543 { 4544 ossaStallThread(agRoot, WAIT_INCREMENT); 4545 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4546 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4547 4548 if (!max_wait_count) 4549 { 4550 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 4551 return( AGSA_RC_FAILURE); 4552 4553 } 4554 4555 /* IOP1 */ 4556 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4557 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4558 do 4559 { 4560 ossaStallThread(agRoot, WAIT_INCREMENT); 4561 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4562 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4563 4564 if (!max_wait_count) 4565 { 4566 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); 4567 // return( AGSA_RC_FAILURE); 4568 } 4569 4570 return(ret); 4571 } 4572 4573 GLOBAL bit32 siScratchDump(agsaRoot_t *agRoot) 4574 { 4575 bit32 SCRATCH_PAD1; 4576 bit32 ret =0; 4577 #ifdef SALLSDK_DEBUG 4578 bit32 SCRATCH_PAD2; 4579 bit32 SCRATCH_PAD3; 4580 bit32 SCRATCH_PAD0; 4581 4582 SCRATCH_PAD0 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0); 4583 SCRATCH_PAD2 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2); 4584 SCRATCH_PAD3 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3); 4585 #endif /* SALLSDK_DEBUG */ 4586 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4587 SA_DBG1(("siScratchDump: SCRATCH_PAD 0 0x%08x 1 0x%08x 2 0x%08x 3 0x%08x\n",SCRATCH_PAD0,SCRATCH_PAD1,SCRATCH_PAD2,SCRATCH_PAD3 )); 4588 4589 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RESERVED) == SCRATCH_PAD1_V_RESERVED ) 4590 { 4591 SA_DBG1(("siScratchDump: SCRATCH_PAD1 SCRATCH_PAD1_V_RESERVED 0x%08x\n", SCRATCH_PAD1_V_RESERVED)); 4592 } 4593 else 4594 { 4595 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK ) 4596 { 4597 SA_DBG1(("siScratchDump: SCRATCH_PAD1 valid 0x%08x\n",SCRATCH_PAD0 )); 4598 SA_DBG1(("siScratchDump: RAAE ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK)); 4599 } 4600 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) == SCRATCH_PAD1_V_ILA_MASK) 4601 { 4602 SA_DBG1(("siScratchDump: ILA ready 0x%08x\n", SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK)); 4603 } 4604 4605 if(SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) 4606 { 4607 SA_DBG1(("siScratchDump: BOOTSTATE not success 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK)); 4608 } 4609 4610 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) == SCRATCH_PAD1_V_IOP0_MASK) 4611 { 4612 SA_DBG1(("siScratchDump: IOP0 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK)); 4613 } 4614 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) == SCRATCH_PAD1_V_IOP1_MASK) 4615 { 4616 SA_DBG1(("siScratchDump: IOP1 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK )); 4617 } 4618 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY) 4619 { 4620 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_READY 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_READY )); 4621 } 4622 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) == SCRATCH_PAD1_V_BOOTSTATE_MASK) 4623 { 4624 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_BOOTSTATE_MASK 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK )); 4625 } 4626 } 4627 return(ret); 4628 4629 } 4630 4631 4632 void si_macro_check(agsaRoot_t *agRoot) 4633 { 4634 4635 SA_DBG1(("si_macro_check:smIS_SPC %d\n",smIS_SPC(agRoot) )); 4636 SA_DBG1(("si_macro_check:smIS_HIL %d\n",smIS_HIL(agRoot) )); 4637 SA_DBG1(("si_macro_check:smIS_SFC %d\n",smIS_SFC(agRoot) )); 4638 4639 SA_DBG1(("si_macro_check:smIS_spc8001 %d\n",smIS_spc8001(agRoot) )); 4640 SA_DBG1(("si_macro_check:smIS_spc8081 %d\n",smIS_spc8081(agRoot) )); 4641 4642 SA_DBG1(("si_macro_check:smIS_SPCV8008 %d\n",smIS_SPCV8008(agRoot) )); 4643 SA_DBG1(("si_macro_check:smIS_SPCV8009 %d\n",smIS_SPCV8009(agRoot) )); 4644 SA_DBG1(("si_macro_check:smIS_SPCV8018 %d\n",smIS_SPCV8018(agRoot) )); 4645 SA_DBG1(("si_macro_check:smIS_SPCV8019 %d\n",smIS_SPCV8019(agRoot) )); 4646 SA_DBG1(("si_macro_check:smIS_ADAP8088 %d\n",smIS_ADAP8088(agRoot) )); 4647 SA_DBG1(("si_macro_check:smIS_ADAP8089 %d\n",smIS_ADAP8089(agRoot) )); 4648 SA_DBG1(("si_macro_check:smIS_SPCV8070 %d\n",smIS_SPCV8070(agRoot) )); 4649 SA_DBG1(("si_macro_check:smIS_SPCV8071 %d\n",smIS_SPCV8071(agRoot) )); 4650 SA_DBG1(("si_macro_check:smIS_SPCV8072 %d\n",smIS_SPCV8072(agRoot) )); 4651 SA_DBG1(("si_macro_check:smIS_SPCV8073 %d\n",smIS_SPCV8073(agRoot) )); 4652 SA_DBG1(("si_macro_check:smIS_SPCV8074 %d\n",smIS_SPCV8074(agRoot) )); 4653 SA_DBG1(("si_macro_check:smIS_SPCV8075 %d\n",smIS_SPCV8075(agRoot) )); 4654 SA_DBG1(("si_macro_check:smIS_SPCV8076 %d\n",smIS_SPCV8076(agRoot) )); 4655 SA_DBG1(("si_macro_check:smIS_SPCV8077 %d\n",smIS_SPCV8077(agRoot) )); 4656 SA_DBG1(("si_macro_check:smIS_SPCV9015 %d\n",smIS_SPCV9015(agRoot) )); 4657 SA_DBG1(("si_macro_check:smIS_SPCV9060 %d\n",smIS_SPCV9060(agRoot) )); 4658 SA_DBG1(("si_macro_check:smIS_SPCV %d\n",smIS_SPCV(agRoot) )); 4659 4660 SA_DBG1(("si_macro_check:smIS64bInt %d\n", smIS64bInt(agRoot) )); 4661 4662 } 4663 4664