1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * $FreeBSD$ 22 * 23 ********************************************************************************/ 24 /*******************************************************************************/ 25 /*! \file sahwreg.h 26 * \brief The file defines the register offset of hardware 27 */ 28 /******************************************************************************/ 29 #ifndef __SAHWREG_H__ 30 31 #define __SAHWREG_H__ 32 33 /* #define MSGU_ACCESS_VIA_XCBI */ /* Defined in build script now */ 34 35 /* Message Unit Registers - BAR0(0x10), BAR0(win) */ 36 #ifdef SPC_I2O_ENABLE 37 /* i2o=1 space register offsets - MU_I2O_ENABLE */ 38 /* Currently FPGA use these offset */ 39 #define MSGU_IBDB_SET 0x20 40 #define MSGU_HOST_INT_STATUS 0x30 41 #define MSGU_HOST_INT_MASK 0x34 42 #define MSGU_IOPIB_INT_STATUS 0x40 43 #define MSGU_IOPIB_INT_MASK 0x44 44 #define MSGU_IBDB_CLEAR 0x70 45 #define MSGU_MSGU_CONTROL 0x74 46 #define MSGU_ODR 0x9C 47 #define MSGU_ODCR 0xA0 48 #define MSGU_SCRATCH_PAD_0 0xB0 49 #define MSGU_SCRATCH_PAD_1 0xB4 50 #define MSGU_SCRATCH_PAD_2 0xB8 51 #define MSGU_SCRATCH_PAD_3 0xBC 52 #else 53 /* i2o=0 space register offsets - ~MU_I2O_ENABLE */ 54 #define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */ 55 #define MSGU_HOST_INT_STATUS 0x08 56 #define MSGU_HOST_INT_MASK 0x0C 57 #define MSGU_IOPIB_INT_STATUS 0x18 58 #define MSGU_IOPIB_INT_MASK 0x1C 59 #define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */ 60 #define MSGU_MSGU_CONTROL 0x24 61 #define MSGU_ODR 0x3C /* RevB */ 62 #define MSGU_ODCR 0x40 /* RevB */ 63 #define MSGU_SCRATCH_PAD_0 0x44 64 #define MSGU_SCRATCH_PAD_1 0x48 65 #define MSGU_SCRATCH_PAD_2 0x4C 66 #define MSGU_SCRATCH_PAD_3 0x50 67 #define MSGU_HOST_SCRATCH_PAD_0 0x54 68 #define MSGU_HOST_SCRATCH_PAD_1 0x58 69 #define MSGU_HOST_SCRATCH_PAD_2 0x5C 70 #define MSGU_HOST_SCRATCH_PAD_3 0x60 71 #define MSGU_HOST_SCRATCH_PAD_4 0x64 72 #define MSGU_HOST_SCRATCH_PAD_5 0x68 73 #define MSGU_HOST_SCRATCH_PAD_6 0x6C 74 #define MSGU_HOST_SCRATCH_PAD_7 0x70 75 #define MSGU_ODMR 0x74 /* RevB */ 76 #endif 77 78 79 80 81 /* 82 Table 215 Messaging Unit Address Map 83 Offset (Hex) Name Access Internal Offset Internal Name Comment 84 */ 85 86 #define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound Doorbell Set */ 87 #define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound Doorbell Set */ 88 #define V_Inbound_Doorbell_Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Clear */ 89 #define V_Inbound_Doorbell_Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Clear */ 90 #define V_Inbound_Doorbell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New in SPCv */ 91 #define V_Inbound_Doorbell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New in SPCv */ 92 #define V_Inbound_Doorbell_Mask_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New in SPCv */ 93 #define V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New in SPCv */ 94 #define V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound Doorbell Set */ 95 #define V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound Doorbell Set */ 96 #define V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - Outbound Doorbell Clear */ 97 #define V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - Outbound Doorbell Clear */ 98 #define V_Outbound_Doorbell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */ 99 #define V_Outbound_Doorbell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */ 100 #define V_Outbound_Doorbell_Mask_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */ 101 #define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */ 102 /* 0x40 Reserved R all 0s */ 103 #define V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpad 0 */ 104 #define V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpad 1 */ 105 #define V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpad 2 */ 106 #define V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpad 3 */ 107 #define V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad 4 */ 108 #define V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad 5 */ 109 #define V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad 6 */ 110 #define V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad 7 */ 111 #define V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpad 8 */ 112 #define V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpad 9 */ 113 #define V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpad 10 */ 114 #define V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpad 11 */ 115 /* 0x74 - 0xFF Reserved R all 0s */ 116 #define V_Outbound_Queue_Consumer_Indices_Base 0x100 /* typical value real offset is read from table to 0x1FF Host RW Local RO 0x1F100 � 0x1F1FF In DQ storage area*/ 117 #define V_Inbound_Queue_Producer_Indices 0x200 /* typical value real offset is read from table to 0x3FF Host RW Local RO 0x1F200 � 0x1F3FF In DQ storage area, also mapped as WSM*/ 118 /* 119 SPC_V SPC 120 Bar Name Offset Bar Name Offset 121 PCIBAR0, V_Inbound_Doorbell_Set_Register, 0x00 PCIBAR0, MSGU_IBDB_SET, 0x04 122 PCIBAR0, V_Inbound_Doorbell_Clear_Register, 0x08 NA 123 PCIBAR0, V_Inbound_Doorbell_Mask_Set_Register, 0x10 NA 124 PCIBAR0, V_Inbound_Doorbell_Mask_Clear_Register, 0x18 NA 125 PCIBAR0, V_Outbound_Doorbell_Set_Register, 0x20 PCIBAR0, MSGU_ODR, 0x3C 126 PCIBAR0, V_Outbound_Doorbell_Clear_Register, 0x28 PCIBAR0, MSGU_ODCR, 0x40 127 PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, 0x30 PCIBAR0, MSGU_ODMR, 0x74 128 PCIBAR0, V_Outbound_Doorbell_Mask_Clear_Register, 0x38 NA 129 PCIBAR0, V_Scratchpad_0_Register, 0x44 PCIBAR0, MSGU_SCRATCH_PAD_0, 0x44 130 PCIBAR0, V_Scratchpad_1_Register, 0x48 PCIBAR0, MSGU_SCRATCH_PAD_1, 0x48 131 PCIBAR0, V_Scratchpad_2_Register, 0x4C PCIBAR0, MSGU_SCRATCH_PAD_2, 0x4C 132 PCIBAR0, V_Scratchpad_3_Register, 0x50 PCIBAR0, MSGU_SCRATCH_PAD_3, 0x50 133 PCIBAR0, V_Host_Scratchpad_0_Register, 0x54 PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, 0x54 134 PCIBAR0, V_Host_Scratchpad_1_Register, 0x58 PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, 0x58 135 PCIBAR0, V_Host_Scratchpad_2_Register, 0x5C PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, 0x5C 136 PCIBAR0, V_Host_Scratchpad_3_Register, 0x60 PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, 0x60 137 138 */ 139 140 141 #define V_RamEccDbErr 0x00000018 142 #define V_SoftResetRegister 0x1000 143 #define V_MEMBASE_II_ShiftRegister 0x1010 144 145 #define V_GsmConfigReset 0 146 #define V_GsmReadAddrParityCheck 0x38 147 #define V_GsmWriteAddrParityCheck 0x40 148 #define V_GsmWriteDataParityCheck 0x48 149 #define V_GsmReadAddrParityIndic 0x58 150 #define V_GsmWriteAddrParityIndic 0x60 151 #define V_GsmWriteDataParityIndic 0x68 152 153 154 #define SPCv_Reset_Reserved 0xFFFFFF3C 155 #define SPCv_Reset_Read_Mask 0xC0 156 #define SPCv_Reset_Read_NoReset 0x0 157 #define SPCv_Reset_Read_NormalResetOccurred 0x40 158 #define SPCv_Reset_Read_SoftResetHDAOccurred 0x80 159 #define SPCv_Reset_Read_ChipResetOccurred 0xC0 160 161 162 #define SPCv_Reset_Write_NormalReset 0x1 163 #define SPCv_Reset_Write_SoftResetHDA 0x2 164 #define SPCv_Reset_Write_ChipReset 0x3 165 166 /* [31:8] Reserved -- Reserved Host R / Local R/W */ 167 168 /* Indicator that a controller soft reset has occurred. 169 The bootloader sets this field when a soft reset occurs. Host is read only. 170 [7:6] 171 b00: No soft reset occurred. Device reset value. 172 b01: Normal soft reset occurred. 173 b10: Soft reset HDA mode occurred. 174 b11: Chip reset occurred. 175 Soft Reset Occurred SFT_RST_OCR 176 [5:2] Reserved -- Reserved b0000 Reserved 177 Host R/W / Local R 178 The controller soft reset type that is required by the host side. The host sets this field and the bootloader clears it. 179 b00: Ready for soft reset / normal status. 180 b01: Normal soft reset. 181 b10: Soft reset HDA mode. 182 b11: Chip reset. 183 Soft Reset Requested 184 SFT_RST_RQST 185 [1:0] 186 */ 187 188 189 190 191 /***** RevB - ODAR - Outbound DoorBell Auto-Clearing Register 192 ICT - Interrupt Coalescing Timer Register 193 ICC - Interrupt Coalescing Control Register 194 - BAR2(0x18), BAR1(win) *****/ 195 /****************** 64 KB BAR *****************/ 196 #define SPC_ODAR 0x00335C 197 #define SPC_ICTIMER 0x0033C0 198 #define SPC_ICCONTROL 0x0033C4 199 200 /* BAR2(0x18), BAR1(win) */ 201 #define MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell register */ 202 #define MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell Interrupt Register */ 203 #define MSGU_XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Mask Register */ 204 #define MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell Interrupt Clear Register */ 205 206 /* RB6 offset */ 207 #define SPC_RB6_OFFSET 0x80C0 208 209 #define RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */ 210 211 #ifdef MSGU_ACCESS_VIA_XCBI 212 #define MSGU_READ_IDR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_IBDB_REG) 213 #define MSGU_READ_ODMR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_MASK) 214 #define MSGU_READ_ODR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_REG) 215 #define MSGU_READ_ODCR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_CLEAR) 216 #else 217 #define MSGU_READ_IDR siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET) 218 #define MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR) 219 #define MSGU_READ_ODR siHalRegReadExt(agRoot, GEN_MSGU_ODR, MSGU_ODR) 220 #define MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR) 221 #endif 222 223 /* bit definition for ODMR register */ 224 #define ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */ 225 #define ODMR_CLEAR_ALL 0 /* clear all interrupt vector */ 226 /* bit definition for ODMR register */ 227 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */ 228 229 /* bit definition for Inbound Doorbell register */ 230 #define IBDB_IBQ_UNFREEZE 0x08 /* Inbound doorbell bit3 */ 231 #define IBDB_IBQ_FREEZE 0x04 /* Inbound doorbell bit2 */ 232 #define IBDB_CFG_TABLE_RESET 0x02 /* Inbound doorbell bit1 */ 233 #define IBDB_CFG_TABLE_UPDATE 0x01 /* Inbound doorbell bit0 */ 234 235 #define IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */ 236 #define IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */ 237 #define IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Termination */ 238 #define IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initialization */ 239 240 /* bit mask definition for Scratch Pad0 register */ 241 #define SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */ 242 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */ 243 #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF /* if AAP error state */ 244 245 /* state definition for Scratch Pad1 register */ 246 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */ 247 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */ 248 #define SCRATCH_PAD1_ERR 0x02 /* error state */ 249 #define SCRATCH_PAD1_RDY 0x03 /* ready state */ 250 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */ 251 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */ 252 #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, bit1-0 State */ 253 #define SCRATCH_PAD1_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */ 254 255 256 257 #define SCRATCH_PAD1_V_RAAE_MASK 0x00000003 /* 0 1 also ready */ 258 #define SCRATCH_PAD1_V_RAAE_ERR 0x00000002 /* 1 */ 259 #define SCRATCH_PAD1_V_ILA_MASK 0x0000000C /* 2 3 also ready */ 260 #define SCRATCH_PAD1_V_ILA_ERR 0x00000008 /* 3 */ 261 #define SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070 /* 456 */ 262 #define SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000 /* Load successful */ 263 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010 /* HDA Mode SEEPROM Setting */ 264 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020 /* HDA Mode BootStrap Setting */ 265 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */ 266 #define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040 /* HDA Mode due to critical error */ 267 #define SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050 /* Reserved */ 268 #define SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060 /* Reserved */ 269 #define SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070 /* Fatal Error Boot process halted */ 270 271 272 #define SCRATCH_PAD1_V_ILA_IMAGE 0x00000080 /* 7 */ 273 #define SCRATCH_PAD1_V_FW_IMAGE 0x00000100 /* 8 */ 274 #define SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200 /* 9 */ 275 #define SCRATCH_PAD1_V_IOP0_MASK 0x00000C00 /* 10 11 also ready */ 276 #define SCRATCH_PAD1_V_IOP0_ERR 0x00000800 /* 11 */ 277 #define SCRATCH_PAD1_V_IOP1_MASK 0x00003000 /* 12 13 also ready */ 278 #define SCRATCH_PAD1_V_IOP1_ERR 0x00002000 /* 13 */ 279 #define SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */ 280 281 #define SCRATCH_PAD1_V_READY ( SCRATCH_PAD1_V_RAAE_MASK | SCRATCH_PAD1_V_ILA_MASK | SCRATCH_PAD1_V_IOP0_MASK ) /* */ 282 #define SCRATCH_PAD1_V_ERROR ( SCRATCH_PAD1_V_RAAE_ERR | SCRATCH_PAD1_V_ILA_ERR | SCRATCH_PAD1_V_IOP0_ERR | SCRATCH_PAD1_V_IOP1_ERR ) /* Scratch Pad1 13 11 3 1 */ 283 284 #define SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ? 0: \ 285 (((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ? SCRATCH_PAD1_V_ILA_ERR : 0 ) 286 287 #define SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ? 0: \ 288 (((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR) ? SCRATCH_PAD1_V_RAAE_ERR : 0 ) 289 290 #define SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ? 0: \ 291 (((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR) ? SCRATCH_PAD1_V_IOP0_ERR : 0 ) 292 293 #define SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ? 0: \ 294 (((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR) ? SCRATCH_PAD1_V_IOP1_ERR : 0 ) 295 296 #define SCRATCH_PAD1_V_ERROR_STATE(ScratchPad1) ( SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) | \ 297 SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) | \ 298 SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) | \ 299 SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ) 300 301 #define SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070 /* Scratch Pad1 (6 5 4) */ 302 303 304 /* error bit definition */ 305 #define SCRATCH_PAD1_BDMA_ERR 0x80000000 /* bit31 */ 306 #define SCRATCH_PAD1_GSM_ERR 0x40000000 /* bit30 */ 307 #define SCRATCH_PAD1_MBIC1_ERR 0x20000000 /* bit29 */ 308 #define SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000 /* bit28 */ 309 #define SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000 /* bit27 */ 310 #define SCRATCH_PAD1_PMIC1_ERR 0x04000000 /* bit26 */ 311 #define SCRATCH_PAD1_PMIC2_ERR 0x02000000 /* bit25 */ 312 #define SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000 /* bit24 */ 313 #define SCRATCH_PAD1_OSSP_ERR 0x00800000 /* bit23 */ 314 #define SCRATCH_PAD1_SSPA_ERR 0x00400000 /* bit22 */ 315 #define SCRATCH_PAD1_SSPL_ERR 0x00200000 /* bit21 */ 316 #define SCRATCH_PAD1_HSST_ERR 0x00100000 /* bit20 */ 317 #define SCRATCH_PAD1_PCS_ERR 0x00080000 /* bit19 */ 318 #define SCRATCH_PAD1_FW_INIT_ERR 0x00008000 /* bit15 */ 319 #define SCRATCH_PAD1_FW_ASRT_ERR 0x00004000 /* bit14 */ 320 #define SCRATCH_PAD1_FW_WDG_ERR 0x00002000 /* bit13 */ 321 #define SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002 /* bit1 */ 322 #define SCRATCH_PAD1_AAP_READY 0x00000003 /* bit1 & bit0 */ 323 324 325 /* state definition for Scratch Pad2 register */ 326 #define SCRATCH_PAD2_POR 0x00 /* power on state */ 327 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ 328 #define SCRATCH_PAD2_ERR 0x02 /* error state */ 329 #define SCRATCH_PAD2_RDY 0x03 /* ready state */ 330 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */ 331 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ 332 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:4, bit1-0 State*/ 333 #define SCRATCH_PAD2_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */ 334 335 /* error bit definition */ 336 #define SCRATCH_PAD2_BDMA_ERR 0x80000000 /* bit31 */ 337 #define SCRATCH_PAD2_GSM_ERR 0x40000000 /* bit30 */ 338 #define SCRATCH_PAD2_MBIC3_ERR 0x20000000 /* bit29 */ 339 #define SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000 /* bit28 */ 340 #define SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000 /* bit27 */ 341 #define SCRATCH_PAD2_PMIC1_ERR 0x04000000 /* bit26 */ 342 #define SCRATCH_PAD2_PMIC2_ERR 0x02000000 /* bit25 */ 343 #define SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000 /* bit24 */ 344 #define SCRATCH_PAD2_OSSP_ERR 0x00800000 /* bit23 */ 345 #define SCRATCH_PAD2_SSPA_ERR 0x00400000 /* bit22 */ 346 #define SCRATCH_PAD2_SSPL_ERR 0x00200000 /* bit21 */ 347 #define SCRATCH_PAD2_HSST_ERR 0x00100000 /* bit20 */ 348 #define SCRATCH_PAD2_PCS_ERR 0x00080000 /* bit19 */ 349 350 #define SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000 /* bit16 */ 351 #define SCRATCH_PAD2_FW_ILA_ERR 0x00008000 /* bit15 */ 352 #define SCRATCH_PAD2_FW_FLM_ERR 0x00004000 /* bit14 */ 353 #define SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000 /* bit13 */ 354 #define SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000 /* bit12 */ 355 #define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800 /* bit11 */ 356 #define SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400 /* bit10 */ 357 #define SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200 /* bit9 */ 358 #define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100 /* bit8 */ 359 #define SCRATCH_PAD2_FW_HW_MASK 0x000000FF 360 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00 361 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01 362 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02 363 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03 364 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04 365 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05 366 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06 367 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08 368 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C 369 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E 370 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F 371 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10 372 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13 373 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14 374 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF 375 376 377 378 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */ 379 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */ 380 381 #define SPCV_RAAE_STATE_MASK 0x3 382 #define SPCV_IOP0_STATE_MASK ((1 << 10) | (1 << 11)) 383 #define SPCV_IOP1_STATE_MASK ((1 << 12) | (1 << 13)) 384 #define SPCV_ERROR_VALUE 0x2 385 386 387 #define SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F /* SPC 8x6G boots from Image */ 388 #define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008 /* Image flag is valid */ 389 #define SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004 /* Image B is valid */ 390 #define SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002 /* Image A is valid */ 391 #define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001 /* Image B is active */ 392 393 394 #define SCRATCH_PAD3_V_ 0x00000001 /* Image B is valid */ 395 396 #define SCRATCH_PAD3_V_ENC_DISABLED 0x00000000 /* */ 397 #define SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001 /* */ 398 #define SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002 /* */ 399 #define SCRATCH_PAD3_V_ENC_READY 0x00000003 /* */ 400 #define SCRATCH_PAD3_V_ENC_MASK SCRATCH_PAD3_V_ENC_READY /* */ 401 402 #define SCRATCH_PAD3_V_AUT 0x00000008 /* AUT Operator authentication*/ 403 #define SCRATCH_PAD3_V_ARF 0x00000004 /* ARF factory mode. */ 404 405 #define SCRATCH_PAD3_V_XTS_ENABLED (1 << SHIFT14) /* */ 406 #define SCRATCH_PAD3_V_SMA_ENABLED (1 << SHIFT4 ) /* */ 407 #define SCRATCH_PAD3_V_SMB_ENABLED (1 << SHIFT5 ) /* */ 408 #define SCRATCH_PAD3_V_SMF_ENABLED 0 /* */ 409 #define SCRATCH_PAD3_V_SM_MASK 0x000000F0 /* */ 410 #define SCRATCH_PAD3_V_ERR_CODE 0x00FF0000 /* */ 411 412 413 /* Dynamic map through Bar4 - 0x00700000 */ 414 #define GSM_CONFIG_RESET 0x00000000 415 #define RAM_ECC_DB_ERR 0x00000018 416 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058 417 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 418 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 419 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038 420 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 421 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 422 423 /* signature defintion for host scratch pad0 register */ 424 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */ 425 #define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset without PCIe resetting */ 426 427 /**** SPC Top-level Registers definition for Soft Reset/HDA mode ****/ 428 /****************** 64 KB BAR *****************/ 429 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ 430 #define SPC_REG_RESET 0x000000 /* reset register */ 431 #define SPC_REG_DEVICE_LCLK 0x000058 /* Device LCLK generation register */ 432 433 #define SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET) 434 435 #define SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value); 436 /* NMI register - BAR4(0x20), BAR2(win) 0x060000/0x070000 */ 437 //#define MBIC_RAW_NMI_STAT_VPE0_IOP 0x0004C8 not used anymore 438 //#define MBIC_RAW_NMI_STAT_VPE0_AAP1 0x0104C8 not used anymore 439 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 440 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 441 442 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ 443 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 444 #define PCIE_EVENT_INTERRUPT 0x003044 445 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 446 #define PCIE_ERROR_INTERRUPT 0x00304C 447 448 /* PCIe Message Unit Configuration Registers offset - BAR2(0x18), BAR1(win) 0x010000 */ 449 #define SPC_REG_MSGU_CONFIG 0x003018 450 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010 451 452 /* bit difination for SPC_RESET register */ 453 #define SPC_REG_RESET_OSSP 0x00000001 454 #define SPC_REG_RESET_RAAE 0x00000002 455 #define SPC_REG_RESET_PCS_SPBC 0x00000004 456 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008 457 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 458 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 459 #define SPC_REG_RESET_PCS_LM 0x00000040 460 #define SPC_REG_RESET_PCS 0x00000080 461 #define SPC_REG_RESET_GSM 0x00000100 462 #define SPC_REG_RESET_DDR2 0x00010000 463 #define SPC_REG_RESET_BDMA_CORE 0x00020000 464 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000 465 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 466 #define SPC_REG_RESET_PCIE_PWR 0x00100000 467 #define SPC_REG_RESET_PCIE_SFT 0x00200000 468 #define SPC_REG_RESET_PCS_SXCBI 0x00400000 469 #define SPC_REG_RESET_LMS_SXCBI 0x00800000 470 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000 471 #define SPC_REG_RESET_PMIC_CORE 0x02000000 472 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 473 #define SPC_REG_RESET_DEVICE 0x80000000 474 475 /* bit definition for SPC Device Revision register - BAR1 */ 476 #define SPC_REG_DEVICE_REV 0x000024 477 #define SPC_REG_DEVICE_REV_MASK 0x0000000F 478 479 480 /* bit definition for SPC_REG_TOP_DEVICE_ID - BAR2 */ 481 #define SPC_REG_TOP_DEVICE_ID 0x20 482 #define SPC_TOP_DEVICE_ID 0x8001 483 484 #define SPC_REG_TOP_BOOT_STRAP 0x8 485 #define SPC_TOP_BOOT_STRAP 0x02C0A682 486 487 488 /* For PHY Error */ 489 #define COUNT_OFFSET 0x4000 490 #define LCLK_CLEAR 0x2 491 #define LCLK 0x1 492 #define CNTL_OFFSET 0x100 493 #define L0_LCLK_CLEAR 0x2 494 #define L0_LCLK 0x1 495 #define DEVICE_LCLK_CLEAR 0x40 496 497 /****************** 64 KB BAR *****************/ 498 /* PHY Error Count Registers - BAR4(0x20), BAR2(win) (need dynamic mapping) */ 499 #define SPC_SSPL_COUNTER_CNTL 0x001030 500 #define SPC_INVALID_DW_COUNT 0x001034 501 #define SPC_RUN_DISP_ERROR_COUNT 0x001038 502 #define SPC_CODE_VIOLATION_COUNT 0x00103C 503 #define SPC_LOSS_DW_SYNC_COUNT 0x001040 504 #define SPC_PHY_RESET_PROBLEM_COUNT 0x001044 505 #define SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV); 506 507 #define SPC_READ_COUNTER_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId)) 508 #define SPC_WRITE_COUNTER_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value) 509 #define SPC_READ_INV_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId)) 510 #define SPC_READ_DISP_ERR_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId)) 511 #define SPC_READ_CODE_VIO_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId)) 512 #define SPC_READ_LOSS_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId)) 513 #define SPC_READ_PHY_RESET_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId)) 514 /* PHY Error Count Control Registers - BAR2(0x18), BAR1(win) */ 515 #define SPC_L0_ERR_CNT_CNTL 0x0041B0 516 #define SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId)) 517 #define SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value) 518 519 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ 520 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258 521 522 /* HDA mode definitions */ 523 /* 256KB */ 524 #define HDA_CMD_OFFSET256K 0x0003FFC0 525 #define HDA_RSP_OFFSET256K 0x0003FFE0 526 527 /* 512KB */ 528 #define HDA_CMD_OFFSET512K 0x0007FFC0 529 #define HDA_RSP_OFFSET512K 0x0007FFE0 530 531 /* 768KB */ 532 #define HDA_CMD_OFFSET768K 0x000BFFC0 533 #define HDA_RSP_OFFSET768K 0x000BFFE0 534 535 /* 1024KB - by default */ 536 #define HDA_CMD_OFFSET1MB 0x0000FEC0 537 #define HDA_RSP_OFFSET1MB 0x0000FEE0 538 539 540 541 /* Table 27 Boot ROM HDA Protocol Command Format */ 542 typedef struct spcv_hda_cmd_s { 543 /* Offset Byte 3 Byte 2 Byte 1 Byte 0 */ 544 bit32 cmdparm_0; /* 0 Command Parameter 0 */ 545 bit32 cmdparm_1; /* 4 Command Parameter 1 */ 546 bit32 cmdparm_2; /* 8 Command Parameter 2 */ 547 bit32 cmdparm_3; /* 12 Command Parameter 3 */ 548 bit32 cmdparm_4; /* 16 Command Parameter 4 */ 549 bit32 cmdparm_5; /* 20 Command Parameter 5 */ 550 bit32 cmdparm_6; /* 24 Command Parameter 6 */ 551 bit32 C_PA_SEQ_ID_CMD_CODE; /* 28 C_PA SEQ_ID CMD_CODE */ 552 } spcv_hda_cmd_t; 553 554 /* Table 28 Boot ROM HDA Protocol Response Format */ 555 typedef struct spcv_hda_rsp_s { 556 /* Offset Byte 3 Byte 2 Byte 1 Byte 0 */ 557 bit32 cmdparm_0; /* 0 Command Parameter 0 */ 558 bit32 cmdparm_1; /* 4 Command Parameter 1 */ 559 bit32 cmdparm_2; /* 8 Command Parameter 2 */ 560 bit32 cmdparm_3; /* 12 Command Parameter 3 */ 561 bit32 cmdparm_4; /* 16 Command Parameter 4 */ 562 bit32 cmdparm_5; /* 20 Command Parameter 5 */ 563 bit32 cmdparm_6; /* 24 Command Parameter 6 */ 564 bit32 R_PA_SEQ_ID_RSP_CODE; /* 28 C_PA SEQ_ID CMD_CODE */ 565 } spcv_hda_rsp_t; 566 567 #define SPC_V_HDA_COMMAND_OFFSET 0x000042c0 568 #define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0 569 570 571 #define HDA_C_PA_OFFSET 0x1F 572 #define HDA_SEQ_ID_OFFSET 0x1E 573 #define HDA_PAR_LEN_OFFSET 0x04 574 #define HDA_CMD_CODE_OFFSET 0x1C 575 #define HDA_RSP_CODE_OFFSET 0x1C 576 #define SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET) 577 578 /* commands */ 579 #define SPC_V_HDAC_PA 0xCB 580 #define SPC_V_HDAC_BUF_INFO 0x0001 581 #define SPC_V_HDAC_EXEC 0x0002 582 #define SPC_V_HDAC_RESET 0x0003 583 #define SPC_V_HDAC_DMA 0x0004 584 585 #define SPC_V_HDAC_PA_MASK 0xFF000000 586 #define SPC_V_HDAC_SEQID_MASK 0x00FF0000 587 #define SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF 588 589 /* responses */ 590 #define SPC_V_HDAR_PA 0xDB 591 #define SPC_V_HDAR_BUF_INFO 0x8001 592 #define SPC_V_HDAR_IDLE 0x8002 593 #define SPC_V_HDAR_BAD_IMG 0x8003 594 #define SPC_V_HDAR_BAD_CMD 0x8004 595 #define SPC_V_HDAR_INTL_ERR 0x8005 596 #define SPC_V_HDAR_EXEC 0x8006 597 598 #define SPC_V_HDAR_PA_MASK 0xFF000000 599 #define SPC_V_HDAR_SEQID_MASK 0x00FF0000 600 #define SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF 601 602 #define ILAHDA_RAAE_IMG_GET 0x11 603 #define ILAHDA_IOP_IMG_GET 0x10 604 605 #define ILAHDAC_RAAE_IMG_DONE 0x81 606 607 608 #define HDA_AES_DIF_FUNC 0xFEDFAE1F 609 610 611 /* Set MSGU Mapping Registers in BAR0 */ 612 #define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001 613 #define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C 614 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010 615 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00 616 617 /* PMIC Init */ 618 #define MU_MEM_OFFSET 0x0 619 #define MSGU_MU_IO_WIR 0x8 /* Window 0 */ 620 621 #define BOOTTLOADERHDA_IDLE 0x8002 622 #define HDAR_BAD_IMG 0x8003 623 #define HDAR_BAD_CMD 0x8004 624 #define HDAR_EXEC 0x8006 625 626 #define CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem)) 627 628 #define GSMSM_AXI_LOWERADDR 0x00400000 629 #define SHIFT_MASK 0xFFFF0000 630 #define OFFSET_MASK 0x0000FFFF 631 #define SIZE_64KB 0x00010000 632 #define ILA_ISTR_ADDROFFSETHDA 0x0007E000 633 #define HDA_STATUS_BITS 0x0000FFFF 634 635 /* Scratchpad Reg: bit[31]: 1-CMDFlag 0-RSPFlag; bit[30,24]:CMD/RSP; bit[23,0]:Offset/Size - Shared with the host driver */ 636 /* ILA: Mandatory response / state codes in MSGU Scratchpad 0 */ 637 #define ILAHDA_IOP_IMG_GET 0x10 638 #define ILAHDA_AAP1_IMG_GET 0x11 639 #define ILAHDA_AAP2_IMG_GET 0x12 640 #define ILAHDA_EXITGOOD 0x1F 641 642 /* HOST: Mandatory command codes in Host Scratchpad 3 */ 643 #define ILAHDAC_IOP_IMG_DONE 0x00000080 644 #define ILAHDAC_AAP1_IMG_DONE 0x00000081 645 #define ILAHDAC_AAP2_IMG_DONE 0x00000082 646 #define ILAHDAC_ISTR_IMG_DONE 0x00000083 647 #define ILAHDAC_GOTOHDA 0x000000ff 648 649 #define HDA_ISTR_DONE (bit32)(ILAHDAC_ISTR_IMG_DONE << 24) 650 #define HDA_AAP1_DONE (bit32)(ILAHDAC_AAP1_IMG_DONE << 24) 651 #define HDA_IOP_DONE (bit32)(ILAHDAC_IOP_IMG_DONE << 24) 652 653 #define RB6_ACCESS_REG 0x6A0000 654 #define HDAC_EXEC_CMD 0x0002 655 #define HDA_C_PA 0xcb 656 #define HDA_SEQ_ID_BITS 0x00ff0000 657 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF 658 #define MBIC_AAP1_ADDR_BASE 0x060000 659 #define MBIC_GSM_SM_BASE 0x04F0000 660 #define MBIC_IOP_ADDR_BASE 0x070000 661 #define GSM_ADDR_BASE 0x0700000 662 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000 663 #define GSM_CONFIG_RESET_VALUE 0x00003b00 664 #define GPIO_ADDR_BASE 0x00090000 665 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c 666 667 668 /* Scratchpad registers for fatal errors */ 669 #define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3 670 #define SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3 671 #define SA_FATAL_ERROR_FATAL_ERROR 0x2 672 673 /* PCIe Analyzer trigger */ 674 #define PCIE_TRIGGER_ON_REGISTER_READ V_Host_Scratchpad_2_Register /* PCI trigger on this offset */ 675 676 #define PCI_TRIGGER_INIT_TEST 1 /* Setting adjustable paramater PciTrigger to match this value */ 677 #define PCI_TRIGGER_OFFSET_MISMATCH 2 /* Setting adjustable paramater PciTrigger to match this value */ 678 #define PCI_TRIGGER_COAL_IOMB_ERROR 4 /* Setting adjustable paramater PciTrigger to match this value */ 679 #define PCI_TRIGGER_COAL_INVALID 8 /* Setting adjustable paramater PciTrigger to match this value */ 680 681 682 683 684 /* */ 685 686 enum spc_spcv_offsetmap_e 687 { 688 GEN_MSGU_IBDB_SET=0, 689 GEN_MSGU_ODR, 690 GEN_MSGU_ODCR, 691 GEN_MSGU_SCRATCH_PAD_0, 692 GEN_MSGU_SCRATCH_PAD_1, 693 GEN_MSGU_SCRATCH_PAD_2, 694 GEN_MSGU_SCRATCH_PAD_3, 695 GEN_MSGU_HOST_SCRATCH_PAD_0, 696 GEN_MSGU_HOST_SCRATCH_PAD_1, 697 GEN_MSGU_HOST_SCRATCH_PAD_2, 698 GEN_MSGU_HOST_SCRATCH_PAD_3, 699 GEN_MSGU_ODMR, 700 GEN_PCIE_TRIGGER, 701 GEN_SPC_REG_RESET, 702 }; 703 704 705 #endif /*__SAHWREG_H__ */ 706 707 708 709 710