xref: /freebsd/sys/dev/pms/RefTisa/sallsdk/spc/sahw.c (revision f81cdf24ba5436367377f7c8e8f51f6df2a75ca7)
1 /*******************************************************************************
2 *Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved.
3 *
4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided
5 *that the following conditions are met:
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7 *following disclaimer.
8 *2. Redistributions in binary form must reproduce the above copyright notice,
9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided
10 *with the distribution.
11 *
12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20 
21 ********************************************************************************/
22 /*******************************************************************************/
23 /*! \file sahw.c
24  *  \brief The file implements the functions for reset and shutdown
25  */
26 /******************************************************************************/
27 #include <sys/cdefs.h>
28 #include <dev/pms/config.h>
29 
30 #include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
31 #ifdef SA_ENABLE_HDA_FUNCTIONS
32 #ifndef SA_EXCLUDE_FW_IMG
33 /*
34 #include "istrimg.h"
35 #include "ilaimg.h"
36 #include "aap1img.h"
37 #include "iopimg.h"
38 */
39 #endif
40 #endif
41 #if defined(SALLSDK_DEBUG)
42 extern bit32 gLLSoftResetCounter;
43 #endif
44 
45 #ifdef SA_ENABLE_TRACE_FUNCTIONS
46 #ifdef siTraceFileID
47 #undef siTraceFileID
48 #endif
49 #define siTraceFileID 'E'
50 #endif
51 
52 
53 bit32 gWait_3 = 3;
54 bit32 gWait_2 = 2;
55 
56 bit32 gWaitmSec = 0;
57 
58 
59 
60 LOCAL bit32 si_V_SoftReset(agsaRoot_t  *agRoot, bit32       signature);
61 
62 
63 LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot);
64 
65 #ifdef SA_ENABLE_HDA_FUNCTIONS
66 LOCAL void siPciMemCpy(agsaRoot_t *agRoot, bit32 dstoffset, void *src,
67                        bit32 DWcount, bit32 busBaseNumber);
68 
69 LOCAL bit32 siBar4Cpy(agsaRoot_t  *agRoot, bit32 offset, bit8 *parray, bit32 array_size);
70 #endif
71 
72 /******************************************************************************/
73 /*! \brief Function to reset the Hardware
74  *
75  *  The saHwReset() function is called to reset the SAS/SATA HW controller
76  *  All outstanding I/Os are explicitly aborted.
77  *  This API need to access before saInitialize() so checking saRoot is needed
78  *
79  *  \param agRoot       Handles for this instance of SAS/SATA hardware
80  *  \param resetType    The reset type
81  *  \param resetParm    The paramter passed for reset operation
82  *
83  *  \return -void-
84  */
85 /*******************************************************************************/
86 GLOBAL void saHwReset(
87                      agsaRoot_t  *agRoot,
88                      bit32       resetType,
89                      bit32       resetParm
90                      )
91 {
92   agsaLLRoot_t *saRoot = agNULL;
93   bit32        ret = AGSA_RC_SUCCESS;
94   bit32        value;
95   bit32        sysIntsActive = agFALSE;
96 #if defined(SALLSDK_DEBUG)
97   bit32        value1;
98   agsaControllerStatus_t controllerStatus;
99   agsaFatalErrorInfo_t fatal_error;
100 #endif
101 
102 #ifdef SOFT_RESET_TEST
103   DbgPrint("Reset Start\n");
104 #endif
105 
106   smTraceFuncEnter(hpDBG_VERY_LOUD, "5a");
107 
108   /* sanity check */
109   SA_ASSERT( (agNULL != agRoot), "");
110   if (agNULL != agRoot)
111   {
112     if (agNULL != agRoot->sdkData)
113     {
114       saRoot = (agsaLLRoot_t*) agRoot->sdkData;
115       sysIntsActive =  saRoot->sysIntsActive;
116       if(sysIntsActive)
117       {
118         saSystemInterruptsActive(agRoot,agFALSE);
119       }
120     }
121   }
122   else
123   {
124     smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5a");
125     return;
126   }
127 
128 
129 #if defined(SALLSDK_DEBUG)
130   {
131     if (agNULL != agRoot->sdkData)
132     {
133       /* check fatal errors */
134       value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1);
135       value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2);
136       /* check AAP error */
137       if( smIS_SPC(agRoot) )
138       {
139         value &= SCRATCH_PAD_STATE_MASK;
140         value1 &= SCRATCH_PAD_STATE_MASK;
141 
142         if ((SCRATCH_PAD1_ERR == value) || (SCRATCH_PAD2_ERR == value1))
143         {
144 
145           si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t));
146           /* read detail fatal errors */
147           value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0);
148           fatal_error.errorInfo0 = value;
149           SA_DBG1(("saHwReset: ScratchPad0 AAP error code 0x%x\n", value));
150           value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1);
151           fatal_error.errorInfo1 = value;
152           /* AAP error state */
153           SA_DBG1(("saHwReset: AAP error state and error code 0x%x\n", value));
154           value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2);
155           fatal_error.errorInfo2 = value;
156           /* IOP error state */
157           SA_DBG1(("saHwReset: IOP error state and error code 0x%x\n", value));
158           value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3);
159           SA_DBG1(("saHwReset: ScratchPad3 IOP error code 0x%x\n", value));
160           fatal_error.errorInfo3 = value;
161           if (agNULL != saRoot)
162           {
163             fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR;
164             fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR;
165             fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0;
166             fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1;
167             fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0;
168             fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1;
169           }
170 
171           /* Call Back with error */
172           SA_DBG1(("saHwReset: OSSA_HW_EVENT_MALFUNCTION SPC SP1 0x%x\n", value1));
173           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL);
174         }
175       }
176       else
177       {
178         if( ( (value & SCRATCH_PAD1_V_BOOTLDR_ERROR) == SCRATCH_PAD1_V_BOOTLDR_ERROR))
179         {
180           SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_BOOTLDR_ERROR 0x%x\n", value));
181         }
182         if(SCRATCH_PAD1_V_ERROR_STATE(value))
183         {
184           SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_ERROR_STATE  0x%x\n",SCRATCH_PAD1_V_ERROR_STATE(value) ));
185         }
186         if( (value & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY )
187         {
188           SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_READY  0x%x\n", value));
189         }
190       }
191       saGetControllerStatus(agRoot, &controllerStatus);
192       if (agNULL != saRoot)
193       {
194         /* display all pending Ios */
195         siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs);
196       }
197     }
198   }
199 #endif /* SALLSDK_DEBUG */
200 
201   /* Check the resetType */
202   switch (resetType)
203   {
204     /* Reset the whole chip */
205     case AGSA_CHIP_RESET:
206     {
207       /* callback with RESET_START */
208       ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
209 
210       if (agNULL != agRoot->sdkData && agNULL != saRoot)
211       {
212         /* Set chip status */
213         saRoot->chipStatus |= CHIP_RESETTING;
214 
215         /* Disable all interrupt */
216         saSystemInterruptsActive(agRoot,agFALSE);
217       }
218 
219       /* do chip reset */
220       siChipReset(agRoot);
221 
222       if (agNULL != saRoot)
223       {
224         /* clear up the internal resource */
225         siInitResources(agRoot,
226                         &saRoot->memoryAllocated,
227                         &saRoot->hwConfig,
228                         &saRoot->swConfig,
229                         saRoot->usecsPerTick);
230       }
231 
232       /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */
233       ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
234 
235       if (agNULL != saRoot)
236       {
237           /* mask off reset FW status */
238           saRoot->chipStatus &= ~CHIP_RESETTING;
239       }
240       break;
241     }
242     case AGSA_SOFT_RESET:
243     {
244 
245       if( smIS_SPCV(agRoot) )
246       {
247         SA_DBG1(("saHwReset: AGSA_SOFT_RESET chip type V %d\n",smIS_SPCV(agRoot) ));
248         ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
249         if (agNULL != saRoot)
250         {
251           saRoot->ResetStartTick = saRoot->timeTick;
252           saCountActiveIORequests( agRoot);
253 	} //delray end
254 
255         ret = siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE );
256 
257 	if(agNULL !=saRoot)
258 	{
259            /* clear up the internal resource */
260           siInitResources(agRoot,
261                           &saRoot->memoryAllocated,
262                           &saRoot->hwConfig,
263                           &saRoot->swConfig,
264                           saRoot->usecsPerTick);
265         }
266 
267         if (AGSA_RC_SUCCESS == ret)
268         {
269            /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */
270           SA_DBG1(("saHwReset: siChipResetV AGSA_RC_SUCCESS\n" ));
271           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
272         }
273         else
274         {
275           /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */
276           SA_DBG1(("saHwReset: siChipResetV not AGSA_RC_SUCCESS (0x%x)\n" ,ret));
277           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_FAILURE << SHIFT8, agNULL, agNULL);
278           if (agNULL != saRoot)
279           {
280             saRoot->ResetFailed = agTRUE;
281             SA_DBG1(("saHwReset: siChipResetV saRoot->ResetFailed  ret (0x%x)\n" ,ret));
282           }
283 
284         }
285         break;
286       }
287       else
288       {
289         if (agNULL != saRoot)
290         {
291           /* get register dump from GSM and save it to LL local memory */
292           siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0],
293                REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0);
294           siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0],
295                REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1);
296         }
297 
298         /* callback with RESET_START */
299         ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
300 
301         if (agNULL != agRoot->sdkData && agNULL != saRoot)
302         {
303           /* Set chip status */
304           saRoot->chipStatus |= CHIP_RESET_FW;
305 
306           /* Disable all interrupt */
307           saSystemInterruptsActive(agRoot,agFALSE);
308           saCountActiveIORequests( agRoot); //delray start
309 
310         }
311 
312         /* check HDA mode */
313         value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
314 
315         if (value == BOOTTLOADERHDA_IDLE)
316         {
317           /* HDA mode */
318           SA_DBG1(("saHwReset: HDA mode, value = 0x%x\n", value));
319           ret = AGSA_RC_HDA_NO_FW_RUNNING;
320         }
321         else
322         {
323           /* do Soft Reset */
324           ret = siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
325         }
326 	if(agNULL !=saRoot)
327 	{
328           /* clear up the internal resource */
329           siInitResources(agRoot,
330                           &saRoot->memoryAllocated,
331                           &saRoot->hwConfig,
332                           &saRoot->swConfig,
333                           saRoot->usecsPerTick);
334 	}
335         if (AGSA_RC_SUCCESS == ret)
336         {
337           /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */
338           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
339         }
340         else if (AGSA_RC_HDA_NO_FW_RUNNING == ret)
341         {
342           /* callback with CHIP_RESET_COMPLETE with OSSA_CHIP_FAILED */
343           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL);
344         }
345         else
346         {
347           /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */
348           ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, (OSSA_FAILURE << SHIFT8), agNULL, agNULL);
349         }
350 
351         if (agNULL != saRoot)
352         {
353           /* mask off reset FW status */
354           saRoot->chipStatus &= ~CHIP_RESET_FW;
355         }
356         break;
357       }
358     }
359     /* Unsupported type */
360     default:
361     {
362       SA_DBG1(("saHwReset: Unsupported reset type %X\n",resetType));
363       break;
364     }
365   }
366 
367   if (agNULL != saRoot)
368   {
369     if(sysIntsActive &&  ret == AGSA_RC_SUCCESS)
370     {
371       saSystemInterruptsActive(agRoot,agTRUE);
372     }
373 
374     saCountActiveIORequests( agRoot);
375     smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5a");
376   }
377 
378   return;
379 }
380 
381 /******************************************************************************/
382 /*! \brief Function to shutdown the Hardware
383  *
384  *  The saHwShutdown() function is called to discontinue the use of the SAS/SATA
385  *  hardware. Upon return, the SASA/SAT hardware instance does not generate any
386  *  interrupts or any other bus accesses. All LL Layer hardware host resources
387  * (i.e. both cached and noncached memory) are no longer owned by the LL Layer.
388  *
389  *  \param agRoot handles for this instance of SAS/SATA hardware
390  *
391  *  \return -void-
392  */
393 /*******************************************************************************/
394 GLOBAL void saHwShutdown(
395                         agsaRoot_t  *agRoot
396                         )
397 {
398   agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
399   bit32 spad0 = 0;
400   smTraceFuncEnter(hpDBG_VERY_LOUD,"5b");
401 
402   /* sanity check */
403   SA_ASSERT( (agNULL != agRoot), "");
404   SA_DBG1(("saHwShutdown: Shutting down .....\n"));
405 
406   if (agRoot->sdkData)
407   {
408 
409     spad0 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0);
410 
411     if(0xFFFFFFFF ==  spad0)
412     {
413       SA_ASSERT(0xFFFFFFFF ==  spad0, "saHwShutdown Chip PCI dead");
414 
415       SA_DBG1(("saHwShutdown: Chip PCI dead  SCRATCH_PAD0 0x%x\n", spad0));
416       smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5b");
417       return;
418     }
419 
420 
421 #if defined(SALLSDK_DEBUG)
422     SA_DBG1(("saHwShutdown: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0)));
423     SA_DBG1(("saHwShutdown: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1)));
424     SA_DBG1(("saHwShutdown: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2)));
425     SA_DBG1(("saHwShutdown: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3)));
426 
427     if(1)
428     {
429       mpiOCQueue_t         *circularQ;
430       int i;
431       SA_DBG4(("saHwShutdown:\n"));
432       for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ )
433       {
434         circularQ = &saRoot->outboundQueue[i];
435         OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
436         if(circularQ->producerIdx != circularQ->consumerIdx)
437         {
438           SA_DBG1(("saHwShutdown: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx ));
439         }
440       }
441     }
442 #endif /* SALLSDK_DBG */
443 
444     if(smIS_SPCV(agRoot))
445     {
446 
447       siScratchDump(agRoot);
448 
449       SA_DBG1(("saHwShutdown: SPC_V\n" ));
450     }
451     /* Set chip status */
452     saRoot->chipStatus |= CHIP_SHUTDOWN;
453 
454     /* Un-Initialization Configuration Table */
455     mpiUnInitConfigTable(agRoot);
456     if (saRoot->swConfig.hostDirectAccessSupport && !saRoot->swConfig.hostDirectAccessMode)
457     {
458       /* HDA mode -  do HDAsoftReset */
459       if(smIS_SPC(agRoot))
460       {
461         /* HDA soft reset */
462         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
463       }
464       if(smIS_SPCV(agRoot))
465       {
466         siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
467         SA_DBG1(("saHwShutdown: HDA saRoot->ChipId == VEN_DEV_SPCV\n"));
468       }
469     }
470     else
471     {
472       /*  do Normal softReset */
473       if(smIS_SPC(agRoot))
474       {
475         /* Soft Reset the SPC */
476         siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
477       }
478       if(smIS_SPCV(agRoot))
479       {
480         SA_DBG1(("saHwShutdown: saRoot->ChipId == VEN_DEV_SPCV\n"));
481         siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE);
482       }
483 
484     }
485 
486     /* clean the LL resources */
487     siInitResources(agRoot,
488                     &saRoot->memoryAllocated,
489                     &saRoot->hwConfig,
490                     &saRoot->swConfig,
491                     saRoot->usecsPerTick);
492     SA_DBG1(("saHwShutdown: Shutting down Complete\n"));
493   }
494   else
495   {
496     SA_DBG1(("saHwShutdown: No saRoot\n"));
497     if( smIS_SPCV(agRoot) )
498     {
499       siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE);
500     }
501     else
502     {
503        siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
504     }
505   }
506   /* agroot/saroot null do not access -trace OK */
507 
508   SA_ASSERT( (agNULL != agRoot), "10");
509   /* return */
510   smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5b");
511   return;
512 }
513 
514 
515 /******************************************************************************/
516 /*! \brief Generic Reset
517  *
518  *  The siChipReset() function is called to reset the SPC chip. Upon return,
519  *  the SPC chip got reset. The PCIe bus got reset.
520  *
521  *  \param agRoot handles for this instance of SAS/SATA hardware
522  *
523  *  \return -void-
524  */
525 /*******************************************************************************/
526 
527 GLOBAL void siChipReset(
528                       agsaRoot_t  *agRoot
529                 )
530 {
531   agsaLLRoot_t      *saRoot;
532 
533   /* sanity check */
534   SA_ASSERT( (agNULL != agRoot), "");
535 
536   saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
537   if(agNULL != saRoot)
538   {
539     smTraceFuncEnter(hpDBG_VERY_LOUD,"2C");
540 
541     SA_DBG1(("siChipReset: saRoot->ChipId == VEN_DEV_SPCV\n"));
542     if(smIS_SPC(agRoot) )
543     {
544       /* Soft Reset the SPC */
545       siChipResetSpc(   agRoot);
546     }else /* saRoot->ChipId == VEN_DEV_SPCV */
547     {
548       siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE);
549     }
550     smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2C");
551   }
552 
553 }
554 
555 
556 /******************************************************************************/
557 /*! \brief Function to Reset the SPC V Hardware
558  *
559  *  The siChipResetV() function is called to reset the SPC chip. Upon return,
560  *  the SPC chip got reset. The PCIe bus got reset.
561  *
562  *  \param agRoot handles for this instance of SAS/SATA hardware
563  *
564  *  \return -void-
565  */
566 /*******************************************************************************/
567 
568 GLOBAL bit32 siChipResetV(
569                        agsaRoot_t  *agRoot,
570                        bit32       signature
571                        )
572 {
573   bit32 regVal;
574   bit32 returnVal = AGSA_RC_SUCCESS;
575 
576   smTraceFuncEnter(hpDBG_VERY_LOUD,"3A");
577   smTrace(hpDBG_LOUD,"Lr",ossaTimeStamp64(agRoot));
578   regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister );
579 
580   SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal));
581 
582   if (signature == SPC_SOFT_RESET_SIGNATURE)
583   {
584     SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal));
585     regVal = SPCv_Reset_Write_NormalReset;
586   }
587   else if (signature == SPC_HDASOFT_RESET_SIGNATURE)
588   {
589     SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal));
590     regVal = SPCv_Reset_Write_SoftResetHDA;
591   }
592   else
593   {
594     SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X  regVal 0x%X  a\n",signature ,regVal));
595     regVal = 1;
596   }
597 
598   smTrace(hpDBG_LOUD,"Ls",ossaTimeStamp64(agRoot));
599   ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */
600   smTrace(hpDBG_LOUD,"Lt",ossaTimeStamp64(agRoot));
601   ossaStallThread(agRoot, (500 * 1000)); /* wait 500 milliseconds or PCIe will hang */
602   /* Soft reset sequence (Normal mode) */
603   smTrace(hpDBG_LOUD,"Lv",ossaTimeStamp64(agRoot));
604 
605   if (signature == SPC_HDASOFT_RESET_SIGNATURE)
606   {
607     bit32 hda_status;
608 
609     hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28));
610 
611     SA_DBG1(("siChipResetV: hda_status 0x%x\n",hda_status));
612 
613     if((hda_status  & SPC_V_HDAR_RSPCODE_MASK)  != SPC_V_HDAR_IDLE)
614     {
615       SA_DBG1(("siChipResetV:SPC_HDASOFT_RESET_SIGNATURE SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)));
616     }
617 
618     SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal));
619 
620     regVal =   ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */
621     SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE  %X\n",regVal));
622 
623     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset)
624     {
625       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
626       returnVal = AGSA_RC_FAILURE;
627     }
628     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred  )
629     {
630       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
631       returnVal = AGSA_RC_FAILURE;
632     }
633     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred)
634     {
635       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_SUCCESS %X\n",regVal));
636       returnVal = AGSA_RC_SUCCESS;
637     }
638     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred)
639     {
640       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
641       returnVal = AGSA_RC_FAILURE;
642     }
643     if(regVal  == 0xFFFFFFFF)
644     {
645       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
646       returnVal = AGSA_RC_FAILURE;
647     }
648 
649     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x a\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)));
650 
651     smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3A");
652     return returnVal;
653   }
654   else if (signature == SPC_SOFT_RESET_SIGNATURE)
655   {
656     bit32 SCRATCH_PAD1;
657     bit32 max_wait_time;
658     bit32 max_wait_count;
659     smTrace(hpDBG_LOUD,"Lw",ossaTimeStamp64(agRoot));
660     regVal =   ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */
661     SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE  0x%X\n",regVal));
662 
663     if(regVal  == 0xFFFFFFFF)
664     {
665       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
666       returnVal = AGSA_RC_FAILURE;
667     }
668     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset)
669     {
670       SA_DBG1(("siChipResetV:SPC_SOFT_RESET_SIGNATURE  AGSA_RC_FAILURE %X\n",regVal));
671       returnVal = AGSA_RC_FAILURE;
672     }
673     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred)
674     {
675       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal));
676       returnVal = AGSA_RC_FAILURE;
677     }
678     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred)
679     {
680       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal));
681       returnVal = AGSA_RC_FAILURE;
682     }
683     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred  )
684     {
685       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_SUCCESS 0x%X\n",regVal));
686       returnVal = AGSA_RC_SUCCESS;
687     }
688     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x b\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)));
689 
690     if( returnVal != AGSA_RC_SUCCESS)
691     {
692       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)  & SCRATCH_PAD1_V_BOOTSTATE_MASK;
693       if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM )
694       {
695         SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SEEPROM\n"));
696         return (returnVal);
697       }
698       else if(SCRATCH_PAD1 ==  SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP)
699       {
700         SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_BOOTSTRAP\n"));
701         return (returnVal);
702       }
703       else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET )
704       {
705         SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SOFTRESET\n"));
706         return (returnVal);
707       }
708       else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR )
709       {
710         SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_CRIT_ERROR\n"));
711         smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3A");
712         return (returnVal);
713       }
714     }
715 
716      /* RESET */
717     smTrace(hpDBG_LOUD,"Lx",ossaTimeStamp64(agRoot));
718     max_wait_time = (100 * 1000); /* wait 100 milliseconds */
719     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
720     do
721     {
722       ossaStallThread(agRoot, WAIT_INCREMENT);
723       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
724     } while ((SCRATCH_PAD1  == 0xFFFFFFFF  ) && (max_wait_count -= WAIT_INCREMENT));
725 
726     smTrace(hpDBG_LOUD,"Ly",ossaTimeStamp64(agRoot));
727     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x (0x%x) PCIe ready took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
728     /* ILA */
729     max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */
730     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
731     do
732     {
733       ossaStallThread(agRoot, WAIT_INCREMENT);
734       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
735     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT));
736     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
737 
738     if (!max_wait_count)
739     {
740       returnVal = AGSA_RC_FAILURE;
741       SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x)  not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1));
742     }
743     /* RAAE */
744     smTrace(hpDBG_LOUD,"Lz",ossaTimeStamp64(agRoot));
745     max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */
746     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
747     do
748     {
749       ossaStallThread(agRoot, WAIT_INCREMENT);
750       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
751     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT));
752 
753     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
754 
755     if (!max_wait_count)
756     {
757       returnVal = AGSA_RC_FAILURE;
758       SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1));
759     }
760     /* IOP0 */
761     smTrace(hpDBG_LOUD,"La",ossaTimeStamp64(agRoot));
762     max_wait_time = (600 * 1000); /* wait 600 milliseconds */
763     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
764     do
765     {
766       ossaStallThread(agRoot, WAIT_INCREMENT);
767       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
768     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT));
769     SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x  SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
770 
771     if (!max_wait_count)
772     {
773       returnVal = AGSA_RC_FAILURE;
774       SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1));
775     }
776 
777     if(smIS_SPCV_2_IOP(agRoot))
778     {
779       /* IOP1 */
780       smTrace(hpDBG_LOUD,"Lb",ossaTimeStamp64(agRoot));
781       max_wait_time = (200 * 1000); /* wait 200 milliseconds */
782       max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
783       do
784       {
785         ossaStallThread(agRoot, WAIT_INCREMENT);
786         SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
787       } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT));
788       SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP1_MASK (0x%x) (0x%x)(0x%x)\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP1_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
789 
790       if (!max_wait_count)
791       {
792         returnVal = AGSA_RC_FAILURE;
793         SA_DBG1(("siChipResetV: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1));
794       }
795     }
796     smTrace(hpDBG_LOUD,"Lc",ossaTimeStamp64(agRoot));
797     regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister );
798     SA_DBG1(("siChipResetV: Reset done 0x%X ERROR_STATE 0x%X\n",regVal,
799     SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) ));
800     if(SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)) )
801     {
802       smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3A");
803       return AGSA_RC_FAILURE;
804     }
805 
806   }
807   else  /* signature = unknown */
808   {
809     smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3A");
810     return AGSA_RC_FAILURE;
811   }
812 
813   smTrace(hpDBG_LOUD,"Ld",ossaTimeStamp64(agRoot));
814 
815   SA_DBG1(("siChipResetV: out V_SoftResetRegister  %08X\n",  ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister) ));
816 #ifdef SOFT_RESET_TEST
817   DbgPrint("SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1));
818 #endif
819   smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "3A");
820   return returnVal;
821 
822 }
823 /******************************************************************************/
824 /*! \brief Function to Reset the SPC Hardware
825  *
826  *  The siChipResetSpc() function is called to reset the SPC chip. Upon return,
827  *  the SPC chip got reset. The PCIe bus got reset.
828  *
829  *  \param agRoot handles for this instance of SAS/SATA hardware
830  *
831  *  \return -void-
832  */
833 /*******************************************************************************/
834 GLOBAL void siChipResetSpc(
835                       agsaRoot_t  *agRoot
836                       )
837 {
838     bit32        regVal;
839 
840     smTraceFuncEnter(hpDBG_VERY_LOUD,"5c");
841 
842     SA_DBG1(("siChipResetSpc: Chip Reset start\n"));
843 
844     /* Reset the chip */
845     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
846     regVal &= ~(SPC_REG_RESET_DEVICE);
847     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */
848 
849     /* delay 10 usec */
850     ossaStallThread(agRoot, WAIT_INCREMENT);
851 
852     /* bring chip reset out of reset */
853     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
854     regVal |= SPC_REG_RESET_DEVICE;
855     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */
856 
857     /* delay 10 usec */
858     ossaStallThread(agRoot, WAIT_INCREMENT);
859 
860     /* wait for 20 msec until the firmware gets reloaded */
861     ossaStallThread(agRoot, (20 * 1000));
862 
863     smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5c");
864 
865     SA_DBG1(("siChipResetSpc: Chip Reset Complete\n"));
866 
867     return;
868 }
869 
870 
871 GLOBAL bit32 siSoftReset(
872                        agsaRoot_t  *agRoot,
873                        bit32       signature
874                        )
875 {
876   bit32 ret = AGSA_RC_SUCCESS;
877 
878   if(smIS_SPCV(agRoot))
879   {
880     ret = si_V_SoftReset(agRoot, signature  );
881   }
882   else
883   {
884     ret = siSpcSoftReset(agRoot, signature  );
885   }
886 
887   return(ret);
888 }
889 
890 LOCAL bit32 si_V_SoftReset(
891                        agsaRoot_t  *agRoot,
892                        bit32       signature
893                        )
894 {
895 
896   bit32 ret = AGSA_RC_SUCCESS;
897 
898   ret = siChipResetV(agRoot, signature);
899 
900   if (signature == SPC_SOFT_RESET_SIGNATURE)
901   {
902     SA_DBG1(("si_V_SoftReset:SPC_SOFT_RESET_SIGNATURE\n"));
903   }
904   else if (signature == SPC_HDASOFT_RESET_SIGNATURE)
905   {
906     SA_DBG1(("si_V_SoftReset: SPC_HDASOFT_RESET_SIGNATURE\n"));
907   }
908 
909   SA_DBG1(("si_V_SoftReset: Reset Complete status 0x%X\n",ret));
910   return ret;
911 }
912 
913 /******************************************************************************/
914 /*! \brief Function to soft/FW reset the SPC
915  *
916  *  The siSpcSoftReset() function is called to soft reset SPC. Upon return,
917  *  the SPC FW got reset. The PCIe bus is not touched.
918  *
919  *  \param agRoot    handles for this instance of SAS/SATA hardware
920  *  \param signature soft reset normal signature or HDA soft reset signature
921  *
922  *  \return -void-
923  */
924 /*******************************************************************************/
925 GLOBAL bit32 siSpcSoftReset(
926                        agsaRoot_t  *agRoot,
927                        bit32       signature
928                        )
929 {
930     spc_configMainDescriptor_t mainCfg;
931     bit32                      regVal, toggleVal;
932     bit32                      max_wait_time;
933     bit32                      max_wait_count;
934     bit32                      regVal1, regVal2, regVal3;
935 
936 
937     /* sanity check */
938     SA_ASSERT( (agNULL != agRoot), "agNULL != agRoot");
939     if(agNULL != agRoot->sdkData)
940     {
941       smTraceFuncEnter(hpDBG_VERY_LOUD,"5t");
942     }
943 
944     SA_DBG1(("siSpcSoftReset: start\n"));
945 
946 
947 #if defined(SALLSDK_DEBUG)
948     /* count SoftReset */
949     gLLSoftResetCounter++;
950     SA_DBG1(("siSpcSoftReset: ResetCount = 0x%x\n", gLLSoftResetCounter));
951 #endif
952 
953     /* step1: Check FW is ready for soft reset */
954 
955     smTrace(hpDBG_VERY_LOUD,"Q1", 1);
956     /* TP:Q1 siSpcSoftReset */
957 
958     if(AGSA_RC_FAILURE == siSpcSoftResetRDYChk(agRoot))
959     {
960       SA_DBG1(("siSoftReset:siSoftResetRDYChk failed\n"));
961       if(agNULL != agRoot->sdkData)
962       {
963         smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5t");
964       }
965       return AGSA_RC_FAILURE;
966     }
967 
968      /* step 2: clear NMI status register on AAP1 and IOP, write the same value to clear */
969     /* map 0x60000 to BAR4(0x20), BAR2(win) */
970     smTrace(hpDBG_VERY_LOUD,"Q2", 2);
971     /* TP:Q2 siSpcSoftReset */
972     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_AAP1_ADDR_BASE))
973     {
974       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_AAP1_ADDR_BASE));
975       if(agNULL != agRoot->sdkData)
976       {
977         smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5t");
978       }
979 
980       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",1));
981       return AGSA_RC_FAILURE;
982     }
983     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP);
984     SA_DBG1(("MBIC(A) - NMI Enable VPE0 (IOP): = 0x%x\n", regVal));
985     ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);   /* siSpcSoftReset */
986 
987     /* map 0x70000 to BAR4(0x20), BAR2(win) */
988     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_IOP_ADDR_BASE))
989     {
990       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_IOP_ADDR_BASE));
991       if(agNULL != agRoot->sdkData)
992       {
993         smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5t");
994       }
995       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",2));
996       return AGSA_RC_FAILURE;
997     }
998     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1);
999     SA_DBG1(("MBIC(A) - NMI Enable VPE0 (AAP1): = 0x%x\n", regVal));
1000     ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); /* siSpcSoftReset */
1001 
1002     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE);
1003     SA_DBG1(("PCIE - Event Interrupt Enable Register: = 0x%x\n", regVal));
1004     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
1005 
1006     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT);
1007     SA_DBG1(("PCIE - Event Interrupt Register: = 0x%x\n", regVal));
1008     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal);  /* siSpcSoftReset */
1009 
1010     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE);
1011     SA_DBG1(("PCIE - Error Interrupt Enable Register: = 0x%x\n", regVal));
1012     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
1013 
1014     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT);
1015     SA_DBG1(("PCIE - Error Interrupt Register: = 0x%x\n", regVal));
1016     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */
1017 
1018     /* read the scratch pad 1 register bit 2 */
1019     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1020     toggleVal = regVal ^ SCRATCH_PAD1_RST;
1021 
1022     /* set signature in host scratch pad0 register to tell SPC that the host performs the soft reset */
1023     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, signature);
1024 
1025     /* read required registers for confirmming */
1026     /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1027     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE))
1028     {
1029       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE));
1030       if(agNULL != agRoot->sdkData)
1031       {
1032         smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5t");
1033       }
1034       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",3));
1035       return AGSA_RC_FAILURE;
1036     }
1037 
1038     SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET)));
1039 
1040     smTrace(hpDBG_VERY_LOUD,"Q3", 3);
1041     /* TP:Q3 siSpcSoftReset */
1042 
1043     /* step 3: host read GSM Configuration and Reset register */
1044     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET);
1045     /* Put those bits to low */
1046     /* GSM XCBI offset = 0x70 0000
1047       0x00 Bit 13 COM_SLV_SW_RSTB 1
1048       0x00 Bit 12 QSSP_SW_RSTB 1
1049       0x00 Bit 11 RAAE_SW_RSTB 1
1050       0x00 Bit 9   RB_1_SW_RSTB 1
1051       0x00 Bit 8   SM_SW_RSTB 1
1052       */
1053     regVal &= ~(0x00003b00);
1054     /* host write GSM Configuration and Reset register */
1055     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1056     SA_DBG1(("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET)));
1057 
1058 #if defined(SALLSDK_DEBUG)
1059     /* debugging messge */
1060     SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR)));
1061 
1062     SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC)));
1063     SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC)));
1064     SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC)));
1065 #endif
1066 
1067     /* step 4: */
1068     /* disable GSM - Read Address Parity Check */
1069     smTrace(hpDBG_VERY_LOUD,"Q4", 4);
1070     /* TP:Q4 siSpcSoftReset */
1071     regVal1 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK);
1072     SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal1));
1073     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1074     SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK)));
1075 
1076     /* disable GSM - Write Address Parity Check */
1077     regVal2 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK);
1078     SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal2));
1079     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1080     SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK)));
1081 
1082     /* disable GSM - Write Data Parity Check */
1083     regVal3 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK);
1084     SA_DBG1(("GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", regVal3));
1085     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1086     SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK)));
1087     /* step 5-a: delay 10 usec */
1088     smTrace(hpDBG_VERY_LOUD,"Q5", 5);
1089     /* TP:Q5 siSpcSoftReset */
1090     ossaStallThread(agRoot, 10);
1091 
1092     /* step 5-b: set GPIO-0 output control to tristate anyway */
1093     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GPIO_ADDR_BASE))
1094     {
1095       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GPIO_ADDR_BASE));
1096       if(agNULL != agRoot->sdkData)
1097       {
1098         smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5t");
1099       }
1100       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",4));
1101       return AGSA_RC_FAILURE;
1102     }
1103     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
1104     SA_DBG1(("GPIO Output Control Register: = 0x%x\n", regVal));
1105     /* set GPIO-0 output control to tri-state */
1106     regVal &= 0xFFFFFFFC;
1107     ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */
1108 
1109     /* Step 6: Reset the IOP and AAP1 */
1110     /* map 0x00000 to BAR4(0x20), BAR2(win) */
1111     smTrace(hpDBG_VERY_LOUD,"Q6", 6);
1112     /* TP:Q6 siSpcSoftReset */
1113     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE))
1114     {
1115       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE));
1116       if(agNULL != agRoot->sdkData)
1117       {
1118         smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5t");
1119       }
1120       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5));
1121       return AGSA_RC_FAILURE;
1122     }
1123     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1124     SA_DBG1(("Top Register before resetting IOP/AAP1: = 0x%x\n", regVal));
1125     regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1126     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1127 
1128     /* step 7: Reset the BDMA/OSSP */
1129     smTrace(hpDBG_VERY_LOUD,"Q7", 7);
1130     /* TP:Q7 siSpcSoftReset */
1131     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1132     SA_DBG1(("Top Register before resetting BDMA/OSSP: = 0x%x\n", regVal));
1133     regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1134     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1135 
1136     /* step 8: delay 10 usec */
1137     smTrace(hpDBG_VERY_LOUD,"Q8", 8);
1138     /* TP:Q8 siSpcSoftReset */
1139 
1140     ossaStallThread(agRoot, WAIT_INCREMENT);
1141 
1142     /* step 9: bring the BDMA and OSSP out of reset */
1143     smTrace(hpDBG_VERY_LOUD,"Q9", 9);
1144     /* TP:Q9 siSpcSoftReset */
1145     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1146     SA_DBG1(("Top Register before bringing up BDMA/OSSP: = 0x%x\n", regVal));
1147     regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1148     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1149 
1150     /* step 10: delay 10 usec */
1151     smTrace(hpDBG_VERY_LOUD,"QA", 10);
1152     /* TP:QA siSpcSoftReset */
1153     ossaStallThread(agRoot, WAIT_INCREMENT);
1154 
1155     /* step 11: reads and sets the GSM Configuration and Reset Register */
1156     /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1157     smTrace(hpDBG_VERY_LOUD,"QB", 11);
1158     /* TP:QB siSpcSoftReset */
1159     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE))
1160     {
1161       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE));
1162       if(agNULL != agRoot->sdkData)
1163       {
1164         smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5t");
1165       }
1166       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5));
1167       return AGSA_RC_FAILURE;
1168     }
1169     SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET)));
1170     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET);
1171     /* Put those bits to high */
1172     /* GSM XCBI offset = 0x70 0000
1173       0x00 Bit 13 COM_SLV_SW_RSTB 1
1174       0x00 Bit 12 QSSP_SW_RSTB 1
1175       0x00 Bit 11 RAAE_SW_RSTB 1
1176       0x00 Bit 9   RB_1_SW_RSTB 1
1177       0x00 Bit 8   SM_SW_RSTB 1
1178       */
1179     regVal |= (GSM_CONFIG_RESET_VALUE);
1180     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1181     SA_DBG1(("GSM 0x0 (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET)));
1182 
1183 #if defined(SALLSDK_DEBUG)
1184     /* debugging messge */
1185     SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR)));
1186     SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC)));
1187     SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC)));
1188     SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC)));
1189 #endif
1190 
1191     /* step 12: Restore GSM - Read Address Parity Check */
1192     smTrace(hpDBG_VERY_LOUD,"QC", 12);
1193     /* TP:QC siSpcSoftReset */
1194     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); /* just for debugging */
1195     SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal));
1196     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, regVal1); /* siSpcSoftReset */
1197     SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK)));
1198 
1199     /* Restore GSM - Write Address Parity Check */
1200     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); /* just for debugging */
1201     SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal));
1202     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); /* siSpcSoftReset */
1203     SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK)));
1204 
1205     /* Restore GSM - Write Data Parity Check */
1206     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); /* just for debugging */
1207     SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable = 0x%x\n", regVal));
1208     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); /* siSpcSoftReset */
1209     SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK)));
1210 
1211     /* step 13: bring the IOP and AAP1 out of reset */
1212     /* map 0x00000 to BAR4(0x20), BAR2(win) */
1213     smTrace(hpDBG_VERY_LOUD,"QD", 13);
1214     /* TP:QD siSpcSoftReset */
1215     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE))
1216     {
1217       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE));
1218       if(agNULL != agRoot->sdkData)
1219       {
1220         smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5t");
1221       }
1222       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",7));
1223       return AGSA_RC_FAILURE;
1224     }
1225     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1226     SA_DBG1(("Top Register before bringing up IOP/AAP1: = 0x%x\n", regVal));
1227     regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1228     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1229 
1230     if (signature == SPC_SOFT_RESET_SIGNATURE)
1231     {
1232       /* step 14: delay 20 milli - Normal Mode */
1233       ossaStallThread(agRoot, WAIT_INCREMENT);
1234     }else if (signature == SPC_HDASOFT_RESET_SIGNATURE)
1235     {
1236       /* step 14: delay 200 milli - HDA Mode */
1237       ossaStallThread(agRoot, 200 * 1000);
1238     }
1239 
1240     /* check Soft Reset Normal mode or Soft Reset HDA mode */
1241     if (signature == SPC_SOFT_RESET_SIGNATURE)
1242     {
1243         /* step 15 (Normal Mode): wait until scratch pad1 register bit 2 toggled */
1244         max_wait_time = WAIT_SECONDS(2);  /* 2 sec */
1245         max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1246         do
1247         {
1248             ossaStallThread(agRoot, WAIT_INCREMENT);
1249             regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1250         } while ((regVal != toggleVal) && (max_wait_count -=WAIT_INCREMENT));
1251 
1252         if ( !max_wait_count)
1253         {
1254             regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1255             SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal));
1256             if(agNULL != agRoot->sdkData)
1257             {
1258               smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5t");
1259             }
1260 #if defined(SALLSDK_DEBUG)
1261             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1262             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1263             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1264 #endif
1265             SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",8));
1266             return AGSA_RC_FAILURE;
1267         }
1268 
1269     /* step 16 (Normal)step 15 (HDA) - Clear ODMR and ODCR */
1270         smTrace(hpDBG_VERY_LOUD,"QG", 16);
1271         /* TP:QG siSpcSoftReset */
1272 
1273         ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL);
1274         ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL);
1275     }
1276     else if (signature == SPC_HDASOFT_RESET_SIGNATURE)
1277     {
1278       if(agNULL != agRoot->sdkData)
1279       {
1280         SA_DBG1(("siSpcSoftReset: HDA Soft Reset Complete\n"));
1281         smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5t");
1282       }
1283       return AGSA_RC_SUCCESS;
1284     }
1285 
1286 
1287     /* step 17 (Normal Mode): wait for the FW and IOP to get ready - 1 sec timeout */
1288     /* Wait for the SPC Configuration Table to be ready */
1289     if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE)
1290     {
1291        regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1292        /* return error if MPI Configuration Table not ready */
1293        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal));
1294        regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
1295        /* return error if MPI Configuration Table not ready */
1296        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal));
1297        if(agNULL != agRoot->sdkData)
1298        {
1299           smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5t");
1300        }
1301 #if defined(SALLSDK_DEBUG)
1302        SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1303        SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1304 #endif
1305        SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",9));
1306             return AGSA_RC_FAILURE;
1307     }
1308     smTrace(hpDBG_VERY_LOUD,"QI", 18);
1309     /* TP:QI siSpcSoftReset */
1310 
1311     if(agNULL != agRoot->sdkData)
1312     {
1313       smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5t");
1314     }
1315 
1316     SA_DBG1(("siSpcSoftReset: Soft Reset Complete\n"));
1317 
1318     return AGSA_RC_SUCCESS;
1319 }
1320 
1321 /******************************************************************************/
1322 /*! \brief Function to do BAR shifting
1323  *
1324  *  The siBarShift() function is called to shift BAR base address
1325  *
1326  *  \param agRoot handles for this instance of SAS/SATA hardware
1327  *  \param shiftValue shifting value
1328  *
1329  *  \return success or fail
1330  */
1331 /*******************************************************************************/
1332 GLOBAL bit32 siBar4Shift(
1333                       agsaRoot_t  *agRoot,
1334                       bit32       shiftValue
1335                       )
1336 {
1337     bit32 regVal;
1338     bit32 max_wait_time;
1339     bit32 max_wait_count;
1340 
1341     smTraceFuncEnter(hpDBG_VERY_LOUD,"5e");
1342     smTrace(hpDBG_VERY_LOUD,"GA",shiftValue);
1343     /* TP:GA shiftValue */
1344 
1345     SA_DBG2(("siBar4Shift: shiftValue 0x%x\n",shiftValue));
1346 
1347     if(smIS_SPCV(agRoot) )
1348     {
1349       ossaHwRegWriteExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister, shiftValue);
1350       /* confirm the setting is written */
1351       max_wait_time = WAIT_SECONDS(1);  /* 1 sec */
1352       max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1353       do
1354       {
1355         ossaStallThread(agRoot, WAIT_INCREMENT);
1356         regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister);
1357       } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT));
1358 
1359       if (!max_wait_count)
1360       {
1361         SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal));
1362         smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5e");
1363         return AGSA_RC_FAILURE;
1364       }
1365     }
1366     else if(smIS_SPC(agRoot))
1367     {
1368       /* program the inbound AXI translation Lower Address */
1369       ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
1370 
1371       /* confirm the setting is written */
1372       max_wait_time = WAIT_SECONDS(1);  /* 1 sec */
1373       max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1374       do
1375       {
1376         ossaStallThread(agRoot, WAIT_INCREMENT);
1377         regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW);
1378       } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT));
1379 
1380       if (!max_wait_count)
1381       {
1382         SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal));
1383         smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5e");
1384         return AGSA_RC_FAILURE;
1385       }
1386     }
1387     else
1388     {
1389         SA_DBG1(("siBar4Shift: hba type is not support\n"));
1390         return AGSA_RC_FAILURE;
1391     }
1392     smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5e");
1393 
1394     return AGSA_RC_SUCCESS;
1395 }
1396 
1397 #ifdef SA_ENABLE_HDA_FUNCTIONS
1398 /******************************************************************************/
1399 /*! \brief Function to force HDA mode the SPC
1400  *
1401  *  The siHDAMode() function is called to force to HDA mode. Upon return,
1402  *  the SPC FW loaded. The PCIe bus is not touched.
1403  *
1404  *  \param agRoot handles for this instance of SAS/SATA hardware
1405  *  \param HDAMode 0 - HDA soft reset mode, 1 - HDA mode
1406  *  \param fwImg points to structure containing fw images
1407  *
1408  *  \return -void-
1409  */
1410 /*******************************************************************************/
1411 GLOBAL bit32 siHDAMode(
1412                       agsaRoot_t  *agRoot,
1413                       bit32       HDAMode,
1414                       agsaFwImg_t *userFwImg
1415                       )
1416 {
1417     spc_configMainDescriptor_t mainCfg;
1418     bit32                      regVal;
1419     bit32                      max_wait_time;
1420     bit32                      max_wait_count;
1421     agsaFwImg_t                flashImg;
1422     bit32                      startTime, endTime; // TestBase
1423     bit32                      stepTime[12]; // TestBase
1424 
1425     bit32 HDA_Been_Reset = agFALSE;
1426 
1427     smTraceFuncEnter(hpDBG_VERY_LOUD,"5d");
1428 
1429     /* sanity check */
1430     SA_ASSERT( (agNULL != agRoot), "");
1431 
1432     SA_DBG1(("siHDAMode: start\n"));
1433 
1434     si_memset(&flashImg, 0, sizeof(flashImg));
1435 #ifndef SA_EXCLUDE_FW_IMG
1436 
1437     /* Set up built-in (default) FW image pointers */
1438 /*
1439     flashImg.aap1Img = (bit8*)(&aap1array);
1440     flashImg.aap1Len = sizeof(aap1array);
1441     flashImg.ilaImg  = (bit8*)(&ilaarray);
1442     flashImg.ilaLen  = sizeof(ilaarray);
1443     flashImg.iopImg  = (bit8*)(&ioparray);
1444     flashImg.iopLen  = sizeof(ioparray);
1445 */
1446 #endif
1447     TryAfterReset:
1448 
1449     /* Set up user FW image pointers (if passed in) */
1450     if (userFwImg)
1451     {
1452       SA_DBG1(("siHDAMode: User fw structure @ %p\n",userFwImg));
1453       if (userFwImg->aap1Img && userFwImg->aap1Len)
1454       {
1455         flashImg.aap1Img = userFwImg->aap1Img;
1456         flashImg.aap1Len = userFwImg->aap1Len;
1457         SA_DBG1(("siHDAMode: User fw aap1 @ %p (%d)\n", flashImg.aap1Img, flashImg.aap1Len));
1458       }
1459       if (userFwImg->ilaImg && userFwImg->ilaLen)
1460       {
1461         flashImg.ilaImg = userFwImg->ilaImg;
1462         flashImg.ilaLen = userFwImg->ilaLen;
1463         SA_DBG1(("siHDAMode: User fw ila @ %p (%d)\n",  flashImg.ilaImg, flashImg.ilaLen));
1464       }
1465       if (userFwImg->iopImg && userFwImg->iopLen)
1466       {
1467         flashImg.iopImg = userFwImg->iopImg;
1468         flashImg.iopLen = userFwImg->iopLen;
1469         SA_DBG1(("siHDAMode: User fw iop @ %p (%d)\n", flashImg.iopImg, flashImg.iopLen));
1470       }
1471       if (userFwImg->istrImg && userFwImg->istrLen)
1472       {
1473         flashImg.istrImg = userFwImg->istrImg;
1474         flashImg.istrLen = userFwImg->istrLen;
1475         SA_DBG1(("siHDAMode: User fw istr @ %p (%d)\n", flashImg.istrImg, flashImg.istrLen));
1476       }
1477     }
1478     else
1479     {
1480       SA_DBG1(("siHDAMode: user supplied FW is not found\n"));
1481       smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5d");
1482       return AGSA_RC_FAILURE;
1483     }
1484 
1485 #ifdef SA_EXCLUDE_FW_IMG
1486     /* Check that fw images are setup properly */
1487     if (!(flashImg.aap1Img && flashImg.aap1Len &&
1488           flashImg.ilaImg  && flashImg.ilaLen  &&
1489           flashImg.iopImg  && flashImg.iopLen  &&
1490           flashImg.istrImg && flashImg.istrLen))
1491     {
1492       SA_DBG1(("siHDAMode: Built-in FW img excluded and not user defined.\n"));
1493       smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5d");
1494       return AGSA_RC_FAILURE;
1495     }
1496 #endif
1497 
1498     /* Check HDA mode with Soft Reset */
1499     if (!HDAMode)
1500     {
1501       /* Try soft reset until it goes into HDA mode */
1502       siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
1503 
1504       /* read response state */
1505       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1506       if (regVal != BOOTTLOADERHDA_IDLE)
1507       {
1508         /* Can not go into HDA mode with 200 ms wait - HDA Soft Reset failed */
1509         SA_DBG1(("siHDAMode: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1510         smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5d");
1511         return AGSA_RC_FAILURE;
1512       }
1513 
1514       /* HDA Mode - Clear ODMR and ODCR */
1515       ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL);
1516       ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL);
1517     }
1518 
1519     /* Step 1: Poll BOOTTLOADERHDA_IDLE - HDA mode */
1520     SA_DBG1(("siHDAMode: Step1:Poll for HDAR_IDLE\n"));
1521     max_wait_time = WAIT_SECONDS(gWait_2);  /* 2 sec */
1522     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1523     do
1524     {
1525       ossaStallThread(agRoot, WAIT_INCREMENT);
1526       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1527     } while ((regVal != BOOTTLOADERHDA_IDLE) && (max_wait_count -= WAIT_INCREMENT));
1528 
1529     if (!max_wait_count)
1530     {
1531 
1532       if( !HDA_Been_Reset )
1533       {
1534 
1535         SA_DBG1(("siHDAMode: Reset: Step1:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1536         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
1537         HDA_Been_Reset  = agTRUE;
1538         goto TryAfterReset;
1539 
1540       }
1541 
1542       SA_DBG1(("siHDAMode: Step1:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1543       smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5d");
1544       return AGSA_RC_FAILURE;
1545     }
1546 
1547     /* Step 2: Push the init string to 0x0047E000 & data compare */
1548     SA_DBG1(("siHDAMode: Step2:Push the init string to 0x0047E000!\n"));
1549 
1550     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, ILA_ISTR_ADDROFFSETHDA, flashImg.istrImg, flashImg.istrLen))
1551     {
1552       SA_DBG1(("siHDAMode: Step2:Copy ISTR array to 0x%x failed\n", ILA_ISTR_ADDROFFSETHDA));
1553       smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5d");
1554       return AGSA_RC_FAILURE;
1555     }
1556 
1557     /* Tell FW ISTR is ready */
1558     regVal = (HDA_ISTR_DONE | (bit32)flashImg.istrLen);
1559     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1560     SA_DBG1(("siHDAMode: Step2:Host Scratchpad 3 (AAP1-ISTR): 0x%x\n", regVal));
1561 
1562     stepTime[2] = ossaTimeStamp(agRoot);  // TestBase
1563     SA_DBG1(("siHDAMode: End Step2: (step_time[2] = %d)\n", stepTime[2]));  // TestBase
1564 
1565     /* Step 3: Write the HDA mode SoftReset signature */
1566     SA_DBG1(("siHDAMode: Step3:Set Signature!\n"));
1567     /* set signature in host scratch pad0 register to tell SPC that the host performs the HDA mode */
1568     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, SPC_HDASOFT_RESET_SIGNATURE);
1569 
1570     stepTime[3] = ossaTimeStamp(agRoot);  // TestBase
1571     SA_DBG1(("siHDAMode: End Step3: (step_time[3] =  %d)\n", stepTime[3]));  // TestBase
1572 
1573     // Priya (Apps) requested that the FW load time measurement be started here
1574     startTime = ossaTimeStamp(agRoot);
1575     SA_DBG1(("siHDAMode: Step4: Ready to push ILA to 0x00400000! (start_time =  %d)\n", startTime));  // TestBase
1576 
1577     /* Step 4: Push the ILA image to 0x00400000 */
1578     SA_DBG1(("siHDAMode: Step4:Push the ILA to 0x00400000!\n"));
1579 
1580     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, 0x0, flashImg.ilaImg, flashImg.ilaLen))
1581     {
1582       SA_DBG1(("siHDAMode:Step4:Copy ILA array to 0x%x failed\n", 0x0));
1583       smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5d");
1584       return AGSA_RC_FAILURE;
1585     }
1586 
1587     stepTime[4] = ossaTimeStamp(agRoot);
1588     SA_DBG1(("siHDAMode: End Step4: (step_time[4] = %d, %d ms)\n", stepTime[4], (stepTime[4] - startTime)));  // TestBase
1589 
1590     /* Step 5: Tell boot ROM to authenticate ILA and execute it */
1591     ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB, 0);
1592     ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_PAR_LEN_OFFSET, flashImg.ilaLen);
1593     regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16;
1594     regVal ++;
1595     regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD;
1596     SA_DBG1(("siHDAMode: Step5:Execute ILA CMD: 0x%x\n", regVal));
1597     ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_CMD_CODE_OFFSET, regVal); /* Execute Command */
1598 
1599     stepTime[5] = ossaTimeStamp(agRoot);
1600     SA_DBG1(("siHDAMode: End Step5: (step_time[5] = %d, %d ms)\n", stepTime[5], (stepTime[5] - startTime)));  // TestBase
1601 
1602 
1603     /* Step 6: Checking response status from boot ROM, HDAR_EXEC (good), HDAR_BAD_CMD and HDAR_BAD_IMG */
1604     SA_DBG1(("siHDAMode: Step6:Checking boot ROM reponse status!\n"));
1605     max_wait_time = WAIT_SECONDS(gWait_2);  /* 2 sec */
1606     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1607     do
1608     {
1609       ossaStallThread(agRoot, WAIT_INCREMENT);
1610       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1611       if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal))
1612         break;
1613     } while (max_wait_count-=WAIT_INCREMENT);
1614 
1615     if (HDAR_BAD_IMG == regVal)
1616     {
1617       SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1618       smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5d");
1619       return AGSA_RC_FAILURE;
1620     }
1621     if (HDAR_BAD_CMD == regVal)
1622     {
1623       SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1624       smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5d");
1625       return AGSA_RC_FAILURE;
1626     }
1627     if (!max_wait_count)
1628     {
1629       SA_DBG1(("siHDAMode: Step6:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1630       smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5d");
1631       return AGSA_RC_FAILURE;
1632     }
1633 
1634     stepTime[6] = ossaTimeStamp(agRoot);
1635     SA_DBG1(("siHDAMode: End Step6: (step_time[6] = %d, %d ms)\n", stepTime[6], (stepTime[6] - startTime)));  // TestBase
1636 
1637     /* Step 7: Poll ILAHDA_AAP1IMGGET/Offset in MSGU Scratchpad 0 */
1638     /* Check MSGU Scratchpad 1 [1,0] == 00 */
1639     SA_DBG1(("siHDAMode: Step7:Poll ILAHDA_AAP1_IMG_GET!\n"));
1640     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1641     SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 1: 0x%x\n", regVal));
1642     max_wait_time = WAIT_SECONDS(gWait_3);  /* 3 sec */
1643     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1644     do
1645     {
1646       ossaStallThread(agRoot, WAIT_INCREMENT);
1647       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
1648     } while ((regVal != ILAHDA_AAP1_IMG_GET) && (max_wait_count -= WAIT_INCREMENT));
1649 
1650     if (!max_wait_count)
1651     {
1652 
1653       if( !HDA_Been_Reset )
1654       {
1655 
1656         SA_DBG1(("siHDAMode: Reset: Step7:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1657         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
1658         HDA_Been_Reset  = agTRUE;
1659         goto TryAfterReset;
1660 
1661       }
1662 
1663       SA_DBG1(("siHDAMode: TIMEOUT: Step7:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1664 #if defined(SALLSDK_DEBUG)
1665       SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1666       SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1)));
1667       SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1668       SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1669 #endif
1670       smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5d");
1671       return AGSA_RC_FAILURE;
1672     }
1673     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1674     SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 0: 0x%x\n", regVal));
1675     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & 0x00FFFFFF;
1676 
1677     stepTime[7] = ossaTimeStamp(agRoot);
1678     SA_DBG1(("siHDAMode: End Step7: (step_time[7] = %d, %d ms)\n", stepTime[7], (stepTime[7] - startTime)));  // TestBase
1679 
1680     /* Step 8: Copy AAP1 image, update the Host Scratchpad 3 */
1681     SA_DBG1(("siHDAMode: Step8:Push the AAP1 to 0x00400000 plus 0x%x\n", regVal));
1682 
1683     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.aap1Img, flashImg.aap1Len))
1684     {
1685       SA_DBG1(("siHDAMode: Step8:Copy AAP1 array to 0x%x failed\n", regVal));
1686 #if defined(SALLSDK_DEBUG)
1687       SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1688       SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1)));
1689       SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1690       SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1691 #endif
1692       smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5d");
1693       return AGSA_RC_FAILURE;
1694     }
1695 
1696     regVal = (HDA_AAP1_DONE | (bit32)flashImg.aap1Len);
1697     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1698     SA_DBG1(("siHDAMode: Step8:Host Scratchpad 3 (AAP1): 0x%x\n", regVal));
1699 
1700     stepTime[8] = ossaTimeStamp(agRoot);
1701     SA_DBG1(("siHDAMode: End Step8: (step_time[8] = %d, %d ms)\n", stepTime[8], (stepTime[8] - startTime)));  // TestBase
1702 
1703     /* Step 9: Poll ILAHDA_IOPIMGGET/Offset in MSGU Scratchpad 0 */
1704     SA_DBG1(("siHDAMode: Step9:Poll ILAHDA_IOP_IMG_GET!\n"));
1705     max_wait_time = WAIT_SECONDS(gWait_2);  /* 2 sec */
1706     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
1707     do
1708     {
1709       ossaStallThread(agRoot, WAIT_INCREMENT);
1710       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
1711     } while ((regVal != ILAHDA_IOP_IMG_GET) && (max_wait_count -= WAIT_INCREMENT));
1712 
1713     if (!max_wait_count)
1714     {
1715       SA_DBG1(("siHDAMode: Step9:TIMEOUT:MSGU_SCRATCH_PAD_0 = 0x%x\n", regVal));
1716 #if defined(SALLSDK_DEBUG)
1717       SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1)));
1718       SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1719       SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1720 #endif
1721       smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5d");
1722       return AGSA_RC_FAILURE;
1723     }
1724     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1725     SA_DBG1(("siHDAMode: Step9:MSG Scratchpad 0: 0x%x\n", regVal));
1726     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & HDA_GSM_OFFSET_BITS;
1727 
1728     stepTime[9] = ossaTimeStamp(agRoot);
1729     SA_DBG1(("siHDAMode: End Step9: (step_time[9] = %d, %d ms)\n", stepTime[9], (stepTime[9] - startTime)));  // TestBase
1730 
1731     // saHdaLoadForceHalt(agRoot);  // TestBase
1732 
1733     /* Step 10: Copy IOP image, update the Host Scratchpad 3 */
1734     SA_DBG1(("siHDAMode: Step10:Push the IOP to 0x00400000 plus 0x%x!\n", regVal));
1735 
1736     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.iopImg, flashImg.iopLen))
1737     {
1738       SA_DBG1(("siHDAMode: Step10:Copy IOP array to 0x%x failed\n", regVal));
1739 #if defined(SALLSDK_DEBUG)
1740       SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1)));
1741       SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1742       SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1743 #endif
1744       smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "5d");
1745       return AGSA_RC_FAILURE;
1746     }
1747 
1748     regVal = (HDA_IOP_DONE | (bit32)flashImg.iopLen);
1749     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1750     SA_DBG1(("siHDAMode: Step10:Host Scratchpad 3 (IOP): 0x%x\n", regVal));
1751 
1752     stepTime[10] = ossaTimeStamp(agRoot);
1753     SA_DBG1(("siHDAMode: End Step10: (step_time[10] = %d, %d ms)\n", stepTime[10], (stepTime[10] - startTime)));  // TestBase
1754 
1755     /* Clear the signature */
1756     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, 0);
1757 
1758     /* step 11: wait for the FW and IOP to get ready - 1 sec timeout */
1759     /* Wait for the SPC Configuration Table to be ready */
1760     stepTime[11] = ossaTimeStamp(agRoot);
1761     SA_DBG1(("siHDAMode: Start Step11: Wait for FW ready. (step_time[11.1] =  %d, %d ms)\n", stepTime[11], (stepTime[11] - startTime))); // TestBase
1762 
1763     endTime = ossaTimeStamp(agRoot);
1764     SA_DBG1(("siHDAMode: End Step11: FW ready! (end_time= %d, fw_load_time = %d ms)\n", endTime, endTime - startTime)); // TestBase
1765 
1766     SA_DBG1(("siHDAMode: Step11:Poll for FW ready!\n"));
1767     if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE)
1768     {
1769       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1770       /* return error if MPI Configuration Table not ready */
1771       SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal));
1772       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
1773       /* return error if MPI Configuration Table not ready */
1774       SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal));
1775       /* read detail fatal errors */
1776       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1777       SA_DBG1(("siHDAMode: Step11:ScratchPad0 AAP error code 0x%x\n", regVal));
1778       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3);
1779       SA_DBG1(("siHDAMode: Step11:ScratchPad3 IOP error code 0x%x\n", regVal));
1780       smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "5d");
1781       return AGSA_RC_FAILURE;
1782     }
1783 
1784     smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "5d");
1785 
1786     SA_DBG1(("siHDAMode: HDA Mode Complete\n"));
1787 
1788     return AGSA_RC_SUCCESS;
1789 }
1790 
1791 /******************************************************************************/
1792 /*! \brief memcopy cross PCI from host memory to card memory
1793  *
1794  *  \param agRoot        handles for this instance of SAS/SATA hardware
1795  *  \param dstoffset     distination offset
1796  *  \param src           source pointer
1797  *  \param DWcount       DWord count
1798  *  \param busBaseNumber PCI Bus Base number
1799  *
1800  *  \return -void-
1801  *
1802  */
1803 /*******************************************************************************/
1804 LOCAL void siPciMemCpy(agsaRoot_t *agRoot,
1805                        bit32 dstoffset,
1806                        void *src,
1807                        bit32 DWcount,
1808                        bit32 busBaseNumber
1809                        )
1810 {
1811     bit32 i, val;
1812     bit32 *src1;
1813 
1814     src1 = (bit32 *)src;
1815 
1816     for (i= 0; i < DWcount; i++)
1817     {
1818         val = BIT32_TO_LEBIT32(src1[i]);
1819         ossaHwRegWriteExt(agRoot, busBaseNumber, (dstoffset + i * 4), val);
1820     }
1821 
1822     return;
1823 }
1824 
1825 /******************************************************************************/
1826 /*! \brief Function to copy FW array
1827  *
1828  *  The siBar4Cpy() function is called to copy FW array via BAR4
1829  *  (PCIe spec: BAR4, MEMBASE-III in PM, PCIBAR2 in host driver)
1830  *  in 64-KB MEMBASE MODE.
1831  *
1832  *  \param agRoot     handles for this instance of SAS/SATA hardware
1833  *  \param offset     destination offset
1834  *  \param parray     pointer of array
1835  *  \param array_size size of array
1836  *
1837  *  \return AGSA_RC_SUCCESS or AGSA_RC_FAILURE
1838  */
1839 /*******************************************************************************/
1840 LOCAL bit32 siBar4Cpy(
1841                       agsaRoot_t  *agRoot,
1842                       bit32       offset,
1843                       bit8        * parray,
1844                       bit32       array_size
1845                       )
1846 {
1847     bit32       dest_shift_addr, dest_offset, cpy_size;
1848 
1849     smTraceFuncEnter(hpDBG_VERY_LOUD,"5f");
1850 
1851     /* first time to shift */
1852     dest_shift_addr = (GSMSM_AXI_LOWERADDR+offset) & SHIFT_MASK;
1853     dest_offset = offset & OFFSET_MASK;
1854     do
1855     {
1856         if (AGSA_RC_FAILURE == siBar4Shift(agRoot, dest_shift_addr))
1857         {
1858             SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", dest_shift_addr));
1859             smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5f");
1860             return AGSA_RC_FAILURE;
1861         }
1862 
1863         if ((dest_offset+array_size) > SIZE_64KB)
1864         {
1865             cpy_size = SIZE_64KB - dest_offset;
1866         }
1867         else
1868             cpy_size = array_size;
1869 
1870         siPciMemCpy(agRoot, dest_offset, parray, (bit32)(CEILING(cpy_size,4)), PCIBAR2);
1871 
1872         array_size -= cpy_size;
1873         dest_shift_addr += SIZE_64KB;
1874         dest_offset = 0;
1875         parray = parray + cpy_size;
1876     } while (array_size !=0 );
1877 
1878     /* Shift back to BAR4 original address */
1879     if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0))
1880     {
1881         SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", 0x0));
1882         smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5f");
1883         return AGSA_RC_FAILURE;
1884     }
1885 
1886     smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5f");
1887 
1888     return AGSA_RC_SUCCESS;
1889 }
1890 
1891 GLOBAL
1892 bit32 siHDAMode_V(
1893                       agsaRoot_t  *agRoot,
1894                       bit32       HDAMode,
1895                       agsaFwImg_t *userFwImg
1896                       )
1897 {
1898   bit32 returnVal = AGSA_RC_FAILURE;
1899   bit32 save,i,biggest;
1900   bit32 hda_status;
1901   bit32 hda_command_complete = 0;
1902   bit32 max_wait_time;
1903   bit32 max_wait_count;
1904   bit32 seq_id = 0;
1905   bit32 base_Hi = 0;
1906   bit32 base_Lo = 0;
1907   bit8 * pbase;
1908 
1909   spcv_hda_cmd_t hdacmd;
1910   spcv_hda_rsp_t hdarsp;
1911 
1912   agsaLLRoot_t      *saRoot;
1913 
1914   /* sanity check */
1915   SA_ASSERT( (agNULL != agRoot), "");
1916 
1917   saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
1918 
1919   /* sanity check */
1920   SA_ASSERT( (agNULL != saRoot), "saRoot is NULL");
1921 
1922   smTraceFuncEnter(hpDBG_VERY_LOUD,"2W");
1923 
1924   SA_DBG1(("siHDAMode_V: HDAMode %X\n",HDAMode));
1925 
1926   siScratchDump(agRoot);
1927   if( agNULL == userFwImg)
1928   {
1929     SA_DBG1(("siHDAMode_V: No image agNULL == userFwImg\n" ));
1930     smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2W");
1931     return returnVal;
1932   }
1933 
1934   hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28));
1935 
1936   SA_DBG1(("siHDAMode_V: hda_status 0x%08X\n",hda_status ));
1937   SA_DBG1(("siHDAMode_V:                                                                   STEP 1\n"));
1938 
1939   smTrace(hpDBG_VERY_LOUD,"2X",1 );
1940   /* TP:2X STEP 1 */
1941 
1942   /* Find largest Physical chunk memory */
1943   for(i=0,biggest = 0,save = 0; i < saRoot->memoryAllocated.count; i++)
1944   {
1945     if( saRoot->memoryAllocated.agMemory[i].totalLength > biggest)
1946     {
1947 
1948       if(biggest < saRoot->memoryAllocated.agMemory[i].totalLength)
1949       {
1950         save = i;
1951         biggest = saRoot->memoryAllocated.agMemory[i].totalLength;
1952       }
1953 
1954     }
1955   }
1956 /*
1957 Step 1 The host reads the HDA response field RSP_CODE at byte offset 28:29 of the response block
1958 for HDAR_IDLE (0x8002) via MEMBASE-I. A value other than HDAR_IDLE (0x8002) indicates that the
1959 SPCv controller is not in HDA mode. Follow the steps described in Section 4.21.1 to bring the
1960 SPCv controller into HDA mode. When the host reads the correct RSP_CODE, it indicates that the
1961 SPCv controller boot ROM is ready to proceed to the next step of HDA initialization
1962 */
1963 
1964   base_Hi = saRoot->memoryAllocated.agMemory[save].phyAddrUpper;
1965   base_Lo = saRoot->memoryAllocated.agMemory[save].phyAddrLower;
1966   pbase = saRoot->memoryAllocated.agMemory[save].virtPtr;
1967   SA_DBG1(("siHDAMode_V:Use DMA memory at [%d] size 0x%x (%d) DMA Loc U 0x%08x L 0x%08x @%p\n",save,
1968                                 biggest,
1969                                 biggest,
1970                                 base_Hi,
1971                                 base_Lo,
1972                                 pbase
1973                                ));
1974 
1975 
1976   SA_DBG1(("siHDAMode_V: HDA aap1Img %p len %8d 0x%x\n", userFwImg->aap1Img, userFwImg->aap1Len , userFwImg->aap1Len ));
1977   SA_DBG1(("siHDAMode_V: HDA ilaImg  %p len %8d 0x%x\n", userFwImg->ilaImg,  userFwImg->ilaLen ,  userFwImg->ilaLen ));
1978   SA_DBG1(("siHDAMode_V: HDA iopImg  %p len %8d 0x%x\n", userFwImg->iopImg,  userFwImg->iopLen  , userFwImg->iopLen ));
1979   if(userFwImg->aap1Len > biggest)
1980   {
1981     SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d aap1Len\n", biggest ,userFwImg->aap1Len));
1982     SA_ASSERT( (agNULL != agRoot), "aap1Len > biggest");
1983     smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2W");
1984     return returnVal;
1985   }
1986   if(userFwImg->ilaLen > biggest)
1987   {
1988     SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d ilaLen\n", biggest ,userFwImg->ilaLen));
1989     SA_ASSERT( (agNULL != agRoot), "ilaLen > biggest");
1990     smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2W");
1991     return returnVal;
1992   }
1993   if(userFwImg->iopLen > biggest)
1994   {
1995     SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d iopLen\n", biggest ,userFwImg->iopLen));
1996     SA_ASSERT( (agNULL != agRoot), "iopLen > biggest");
1997     smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2W");
1998     return returnVal;
1999   }
2000 
2001 
2002   if(HDA_STEP_2)
2003   { /* ILA */
2004     si_memset(pbase, 0, biggest);
2005 
2006     if( userFwImg->ilaLen < biggest)
2007     {
2008       si_memcpy(pbase,userFwImg->ilaImg, userFwImg->ilaLen );
2009     }
2010     else
2011     {
2012       SA_DBG1(("siHDAMode_V:  userFwImg->ilaLen 0x%x < biggest 0x%x\n",userFwImg->ilaLen,biggest));
2013     }
2014 
2015     si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t));
2016     si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t));
2017 
2018     hda_status = ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28);
2019     if((hda_status  & SPC_V_HDAR_RSPCODE_MASK)  == SPC_V_HDAR_IDLE)
2020     {
2021 
2022       hdacmd.cmdparm_0 = base_Lo; /* source DmaBase_l*/
2023       hdacmd.cmdparm_1 = base_Hi; /* source DmaBase_u*/
2024       hdacmd.cmdparm_2 = 0x1e200000; /* destin */
2025       hdacmd.cmdparm_3 = 0; /* destin */
2026       hdacmd.cmdparm_4 = userFwImg->ilaLen ; /* length */
2027       hdacmd.cmdparm_5 = 0;/* not used */
2028       hdacmd.cmdparm_6 = 0;/* not used */
2029       seq_id++;
2030       hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA;
2031 
2032       SA_DBG1(("siHDAMode_V:          Write SPC_V_HDAC_DMA                                     STEP 2\n"));
2033       /*
2034       Step 2
2035       The host writes the HDAC_DMA (0x000 24) in the command field CMD_CODE via MEMBASE-I
2036       for issuing the DMA command to ask the boot ROM to pull the ILA image via DMA into
2037       GSM with the following parameters set up first:
2038       Parameter 1:0: Host physical address for holding the HDA-ILA image.
2039       Parameter 3:2: GSM physical address 0x1E20_0000.
2040       Parameter 4: the length of the HDAILA  image.
2041       */
2042 
2043       SA_DBG2(("siHDAMode_V: Write ILA to offset %X\n",hdacmd.cmdparm_2));
2044 
2045       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0,hdacmd.cmdparm_0);
2046       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4,hdacmd.cmdparm_1);
2047       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8,hdacmd.cmdparm_2);
2048       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3);
2049       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4);
2050       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5);
2051       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6);
2052       ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE);
2053 
2054       SA_DBG2(("siHDAMode_V:  Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2055                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0),
2056                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4),
2057                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8),
2058                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12),
2059                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16),
2060                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20),
2061                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24),
2062                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) ));
2063 
2064       SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE ));
2065 
2066       max_wait_time = (2000 * 1000); /* wait 2 seconds */
2067       max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2068       hda_command_complete = 0;
2069       do
2070       {
2071         ossaStallThread(agRoot, WAIT_INCREMENT);
2072         hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
2073       } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT));
2074       SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 2 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2075 
2076       smTrace(hpDBG_VERY_LOUD,"2Y",(max_wait_time -  max_wait_count) );
2077       /* TP:2Y STEP 2 took */
2078 
2079 
2080       if(! hda_command_complete)
2081       {
2082         SA_DBG1(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2083         SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2084         SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2085         SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2086         SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 2\n" ));
2087         smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2W");
2088         return returnVal;
2089       }
2090 
2091 
2092       SA_DBG2(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2093       SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2094       SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2095       SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2096 
2097     }
2098 
2099     SA_DBG1(("siHDAMode_V: ILA DMA done\n" ));
2100   } /* end ila   */
2101 
2102   if(HDA_STEP_3)
2103   {
2104 
2105     SA_DBG1(("siHDAMode_V:                                                                   STEP 3\n"));
2106     /*
2107       Step 3
2108       The host polls the HDA response field RSP_CODE for HDAR_IDLE (0x8002) via MEMBASE-I. The polling timeout
2109       should be no more than 1 second. The response status, HDAR_IDLE with its status equal to 0x10,
2110       indicates a DMA success response from the boot ROM. Response states that indicate a failure are:
2111       HDAR_BAD_CMD HDAR_BAD_IMG HDAR_IDLE with its status equal to 0x11
2112 
2113     */
2114 
2115     max_wait_time = (2000 * 1000); /* wait 2 seconds */
2116     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2117     hda_command_complete = 0;
2118     do
2119     {
2120       ossaStallThread(agRoot, WAIT_INCREMENT);
2121       hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
2122     } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT));
2123 
2124     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 3 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2125     smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time -  max_wait_count) );
2126     /* TP:2Z STEP 3 took */
2127 
2128     if(! hda_command_complete)
2129     {
2130 
2131       SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2132                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0),
2133                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4),
2134                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8),
2135                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12),
2136                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16),
2137                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20),
2138                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24),
2139                           ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) ));
2140 
2141 
2142       SA_DBG1(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2143       SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2144       SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2145       SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2146       SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 3\n" ));
2147       smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2W");
2148       return returnVal;
2149     }
2150 
2151 
2152     hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
2153     hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK );
2154 
2155     SA_DBG2(("siHDAMode_V:ILA is ready hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete));
2156 
2157     /* Tell FW ILA is ready */
2158     SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2159                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0),
2160                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4),
2161                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8),
2162                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12),
2163                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16),
2164                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20),
2165                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24),
2166                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) ));
2167 
2168     SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2169     SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2170     SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2171     SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2172 
2173     SA_DBG2(("siHDAMode_V: Step 3 MSGU_HOST_SCRATCH_PAD_3 write %X\n",HDA_ISTR_DONE));
2174     ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,HDA_ISTR_DONE );
2175 
2176     SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2177     SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2178     SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2179     SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2180 
2181   }
2182 
2183   if(HDA_STEP_4)
2184   {
2185 
2186     SA_DBG2(("siHDAMode_V: Exec ILA\n"));
2187     si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t));
2188     si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t));
2189 
2190     hdacmd.cmdparm_0 = 0x200000; /* length  SPC_V_HDAC_EXEC*/;
2191     hdacmd.cmdparm_1 = userFwImg->ilaLen ; /* length  SPC_V_HDAC_EXEC*/;
2192     seq_id++;
2193 
2194     hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC;
2195 
2196     SA_DBG1(("siHDAMode_V:                                                                   STEP 4\n"));
2197 
2198     /*
2199     Step 4
2200     The host writes the HDAC_EXEC command (0x0002) via MEMBASE-I for the boot ROM to authenticate
2201     and execute the HDA-ILA image. The host sets parameter 0 and parameter 1 for the HDA-ILA image
2202     appropriately:
2203     Parameter 0: Entry offset this value must be 0x20_0000.
2204     Parameter 1: the HDA-ILA image length.
2205     */
2206 
2207     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0 ,hdacmd.cmdparm_0);
2208     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4 ,hdacmd.cmdparm_1);
2209     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8 ,hdacmd.cmdparm_2);
2210     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3);
2211     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4);
2212     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5);
2213     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6);
2214     ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE);
2215 
2216     SA_DBG1(("siHDAMode_V: Exec ILA\n" ));
2217 
2218     SA_DBG2(("siHDAMode_V:  Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2219                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0),
2220                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4),
2221                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8),
2222                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12),
2223                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16),
2224                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20),
2225                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24),
2226                         ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) ));
2227 
2228     SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE ));
2229 
2230     SA_DBG2(("siHDAMode_V:4SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2231     SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2232     SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2233     SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2234   } // End Step 4
2235   if(HDA_STEP_5)
2236   {
2237     SA_DBG1(("siHDAMode_V:                                             start wait            STEP 5\n"));
2238 
2239     /*
2240       Step 5
2241       The host continues polling for the HDA-ILA status via MEMBASE-I. The polling timeout should
2242       be no more than 1 second. The response status HDAR_EXEC indicates a good response from the
2243       boot ROM. Response states that indicate a failure are:
2244       HDAR_BAD_CMD
2245       HDAR_BAD_IMG
2246     */
2247 
2248     max_wait_time = (2000 * 1000); /* wait 2 seconds */
2249     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2250     hda_command_complete = 0;
2251     hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK );
2252     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x Begin STEP 5\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),hda_status));
2253     hda_status = 0;
2254     do
2255     {
2256       ossaStallThread(agRoot, WAIT_INCREMENT);
2257       hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK );
2258       hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
2259     } while (hda_status != SPC_V_HDAR_EXEC && (max_wait_count -= WAIT_INCREMENT));
2260 
2261     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x hda_command_complete 0x%x STEP 5 wait for seq_id took %d\n",
2262                ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),
2263                hda_status,
2264                hda_command_complete,
2265                (max_wait_time -  max_wait_count)));
2266 
2267     smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time -  max_wait_count) );
2268     /* TP:2Z STEP 5 took */
2269 
2270     if(! hda_command_complete)
2271     {
2272         SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2273                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0),
2274                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4),
2275                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8),
2276                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12),
2277                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16),
2278                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20),
2279                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24),
2280                             ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) ));
2281 
2282       SA_DBG1(("siHDAMode_V:5SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2283       SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2284       SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2285       SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2286       SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 5\n" ));
2287       smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "2W");
2288       return returnVal;
2289     }
2290 
2291     if (hda_status != SPC_V_HDAR_EXEC)
2292     {
2293       SA_DBG1(("siHDAMode_V:ILA_EXEC_ERROR hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete));
2294       smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "2W");
2295       goto bootrom_err;
2296     }
2297     SA_DBG1(("siHDAMode_V:           end    seq_id updated                                   STEP 5\n"));
2298   } // End Step 5
2299 
2300   if(HDA_STEP_6)
2301   {
2302     SA_DBG1(("siHDAMode_V:  start                                                            STEP 6\n"));
2303 
2304     /*
2305       Step 6
2306       The host polls the upper 8 bits [31:24] 5 of the Scratchpad 0 Register
2307       (page 609) for the ILAHDA_RAAE_IMG_GET (0x11) state. Polling timeout
2308       should be no more than 2 seconds. If a polling timeout occurs, the host
2309       should check for a fatal error as described in Section 12.2.
2310       If successful, the Host Scratchpad 4 Register (page 620) and Host
2311       Scratchpad 5 Register (page 621) are set as follows: Host Scratchpad 4
2312       Register (page 620) holds the lower 32-bit host address of
2313       the RAAE image. Host Scratchpad 5 Register (page 621)
2314       holds the upper 32-bit host address of the RAAE image.
2315       Then the host writes the command ILAHDAC_RAAE_IMG_DONE(0x81) to the upper
2316       8 bits [31:24] of the Host Scratchpad 3 Register (page 619) and writes the
2317       sizeof the RAAE image to the lower 24 bits [23:0].
2318     */
2319 
2320     max_wait_time = (2000 * 1000); /* wait 2 seconds */
2321     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2322     hda_command_complete = 0;
2323     do
2324     {
2325       ossaStallThread(agRoot, WAIT_INCREMENT);
2326       hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_RAAE_IMG_GET;
2327     } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT));
2328 
2329     SA_DBG1(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 6 wait for ILAHDA_RAAE_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time -  max_wait_count)));
2330     smTrace(hpDBG_VERY_LOUD,"2b",(max_wait_time -  max_wait_count) );
2331     /* TP:2b STEP 6 took */
2332     if(! hda_command_complete)
2333     {
2334       SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 6\n" ));
2335       smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "2W");
2336       goto fw_err;
2337     }
2338 
2339     si_memset(pbase, 0, biggest);
2340 
2341     if( userFwImg->aap1Len < biggest)
2342     {
2343       si_memcpy(pbase,userFwImg->aap1Img, userFwImg->aap1Len );
2344     }
2345     else
2346     {
2347       SA_DBG1(("siHDAMode_V:  userFwImg->aap1Len 0x%x < biggest 0x%x\n",userFwImg->aap1Len,biggest));
2348     }
2349     /*
2350     */
2351     /* upper */
2352     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi );
2353     SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi));
2354     /* lower */
2355     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo );
2356     SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo));
2357     /* len */
2358     ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len );
2359     SA_DBG1(("siHDAMode_V: write ILAHDAC_RAAE_IMG_DONE to MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len));
2360     //    ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_4 , userFwImg->DmaBase_l);
2361 
2362     ossaStallThread(agRoot, gWaitmSec * 1000);
2363     if(1) /* step in question */
2364     {
2365       max_wait_time = (2000 * 1000); /* wait 2 seconds */
2366       max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2367       hda_command_complete = 0;
2368       do
2369       {
2370         ossaStallThread(agRoot, WAIT_INCREMENT);
2371         hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET;
2372       } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT));
2373 
2374       SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2375       smTrace(hpDBG_VERY_LOUD,"2c",(max_wait_time -  max_wait_count) );
2376       /* TP:2c STEP 6a ILAHDA_IOP_IMG_GET took */
2377       smTrace(hpDBG_VERY_LOUD,"2y",hda_command_complete );
2378       /* TP:2y hda_command_complete */
2379 
2380       if(! hda_command_complete)
2381       {
2382         SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" ));
2383         smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "2W");
2384         goto fw_err;
2385       }
2386     }
2387     SA_DBG1(("siHDAMode_V:  End                  V_Scratchpad_0_Register 0x%08X          STEP 6\n",ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register)));
2388   }
2389 
2390   if(HDA_STEP_7)
2391   {
2392     SA_DBG1(("siHDAMode_V:                                                                   STEP 7\n"));
2393     /*
2394       Step 7
2395       The host polls (reads) the upper 8 bits 7 [31:24] of the Scratchpad 0 Register (page 609)
2396       for ILAHDA_IOP_IMG_GET (0x10) state. The polling timeout should be no more than 2 seconds.
2397       If a polling timeout occurs, the host should check for a fatal error as described in
2398       Section 12.2. If successful, the Host Scratchpad 4 Register (page 620) and Host
2399       Scratchpad 5 Register (page 621) are set as follows:
2400       Host Scratchpad 4 Register (page 620) holds the lower host address of the IOP image.
2401       Host Scratchpad 5 Register (page 621) holds the upper host address of the IOP image.
2402       Then host writes the command ILAHDAC_IOP_IMG_DONE(0x80) to the upper 8 bits [31:24] of the
2403       Host Scratchpad 3 Register  (page 614)and writes the sizeof the IOP image to the lower 24
2404       bits [23:0].
2405 
2406     */
2407 
2408     si_memset(pbase, 0, biggest);
2409 
2410     if( userFwImg->iopLen < biggest)
2411     {
2412       si_memcpy(pbase,userFwImg->iopImg, userFwImg->iopLen );
2413     }
2414     else
2415     {
2416       SA_DBG1(("siHDAMode_V:  userFwImg->iopImg 0x%x < biggest 0x%x\n",userFwImg->iopLen,biggest));
2417     }
2418 
2419     /* upper */
2420     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi );
2421     SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi));
2422     /* lower */
2423     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo );
2424     SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo));
2425     SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4\n"));
2426     /* len */
2427     ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen );
2428     SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen));
2429 
2430 
2431     if(saRoot->swConfig.hostDirectAccessMode & 2 )
2432     {
2433   /* Hda AES DIF offload */
2434     ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC);
2435     SA_DBG1(("siHDAMode_V: V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC 0x%X\n",HDA_AES_DIF_FUNC));
2436   /* Hda AES DIF offload */
2437     }
2438 
2439     SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2440     SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2441 
2442 
2443     max_wait_time = (2000 * 1000); /* wait 2 seconds */
2444     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2445     hda_command_complete = 0;
2446     do
2447     {
2448       ossaStallThread(agRoot, WAIT_INCREMENT);
2449       hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET;
2450     } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT));
2451 
2452     smTrace(hpDBG_VERY_LOUD,"2d",(max_wait_time -  max_wait_count) );
2453     /* TP:2d STEP 7 ILAHDA_IOP_IMG_GET took */
2454     smTrace(hpDBG_VERY_LOUD,"2z",hda_command_complete );
2455     /* TP:2z hda_command_complete */
2456 
2457     SA_DBG2(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time -  max_wait_count)));
2458 
2459     if(! hda_command_complete)
2460     {
2461       SA_DBG1(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2462       SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2463       SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2464       SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2465       SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" ));
2466       smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "2W");
2467       return returnVal;
2468     }
2469 
2470 
2471     SA_DBG2(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2472     SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2473     SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2474     SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2475     SA_DBG1(("siHDAMode_V:  End                    STEP 7\n"));
2476   }
2477 
2478 
2479   if(HDA_STEP_8)
2480   {
2481     bit32  SCRATCH_PAD1;
2482 
2483     SA_DBG1(("siHDAMode_V:     Check fw ready                                                Step 8\n"));
2484 
2485     /*
2486     Step 8
2487     IOP0/1 start-up sequence. The host polls the Scratchpad 1 Register (page 610)
2488     bits [1:0] for RAAE_STATE, bits [13:12] for IOP1_STATE, and
2489     bits [11:10] for IOP0_STATE to go to 11b (Ready state).
2490     The polling timeout should be no more than 1 second. If a polling timeout occurs,
2491     the host should check for a fatal error in Section 12.2.
2492     */
2493 
2494     returnVal = AGSA_RC_SUCCESS;
2495 
2496     max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */
2497     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2498     do
2499     {
2500       ossaStallThread(agRoot, WAIT_INCREMENT);
2501       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
2502     } while ((SCRATCH_PAD1  == 0xFFFFFFFF  ) && (max_wait_count -= WAIT_INCREMENT));
2503     smTrace(hpDBG_VERY_LOUD,"HZ",(max_wait_time -  max_wait_count) );
2504     /* TP:2f Step 8 PCI took */
2505 
2506     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x (0x%x) Step 8 PCIe took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2507     /* ILA */
2508     max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */
2509     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2510     do
2511     {
2512       ossaStallThread(agRoot, WAIT_INCREMENT);
2513       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
2514     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT));
2515 
2516     smTrace(hpDBG_VERY_LOUD,"2g",(max_wait_time -  max_wait_count) );
2517     /* TP:2g Step 8 ILA took */
2518 
2519     SA_DBG2(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2520 
2521     if (!max_wait_count)
2522     {
2523       // Ignore for now returnVal = AGSA_RC_FAILURE;
2524       SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x)  not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1));
2525     }
2526 
2527     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2528 
2529     /* RAAE */
2530     max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */
2531     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2532     do
2533     {
2534       ossaStallThread(agRoot, WAIT_INCREMENT);
2535       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
2536     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT));
2537 
2538     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2539     smTrace(hpDBG_VERY_LOUD,"2h",(max_wait_time -  max_wait_count) );
2540     /* TP:2h Step 8 RAAE took */
2541 
2542     if (!max_wait_count)
2543     {
2544       SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1));
2545 
2546     }
2547     /* IOP0 */
2548     max_wait_time = (600 * 1000); /* wait 600 milliseconds */
2549     max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT;
2550     do
2551     {
2552       ossaStallThread(agRoot, WAIT_INCREMENT);
2553       SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1);
2554     } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT));
2555 
2556     SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x  SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time -  max_wait_count)));
2557     smTrace(hpDBG_VERY_LOUD,"2i",(max_wait_time -  max_wait_count) );
2558     /* TP:2i Step 8 IOP took */
2559 
2560     if (!max_wait_count)
2561     {
2562       returnVal = AGSA_RC_FAILURE;
2563       SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1));
2564 
2565     }
2566 
2567 
2568   SA_DBG1(("siHDAMode_V: Step 8 0x%X ERROR_STATE 0x%X\n",ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ),
2569   SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) ));
2570   if (SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ))
2571   {
2572       if(smIS_ENCRYPT(agRoot))
2573       {
2574         SA_DBG1(("siHDAMode_V: Encryption and HDA mode not supported - failed Step 8\n" ));
2575       }
2576       else
2577       {
2578          SA_DBG1(("siHDAMode_V: ERROR_STATE failed Step 8\n" ));
2579       }
2580       returnVal = AGSA_RC_FAILURE;
2581       smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "2W");
2582       goto fw_err;
2583   }
2584 
2585   }
2586   SA_DBG1(("siHDAMode_V:                      returnVal  0x%X                               Step 8\n",returnVal));
2587 /*
2588 Step 10
2589 The host continues with the normal SPCv Configuration Table initialization sequence
2590 as described in Section 6.2.8.1.
2591 */
2592   if(saRoot->swConfig.hostDirectAccessMode & 2 )
2593   {
2594     /* Hda AES DIF offload */
2595     SA_DBG1(("siHDAMode_V: AES/DIF 0x%08X offload enabled %s\n",ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ),
2596                            ((ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ) & (1 << SHIFT15)) ? "yes" :"no") ));
2597     /* Hda AES DIF offload */
2598     /* ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, 0); */
2599     /* Hda AES DIF offload */
2600   }
2601 
2602   smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "2W");
2603   return returnVal;
2604 
2605 bootrom_err:
2606   SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
2607       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0),
2608       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4),
2609       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8),
2610       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12),
2611       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16),
2612       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20),
2613       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24),
2614       ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) ));
2615 
2616 fw_err:
2617   SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register)));
2618   SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register)));
2619   SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register)));
2620   SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register)));
2621   return returnVal;
2622 }
2623 
2624 #endif /* SA_ENABLE_HDA_FUNCTIONS */
2625 
2626 
2627 
2628 
2629 /******************************************************************************/
2630 /*! \brief Function to check FW is ready for soft reset
2631  *
2632  *  The siSpcSoftResetRDYChk() function is called to check status of FW
2633  *
2634  *  \param agRoot handles for this instance of SAS/SATA hardware
2635  *
2636  *  \return success or fail
2637  */
2638 /*******************************************************************************/
2639 LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot)
2640 {
2641   bit32 regVal;
2642   bit32 Scratchpad1;
2643   bit32 Scratchpad2;
2644   bit32 spad2notready = 0;
2645 #if defined(SALLSDK_DEBUG)
2646   bit32 regVal1;
2647   bit32 regVal2;
2648 #endif /* SALLSDK_DEBUG */
2649 
2650   /* read the scratch pad 2 register bit 2 */
2651   regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_FWRDY_RST;
2652   Scratchpad1 =  ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
2653   if (regVal == SCRATCH_PAD2_FWRDY_RST)
2654   {
2655       /* FW assert happened, it is ready for soft reset */
2656       /* Do nothing */
2657   }
2658   else
2659   {
2660     /* read bootloader response state */
2661     regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
2662     if (regVal == BOOTTLOADERHDA_IDLE)
2663     {
2664      /* For customers wants to do soft reset even the chip is already in HDA mode */
2665      /* Do not need to trigger RB6 twice */
2666      ;
2667     }
2668     else
2669     {
2670       /* Trigger NMI twice via RB6 */
2671       if (AGSA_RC_FAILURE == siBar4Shift(agRoot, RB6_ACCESS_REG))
2672       {
2673         SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", RB6_ACCESS_REG));
2674         return AGSA_RC_FAILURE;
2675       }
2676 
2677       if(Scratchpad1  != (SCRATCH_PAD1_FW_INIT_ERR | SCRATCH_PAD1_AAP_ERROR_STATE))
2678       {
2679         ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST);
2680 
2681         ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST);
2682       }
2683       else
2684       {
2685         SA_DBG1(("siSoftReset: ILA load fail SKIP RB6 access 0x%x\n",Scratchpad1 ));
2686       }
2687       SPAD2_NOT_READY:
2688       /* wait for 100 ms */
2689       ossaStallThread(agRoot, ONE_HUNDRED_MILLISECS  );
2690       Scratchpad2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
2691       regVal = Scratchpad2 & SCRATCH_PAD2_FWRDY_RST;
2692       if (regVal != SCRATCH_PAD2_FWRDY_RST)
2693       {
2694         if (spad2notready > WAIT_SECONDS(12) / ONE_HUNDRED_MILLISECS ) /**/
2695         {
2696 #if defined(SALLSDK_DEBUG)
2697           regVal1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
2698           regVal2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
2699           SA_DBG1(("siSpcSoftResetRDYChk: TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", regVal1, regVal2));
2700           SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
2701           SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
2702 #endif /* SALLSDK_DEBUG */
2703           return AGSA_RC_SUCCESS; /* Timeout Ok reset anyway */
2704         }
2705 
2706         spad2notready++;
2707         goto SPAD2_NOT_READY;
2708       }
2709     }
2710   }
2711 
2712   return AGSA_RC_SUCCESS;
2713 }
2714 
2715 
2716 agsaBarOffset_t SPCTable[] =
2717 {
2718 
2719   { GEN_MSGU_IBDB_SET,                 PCIBAR0, MSGU_IBDB_SET,                   SIZE_DW }, /* 0x00  */
2720   { GEN_MSGU_ODR,                      PCIBAR0, MSGU_ODR,                        SIZE_DW }, /* 0x01  */
2721   { GEN_MSGU_ODCR,                     PCIBAR0, MSGU_ODCR,                       SIZE_DW }, /* 0x02  */
2722   { GEN_MSGU_SCRATCH_PAD_0,            PCIBAR0, MSGU_SCRATCH_PAD_0,              SIZE_DW }, /* 0x03  */
2723   { GEN_MSGU_SCRATCH_PAD_1,            PCIBAR0, MSGU_SCRATCH_PAD_1,              SIZE_DW }, /* 0x04  */
2724   { GEN_MSGU_SCRATCH_PAD_2,            PCIBAR0, MSGU_SCRATCH_PAD_2,              SIZE_DW }, /* 0x05  */
2725   { GEN_MSGU_SCRATCH_PAD_3,            PCIBAR0, MSGU_SCRATCH_PAD_3,              SIZE_DW }, /* 0x06  */
2726   { GEN_MSGU_HOST_SCRATCH_PAD_0,       PCIBAR0, MSGU_HOST_SCRATCH_PAD_0,         SIZE_DW }, /* 0x07  */
2727   { GEN_MSGU_HOST_SCRATCH_PAD_1,       PCIBAR0, MSGU_HOST_SCRATCH_PAD_1,         SIZE_DW }, /* 0x08  */
2728   { GEN_MSGU_HOST_SCRATCH_PAD_2,       PCIBAR0, MSGU_HOST_SCRATCH_PAD_2,         SIZE_DW }, /* 0x09  */
2729   { GEN_MSGU_HOST_SCRATCH_PAD_3,       PCIBAR0, MSGU_HOST_SCRATCH_PAD_3,         SIZE_DW }, /* 0x0a  */
2730   { GEN_MSGU_ODMR,                     PCIBAR0, MSGU_ODMR,                       SIZE_DW }, /* 0x0b  */
2731   { GEN_PCIE_TRIGGER,                  PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ,   SIZE_DW }, /* 0x0c  */
2732   { GEN_SPC_REG_RESET,                 PCIBAR2, SPC_REG_RESET,                   SIZE_DW }, /* 0x0d  */
2733 };
2734 
2735 agsaBarOffset_t SPC_V_Table[] =
2736 {
2737 
2738   { GEN_MSGU_IBDB_SET,                 PCIBAR0, V_Inbound_Doorbell_Set_Register,       SIZE_DW }, /* 0x00  */
2739   { GEN_MSGU_ODR,                      PCIBAR0, V_Outbound_Doorbell_Set_Register,      SIZE_DW }, /* 0x01  */
2740   { GEN_MSGU_ODCR,                     PCIBAR0, V_Outbound_Doorbell_Clear_Register,    SIZE_DW }, /* 0x02  */
2741   { GEN_MSGU_SCRATCH_PAD_0,            PCIBAR0, V_Scratchpad_0_Register,               SIZE_DW }, /* 0x03  */
2742   { GEN_MSGU_SCRATCH_PAD_1,            PCIBAR0, V_Scratchpad_1_Register,               SIZE_DW }, /* 0x04  */
2743   { GEN_MSGU_SCRATCH_PAD_2,            PCIBAR0, V_Scratchpad_2_Register,               SIZE_DW }, /* 0x05  */
2744   { GEN_MSGU_SCRATCH_PAD_3,            PCIBAR0, V_Scratchpad_3_Register,               SIZE_DW }, /* 0x06  */
2745   { GEN_MSGU_HOST_SCRATCH_PAD_0,       PCIBAR0, V_Host_Scratchpad_0_Register,          SIZE_DW }, /* 0x07  */
2746   { GEN_MSGU_HOST_SCRATCH_PAD_1,       PCIBAR0, V_Host_Scratchpad_1_Register,          SIZE_DW }, /* 0x08  */
2747   { GEN_MSGU_HOST_SCRATCH_PAD_2,       PCIBAR0, V_Host_Scratchpad_2_Register,          SIZE_DW }, /* 0x09  */
2748   { GEN_MSGU_HOST_SCRATCH_PAD_3,       PCIBAR0, V_Host_Scratchpad_3_Register,          SIZE_DW }, /* 0x0a  */
2749   { GEN_MSGU_ODMR,                     PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, SIZE_DW }, /* 0x0b  */
2750   { GEN_PCIE_TRIGGER,                  PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ,         SIZE_DW }, /* 0x0c  */
2751   { GEN_SPC_REG_RESET,                 PCIBAR0, V_SoftResetRegister,                   SIZE_DW }, /* 0x0d  */
2752 };
2753 
2754 
2755 /*******************************************************************************/
2756 /**
2757  *
2758  *  \brief
2759  *  \param agsaRoot         Pointer to a data structure containing both application
2760  *                          and LL layer context handles
2761  *  \param Spc_type         Device  Id of hardware
2762  *
2763  * Return:
2764  *         None
2765  */
2766 /*******************************************************************************/
2767 GLOBAL void siUpdateBarOffsetTable(agsaRoot_t     *agRoot,
2768                                    bit32         Spc_Type
2769  )
2770 {
2771 
2772   agsaLLRoot_t        *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
2773   bit32 x;
2774 
2775   smTraceFuncEnter(hpDBG_VERY_LOUD,"mf");
2776 
2777   smTrace(hpDBG_VERY_LOUD,"9A",Spc_Type);
2778   /* TP:9A Spc_Type */
2779 
2780   if(Spc_Type == VEN_DEV_SPC)
2781   {
2782     si_memcpy(&saRoot->SpcBarOffset, SPCTable, sizeof(SPCTable));
2783     SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPCTable) sizeof(agsaBarOffset_t)sizeof(SPCTable) / sizeof(agsaBarOffset_t) %X %X %X\n",
2784         (unsigned int)sizeof(SPCTable), (unsigned int)sizeof(agsaBarOffset_t),
2785         (unsigned int)(sizeof(SPCTable) / sizeof(agsaBarOffset_t))
2786       ));
2787   }
2788   else /* VEN_DEV_SPCV */
2789   {
2790     si_memcpy(&saRoot->SpcBarOffset, SPC_V_Table, sizeof(SPC_V_Table));
2791     SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPC_V_Table) sizeof(agsaBarOffset_t)sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t) %X %X %X\n",
2792         (unsigned int)sizeof(SPC_V_Table),
2793         (unsigned int)sizeof(agsaBarOffset_t),
2794         (unsigned int)(sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t))
2795       ));
2796   }
2797 
2798   for(x=0;x < sizeof(SPCTable) / sizeof(agsaBarOffset_t);x++)
2799   {
2800 
2801     SA_DBG4(("%8X: %8X %8X %8X\n",saRoot->SpcBarOffset[x].Generic,
2802                                   saRoot->SpcBarOffset[x].Bar,
2803                                   saRoot->SpcBarOffset[x].Offset,
2804                                   saRoot->SpcBarOffset[x].Length
2805                                          ));
2806     if(saRoot->SpcBarOffset[x].Generic != x)
2807     {
2808       SA_DBG1(("siUpdateBarOffsetTable:  saRoot->SpcBarOffset[%x].Generic %X != %X\n",x, saRoot->SpcBarOffset[x].Generic, x));
2809     }
2810   }
2811 
2812   smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mf");
2813 }
2814 
2815 
2816 
2817 GLOBAL bit32 siHalRegReadExt( agsaRoot_t  *agRoot,
2818                              bit32       generic,
2819                              bit32       regOffset
2820                              )
2821 {
2822 
2823   agsaBarOffset_t * Table = agNULL;
2824   bit32 retVal;
2825 
2826   /* sanity check */
2827   SA_ASSERT( (agNULL != agRoot), "agRoot");
2828   Table = WHATTABLE(agRoot);
2829   SA_ASSERT( (agNULL != Table), "Table");
2830 
2831 /*
2832   if(Table[generic].Offset != regOffset)
2833   {
2834 
2835     SA_DBG1(("siHalRegReadExt: Table[%x].Offset %x != regOffset %x\n",generic,
2836                                         Table[generic].Offset,
2837                                         regOffset ));
2838   }
2839 */
2840 
2841   if(Table[generic].Bar)
2842   {
2843     retVal  = ossaHwRegReadExt(agRoot,
2844                 Table[generic].Bar,
2845                 Table[generic].Offset);
2846   }
2847   else
2848   {
2849     retVal  = ossaHwRegRead(agRoot,
2850                 Table[generic].Offset);
2851   }
2852 
2853   return(retVal);
2854 }
2855 
2856 
2857 GLOBAL void siHalRegWriteExt(
2858                              agsaRoot_t  *agRoot,
2859                              bit32       generic,
2860                              bit32       regOffset,
2861                              bit32       regValue
2862                              )
2863 {
2864   agsaBarOffset_t * Table = agNULL;
2865 
2866   /* sanity check */
2867   SA_ASSERT( (agNULL != agRoot), "agRoot");
2868 
2869   Table = WHATTABLE(agRoot);
2870   SA_ASSERT( (agNULL != Table), "Table");
2871 
2872 
2873 /*
2874     if(Table[generic].Offset != regOffset)
2875     {
2876 
2877       SA_DBG1(("siHalRegWriteExt: Table[%x].Offset %x != regOffset %x\n",generic,
2878                                           Table[generic].Offset,
2879                                           regOffset ));
2880     }
2881 */
2882 
2883     SA_DBG6(("siHalRegWriteExt: Bar %x Offset %8X Wrote %8X\n",
2884                                         Table[generic].Bar,
2885                                         Table[generic].Offset,
2886                                         regValue ));
2887 
2888 
2889   if(Table[generic].Bar)
2890   {
2891     ossaHwRegWriteExt(agRoot,
2892               Table[generic].Bar,
2893               Table[generic].Offset,
2894               regValue  );
2895   }else
2896   {
2897     ossaHwRegWrite(agRoot,
2898             Table[generic].Offset,
2899             regValue  );
2900   }
2901 }
2902 
2903 
2904 
2905 
2906 GLOBAL void siPCITriger(agsaRoot_t *agRoot)
2907 {
2908 
2909   SA_DBG1(("siPCITriger: Read PCIe Bar zero plus 0x%x\n", PCIE_TRIGGER_ON_REGISTER_READ));
2910   ossaHwRegReadExt(agRoot,PCIBAR0 ,PCIE_TRIGGER_ON_REGISTER_READ );
2911 }
2912 
2913 
2914 GLOBAL bit32 siGetPciBar(
2915               agsaRoot_t *agRoot
2916               )
2917 {
2918   bit32 MSGUCfgTblBase = 0;
2919   bit32 pcibar = 0;
2920   MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0);
2921   pcibar = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26;
2922   /* get pci Bar index */
2923   pcibar = (bit8)mpiGetPCIBarIndex(agRoot, pcibar);
2924 
2925   return(pcibar);
2926 }
2927 
2928 GLOBAL bit32 siGetTableOffset(
2929               agsaRoot_t *agRoot,
2930               bit32  TableOffsetInTable
2931               )
2932 {
2933   bit32 TableOffset;
2934   bit32 MSGUCfgTblBase;
2935   /* read scratch pad0 to get PCI BAR and offset of configuration table */
2936   MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0);
2937 
2938   MSGUCfgTblBase &= SCRATCH_PAD0_OFFSET_MASK;
2939 
2940   TableOffset = ossaHwRegReadExt(agRoot,siGetPciBar(agRoot) ,MSGUCfgTblBase +TableOffsetInTable  );
2941   SA_DBG4(("GetTableOffset:TableOffset with size 0x%x\n", TableOffset));
2942 
2943   /* Mask off size */
2944   TableOffset &= 0xFFFFFF;
2945   TableOffset +=MSGUCfgTblBase;
2946   return(TableOffset);
2947 
2948 }
2949 
2950 
2951 GLOBAL void siCheckQs(
2952               agsaRoot_t *agRoot
2953               )
2954 {
2955   agsaLLRoot_t        *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
2956 
2957   mpiOCQueue_t         *circularOQ;
2958   mpiICQueue_t         *circularIQ;
2959   int i;
2960 
2961   for ( i = 0; i < saRoot->QueueConfig.numInboundQueues; i++ )
2962   {
2963     circularIQ = &saRoot->inboundQueue[i];
2964 
2965     OSSA_READ_LE_32(circularIQ->agRoot, &circularIQ->consumerIdx, circularIQ->ciPointer, 0);
2966     if(circularIQ->producerIdx != circularIQ->consumerIdx)
2967     {
2968       SA_DBG1(("siCheckQs: In  Q %d  PI 0x%03x CI 0x%03x (%d) \n",i,
2969       circularIQ->producerIdx,
2970       circularIQ->consumerIdx,
2971       (circularIQ->producerIdx > circularIQ->consumerIdx ? (circularIQ->producerIdx - circularIQ->consumerIdx) :   (circularIQ->numElements -  circularIQ->consumerIdx ) + circularIQ->producerIdx)));
2972     }
2973   }
2974 
2975   for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ )
2976   {
2977     circularOQ = &saRoot->outboundQueue[i];
2978     OSSA_READ_LE_32(circularOQ->agRoot, &circularOQ->producerIdx, circularOQ->piPointer, 0);
2979     if(circularOQ->producerIdx != circularOQ->consumerIdx)
2980     {
2981         SA_DBG1(("siCheckQs: Out Q %d  PI 0x%03x CI 0x%03x (%d) \n",i,
2982         circularOQ->producerIdx,
2983         circularOQ->consumerIdx,
2984         (circularOQ->producerIdx > circularOQ->consumerIdx ? (circularOQ->producerIdx - circularOQ->consumerIdx) :   (circularOQ->numElements -  circularOQ->consumerIdx ) + circularOQ->producerIdx)));
2985 
2986     }
2987   }
2988 
2989 }
2990 GLOBAL void siPciCpyMem(agsaRoot_t *agRoot,
2991                        bit32 soffset,
2992                        const void *dst,
2993                        bit32 DWcount,
2994                        bit32 busBaseNumber
2995                        )
2996 {
2997   bit32 i, val,offset;
2998   bit32 *dst1;
2999 
3000   dst1 = (bit32 *)dst;
3001 
3002   SA_DBG1(("siPciCpyMem:copy DWcount %d from offset 0x%x to %p\n",DWcount,soffset,dst));
3003 
3004   for (i= 0; i < DWcount; i+=4,dst1++)
3005   {
3006     offset = (soffset + i / 4);
3007     SA_ASSERT( (offset < (64 * 1024)), "siPciCpyMem offset too large");
3008     if(offset < (64 * 1024))
3009     {
3010       val = ossaHwRegReadExt(agRoot, busBaseNumber, offset);
3011       *dst1 =  BIT32_TO_LEBIT32(val);
3012     }
3013   }
3014 
3015   return;
3016 }
3017