1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 21 ********************************************************************************/ 22 /*******************************************************************************/ 23 /*! \file sahw.c 24 * \brief The file implements the functions for reset and shutdown 25 */ 26 /******************************************************************************/ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 #include <dev/pms/config.h> 30 31 #include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 32 #ifdef SA_ENABLE_HDA_FUNCTIONS 33 #ifndef SA_EXCLUDE_FW_IMG 34 /* 35 #include "istrimg.h" 36 #include "ilaimg.h" 37 #include "aap1img.h" 38 #include "iopimg.h" 39 */ 40 #endif 41 #endif 42 #if defined(SALLSDK_DEBUG) 43 extern bit32 gLLSoftResetCounter; 44 #endif 45 46 #ifdef SA_ENABLE_TRACE_FUNCTIONS 47 #ifdef siTraceFileID 48 #undef siTraceFileID 49 #endif 50 #define siTraceFileID 'E' 51 #endif 52 53 54 bit32 gWait_3 = 3; 55 bit32 gWait_2 = 2; 56 57 bit32 gWaitmSec = 0; 58 59 60 61 LOCAL bit32 si_V_SoftReset(agsaRoot_t *agRoot, bit32 signature); 62 63 64 LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot); 65 66 #ifdef SA_ENABLE_HDA_FUNCTIONS 67 LOCAL void siPciMemCpy(agsaRoot_t *agRoot, bit32 dstoffset, void *src, 68 bit32 DWcount, bit32 busBaseNumber); 69 70 LOCAL bit32 siBar4Cpy(agsaRoot_t *agRoot, bit32 offset, bit8 *parray, bit32 array_size); 71 #endif 72 73 /******************************************************************************/ 74 /*! \brief Function to reset the Hardware 75 * 76 * The saHwReset() function is called to reset the SAS/SATA HW controller 77 * All outstanding I/Os are explicitly aborted. 78 * This API need to access before saInitialize() so checking saRoot is needed 79 * 80 * \param agRoot Handles for this instance of SAS/SATA hardware 81 * \param resetType The reset type 82 * \param resetParm The paramter passed for reset operation 83 * 84 * \return -void- 85 */ 86 /*******************************************************************************/ 87 GLOBAL void saHwReset( 88 agsaRoot_t *agRoot, 89 bit32 resetType, 90 bit32 resetParm 91 ) 92 { 93 agsaLLRoot_t *saRoot = agNULL; 94 bit32 ret = AGSA_RC_SUCCESS; 95 bit32 value; 96 bit32 sysIntsActive = agFALSE; 97 #if defined(SALLSDK_DEBUG) 98 bit32 value1; 99 agsaControllerStatus_t controllerStatus; 100 agsaFatalErrorInfo_t fatal_error; 101 #endif 102 103 #ifdef SOFT_RESET_TEST 104 DbgPrint("Reset Start\n"); 105 #endif 106 107 smTraceFuncEnter(hpDBG_VERY_LOUD, "5a"); 108 109 /* sanity check */ 110 SA_ASSERT( (agNULL != agRoot), ""); 111 if (agNULL != agRoot) 112 { 113 if (agNULL != agRoot->sdkData) 114 { 115 saRoot = (agsaLLRoot_t*) agRoot->sdkData; 116 sysIntsActive = saRoot->sysIntsActive; 117 if(sysIntsActive) 118 { 119 saSystemInterruptsActive(agRoot,agFALSE); 120 } 121 } 122 } 123 else 124 { 125 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5a"); 126 return; 127 } 128 129 130 #if defined(SALLSDK_DEBUG) 131 { 132 if (agNULL != agRoot->sdkData) 133 { 134 /* check fatal errors */ 135 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 136 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 137 /* check AAP error */ 138 if( smIS_SPC(agRoot) ) 139 { 140 value &= SCRATCH_PAD_STATE_MASK; 141 value1 &= SCRATCH_PAD_STATE_MASK; 142 143 if ((SCRATCH_PAD1_ERR == value) || (SCRATCH_PAD2_ERR == value1)) 144 { 145 146 si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 147 /* read detail fatal errors */ 148 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 149 fatal_error.errorInfo0 = value; 150 SA_DBG1(("saHwReset: ScratchPad0 AAP error code 0x%x\n", value)); 151 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 152 fatal_error.errorInfo1 = value; 153 /* AAP error state */ 154 SA_DBG1(("saHwReset: AAP error state and error code 0x%x\n", value)); 155 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 156 fatal_error.errorInfo2 = value; 157 /* IOP error state */ 158 SA_DBG1(("saHwReset: IOP error state and error code 0x%x\n", value)); 159 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 160 SA_DBG1(("saHwReset: ScratchPad3 IOP error code 0x%x\n", value)); 161 fatal_error.errorInfo3 = value; 162 if (agNULL != saRoot) 163 { 164 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 165 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 166 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 167 fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 168 fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 169 fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 170 } 171 172 /* Call Back with error */ 173 SA_DBG1(("saHwReset: OSSA_HW_EVENT_MALFUNCTION SPC SP1 0x%x\n", value1)); 174 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); 175 } 176 } 177 else 178 { 179 if( ( (value & SCRATCH_PAD1_V_BOOTLDR_ERROR) == SCRATCH_PAD1_V_BOOTLDR_ERROR)) 180 { 181 SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_BOOTLDR_ERROR 0x%x\n", value)); 182 } 183 if(SCRATCH_PAD1_V_ERROR_STATE(value)) 184 { 185 SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_ERROR_STATE 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE(value) )); 186 } 187 if( (value & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY ) 188 { 189 SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_READY 0x%x\n", value)); 190 } 191 } 192 saGetControllerStatus(agRoot, &controllerStatus); 193 if (agNULL != saRoot) 194 { 195 /* display all pending Ios */ 196 siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); 197 } 198 } 199 } 200 #endif /* SALLSDK_DEBUG */ 201 202 /* Check the resetType */ 203 switch (resetType) 204 { 205 /* Reset the whole chip */ 206 case AGSA_CHIP_RESET: 207 { 208 /* callback with RESET_START */ 209 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 210 211 if (agNULL != agRoot->sdkData && agNULL != saRoot) 212 { 213 /* Set chip status */ 214 saRoot->chipStatus |= CHIP_RESETTING; 215 216 /* Disable all interrupt */ 217 saSystemInterruptsActive(agRoot,agFALSE); 218 } 219 220 /* do chip reset */ 221 siChipReset(agRoot); 222 223 if (agNULL != saRoot) 224 { 225 /* clear up the internal resource */ 226 siInitResources(agRoot, 227 &saRoot->memoryAllocated, 228 &saRoot->hwConfig, 229 &saRoot->swConfig, 230 saRoot->usecsPerTick); 231 } 232 233 /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 234 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 235 236 if (agNULL != saRoot) 237 { 238 /* mask off reset FW status */ 239 saRoot->chipStatus &= ~CHIP_RESETTING; 240 } 241 break; 242 } 243 case AGSA_SOFT_RESET: 244 { 245 246 if( smIS_SPCV(agRoot) ) 247 { 248 SA_DBG1(("saHwReset: AGSA_SOFT_RESET chip type V %d\n",smIS_SPCV(agRoot) )); 249 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 250 if (agNULL != saRoot) 251 { 252 saRoot->ResetStartTick = saRoot->timeTick; 253 saCountActiveIORequests( agRoot); 254 } //delray end 255 256 ret = siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE ); 257 258 if(agNULL !=saRoot) 259 { 260 /* clear up the internal resource */ 261 siInitResources(agRoot, 262 &saRoot->memoryAllocated, 263 &saRoot->hwConfig, 264 &saRoot->swConfig, 265 saRoot->usecsPerTick); 266 } 267 268 if (AGSA_RC_SUCCESS == ret) 269 { 270 /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 271 SA_DBG1(("saHwReset: siChipResetV AGSA_RC_SUCCESS\n" )); 272 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 273 } 274 else 275 { 276 /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ 277 SA_DBG1(("saHwReset: siChipResetV not AGSA_RC_SUCCESS (0x%x)\n" ,ret)); 278 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_FAILURE << SHIFT8, agNULL, agNULL); 279 if (agNULL != saRoot) 280 { 281 saRoot->ResetFailed = agTRUE; 282 SA_DBG1(("saHwReset: siChipResetV saRoot->ResetFailed ret (0x%x)\n" ,ret)); 283 } 284 285 } 286 break; 287 } 288 else 289 { 290 if (agNULL != saRoot) 291 { 292 /* get register dump from GSM and save it to LL local memory */ 293 siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0], 294 REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0); 295 siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0], 296 REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1); 297 } 298 299 /* callback with RESET_START */ 300 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 301 302 if (agNULL != agRoot->sdkData && agNULL != saRoot) 303 { 304 /* Set chip status */ 305 saRoot->chipStatus |= CHIP_RESET_FW; 306 307 /* Disable all interrupt */ 308 saSystemInterruptsActive(agRoot,agFALSE); 309 saCountActiveIORequests( agRoot); //delray start 310 311 } 312 313 /* check HDA mode */ 314 value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 315 316 if (value == BOOTTLOADERHDA_IDLE) 317 { 318 /* HDA mode */ 319 SA_DBG1(("saHwReset: HDA mode, value = 0x%x\n", value)); 320 ret = AGSA_RC_HDA_NO_FW_RUNNING; 321 } 322 else 323 { 324 /* do Soft Reset */ 325 ret = siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 326 } 327 if(agNULL !=saRoot) 328 { 329 /* clear up the internal resource */ 330 siInitResources(agRoot, 331 &saRoot->memoryAllocated, 332 &saRoot->hwConfig, 333 &saRoot->swConfig, 334 saRoot->usecsPerTick); 335 } 336 if (AGSA_RC_SUCCESS == ret) 337 { 338 /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 339 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 340 } 341 else if (AGSA_RC_HDA_NO_FW_RUNNING == ret) 342 { 343 /* callback with CHIP_RESET_COMPLETE with OSSA_CHIP_FAILED */ 344 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 345 } 346 else 347 { 348 /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ 349 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, (OSSA_FAILURE << SHIFT8), agNULL, agNULL); 350 } 351 352 if (agNULL != saRoot) 353 { 354 /* mask off reset FW status */ 355 saRoot->chipStatus &= ~CHIP_RESET_FW; 356 } 357 break; 358 } 359 } 360 /* Unsupported type */ 361 default: 362 { 363 SA_DBG1(("saHwReset: Unsupported reset type %X\n",resetType)); 364 break; 365 } 366 } 367 368 if (agNULL != saRoot) 369 { 370 if(sysIntsActive && ret == AGSA_RC_SUCCESS) 371 { 372 saSystemInterruptsActive(agRoot,agTRUE); 373 } 374 375 saCountActiveIORequests( agRoot); 376 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5a"); 377 } 378 379 return; 380 } 381 382 /******************************************************************************/ 383 /*! \brief Function to shutdown the Hardware 384 * 385 * The saHwShutdown() function is called to discontinue the use of the SAS/SATA 386 * hardware. Upon return, the SASA/SAT hardware instance does not generate any 387 * interrupts or any other bus accesses. All LL Layer hardware host resources 388 * (i.e. both cached and noncached memory) are no longer owned by the LL Layer. 389 * 390 * \param agRoot handles for this instance of SAS/SATA hardware 391 * 392 * \return -void- 393 */ 394 /*******************************************************************************/ 395 GLOBAL void saHwShutdown( 396 agsaRoot_t *agRoot 397 ) 398 { 399 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 400 bit32 spad0 = 0; 401 smTraceFuncEnter(hpDBG_VERY_LOUD,"5b"); 402 403 /* sanity check */ 404 SA_ASSERT( (agNULL != agRoot), ""); 405 SA_DBG1(("saHwShutdown: Shutting down .....\n")); 406 407 if (agRoot->sdkData) 408 { 409 410 spad0 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 411 412 if(0xFFFFFFFF == spad0) 413 { 414 SA_ASSERT(0xFFFFFFFF == spad0, "saHwShutdown Chip PCI dead"); 415 416 SA_DBG1(("saHwShutdown: Chip PCI dead SCRATCH_PAD0 0x%x\n", spad0)); 417 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5b"); 418 return; 419 } 420 421 422 #if defined(SALLSDK_DEBUG) 423 SA_DBG1(("saHwShutdown: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); 424 SA_DBG1(("saHwShutdown: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); 425 SA_DBG1(("saHwShutdown: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2))); 426 SA_DBG1(("saHwShutdown: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); 427 428 if(1) 429 { 430 mpiOCQueue_t *circularQ; 431 int i; 432 SA_DBG4(("saHwShutdown:\n")); 433 for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 434 { 435 circularQ = &saRoot->outboundQueue[i]; 436 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 437 if(circularQ->producerIdx != circularQ->consumerIdx) 438 { 439 SA_DBG1(("saHwShutdown: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx )); 440 } 441 } 442 } 443 #endif /* SALLSDK_DBG */ 444 445 if(smIS_SPCV(agRoot)) 446 { 447 448 siScratchDump(agRoot); 449 450 SA_DBG1(("saHwShutdown: SPC_V\n" )); 451 } 452 /* Set chip status */ 453 saRoot->chipStatus |= CHIP_SHUTDOWN; 454 455 /* Un-Initialization Configuration Table */ 456 mpiUnInitConfigTable(agRoot); 457 if (saRoot->swConfig.hostDirectAccessSupport && !saRoot->swConfig.hostDirectAccessMode) 458 { 459 /* HDA mode - do HDAsoftReset */ 460 if(smIS_SPC(agRoot)) 461 { 462 /* HDA soft reset */ 463 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 464 } 465 if(smIS_SPCV(agRoot)) 466 { 467 siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 468 SA_DBG1(("saHwShutdown: HDA saRoot->ChipId == VEN_DEV_SPCV\n")); 469 } 470 } 471 else 472 { 473 /* do Normal softReset */ 474 if(smIS_SPC(agRoot)) 475 { 476 /* Soft Reset the SPC */ 477 siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 478 } 479 if(smIS_SPCV(agRoot)) 480 { 481 SA_DBG1(("saHwShutdown: saRoot->ChipId == VEN_DEV_SPCV\n")); 482 siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 483 } 484 485 } 486 487 /* clean the LL resources */ 488 siInitResources(agRoot, 489 &saRoot->memoryAllocated, 490 &saRoot->hwConfig, 491 &saRoot->swConfig, 492 saRoot->usecsPerTick); 493 SA_DBG1(("saHwShutdown: Shutting down Complete\n")); 494 } 495 else 496 { 497 SA_DBG1(("saHwShutdown: No saRoot\n")); 498 if( smIS_SPCV(agRoot) ) 499 { 500 siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 501 } 502 else 503 { 504 siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 505 } 506 } 507 /* agroot/saroot null do not access -trace OK */ 508 509 SA_ASSERT( (agNULL != agRoot), "10"); 510 /* return */ 511 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5b"); 512 return; 513 } 514 515 516 /******************************************************************************/ 517 /*! \brief Generic Reset 518 * 519 * The siChipReset() function is called to reset the SPC chip. Upon return, 520 * the SPC chip got reset. The PCIe bus got reset. 521 * 522 * \param agRoot handles for this instance of SAS/SATA hardware 523 * 524 * \return -void- 525 */ 526 /*******************************************************************************/ 527 528 GLOBAL void siChipReset( 529 agsaRoot_t *agRoot 530 ) 531 { 532 agsaLLRoot_t *saRoot; 533 534 /* sanity check */ 535 SA_ASSERT( (agNULL != agRoot), ""); 536 537 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 538 if(agNULL != saRoot) 539 { 540 smTraceFuncEnter(hpDBG_VERY_LOUD,"2C"); 541 542 SA_DBG1(("siChipReset: saRoot->ChipId == VEN_DEV_SPCV\n")); 543 if(smIS_SPC(agRoot) ) 544 { 545 /* Soft Reset the SPC */ 546 siChipResetSpc( agRoot); 547 }else /* saRoot->ChipId == VEN_DEV_SPCV */ 548 { 549 siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE); 550 } 551 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2C"); 552 } 553 554 } 555 556 557 /******************************************************************************/ 558 /*! \brief Function to Reset the SPC V Hardware 559 * 560 * The siChipResetV() function is called to reset the SPC chip. Upon return, 561 * the SPC chip got reset. The PCIe bus got reset. 562 * 563 * \param agRoot handles for this instance of SAS/SATA hardware 564 * 565 * \return -void- 566 */ 567 /*******************************************************************************/ 568 569 GLOBAL bit32 siChipResetV( 570 agsaRoot_t *agRoot, 571 bit32 signature 572 ) 573 { 574 bit32 regVal; 575 bit32 returnVal = AGSA_RC_SUCCESS; 576 577 smTraceFuncEnter(hpDBG_VERY_LOUD,"3A"); 578 smTrace(hpDBG_LOUD,"Lr",ossaTimeStamp64(agRoot)); 579 regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); 580 581 SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal)); 582 583 if (signature == SPC_SOFT_RESET_SIGNATURE) 584 { 585 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); 586 regVal = SPCv_Reset_Write_NormalReset; 587 } 588 else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 589 { 590 SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal)); 591 regVal = SPCv_Reset_Write_SoftResetHDA; 592 } 593 else 594 { 595 SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X regVal 0x%X a\n",signature ,regVal)); 596 regVal = 1; 597 } 598 599 smTrace(hpDBG_LOUD,"Ls",ossaTimeStamp64(agRoot)); 600 ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */ 601 smTrace(hpDBG_LOUD,"Lt",ossaTimeStamp64(agRoot)); 602 ossaStallThread(agRoot, (500 * 1000)); /* wait 500 milliseconds or PCIe will hang */ 603 /* Soft reset sequence (Normal mode) */ 604 smTrace(hpDBG_LOUD,"Lv",ossaTimeStamp64(agRoot)); 605 606 if (signature == SPC_HDASOFT_RESET_SIGNATURE) 607 { 608 bit32 hda_status; 609 610 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 611 612 SA_DBG1(("siChipResetV: hda_status 0x%x\n",hda_status)); 613 614 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 615 { 616 SA_DBG1(("siChipResetV:SPC_HDASOFT_RESET_SIGNATURE SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 617 } 618 619 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); 620 621 regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ 622 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); 623 624 if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) 625 { 626 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 627 returnVal = AGSA_RC_FAILURE; 628 } 629 if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) 630 { 631 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 632 returnVal = AGSA_RC_FAILURE; 633 } 634 if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) 635 { 636 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_SUCCESS %X\n",regVal)); 637 returnVal = AGSA_RC_SUCCESS; 638 } 639 if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) 640 { 641 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 642 returnVal = AGSA_RC_FAILURE; 643 } 644 if(regVal == 0xFFFFFFFF) 645 { 646 SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 647 returnVal = AGSA_RC_FAILURE; 648 } 649 650 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x a\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 651 652 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3A"); 653 return returnVal; 654 } 655 else if (signature == SPC_SOFT_RESET_SIGNATURE) 656 { 657 bit32 SCRATCH_PAD1; 658 bit32 max_wait_time; 659 bit32 max_wait_count; 660 smTrace(hpDBG_LOUD,"Lw",ossaTimeStamp64(agRoot)); 661 regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ 662 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); 663 664 if(regVal == 0xFFFFFFFF) 665 { 666 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 667 returnVal = AGSA_RC_FAILURE; 668 } 669 else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) 670 { 671 SA_DBG1(("siChipResetV:SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 672 returnVal = AGSA_RC_FAILURE; 673 } 674 else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) 675 { 676 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); 677 returnVal = AGSA_RC_FAILURE; 678 } 679 else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) 680 { 681 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); 682 returnVal = AGSA_RC_FAILURE; 683 } 684 else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) 685 { 686 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_SUCCESS 0x%X\n",regVal)); 687 returnVal = AGSA_RC_SUCCESS; 688 } 689 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x b\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 690 691 if( returnVal != AGSA_RC_SUCCESS) 692 { 693 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_BOOTSTATE_MASK; 694 if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) 695 { 696 SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SEEPROM\n")); 697 return (returnVal); 698 } 699 else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP) 700 { 701 SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_BOOTSTRAP\n")); 702 return (returnVal); 703 } 704 else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET ) 705 { 706 SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SOFTRESET\n")); 707 return (returnVal); 708 } 709 else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR ) 710 { 711 SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_CRIT_ERROR\n")); 712 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3A"); 713 return (returnVal); 714 } 715 } 716 717 /* RESET */ 718 smTrace(hpDBG_LOUD,"Lx",ossaTimeStamp64(agRoot)); 719 max_wait_time = (100 * 1000); /* wait 100 milliseconds */ 720 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 721 do 722 { 723 ossaStallThread(agRoot, WAIT_INCREMENT); 724 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 725 } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); 726 727 smTrace(hpDBG_LOUD,"Ly",ossaTimeStamp64(agRoot)); 728 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x (0x%x) PCIe ready took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 729 /* ILA */ 730 max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 731 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 732 do 733 { 734 ossaStallThread(agRoot, WAIT_INCREMENT); 735 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 736 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 737 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 738 739 if (!max_wait_count) 740 { 741 returnVal = AGSA_RC_FAILURE; 742 SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 743 } 744 /* RAAE */ 745 smTrace(hpDBG_LOUD,"Lz",ossaTimeStamp64(agRoot)); 746 max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ 747 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 748 do 749 { 750 ossaStallThread(agRoot, WAIT_INCREMENT); 751 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 752 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 753 754 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 755 756 if (!max_wait_count) 757 { 758 returnVal = AGSA_RC_FAILURE; 759 SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 760 } 761 /* IOP0 */ 762 smTrace(hpDBG_LOUD,"La",ossaTimeStamp64(agRoot)); 763 max_wait_time = (600 * 1000); /* wait 600 milliseconds */ 764 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 765 do 766 { 767 ossaStallThread(agRoot, WAIT_INCREMENT); 768 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 769 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 770 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 771 772 if (!max_wait_count) 773 { 774 returnVal = AGSA_RC_FAILURE; 775 SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 776 } 777 778 if(smIS_SPCV_2_IOP(agRoot)) 779 { 780 /* IOP1 */ 781 smTrace(hpDBG_LOUD,"Lb",ossaTimeStamp64(agRoot)); 782 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 783 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 784 do 785 { 786 ossaStallThread(agRoot, WAIT_INCREMENT); 787 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 788 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); 789 SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP1_MASK (0x%x) (0x%x)(0x%x)\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP1_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 790 791 if (!max_wait_count) 792 { 793 returnVal = AGSA_RC_FAILURE; 794 SA_DBG1(("siChipResetV: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); 795 } 796 } 797 smTrace(hpDBG_LOUD,"Lc",ossaTimeStamp64(agRoot)); 798 regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); 799 SA_DBG1(("siChipResetV: Reset done 0x%X ERROR_STATE 0x%X\n",regVal, 800 SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); 801 if(SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)) ) 802 { 803 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3A"); 804 return AGSA_RC_FAILURE; 805 } 806 807 } 808 else /* signature = unknown */ 809 { 810 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3A"); 811 return AGSA_RC_FAILURE; 812 } 813 814 smTrace(hpDBG_LOUD,"Ld",ossaTimeStamp64(agRoot)); 815 816 SA_DBG1(("siChipResetV: out V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister) )); 817 #ifdef SOFT_RESET_TEST 818 DbgPrint("SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)); 819 #endif 820 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "3A"); 821 return returnVal; 822 823 } 824 /******************************************************************************/ 825 /*! \brief Function to Reset the SPC Hardware 826 * 827 * The siChipResetSpc() function is called to reset the SPC chip. Upon return, 828 * the SPC chip got reset. The PCIe bus got reset. 829 * 830 * \param agRoot handles for this instance of SAS/SATA hardware 831 * 832 * \return -void- 833 */ 834 /*******************************************************************************/ 835 GLOBAL void siChipResetSpc( 836 agsaRoot_t *agRoot 837 ) 838 { 839 bit32 regVal; 840 841 smTraceFuncEnter(hpDBG_VERY_LOUD,"5c"); 842 843 SA_DBG1(("siChipResetSpc: Chip Reset start\n")); 844 845 /* Reset the chip */ 846 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 847 regVal &= ~(SPC_REG_RESET_DEVICE); 848 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ 849 850 /* delay 10 usec */ 851 ossaStallThread(agRoot, WAIT_INCREMENT); 852 853 /* bring chip reset out of reset */ 854 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 855 regVal |= SPC_REG_RESET_DEVICE; 856 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ 857 858 /* delay 10 usec */ 859 ossaStallThread(agRoot, WAIT_INCREMENT); 860 861 /* wait for 20 msec until the firmware gets reloaded */ 862 ossaStallThread(agRoot, (20 * 1000)); 863 864 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5c"); 865 866 SA_DBG1(("siChipResetSpc: Chip Reset Complete\n")); 867 868 return; 869 } 870 871 872 GLOBAL bit32 siSoftReset( 873 agsaRoot_t *agRoot, 874 bit32 signature 875 ) 876 { 877 bit32 ret = AGSA_RC_SUCCESS; 878 879 if(smIS_SPCV(agRoot)) 880 { 881 ret = si_V_SoftReset(agRoot, signature ); 882 } 883 else 884 { 885 ret = siSpcSoftReset(agRoot, signature ); 886 } 887 888 return(ret); 889 } 890 891 LOCAL bit32 si_V_SoftReset( 892 agsaRoot_t *agRoot, 893 bit32 signature 894 ) 895 { 896 897 bit32 ret = AGSA_RC_SUCCESS; 898 899 ret = siChipResetV(agRoot, signature); 900 901 if (signature == SPC_SOFT_RESET_SIGNATURE) 902 { 903 SA_DBG1(("si_V_SoftReset:SPC_SOFT_RESET_SIGNATURE\n")); 904 } 905 else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 906 { 907 SA_DBG1(("si_V_SoftReset: SPC_HDASOFT_RESET_SIGNATURE\n")); 908 } 909 910 SA_DBG1(("si_V_SoftReset: Reset Complete status 0x%X\n",ret)); 911 return ret; 912 } 913 914 /******************************************************************************/ 915 /*! \brief Function to soft/FW reset the SPC 916 * 917 * The siSpcSoftReset() function is called to soft reset SPC. Upon return, 918 * the SPC FW got reset. The PCIe bus is not touched. 919 * 920 * \param agRoot handles for this instance of SAS/SATA hardware 921 * \param signature soft reset normal signature or HDA soft reset signature 922 * 923 * \return -void- 924 */ 925 /*******************************************************************************/ 926 GLOBAL bit32 siSpcSoftReset( 927 agsaRoot_t *agRoot, 928 bit32 signature 929 ) 930 { 931 spc_configMainDescriptor_t mainCfg; 932 bit32 regVal, toggleVal; 933 bit32 max_wait_time; 934 bit32 max_wait_count; 935 bit32 regVal1, regVal2, regVal3; 936 937 938 /* sanity check */ 939 SA_ASSERT( (agNULL != agRoot), "agNULL != agRoot"); 940 if(agNULL != agRoot->sdkData) 941 { 942 smTraceFuncEnter(hpDBG_VERY_LOUD,"5t"); 943 } 944 945 SA_DBG1(("siSpcSoftReset: start\n")); 946 947 948 #if defined(SALLSDK_DEBUG) 949 /* count SoftReset */ 950 gLLSoftResetCounter++; 951 SA_DBG1(("siSpcSoftReset: ResetCount = 0x%x\n", gLLSoftResetCounter)); 952 #endif 953 954 /* step1: Check FW is ready for soft reset */ 955 956 smTrace(hpDBG_VERY_LOUD,"Q1", 1); 957 /* TP:Q1 siSpcSoftReset */ 958 959 if(AGSA_RC_FAILURE == siSpcSoftResetRDYChk(agRoot)) 960 { 961 SA_DBG1(("siSoftReset:siSoftResetRDYChk failed\n")); 962 if(agNULL != agRoot->sdkData) 963 { 964 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5t"); 965 } 966 return AGSA_RC_FAILURE; 967 } 968 969 /* step 2: clear NMI status register on AAP1 and IOP, write the same value to clear */ 970 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 971 smTrace(hpDBG_VERY_LOUD,"Q2", 2); 972 /* TP:Q2 siSpcSoftReset */ 973 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_AAP1_ADDR_BASE)) 974 { 975 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_AAP1_ADDR_BASE)); 976 if(agNULL != agRoot->sdkData) 977 { 978 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5t"); 979 } 980 981 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",1)); 982 return AGSA_RC_FAILURE; 983 } 984 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP); 985 SA_DBG1(("MBIC(A) - NMI Enable VPE0 (IOP): = 0x%x\n", regVal)); 986 ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); /* siSpcSoftReset */ 987 988 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 989 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_IOP_ADDR_BASE)) 990 { 991 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_IOP_ADDR_BASE)); 992 if(agNULL != agRoot->sdkData) 993 { 994 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5t"); 995 } 996 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",2)); 997 return AGSA_RC_FAILURE; 998 } 999 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1); 1000 SA_DBG1(("MBIC(A) - NMI Enable VPE0 (AAP1): = 0x%x\n", regVal)); 1001 ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); /* siSpcSoftReset */ 1002 1003 regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE); 1004 SA_DBG1(("PCIE - Event Interrupt Enable Register: = 0x%x\n", regVal)); 1005 ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ 1006 1007 regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT); 1008 SA_DBG1(("PCIE - Event Interrupt Register: = 0x%x\n", regVal)); 1009 ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal); /* siSpcSoftReset */ 1010 1011 regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE); 1012 SA_DBG1(("PCIE - Error Interrupt Enable Register: = 0x%x\n", regVal)); 1013 ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ 1014 1015 regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT); 1016 SA_DBG1(("PCIE - Error Interrupt Register: = 0x%x\n", regVal)); 1017 ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */ 1018 1019 /* read the scratch pad 1 register bit 2 */ 1020 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1021 toggleVal = regVal ^ SCRATCH_PAD1_RST; 1022 1023 /* set signature in host scratch pad0 register to tell SPC that the host performs the soft reset */ 1024 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, signature); 1025 1026 /* read required registers for confirmming */ 1027 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1028 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) 1029 { 1030 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); 1031 if(agNULL != agRoot->sdkData) 1032 { 1033 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5t"); 1034 } 1035 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",3)); 1036 return AGSA_RC_FAILURE; 1037 } 1038 1039 SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1040 1041 smTrace(hpDBG_VERY_LOUD,"Q3", 3); 1042 /* TP:Q3 siSpcSoftReset */ 1043 1044 /* step 3: host read GSM Configuration and Reset register */ 1045 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); 1046 /* Put those bits to low */ 1047 /* GSM XCBI offset = 0x70 0000 1048 0x00 Bit 13 COM_SLV_SW_RSTB 1 1049 0x00 Bit 12 QSSP_SW_RSTB 1 1050 0x00 Bit 11 RAAE_SW_RSTB 1 1051 0x00 Bit 9 RB_1_SW_RSTB 1 1052 0x00 Bit 8 SM_SW_RSTB 1 1053 */ 1054 regVal &= ~(0x00003b00); 1055 /* host write GSM Configuration and Reset register */ 1056 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ 1057 SA_DBG1(("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1058 1059 #if defined(SALLSDK_DEBUG) 1060 /* debugging messge */ 1061 SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); 1062 1063 SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); 1064 SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); 1065 SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); 1066 #endif 1067 1068 /* step 4: */ 1069 /* disable GSM - Read Address Parity Check */ 1070 smTrace(hpDBG_VERY_LOUD,"Q4", 4); 1071 /* TP:Q4 siSpcSoftReset */ 1072 regVal1 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); 1073 SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal1)); 1074 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1075 SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); 1076 1077 /* disable GSM - Write Address Parity Check */ 1078 regVal2 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); 1079 SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal2)); 1080 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1081 SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); 1082 1083 /* disable GSM - Write Data Parity Check */ 1084 regVal3 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); 1085 SA_DBG1(("GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", regVal3)); 1086 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1087 SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); 1088 /* step 5-a: delay 10 usec */ 1089 smTrace(hpDBG_VERY_LOUD,"Q5", 5); 1090 /* TP:Q5 siSpcSoftReset */ 1091 ossaStallThread(agRoot, 10); 1092 1093 /* step 5-b: set GPIO-0 output control to tristate anyway */ 1094 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GPIO_ADDR_BASE)) 1095 { 1096 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GPIO_ADDR_BASE)); 1097 if(agNULL != agRoot->sdkData) 1098 { 1099 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5t"); 1100 } 1101 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",4)); 1102 return AGSA_RC_FAILURE; 1103 } 1104 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 1105 SA_DBG1(("GPIO Output Control Register: = 0x%x\n", regVal)); 1106 /* set GPIO-0 output control to tri-state */ 1107 regVal &= 0xFFFFFFFC; 1108 ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */ 1109 1110 /* Step 6: Reset the IOP and AAP1 */ 1111 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1112 smTrace(hpDBG_VERY_LOUD,"Q6", 6); 1113 /* TP:Q6 siSpcSoftReset */ 1114 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) 1115 { 1116 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); 1117 if(agNULL != agRoot->sdkData) 1118 { 1119 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5t"); 1120 } 1121 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); 1122 return AGSA_RC_FAILURE; 1123 } 1124 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1125 SA_DBG1(("Top Register before resetting IOP/AAP1: = 0x%x\n", regVal)); 1126 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1127 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1128 1129 /* step 7: Reset the BDMA/OSSP */ 1130 smTrace(hpDBG_VERY_LOUD,"Q7", 7); 1131 /* TP:Q7 siSpcSoftReset */ 1132 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1133 SA_DBG1(("Top Register before resetting BDMA/OSSP: = 0x%x\n", regVal)); 1134 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1135 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1136 1137 /* step 8: delay 10 usec */ 1138 smTrace(hpDBG_VERY_LOUD,"Q8", 8); 1139 /* TP:Q8 siSpcSoftReset */ 1140 1141 ossaStallThread(agRoot, WAIT_INCREMENT); 1142 1143 /* step 9: bring the BDMA and OSSP out of reset */ 1144 smTrace(hpDBG_VERY_LOUD,"Q9", 9); 1145 /* TP:Q9 siSpcSoftReset */ 1146 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1147 SA_DBG1(("Top Register before bringing up BDMA/OSSP: = 0x%x\n", regVal)); 1148 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1149 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1150 1151 /* step 10: delay 10 usec */ 1152 smTrace(hpDBG_VERY_LOUD,"QA", 10); 1153 /* TP:QA siSpcSoftReset */ 1154 ossaStallThread(agRoot, WAIT_INCREMENT); 1155 1156 /* step 11: reads and sets the GSM Configuration and Reset Register */ 1157 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1158 smTrace(hpDBG_VERY_LOUD,"QB", 11); 1159 /* TP:QB siSpcSoftReset */ 1160 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) 1161 { 1162 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); 1163 if(agNULL != agRoot->sdkData) 1164 { 1165 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5t"); 1166 } 1167 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); 1168 return AGSA_RC_FAILURE; 1169 } 1170 SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1171 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); 1172 /* Put those bits to high */ 1173 /* GSM XCBI offset = 0x70 0000 1174 0x00 Bit 13 COM_SLV_SW_RSTB 1 1175 0x00 Bit 12 QSSP_SW_RSTB 1 1176 0x00 Bit 11 RAAE_SW_RSTB 1 1177 0x00 Bit 9 RB_1_SW_RSTB 1 1178 0x00 Bit 8 SM_SW_RSTB 1 1179 */ 1180 regVal |= (GSM_CONFIG_RESET_VALUE); 1181 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ 1182 SA_DBG1(("GSM 0x0 (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1183 1184 #if defined(SALLSDK_DEBUG) 1185 /* debugging messge */ 1186 SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); 1187 SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); 1188 SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); 1189 SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); 1190 #endif 1191 1192 /* step 12: Restore GSM - Read Address Parity Check */ 1193 smTrace(hpDBG_VERY_LOUD,"QC", 12); 1194 /* TP:QC siSpcSoftReset */ 1195 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); /* just for debugging */ 1196 SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal)); 1197 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, regVal1); /* siSpcSoftReset */ 1198 SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); 1199 1200 /* Restore GSM - Write Address Parity Check */ 1201 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); /* just for debugging */ 1202 SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal)); 1203 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); /* siSpcSoftReset */ 1204 SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); 1205 1206 /* Restore GSM - Write Data Parity Check */ 1207 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); /* just for debugging */ 1208 SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable = 0x%x\n", regVal)); 1209 ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); /* siSpcSoftReset */ 1210 SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); 1211 1212 /* step 13: bring the IOP and AAP1 out of reset */ 1213 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1214 smTrace(hpDBG_VERY_LOUD,"QD", 13); 1215 /* TP:QD siSpcSoftReset */ 1216 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) 1217 { 1218 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); 1219 if(agNULL != agRoot->sdkData) 1220 { 1221 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5t"); 1222 } 1223 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",7)); 1224 return AGSA_RC_FAILURE; 1225 } 1226 regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1227 SA_DBG1(("Top Register before bringing up IOP/AAP1: = 0x%x\n", regVal)); 1228 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1229 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1230 1231 if (signature == SPC_SOFT_RESET_SIGNATURE) 1232 { 1233 /* step 14: delay 20 milli - Normal Mode */ 1234 ossaStallThread(agRoot, WAIT_INCREMENT); 1235 }else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 1236 { 1237 /* step 14: delay 200 milli - HDA Mode */ 1238 ossaStallThread(agRoot, 200 * 1000); 1239 } 1240 1241 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1242 if (signature == SPC_SOFT_RESET_SIGNATURE) 1243 { 1244 /* step 15 (Normal Mode): wait until scratch pad1 register bit 2 toggled */ 1245 max_wait_time = WAIT_SECONDS(2); /* 2 sec */ 1246 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1247 do 1248 { 1249 ossaStallThread(agRoot, WAIT_INCREMENT); 1250 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1251 } while ((regVal != toggleVal) && (max_wait_count -=WAIT_INCREMENT)); 1252 1253 if ( !max_wait_count) 1254 { 1255 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1256 SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal)); 1257 if(agNULL != agRoot->sdkData) 1258 { 1259 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5t"); 1260 } 1261 #if defined(SALLSDK_DEBUG) 1262 SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1263 SA_DBG1(("siSpcSoftReset: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1264 SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1265 #endif 1266 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",8)); 1267 return AGSA_RC_FAILURE; 1268 } 1269 1270 /* step 16 (Normal)step 15 (HDA) - Clear ODMR and ODCR */ 1271 smTrace(hpDBG_VERY_LOUD,"QG", 16); 1272 /* TP:QG siSpcSoftReset */ 1273 1274 ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 1275 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); 1276 } 1277 else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 1278 { 1279 if(agNULL != agRoot->sdkData) 1280 { 1281 SA_DBG1(("siSpcSoftReset: HDA Soft Reset Complete\n")); 1282 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5t"); 1283 } 1284 return AGSA_RC_SUCCESS; 1285 } 1286 1287 1288 /* step 17 (Normal Mode): wait for the FW and IOP to get ready - 1 sec timeout */ 1289 /* Wait for the SPC Configuration Table to be ready */ 1290 if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) 1291 { 1292 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1293 /* return error if MPI Configuration Table not ready */ 1294 SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); 1295 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 1296 /* return error if MPI Configuration Table not ready */ 1297 SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); 1298 if(agNULL != agRoot->sdkData) 1299 { 1300 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5t"); 1301 } 1302 #if defined(SALLSDK_DEBUG) 1303 SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1304 SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1305 #endif 1306 SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",9)); 1307 return AGSA_RC_FAILURE; 1308 } 1309 smTrace(hpDBG_VERY_LOUD,"QI", 18); 1310 /* TP:QI siSpcSoftReset */ 1311 1312 if(agNULL != agRoot->sdkData) 1313 { 1314 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5t"); 1315 } 1316 1317 SA_DBG1(("siSpcSoftReset: Soft Reset Complete\n")); 1318 1319 return AGSA_RC_SUCCESS; 1320 } 1321 1322 /******************************************************************************/ 1323 /*! \brief Function to do BAR shifting 1324 * 1325 * The siBarShift() function is called to shift BAR base address 1326 * 1327 * \param agRoot handles for this instance of SAS/SATA hardware 1328 * \param shiftValue shifting value 1329 * 1330 * \return success or fail 1331 */ 1332 /*******************************************************************************/ 1333 GLOBAL bit32 siBar4Shift( 1334 agsaRoot_t *agRoot, 1335 bit32 shiftValue 1336 ) 1337 { 1338 bit32 regVal; 1339 bit32 max_wait_time; 1340 bit32 max_wait_count; 1341 1342 smTraceFuncEnter(hpDBG_VERY_LOUD,"5e"); 1343 smTrace(hpDBG_VERY_LOUD,"GA",shiftValue); 1344 /* TP:GA shiftValue */ 1345 1346 SA_DBG2(("siBar4Shift: shiftValue 0x%x\n",shiftValue)); 1347 1348 if(smIS_SPCV(agRoot) ) 1349 { 1350 ossaHwRegWriteExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister, shiftValue); 1351 /* confirm the setting is written */ 1352 max_wait_time = WAIT_SECONDS(1); /* 1 sec */ 1353 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1354 do 1355 { 1356 ossaStallThread(agRoot, WAIT_INCREMENT); 1357 regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister); 1358 } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); 1359 1360 if (!max_wait_count) 1361 { 1362 SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); 1363 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5e"); 1364 return AGSA_RC_FAILURE; 1365 } 1366 } 1367 else if(smIS_SPC(agRoot)) 1368 { 1369 /* program the inbound AXI translation Lower Address */ 1370 ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 1371 1372 /* confirm the setting is written */ 1373 max_wait_time = WAIT_SECONDS(1); /* 1 sec */ 1374 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1375 do 1376 { 1377 ossaStallThread(agRoot, WAIT_INCREMENT); 1378 regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW); 1379 } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); 1380 1381 if (!max_wait_count) 1382 { 1383 SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); 1384 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5e"); 1385 return AGSA_RC_FAILURE; 1386 } 1387 } 1388 else 1389 { 1390 SA_DBG1(("siBar4Shift: hba type is not support\n")); 1391 return AGSA_RC_FAILURE; 1392 } 1393 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5e"); 1394 1395 return AGSA_RC_SUCCESS; 1396 } 1397 1398 #ifdef SA_ENABLE_HDA_FUNCTIONS 1399 /******************************************************************************/ 1400 /*! \brief Function to force HDA mode the SPC 1401 * 1402 * The siHDAMode() function is called to force to HDA mode. Upon return, 1403 * the SPC FW loaded. The PCIe bus is not touched. 1404 * 1405 * \param agRoot handles for this instance of SAS/SATA hardware 1406 * \param HDAMode 0 - HDA soft reset mode, 1 - HDA mode 1407 * \param fwImg points to structure containing fw images 1408 * 1409 * \return -void- 1410 */ 1411 /*******************************************************************************/ 1412 GLOBAL bit32 siHDAMode( 1413 agsaRoot_t *agRoot, 1414 bit32 HDAMode, 1415 agsaFwImg_t *userFwImg 1416 ) 1417 { 1418 spc_configMainDescriptor_t mainCfg; 1419 bit32 regVal; 1420 bit32 max_wait_time; 1421 bit32 max_wait_count; 1422 agsaFwImg_t flashImg; 1423 bit32 startTime, endTime; // TestBase 1424 bit32 stepTime[12]; // TestBase 1425 1426 bit32 HDA_Been_Reset = agFALSE; 1427 1428 smTraceFuncEnter(hpDBG_VERY_LOUD,"5d"); 1429 1430 /* sanity check */ 1431 SA_ASSERT( (agNULL != agRoot), ""); 1432 1433 SA_DBG1(("siHDAMode: start\n")); 1434 1435 si_memset(&flashImg, 0, sizeof(flashImg)); 1436 #ifndef SA_EXCLUDE_FW_IMG 1437 1438 /* Set up built-in (default) FW image pointers */ 1439 /* 1440 flashImg.aap1Img = (bit8*)(&aap1array); 1441 flashImg.aap1Len = sizeof(aap1array); 1442 flashImg.ilaImg = (bit8*)(&ilaarray); 1443 flashImg.ilaLen = sizeof(ilaarray); 1444 flashImg.iopImg = (bit8*)(&ioparray); 1445 flashImg.iopLen = sizeof(ioparray); 1446 */ 1447 #endif 1448 TryAfterReset: 1449 1450 /* Set up user FW image pointers (if passed in) */ 1451 if (userFwImg) 1452 { 1453 SA_DBG1(("siHDAMode: User fw structure @ %p\n",userFwImg)); 1454 if (userFwImg->aap1Img && userFwImg->aap1Len) 1455 { 1456 flashImg.aap1Img = userFwImg->aap1Img; 1457 flashImg.aap1Len = userFwImg->aap1Len; 1458 SA_DBG1(("siHDAMode: User fw aap1 @ %p (%d)\n", flashImg.aap1Img, flashImg.aap1Len)); 1459 } 1460 if (userFwImg->ilaImg && userFwImg->ilaLen) 1461 { 1462 flashImg.ilaImg = userFwImg->ilaImg; 1463 flashImg.ilaLen = userFwImg->ilaLen; 1464 SA_DBG1(("siHDAMode: User fw ila @ %p (%d)\n", flashImg.ilaImg, flashImg.ilaLen)); 1465 } 1466 if (userFwImg->iopImg && userFwImg->iopLen) 1467 { 1468 flashImg.iopImg = userFwImg->iopImg; 1469 flashImg.iopLen = userFwImg->iopLen; 1470 SA_DBG1(("siHDAMode: User fw iop @ %p (%d)\n", flashImg.iopImg, flashImg.iopLen)); 1471 } 1472 if (userFwImg->istrImg && userFwImg->istrLen) 1473 { 1474 flashImg.istrImg = userFwImg->istrImg; 1475 flashImg.istrLen = userFwImg->istrLen; 1476 SA_DBG1(("siHDAMode: User fw istr @ %p (%d)\n", flashImg.istrImg, flashImg.istrLen)); 1477 } 1478 } 1479 else 1480 { 1481 SA_DBG1(("siHDAMode: user supplied FW is not found\n")); 1482 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5d"); 1483 return AGSA_RC_FAILURE; 1484 } 1485 1486 #ifdef SA_EXCLUDE_FW_IMG 1487 /* Check that fw images are setup properly */ 1488 if (!(flashImg.aap1Img && flashImg.aap1Len && 1489 flashImg.ilaImg && flashImg.ilaLen && 1490 flashImg.iopImg && flashImg.iopLen && 1491 flashImg.istrImg && flashImg.istrLen)) 1492 { 1493 SA_DBG1(("siHDAMode: Built-in FW img excluded and not user defined.\n")); 1494 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5d"); 1495 return AGSA_RC_FAILURE; 1496 } 1497 #endif 1498 1499 /* Check HDA mode with Soft Reset */ 1500 if (!HDAMode) 1501 { 1502 /* Try soft reset until it goes into HDA mode */ 1503 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1504 1505 /* read response state */ 1506 regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1507 if (regVal != BOOTTLOADERHDA_IDLE) 1508 { 1509 /* Can not go into HDA mode with 200 ms wait - HDA Soft Reset failed */ 1510 SA_DBG1(("siHDAMode: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1511 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5d"); 1512 return AGSA_RC_FAILURE; 1513 } 1514 1515 /* HDA Mode - Clear ODMR and ODCR */ 1516 ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 1517 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); 1518 } 1519 1520 /* Step 1: Poll BOOTTLOADERHDA_IDLE - HDA mode */ 1521 SA_DBG1(("siHDAMode: Step1:Poll for HDAR_IDLE\n")); 1522 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1523 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1524 do 1525 { 1526 ossaStallThread(agRoot, WAIT_INCREMENT); 1527 regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1528 } while ((regVal != BOOTTLOADERHDA_IDLE) && (max_wait_count -= WAIT_INCREMENT)); 1529 1530 if (!max_wait_count) 1531 { 1532 1533 if( !HDA_Been_Reset ) 1534 { 1535 1536 SA_DBG1(("siHDAMode: Reset: Step1:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1537 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1538 HDA_Been_Reset = agTRUE; 1539 goto TryAfterReset; 1540 1541 } 1542 1543 SA_DBG1(("siHDAMode: Step1:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1544 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5d"); 1545 return AGSA_RC_FAILURE; 1546 } 1547 1548 /* Step 2: Push the init string to 0x0047E000 & data compare */ 1549 SA_DBG1(("siHDAMode: Step2:Push the init string to 0x0047E000!\n")); 1550 1551 if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, ILA_ISTR_ADDROFFSETHDA, flashImg.istrImg, flashImg.istrLen)) 1552 { 1553 SA_DBG1(("siHDAMode: Step2:Copy ISTR array to 0x%x failed\n", ILA_ISTR_ADDROFFSETHDA)); 1554 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5d"); 1555 return AGSA_RC_FAILURE; 1556 } 1557 1558 /* Tell FW ISTR is ready */ 1559 regVal = (HDA_ISTR_DONE | (bit32)flashImg.istrLen); 1560 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1561 SA_DBG1(("siHDAMode: Step2:Host Scratchpad 3 (AAP1-ISTR): 0x%x\n", regVal)); 1562 1563 stepTime[2] = ossaTimeStamp(agRoot); // TestBase 1564 SA_DBG1(("siHDAMode: End Step2: (step_time[2] = %d)\n", stepTime[2])); // TestBase 1565 1566 /* Step 3: Write the HDA mode SoftReset signature */ 1567 SA_DBG1(("siHDAMode: Step3:Set Signature!\n")); 1568 /* set signature in host scratch pad0 register to tell SPC that the host performs the HDA mode */ 1569 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, SPC_HDASOFT_RESET_SIGNATURE); 1570 1571 stepTime[3] = ossaTimeStamp(agRoot); // TestBase 1572 SA_DBG1(("siHDAMode: End Step3: (step_time[3] = %d)\n", stepTime[3])); // TestBase 1573 1574 // Priya (Apps) requested that the FW load time measurement be started here 1575 startTime = ossaTimeStamp(agRoot); 1576 SA_DBG1(("siHDAMode: Step4: Ready to push ILA to 0x00400000! (start_time = %d)\n", startTime)); // TestBase 1577 1578 /* Step 4: Push the ILA image to 0x00400000 */ 1579 SA_DBG1(("siHDAMode: Step4:Push the ILA to 0x00400000!\n")); 1580 1581 if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, 0x0, flashImg.ilaImg, flashImg.ilaLen)) 1582 { 1583 SA_DBG1(("siHDAMode:Step4:Copy ILA array to 0x%x failed\n", 0x0)); 1584 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5d"); 1585 return AGSA_RC_FAILURE; 1586 } 1587 1588 stepTime[4] = ossaTimeStamp(agRoot); 1589 SA_DBG1(("siHDAMode: End Step4: (step_time[4] = %d, %d ms)\n", stepTime[4], (stepTime[4] - startTime))); // TestBase 1590 1591 /* Step 5: Tell boot ROM to authenticate ILA and execute it */ 1592 ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB, 0); 1593 ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_PAR_LEN_OFFSET, flashImg.ilaLen); 1594 regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16; 1595 regVal ++; 1596 regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD; 1597 SA_DBG1(("siHDAMode: Step5:Execute ILA CMD: 0x%x\n", regVal)); 1598 ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_CMD_CODE_OFFSET, regVal); /* Execute Command */ 1599 1600 stepTime[5] = ossaTimeStamp(agRoot); 1601 SA_DBG1(("siHDAMode: End Step5: (step_time[5] = %d, %d ms)\n", stepTime[5], (stepTime[5] - startTime))); // TestBase 1602 1603 1604 /* Step 6: Checking response status from boot ROM, HDAR_EXEC (good), HDAR_BAD_CMD and HDAR_BAD_IMG */ 1605 SA_DBG1(("siHDAMode: Step6:Checking boot ROM reponse status!\n")); 1606 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1607 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1608 do 1609 { 1610 ossaStallThread(agRoot, WAIT_INCREMENT); 1611 regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1612 if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal)) 1613 break; 1614 } while (max_wait_count-=WAIT_INCREMENT); 1615 1616 if (HDAR_BAD_IMG == regVal) 1617 { 1618 SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1619 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5d"); 1620 return AGSA_RC_FAILURE; 1621 } 1622 if (HDAR_BAD_CMD == regVal) 1623 { 1624 SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1625 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5d"); 1626 return AGSA_RC_FAILURE; 1627 } 1628 if (!max_wait_count) 1629 { 1630 SA_DBG1(("siHDAMode: Step6:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1631 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5d"); 1632 return AGSA_RC_FAILURE; 1633 } 1634 1635 stepTime[6] = ossaTimeStamp(agRoot); 1636 SA_DBG1(("siHDAMode: End Step6: (step_time[6] = %d, %d ms)\n", stepTime[6], (stepTime[6] - startTime))); // TestBase 1637 1638 /* Step 7: Poll ILAHDA_AAP1IMGGET/Offset in MSGU Scratchpad 0 */ 1639 /* Check MSGU Scratchpad 1 [1,0] == 00 */ 1640 SA_DBG1(("siHDAMode: Step7:Poll ILAHDA_AAP1_IMG_GET!\n")); 1641 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1642 SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 1: 0x%x\n", regVal)); 1643 max_wait_time = WAIT_SECONDS(gWait_3); /* 3 sec */ 1644 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1645 do 1646 { 1647 ossaStallThread(agRoot, WAIT_INCREMENT); 1648 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; 1649 } while ((regVal != ILAHDA_AAP1_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); 1650 1651 if (!max_wait_count) 1652 { 1653 1654 if( !HDA_Been_Reset ) 1655 { 1656 1657 SA_DBG1(("siHDAMode: Reset: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1658 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1659 HDA_Been_Reset = agTRUE; 1660 goto TryAfterReset; 1661 1662 } 1663 1664 SA_DBG1(("siHDAMode: TIMEOUT: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1665 #if defined(SALLSDK_DEBUG) 1666 SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1667 SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1668 SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1669 SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1670 #endif 1671 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5d"); 1672 return AGSA_RC_FAILURE; 1673 } 1674 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1675 SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 0: 0x%x\n", regVal)); 1676 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & 0x00FFFFFF; 1677 1678 stepTime[7] = ossaTimeStamp(agRoot); 1679 SA_DBG1(("siHDAMode: End Step7: (step_time[7] = %d, %d ms)\n", stepTime[7], (stepTime[7] - startTime))); // TestBase 1680 1681 /* Step 8: Copy AAP1 image, update the Host Scratchpad 3 */ 1682 SA_DBG1(("siHDAMode: Step8:Push the AAP1 to 0x00400000 plus 0x%x\n", regVal)); 1683 1684 if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.aap1Img, flashImg.aap1Len)) 1685 { 1686 SA_DBG1(("siHDAMode: Step8:Copy AAP1 array to 0x%x failed\n", regVal)); 1687 #if defined(SALLSDK_DEBUG) 1688 SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1689 SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1690 SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1691 SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1692 #endif 1693 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5d"); 1694 return AGSA_RC_FAILURE; 1695 } 1696 1697 regVal = (HDA_AAP1_DONE | (bit32)flashImg.aap1Len); 1698 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1699 SA_DBG1(("siHDAMode: Step8:Host Scratchpad 3 (AAP1): 0x%x\n", regVal)); 1700 1701 stepTime[8] = ossaTimeStamp(agRoot); 1702 SA_DBG1(("siHDAMode: End Step8: (step_time[8] = %d, %d ms)\n", stepTime[8], (stepTime[8] - startTime))); // TestBase 1703 1704 /* Step 9: Poll ILAHDA_IOPIMGGET/Offset in MSGU Scratchpad 0 */ 1705 SA_DBG1(("siHDAMode: Step9:Poll ILAHDA_IOP_IMG_GET!\n")); 1706 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1707 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1708 do 1709 { 1710 ossaStallThread(agRoot, WAIT_INCREMENT); 1711 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; 1712 } while ((regVal != ILAHDA_IOP_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); 1713 1714 if (!max_wait_count) 1715 { 1716 SA_DBG1(("siHDAMode: Step9:TIMEOUT:MSGU_SCRATCH_PAD_0 = 0x%x\n", regVal)); 1717 #if defined(SALLSDK_DEBUG) 1718 SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1719 SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1720 SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1721 #endif 1722 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5d"); 1723 return AGSA_RC_FAILURE; 1724 } 1725 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1726 SA_DBG1(("siHDAMode: Step9:MSG Scratchpad 0: 0x%x\n", regVal)); 1727 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & HDA_GSM_OFFSET_BITS; 1728 1729 stepTime[9] = ossaTimeStamp(agRoot); 1730 SA_DBG1(("siHDAMode: End Step9: (step_time[9] = %d, %d ms)\n", stepTime[9], (stepTime[9] - startTime))); // TestBase 1731 1732 // saHdaLoadForceHalt(agRoot); // TestBase 1733 1734 /* Step 10: Copy IOP image, update the Host Scratchpad 3 */ 1735 SA_DBG1(("siHDAMode: Step10:Push the IOP to 0x00400000 plus 0x%x!\n", regVal)); 1736 1737 if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.iopImg, flashImg.iopLen)) 1738 { 1739 SA_DBG1(("siHDAMode: Step10:Copy IOP array to 0x%x failed\n", regVal)); 1740 #if defined(SALLSDK_DEBUG) 1741 SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1742 SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1743 SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1744 #endif 1745 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "5d"); 1746 return AGSA_RC_FAILURE; 1747 } 1748 1749 regVal = (HDA_IOP_DONE | (bit32)flashImg.iopLen); 1750 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1751 SA_DBG1(("siHDAMode: Step10:Host Scratchpad 3 (IOP): 0x%x\n", regVal)); 1752 1753 stepTime[10] = ossaTimeStamp(agRoot); 1754 SA_DBG1(("siHDAMode: End Step10: (step_time[10] = %d, %d ms)\n", stepTime[10], (stepTime[10] - startTime))); // TestBase 1755 1756 /* Clear the signature */ 1757 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, 0); 1758 1759 /* step 11: wait for the FW and IOP to get ready - 1 sec timeout */ 1760 /* Wait for the SPC Configuration Table to be ready */ 1761 stepTime[11] = ossaTimeStamp(agRoot); 1762 SA_DBG1(("siHDAMode: Start Step11: Wait for FW ready. (step_time[11.1] = %d, %d ms)\n", stepTime[11], (stepTime[11] - startTime))); // TestBase 1763 1764 endTime = ossaTimeStamp(agRoot); 1765 SA_DBG1(("siHDAMode: End Step11: FW ready! (end_time= %d, fw_load_time = %d ms)\n", endTime, endTime - startTime)); // TestBase 1766 1767 SA_DBG1(("siHDAMode: Step11:Poll for FW ready!\n")); 1768 if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) 1769 { 1770 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1771 /* return error if MPI Configuration Table not ready */ 1772 SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); 1773 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 1774 /* return error if MPI Configuration Table not ready */ 1775 SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); 1776 /* read detail fatal errors */ 1777 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1778 SA_DBG1(("siHDAMode: Step11:ScratchPad0 AAP error code 0x%x\n", regVal)); 1779 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3); 1780 SA_DBG1(("siHDAMode: Step11:ScratchPad3 IOP error code 0x%x\n", regVal)); 1781 smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "5d"); 1782 return AGSA_RC_FAILURE; 1783 } 1784 1785 smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "5d"); 1786 1787 SA_DBG1(("siHDAMode: HDA Mode Complete\n")); 1788 1789 return AGSA_RC_SUCCESS; 1790 } 1791 1792 /******************************************************************************/ 1793 /*! \brief memcopy cross PCI from host memory to card memory 1794 * 1795 * \param agRoot handles for this instance of SAS/SATA hardware 1796 * \param dstoffset distination offset 1797 * \param src source pointer 1798 * \param DWcount DWord count 1799 * \param busBaseNumber PCI Bus Base number 1800 * 1801 * \return -void- 1802 * 1803 */ 1804 /*******************************************************************************/ 1805 LOCAL void siPciMemCpy(agsaRoot_t *agRoot, 1806 bit32 dstoffset, 1807 void *src, 1808 bit32 DWcount, 1809 bit32 busBaseNumber 1810 ) 1811 { 1812 bit32 i, val; 1813 bit32 *src1; 1814 1815 src1 = (bit32 *)src; 1816 1817 for (i= 0; i < DWcount; i++) 1818 { 1819 val = BIT32_TO_LEBIT32(src1[i]); 1820 ossaHwRegWriteExt(agRoot, busBaseNumber, (dstoffset + i * 4), val); 1821 } 1822 1823 return; 1824 } 1825 1826 /******************************************************************************/ 1827 /*! \brief Function to copy FW array 1828 * 1829 * The siBar4Cpy() function is called to copy FW array via BAR4 1830 * (PCIe spec: BAR4, MEMBASE-III in PM, PCIBAR2 in host driver) 1831 * in 64-KB MEMBASE MODE. 1832 * 1833 * \param agRoot handles for this instance of SAS/SATA hardware 1834 * \param offset destination offset 1835 * \param parray pointer of array 1836 * \param array_size size of array 1837 * 1838 * \return AGSA_RC_SUCCESS or AGSA_RC_FAILURE 1839 */ 1840 /*******************************************************************************/ 1841 LOCAL bit32 siBar4Cpy( 1842 agsaRoot_t *agRoot, 1843 bit32 offset, 1844 bit8 * parray, 1845 bit32 array_size 1846 ) 1847 { 1848 bit32 dest_shift_addr, dest_offset, cpy_size; 1849 1850 smTraceFuncEnter(hpDBG_VERY_LOUD,"5f"); 1851 1852 /* first time to shift */ 1853 dest_shift_addr = (GSMSM_AXI_LOWERADDR+offset) & SHIFT_MASK; 1854 dest_offset = offset & OFFSET_MASK; 1855 do 1856 { 1857 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, dest_shift_addr)) 1858 { 1859 SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", dest_shift_addr)); 1860 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5f"); 1861 return AGSA_RC_FAILURE; 1862 } 1863 1864 if ((dest_offset+array_size) > SIZE_64KB) 1865 { 1866 cpy_size = SIZE_64KB - dest_offset; 1867 } 1868 else 1869 cpy_size = array_size; 1870 1871 siPciMemCpy(agRoot, dest_offset, parray, (bit32)(CEILING(cpy_size,4)), PCIBAR2); 1872 1873 array_size -= cpy_size; 1874 dest_shift_addr += SIZE_64KB; 1875 dest_offset = 0; 1876 parray = parray + cpy_size; 1877 } while (array_size !=0 ); 1878 1879 /* Shift back to BAR4 original address */ 1880 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) 1881 { 1882 SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", 0x0)); 1883 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5f"); 1884 return AGSA_RC_FAILURE; 1885 } 1886 1887 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5f"); 1888 1889 return AGSA_RC_SUCCESS; 1890 } 1891 1892 GLOBAL 1893 bit32 siHDAMode_V( 1894 agsaRoot_t *agRoot, 1895 bit32 HDAMode, 1896 agsaFwImg_t *userFwImg 1897 ) 1898 { 1899 bit32 returnVal = AGSA_RC_FAILURE; 1900 bit32 save,i,biggest; 1901 bit32 hda_status; 1902 bit32 hda_command_complete = 0; 1903 bit32 max_wait_time; 1904 bit32 max_wait_count; 1905 bit32 seq_id = 0; 1906 bit32 base_Hi = 0; 1907 bit32 base_Lo = 0; 1908 bit8 * pbase; 1909 1910 spcv_hda_cmd_t hdacmd; 1911 spcv_hda_rsp_t hdarsp; 1912 1913 agsaLLRoot_t *saRoot; 1914 1915 /* sanity check */ 1916 SA_ASSERT( (agNULL != agRoot), ""); 1917 1918 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1919 1920 /* sanity check */ 1921 SA_ASSERT( (agNULL != saRoot), "saRoot is NULL"); 1922 1923 smTraceFuncEnter(hpDBG_VERY_LOUD,"2W"); 1924 1925 SA_DBG1(("siHDAMode_V: HDAMode %X\n",HDAMode)); 1926 1927 siScratchDump(agRoot); 1928 if( agNULL == userFwImg) 1929 { 1930 SA_DBG1(("siHDAMode_V: No image agNULL == userFwImg\n" )); 1931 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2W"); 1932 return returnVal; 1933 } 1934 1935 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1936 1937 SA_DBG1(("siHDAMode_V: hda_status 0x%08X\n",hda_status )); 1938 SA_DBG1(("siHDAMode_V: STEP 1\n")); 1939 1940 smTrace(hpDBG_VERY_LOUD,"2X",1 ); 1941 /* TP:2X STEP 1 */ 1942 1943 /* Find largest Physical chunk memory */ 1944 for(i=0,biggest = 0,save = 0; i < saRoot->memoryAllocated.count; i++) 1945 { 1946 if( saRoot->memoryAllocated.agMemory[i].totalLength > biggest) 1947 { 1948 1949 if(biggest < saRoot->memoryAllocated.agMemory[i].totalLength) 1950 { 1951 save = i; 1952 biggest = saRoot->memoryAllocated.agMemory[i].totalLength; 1953 } 1954 1955 } 1956 } 1957 /* 1958 Step 1 The host reads the HDA response field RSP_CODE at byte offset 28:29 of the response block 1959 for HDAR_IDLE (0x8002) via MEMBASE-I. A value other than HDAR_IDLE (0x8002) indicates that the 1960 SPCv controller is not in HDA mode. Follow the steps described in Section 4.21.1 to bring the 1961 SPCv controller into HDA mode. When the host reads the correct RSP_CODE, it indicates that the 1962 SPCv controller boot ROM is ready to proceed to the next step of HDA initialization 1963 */ 1964 1965 base_Hi = saRoot->memoryAllocated.agMemory[save].phyAddrUpper; 1966 base_Lo = saRoot->memoryAllocated.agMemory[save].phyAddrLower; 1967 pbase = saRoot->memoryAllocated.agMemory[save].virtPtr; 1968 SA_DBG1(("siHDAMode_V:Use DMA memory at [%d] size 0x%x (%d) DMA Loc U 0x%08x L 0x%08x @%p\n",save, 1969 biggest, 1970 biggest, 1971 base_Hi, 1972 base_Lo, 1973 pbase 1974 )); 1975 1976 1977 SA_DBG1(("siHDAMode_V: HDA aap1Img %p len %8d 0x%x\n", userFwImg->aap1Img, userFwImg->aap1Len , userFwImg->aap1Len )); 1978 SA_DBG1(("siHDAMode_V: HDA ilaImg %p len %8d 0x%x\n", userFwImg->ilaImg, userFwImg->ilaLen , userFwImg->ilaLen )); 1979 SA_DBG1(("siHDAMode_V: HDA iopImg %p len %8d 0x%x\n", userFwImg->iopImg, userFwImg->iopLen , userFwImg->iopLen )); 1980 if(userFwImg->aap1Len > biggest) 1981 { 1982 SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d aap1Len\n", biggest ,userFwImg->aap1Len)); 1983 SA_ASSERT( (agNULL != agRoot), "aap1Len > biggest"); 1984 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2W"); 1985 return returnVal; 1986 } 1987 if(userFwImg->ilaLen > biggest) 1988 { 1989 SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d ilaLen\n", biggest ,userFwImg->ilaLen)); 1990 SA_ASSERT( (agNULL != agRoot), "ilaLen > biggest"); 1991 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2W"); 1992 return returnVal; 1993 } 1994 if(userFwImg->iopLen > biggest) 1995 { 1996 SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d iopLen\n", biggest ,userFwImg->iopLen)); 1997 SA_ASSERT( (agNULL != agRoot), "iopLen > biggest"); 1998 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2W"); 1999 return returnVal; 2000 } 2001 2002 2003 if(HDA_STEP_2) 2004 { /* ILA */ 2005 si_memset(pbase, 0, biggest); 2006 2007 if( userFwImg->ilaLen < biggest) 2008 { 2009 si_memcpy(pbase,userFwImg->ilaImg, userFwImg->ilaLen ); 2010 } 2011 else 2012 { 2013 SA_DBG1(("siHDAMode_V: userFwImg->ilaLen 0x%x < biggest 0x%x\n",userFwImg->ilaLen,biggest)); 2014 } 2015 2016 si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); 2017 si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); 2018 2019 hda_status = ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28); 2020 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) 2021 { 2022 2023 hdacmd.cmdparm_0 = base_Lo; /* source DmaBase_l*/ 2024 hdacmd.cmdparm_1 = base_Hi; /* source DmaBase_u*/ 2025 hdacmd.cmdparm_2 = 0x1e200000; /* destin */ 2026 hdacmd.cmdparm_3 = 0; /* destin */ 2027 hdacmd.cmdparm_4 = userFwImg->ilaLen ; /* length */ 2028 hdacmd.cmdparm_5 = 0;/* not used */ 2029 hdacmd.cmdparm_6 = 0;/* not used */ 2030 seq_id++; 2031 hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA; 2032 2033 SA_DBG1(("siHDAMode_V: Write SPC_V_HDAC_DMA STEP 2\n")); 2034 /* 2035 Step 2 2036 The host writes the HDAC_DMA (0x000 24) in the command field CMD_CODE via MEMBASE-I 2037 for issuing the DMA command to ask the boot ROM to pull the ILA image via DMA into 2038 GSM with the following parameters set up first: 2039 Parameter 1:0: Host physical address for holding the HDA-ILA image. 2040 Parameter 3:2: GSM physical address 0x1E20_0000. 2041 Parameter 4: the length of the HDAILA image. 2042 */ 2043 2044 SA_DBG2(("siHDAMode_V: Write ILA to offset %X\n",hdacmd.cmdparm_2)); 2045 2046 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0,hdacmd.cmdparm_0); 2047 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4,hdacmd.cmdparm_1); 2048 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8,hdacmd.cmdparm_2); 2049 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); 2050 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); 2051 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); 2052 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); 2053 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); 2054 2055 SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2056 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), 2057 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), 2058 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), 2059 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), 2060 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), 2061 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), 2062 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), 2063 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); 2064 2065 SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); 2066 2067 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2068 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2069 hda_command_complete = 0; 2070 do 2071 { 2072 ossaStallThread(agRoot, WAIT_INCREMENT); 2073 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2074 } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2075 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 2 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2076 2077 smTrace(hpDBG_VERY_LOUD,"2Y",(max_wait_time - max_wait_count) ); 2078 /* TP:2Y STEP 2 took */ 2079 2080 2081 if(! hda_command_complete) 2082 { 2083 SA_DBG1(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2084 SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2085 SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2086 SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2087 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 2\n" )); 2088 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2W"); 2089 return returnVal; 2090 } 2091 2092 2093 SA_DBG2(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2094 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2095 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2096 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2097 2098 } 2099 2100 SA_DBG1(("siHDAMode_V: ILA DMA done\n" )); 2101 } /* end ila */ 2102 2103 if(HDA_STEP_3) 2104 { 2105 2106 SA_DBG1(("siHDAMode_V: STEP 3\n")); 2107 /* 2108 Step 3 2109 The host polls the HDA response field RSP_CODE for HDAR_IDLE (0x8002) via MEMBASE-I. The polling timeout 2110 should be no more than 1 second. The response status, HDAR_IDLE with its status equal to 0x10, 2111 indicates a DMA success response from the boot ROM. Response states that indicate a failure are: 2112 HDAR_BAD_CMD HDAR_BAD_IMG HDAR_IDLE with its status equal to 0x11 2113 2114 */ 2115 2116 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2117 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2118 hda_command_complete = 0; 2119 do 2120 { 2121 ossaStallThread(agRoot, WAIT_INCREMENT); 2122 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2123 } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2124 2125 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 3 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2126 smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); 2127 /* TP:2Z STEP 3 took */ 2128 2129 if(! hda_command_complete) 2130 { 2131 2132 SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2133 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2134 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2135 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2136 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2137 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2138 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2139 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2140 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2141 2142 2143 SA_DBG1(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2144 SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2145 SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2146 SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2147 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 3\n" )); 2148 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2W"); 2149 return returnVal; 2150 } 2151 2152 2153 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2154 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2155 2156 SA_DBG2(("siHDAMode_V:ILA is ready hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); 2157 2158 /* Tell FW ILA is ready */ 2159 SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2160 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2161 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2162 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2163 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2164 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2165 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2166 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2167 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2168 2169 SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2170 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2171 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2172 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2173 2174 SA_DBG2(("siHDAMode_V: Step 3 MSGU_HOST_SCRATCH_PAD_3 write %X\n",HDA_ISTR_DONE)); 2175 ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,HDA_ISTR_DONE ); 2176 2177 SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2178 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2179 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2180 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2181 2182 } 2183 2184 if(HDA_STEP_4) 2185 { 2186 2187 SA_DBG2(("siHDAMode_V: Exec ILA\n")); 2188 si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); 2189 si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); 2190 2191 hdacmd.cmdparm_0 = 0x200000; /* length SPC_V_HDAC_EXEC*/; 2192 hdacmd.cmdparm_1 = userFwImg->ilaLen ; /* length SPC_V_HDAC_EXEC*/; 2193 seq_id++; 2194 2195 hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC; 2196 2197 SA_DBG1(("siHDAMode_V: STEP 4\n")); 2198 2199 /* 2200 Step 4 2201 The host writes the HDAC_EXEC command (0x0002) via MEMBASE-I for the boot ROM to authenticate 2202 and execute the HDA-ILA image. The host sets parameter 0 and parameter 1 for the HDA-ILA image 2203 appropriately: 2204 Parameter 0: Entry offset this value must be 0x20_0000. 2205 Parameter 1: the HDA-ILA image length. 2206 */ 2207 2208 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0 ,hdacmd.cmdparm_0); 2209 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4 ,hdacmd.cmdparm_1); 2210 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8 ,hdacmd.cmdparm_2); 2211 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); 2212 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); 2213 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); 2214 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); 2215 ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); 2216 2217 SA_DBG1(("siHDAMode_V: Exec ILA\n" )); 2218 2219 SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2220 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), 2221 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), 2222 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), 2223 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), 2224 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), 2225 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), 2226 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), 2227 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); 2228 2229 SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); 2230 2231 SA_DBG2(("siHDAMode_V:4SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2232 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2233 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2234 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2235 } // End Step 4 2236 if(HDA_STEP_5) 2237 { 2238 SA_DBG1(("siHDAMode_V: start wait STEP 5\n")); 2239 2240 /* 2241 Step 5 2242 The host continues polling for the HDA-ILA status via MEMBASE-I. The polling timeout should 2243 be no more than 1 second. The response status HDAR_EXEC indicates a good response from the 2244 boot ROM. Response states that indicate a failure are: 2245 HDAR_BAD_CMD 2246 HDAR_BAD_IMG 2247 */ 2248 2249 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2250 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2251 hda_command_complete = 0; 2252 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2253 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x Begin STEP 5\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),hda_status)); 2254 hda_status = 0; 2255 do 2256 { 2257 ossaStallThread(agRoot, WAIT_INCREMENT); 2258 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2259 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2260 } while (hda_status != SPC_V_HDAR_EXEC && (max_wait_count -= WAIT_INCREMENT)); 2261 2262 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x hda_command_complete 0x%x STEP 5 wait for seq_id took %d\n", 2263 ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1), 2264 hda_status, 2265 hda_command_complete, 2266 (max_wait_time - max_wait_count))); 2267 2268 smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); 2269 /* TP:2Z STEP 5 took */ 2270 2271 if(! hda_command_complete) 2272 { 2273 SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2274 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2275 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2276 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2277 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2278 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2279 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2280 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2281 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2282 2283 SA_DBG1(("siHDAMode_V:5SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2284 SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2285 SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2286 SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2287 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 5\n" )); 2288 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "2W"); 2289 return returnVal; 2290 } 2291 2292 if (hda_status != SPC_V_HDAR_EXEC) 2293 { 2294 SA_DBG1(("siHDAMode_V:ILA_EXEC_ERROR hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); 2295 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "2W"); 2296 goto bootrom_err; 2297 } 2298 SA_DBG1(("siHDAMode_V: end seq_id updated STEP 5\n")); 2299 } // End Step 5 2300 2301 if(HDA_STEP_6) 2302 { 2303 SA_DBG1(("siHDAMode_V: start STEP 6\n")); 2304 2305 /* 2306 Step 6 2307 The host polls the upper 8 bits [31:24] 5 of the Scratchpad 0 Register 2308 (page 609) for the ILAHDA_RAAE_IMG_GET (0x11) state. Polling timeout 2309 should be no more than 2 seconds. If a polling timeout occurs, the host 2310 should check for a fatal error as described in Section 12.2. 2311 If successful, the Host Scratchpad 4 Register (page 620) and Host 2312 Scratchpad 5 Register (page 621) are set as follows: Host Scratchpad 4 2313 Register (page 620) holds the lower 32-bit host address of 2314 the RAAE image. Host Scratchpad 5 Register (page 621) 2315 holds the upper 32-bit host address of the RAAE image. 2316 Then the host writes the command ILAHDAC_RAAE_IMG_DONE(0x81) to the upper 2317 8 bits [31:24] of the Host Scratchpad 3 Register (page 619) and writes the 2318 sizeof the RAAE image to the lower 24 bits [23:0]. 2319 */ 2320 2321 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2322 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2323 hda_command_complete = 0; 2324 do 2325 { 2326 ossaStallThread(agRoot, WAIT_INCREMENT); 2327 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_RAAE_IMG_GET; 2328 } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2329 2330 SA_DBG1(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 6 wait for ILAHDA_RAAE_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); 2331 smTrace(hpDBG_VERY_LOUD,"2b",(max_wait_time - max_wait_count) ); 2332 /* TP:2b STEP 6 took */ 2333 if(! hda_command_complete) 2334 { 2335 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 6\n" )); 2336 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "2W"); 2337 goto fw_err; 2338 } 2339 2340 si_memset(pbase, 0, biggest); 2341 2342 if( userFwImg->aap1Len < biggest) 2343 { 2344 si_memcpy(pbase,userFwImg->aap1Img, userFwImg->aap1Len ); 2345 } 2346 else 2347 { 2348 SA_DBG1(("siHDAMode_V: userFwImg->aap1Len 0x%x < biggest 0x%x\n",userFwImg->aap1Len,biggest)); 2349 } 2350 /* 2351 */ 2352 /* upper */ 2353 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); 2354 SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); 2355 /* lower */ 2356 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); 2357 SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); 2358 /* len */ 2359 ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len ); 2360 SA_DBG1(("siHDAMode_V: write ILAHDAC_RAAE_IMG_DONE to MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len)); 2361 // ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_4 , userFwImg->DmaBase_l); 2362 2363 ossaStallThread(agRoot, gWaitmSec * 1000); 2364 if(1) /* step in question */ 2365 { 2366 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2367 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2368 hda_command_complete = 0; 2369 do 2370 { 2371 ossaStallThread(agRoot, WAIT_INCREMENT); 2372 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; 2373 } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2374 2375 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2376 smTrace(hpDBG_VERY_LOUD,"2c",(max_wait_time - max_wait_count) ); 2377 /* TP:2c STEP 6a ILAHDA_IOP_IMG_GET took */ 2378 smTrace(hpDBG_VERY_LOUD,"2y",hda_command_complete ); 2379 /* TP:2y hda_command_complete */ 2380 2381 if(! hda_command_complete) 2382 { 2383 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); 2384 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "2W"); 2385 goto fw_err; 2386 } 2387 } 2388 SA_DBG1(("siHDAMode_V: End V_Scratchpad_0_Register 0x%08X STEP 6\n",ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register))); 2389 } 2390 2391 if(HDA_STEP_7) 2392 { 2393 SA_DBG1(("siHDAMode_V: STEP 7\n")); 2394 /* 2395 Step 7 2396 The host polls (reads) the upper 8 bits 7 [31:24] of the Scratchpad 0 Register (page 609) 2397 for ILAHDA_IOP_IMG_GET (0x10) state. The polling timeout should be no more than 2 seconds. 2398 If a polling timeout occurs, the host should check for a fatal error as described in 2399 Section 12.2. If successful, the Host Scratchpad 4 Register (page 620) and Host 2400 Scratchpad 5 Register (page 621) are set as follows: 2401 Host Scratchpad 4 Register (page 620) holds the lower host address of the IOP image. 2402 Host Scratchpad 5 Register (page 621) holds the upper host address of the IOP image. 2403 Then host writes the command ILAHDAC_IOP_IMG_DONE(0x80) to the upper 8 bits [31:24] of the 2404 Host Scratchpad 3 Register (page 614)and writes the sizeof the IOP image to the lower 24 2405 bits [23:0]. 2406 2407 */ 2408 2409 si_memset(pbase, 0, biggest); 2410 2411 if( userFwImg->iopLen < biggest) 2412 { 2413 si_memcpy(pbase,userFwImg->iopImg, userFwImg->iopLen ); 2414 } 2415 else 2416 { 2417 SA_DBG1(("siHDAMode_V: userFwImg->iopImg 0x%x < biggest 0x%x\n",userFwImg->iopLen,biggest)); 2418 } 2419 2420 /* upper */ 2421 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); 2422 SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); 2423 /* lower */ 2424 ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); 2425 SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); 2426 SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4\n")); 2427 /* len */ 2428 ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen ); 2429 SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen)); 2430 2431 2432 if(saRoot->swConfig.hostDirectAccessMode & 2 ) 2433 { 2434 /* Hda AES DIF offload */ 2435 ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC); 2436 SA_DBG1(("siHDAMode_V: V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC 0x%X\n",HDA_AES_DIF_FUNC)); 2437 /* Hda AES DIF offload */ 2438 } 2439 2440 SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2441 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2442 2443 2444 max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2445 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2446 hda_command_complete = 0; 2447 do 2448 { 2449 ossaStallThread(agRoot, WAIT_INCREMENT); 2450 hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; 2451 } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2452 2453 smTrace(hpDBG_VERY_LOUD,"2d",(max_wait_time - max_wait_count) ); 2454 /* TP:2d STEP 7 ILAHDA_IOP_IMG_GET took */ 2455 smTrace(hpDBG_VERY_LOUD,"2z",hda_command_complete ); 2456 /* TP:2z hda_command_complete */ 2457 2458 SA_DBG2(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); 2459 2460 if(! hda_command_complete) 2461 { 2462 SA_DBG1(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2463 SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2464 SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2465 SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2466 SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); 2467 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "2W"); 2468 return returnVal; 2469 } 2470 2471 2472 SA_DBG2(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2473 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2474 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2475 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2476 SA_DBG1(("siHDAMode_V: End STEP 7\n")); 2477 } 2478 2479 2480 if(HDA_STEP_8) 2481 { 2482 bit32 SCRATCH_PAD1; 2483 2484 SA_DBG1(("siHDAMode_V: Check fw ready Step 8\n")); 2485 2486 /* 2487 Step 8 2488 IOP0/1 start-up sequence. The host polls the Scratchpad 1 Register (page 610) 2489 bits [1:0] for RAAE_STATE, bits [13:12] for IOP1_STATE, and 2490 bits [11:10] for IOP0_STATE to go to 11b (Ready state). 2491 The polling timeout should be no more than 1 second. If a polling timeout occurs, 2492 the host should check for a fatal error in Section 12.2. 2493 */ 2494 2495 returnVal = AGSA_RC_SUCCESS; 2496 2497 max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 2498 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2499 do 2500 { 2501 ossaStallThread(agRoot, WAIT_INCREMENT); 2502 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2503 } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); 2504 smTrace(hpDBG_VERY_LOUD,"HZ",(max_wait_time - max_wait_count) ); 2505 /* TP:2f Step 8 PCI took */ 2506 2507 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x (0x%x) Step 8 PCIe took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2508 /* ILA */ 2509 max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 2510 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2511 do 2512 { 2513 ossaStallThread(agRoot, WAIT_INCREMENT); 2514 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2515 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2516 2517 smTrace(hpDBG_VERY_LOUD,"2g",(max_wait_time - max_wait_count) ); 2518 /* TP:2g Step 8 ILA took */ 2519 2520 SA_DBG2(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2521 2522 if (!max_wait_count) 2523 { 2524 // Ignore for now returnVal = AGSA_RC_FAILURE; 2525 SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 2526 } 2527 2528 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2529 2530 /* RAAE */ 2531 max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ 2532 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2533 do 2534 { 2535 ossaStallThread(agRoot, WAIT_INCREMENT); 2536 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2537 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2538 2539 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2540 smTrace(hpDBG_VERY_LOUD,"2h",(max_wait_time - max_wait_count) ); 2541 /* TP:2h Step 8 RAAE took */ 2542 2543 if (!max_wait_count) 2544 { 2545 SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 2546 2547 } 2548 /* IOP0 */ 2549 max_wait_time = (600 * 1000); /* wait 600 milliseconds */ 2550 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2551 do 2552 { 2553 ossaStallThread(agRoot, WAIT_INCREMENT); 2554 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2555 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2556 2557 SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2558 smTrace(hpDBG_VERY_LOUD,"2i",(max_wait_time - max_wait_count) ); 2559 /* TP:2i Step 8 IOP took */ 2560 2561 if (!max_wait_count) 2562 { 2563 returnVal = AGSA_RC_FAILURE; 2564 SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 2565 2566 } 2567 2568 2569 SA_DBG1(("siHDAMode_V: Step 8 0x%X ERROR_STATE 0x%X\n",ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ), 2570 SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); 2571 if (SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) )) 2572 { 2573 if(smIS_ENCRYPT(agRoot)) 2574 { 2575 SA_DBG1(("siHDAMode_V: Encryption and HDA mode not supported - failed Step 8\n" )); 2576 } 2577 else 2578 { 2579 SA_DBG1(("siHDAMode_V: ERROR_STATE failed Step 8\n" )); 2580 } 2581 returnVal = AGSA_RC_FAILURE; 2582 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "2W"); 2583 goto fw_err; 2584 } 2585 2586 } 2587 SA_DBG1(("siHDAMode_V: returnVal 0x%X Step 8\n",returnVal)); 2588 /* 2589 Step 10 2590 The host continues with the normal SPCv Configuration Table initialization sequence 2591 as described in Section 6.2.8.1. 2592 */ 2593 if(saRoot->swConfig.hostDirectAccessMode & 2 ) 2594 { 2595 /* Hda AES DIF offload */ 2596 SA_DBG1(("siHDAMode_V: AES/DIF 0x%08X offload enabled %s\n",ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ), 2597 ((ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ) & (1 << SHIFT15)) ? "yes" :"no") )); 2598 /* Hda AES DIF offload */ 2599 /* ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, 0); */ 2600 /* Hda AES DIF offload */ 2601 } 2602 2603 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "2W"); 2604 return returnVal; 2605 2606 bootrom_err: 2607 SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2608 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2609 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2610 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2611 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2612 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2613 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2614 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2615 ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2616 2617 fw_err: 2618 SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2619 SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2620 SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2621 SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2622 return returnVal; 2623 } 2624 2625 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 2626 2627 2628 2629 2630 /******************************************************************************/ 2631 /*! \brief Function to check FW is ready for soft reset 2632 * 2633 * The siSpcSoftResetRDYChk() function is called to check status of FW 2634 * 2635 * \param agRoot handles for this instance of SAS/SATA hardware 2636 * 2637 * \return success or fail 2638 */ 2639 /*******************************************************************************/ 2640 LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot) 2641 { 2642 bit32 regVal; 2643 bit32 Scratchpad1; 2644 bit32 Scratchpad2; 2645 bit32 spad2notready = 0; 2646 #if defined(SALLSDK_DEBUG) 2647 bit32 regVal1; 2648 bit32 regVal2; 2649 #endif /* SALLSDK_DEBUG */ 2650 2651 /* read the scratch pad 2 register bit 2 */ 2652 regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_FWRDY_RST; 2653 Scratchpad1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 2654 if (regVal == SCRATCH_PAD2_FWRDY_RST) 2655 { 2656 /* FW assert happened, it is ready for soft reset */ 2657 /* Do nothing */ 2658 } 2659 else 2660 { 2661 /* read bootloader response state */ 2662 regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 2663 if (regVal == BOOTTLOADERHDA_IDLE) 2664 { 2665 /* For customers wants to do soft reset even the chip is already in HDA mode */ 2666 /* Do not need to trigger RB6 twice */ 2667 ; 2668 } 2669 else 2670 { 2671 /* Trigger NMI twice via RB6 */ 2672 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, RB6_ACCESS_REG)) 2673 { 2674 SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", RB6_ACCESS_REG)); 2675 return AGSA_RC_FAILURE; 2676 } 2677 2678 if(Scratchpad1 != (SCRATCH_PAD1_FW_INIT_ERR | SCRATCH_PAD1_AAP_ERROR_STATE)) 2679 { 2680 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); 2681 2682 ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); 2683 } 2684 else 2685 { 2686 SA_DBG1(("siSoftReset: ILA load fail SKIP RB6 access 0x%x\n",Scratchpad1 )); 2687 } 2688 SPAD2_NOT_READY: 2689 /* wait for 100 ms */ 2690 ossaStallThread(agRoot, ONE_HUNDRED_MILLISECS ); 2691 Scratchpad2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 2692 regVal = Scratchpad2 & SCRATCH_PAD2_FWRDY_RST; 2693 if (regVal != SCRATCH_PAD2_FWRDY_RST) 2694 { 2695 if (spad2notready > WAIT_SECONDS(12) / ONE_HUNDRED_MILLISECS ) /**/ 2696 { 2697 #if defined(SALLSDK_DEBUG) 2698 regVal1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 2699 regVal2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 2700 SA_DBG1(("siSpcSoftResetRDYChk: TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", regVal1, regVal2)); 2701 SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 2702 SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 2703 #endif /* SALLSDK_DEBUG */ 2704 return AGSA_RC_SUCCESS; /* Timeout Ok reset anyway */ 2705 } 2706 2707 spad2notready++; 2708 goto SPAD2_NOT_READY; 2709 } 2710 } 2711 } 2712 2713 return AGSA_RC_SUCCESS; 2714 } 2715 2716 2717 agsaBarOffset_t SPCTable[] = 2718 { 2719 2720 { GEN_MSGU_IBDB_SET, PCIBAR0, MSGU_IBDB_SET, SIZE_DW }, /* 0x00 */ 2721 { GEN_MSGU_ODR, PCIBAR0, MSGU_ODR, SIZE_DW }, /* 0x01 */ 2722 { GEN_MSGU_ODCR, PCIBAR0, MSGU_ODCR, SIZE_DW }, /* 0x02 */ 2723 { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, MSGU_SCRATCH_PAD_0, SIZE_DW }, /* 0x03 */ 2724 { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, MSGU_SCRATCH_PAD_1, SIZE_DW }, /* 0x04 */ 2725 { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, MSGU_SCRATCH_PAD_2, SIZE_DW }, /* 0x05 */ 2726 { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, MSGU_SCRATCH_PAD_3, SIZE_DW }, /* 0x06 */ 2727 { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, SIZE_DW }, /* 0x07 */ 2728 { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, SIZE_DW }, /* 0x08 */ 2729 { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, SIZE_DW }, /* 0x09 */ 2730 { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, SIZE_DW }, /* 0x0a */ 2731 { GEN_MSGU_ODMR, PCIBAR0, MSGU_ODMR, SIZE_DW }, /* 0x0b */ 2732 { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ 2733 { GEN_SPC_REG_RESET, PCIBAR2, SPC_REG_RESET, SIZE_DW }, /* 0x0d */ 2734 }; 2735 2736 agsaBarOffset_t SPC_V_Table[] = 2737 { 2738 2739 { GEN_MSGU_IBDB_SET, PCIBAR0, V_Inbound_Doorbell_Set_Register, SIZE_DW }, /* 0x00 */ 2740 { GEN_MSGU_ODR, PCIBAR0, V_Outbound_Doorbell_Set_Register, SIZE_DW }, /* 0x01 */ 2741 { GEN_MSGU_ODCR, PCIBAR0, V_Outbound_Doorbell_Clear_Register, SIZE_DW }, /* 0x02 */ 2742 { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, V_Scratchpad_0_Register, SIZE_DW }, /* 0x03 */ 2743 { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, V_Scratchpad_1_Register, SIZE_DW }, /* 0x04 */ 2744 { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, V_Scratchpad_2_Register, SIZE_DW }, /* 0x05 */ 2745 { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, V_Scratchpad_3_Register, SIZE_DW }, /* 0x06 */ 2746 { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, V_Host_Scratchpad_0_Register, SIZE_DW }, /* 0x07 */ 2747 { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, V_Host_Scratchpad_1_Register, SIZE_DW }, /* 0x08 */ 2748 { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, V_Host_Scratchpad_2_Register, SIZE_DW }, /* 0x09 */ 2749 { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, V_Host_Scratchpad_3_Register, SIZE_DW }, /* 0x0a */ 2750 { GEN_MSGU_ODMR, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, SIZE_DW }, /* 0x0b */ 2751 { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ 2752 { GEN_SPC_REG_RESET, PCIBAR0, V_SoftResetRegister, SIZE_DW }, /* 0x0d */ 2753 }; 2754 2755 2756 /*******************************************************************************/ 2757 /** 2758 * 2759 * \brief 2760 * \param agsaRoot Pointer to a data structure containing both application 2761 * and LL layer context handles 2762 * \param Spc_type Device Id of hardware 2763 * 2764 * Return: 2765 * None 2766 */ 2767 /*******************************************************************************/ 2768 GLOBAL void siUpdateBarOffsetTable(agsaRoot_t *agRoot, 2769 bit32 Spc_Type 2770 ) 2771 { 2772 2773 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); 2774 bit32 x; 2775 2776 smTraceFuncEnter(hpDBG_VERY_LOUD,"mf"); 2777 2778 smTrace(hpDBG_VERY_LOUD,"9A",Spc_Type); 2779 /* TP:9A Spc_Type */ 2780 2781 if(Spc_Type == VEN_DEV_SPC) 2782 { 2783 si_memcpy(&saRoot->SpcBarOffset, SPCTable, sizeof(SPCTable)); 2784 SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPCTable) sizeof(agsaBarOffset_t)sizeof(SPCTable) / sizeof(agsaBarOffset_t) %X %X %X\n", 2785 (unsigned int)sizeof(SPCTable), (unsigned int)sizeof(agsaBarOffset_t), 2786 (unsigned int)(sizeof(SPCTable) / sizeof(agsaBarOffset_t)) 2787 )); 2788 } 2789 else /* VEN_DEV_SPCV */ 2790 { 2791 si_memcpy(&saRoot->SpcBarOffset, SPC_V_Table, sizeof(SPC_V_Table)); 2792 SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPC_V_Table) sizeof(agsaBarOffset_t)sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t) %X %X %X\n", 2793 (unsigned int)sizeof(SPC_V_Table), 2794 (unsigned int)sizeof(agsaBarOffset_t), 2795 (unsigned int)(sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t)) 2796 )); 2797 } 2798 2799 for(x=0;x < sizeof(SPCTable) / sizeof(agsaBarOffset_t);x++) 2800 { 2801 2802 SA_DBG4(("%8X: %8X %8X %8X\n",saRoot->SpcBarOffset[x].Generic, 2803 saRoot->SpcBarOffset[x].Bar, 2804 saRoot->SpcBarOffset[x].Offset, 2805 saRoot->SpcBarOffset[x].Length 2806 )); 2807 if(saRoot->SpcBarOffset[x].Generic != x) 2808 { 2809 SA_DBG1(("siUpdateBarOffsetTable: saRoot->SpcBarOffset[%x].Generic %X != %X\n",x, saRoot->SpcBarOffset[x].Generic, x)); 2810 } 2811 } 2812 2813 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mf"); 2814 } 2815 2816 2817 2818 GLOBAL bit32 siHalRegReadExt( agsaRoot_t *agRoot, 2819 bit32 generic, 2820 bit32 regOffset 2821 ) 2822 { 2823 2824 agsaBarOffset_t * Table = agNULL; 2825 bit32 retVal; 2826 2827 /* sanity check */ 2828 SA_ASSERT( (agNULL != agRoot), "agRoot"); 2829 Table = WHATTABLE(agRoot); 2830 SA_ASSERT( (agNULL != Table), "Table"); 2831 2832 /* 2833 if(Table[generic].Offset != regOffset) 2834 { 2835 2836 SA_DBG1(("siHalRegReadExt: Table[%x].Offset %x != regOffset %x\n",generic, 2837 Table[generic].Offset, 2838 regOffset )); 2839 } 2840 */ 2841 2842 if(Table[generic].Bar) 2843 { 2844 retVal = ossaHwRegReadExt(agRoot, 2845 Table[generic].Bar, 2846 Table[generic].Offset); 2847 } 2848 else 2849 { 2850 retVal = ossaHwRegRead(agRoot, 2851 Table[generic].Offset); 2852 } 2853 2854 return(retVal); 2855 } 2856 2857 2858 GLOBAL void siHalRegWriteExt( 2859 agsaRoot_t *agRoot, 2860 bit32 generic, 2861 bit32 regOffset, 2862 bit32 regValue 2863 ) 2864 { 2865 agsaBarOffset_t * Table = agNULL; 2866 2867 /* sanity check */ 2868 SA_ASSERT( (agNULL != agRoot), "agRoot"); 2869 2870 Table = WHATTABLE(agRoot); 2871 SA_ASSERT( (agNULL != Table), "Table"); 2872 2873 2874 /* 2875 if(Table[generic].Offset != regOffset) 2876 { 2877 2878 SA_DBG1(("siHalRegWriteExt: Table[%x].Offset %x != regOffset %x\n",generic, 2879 Table[generic].Offset, 2880 regOffset )); 2881 } 2882 */ 2883 2884 SA_DBG6(("siHalRegWriteExt: Bar %x Offset %8X Wrote %8X\n", 2885 Table[generic].Bar, 2886 Table[generic].Offset, 2887 regValue )); 2888 2889 2890 if(Table[generic].Bar) 2891 { 2892 ossaHwRegWriteExt(agRoot, 2893 Table[generic].Bar, 2894 Table[generic].Offset, 2895 regValue ); 2896 }else 2897 { 2898 ossaHwRegWrite(agRoot, 2899 Table[generic].Offset, 2900 regValue ); 2901 } 2902 } 2903 2904 2905 2906 2907 GLOBAL void siPCITriger(agsaRoot_t *agRoot) 2908 { 2909 2910 SA_DBG1(("siPCITriger: Read PCIe Bar zero plus 0x%x\n", PCIE_TRIGGER_ON_REGISTER_READ)); 2911 ossaHwRegReadExt(agRoot,PCIBAR0 ,PCIE_TRIGGER_ON_REGISTER_READ ); 2912 } 2913 2914 2915 GLOBAL bit32 siGetPciBar( 2916 agsaRoot_t *agRoot 2917 ) 2918 { 2919 bit32 MSGUCfgTblBase = 0; 2920 bit32 pcibar = 0; 2921 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2922 pcibar = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 2923 /* get pci Bar index */ 2924 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, pcibar); 2925 2926 return(pcibar); 2927 } 2928 2929 GLOBAL bit32 siGetTableOffset( 2930 agsaRoot_t *agRoot, 2931 bit32 TableOffsetInTable 2932 ) 2933 { 2934 bit32 TableOffset; 2935 bit32 MSGUCfgTblBase; 2936 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 2937 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2938 2939 MSGUCfgTblBase &= SCRATCH_PAD0_OFFSET_MASK; 2940 2941 TableOffset = ossaHwRegReadExt(agRoot,siGetPciBar(agRoot) ,MSGUCfgTblBase +TableOffsetInTable ); 2942 SA_DBG4(("GetTableOffset:TableOffset with size 0x%x\n", TableOffset)); 2943 2944 /* Mask off size */ 2945 TableOffset &= 0xFFFFFF; 2946 TableOffset +=MSGUCfgTblBase; 2947 return(TableOffset); 2948 2949 } 2950 2951 2952 GLOBAL void siCheckQs( 2953 agsaRoot_t *agRoot 2954 ) 2955 { 2956 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); 2957 2958 mpiOCQueue_t *circularOQ; 2959 mpiICQueue_t *circularIQ; 2960 int i; 2961 2962 for ( i = 0; i < saRoot->QueueConfig.numInboundQueues; i++ ) 2963 { 2964 circularIQ = &saRoot->inboundQueue[i]; 2965 2966 OSSA_READ_LE_32(circularIQ->agRoot, &circularIQ->consumerIdx, circularIQ->ciPointer, 0); 2967 if(circularIQ->producerIdx != circularIQ->consumerIdx) 2968 { 2969 SA_DBG1(("siCheckQs: In Q %d PI 0x%03x CI 0x%03x (%d) \n",i, 2970 circularIQ->producerIdx, 2971 circularIQ->consumerIdx, 2972 (circularIQ->producerIdx > circularIQ->consumerIdx ? (circularIQ->producerIdx - circularIQ->consumerIdx) : (circularIQ->numElements - circularIQ->consumerIdx ) + circularIQ->producerIdx))); 2973 } 2974 } 2975 2976 for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 2977 { 2978 circularOQ = &saRoot->outboundQueue[i]; 2979 OSSA_READ_LE_32(circularOQ->agRoot, &circularOQ->producerIdx, circularOQ->piPointer, 0); 2980 if(circularOQ->producerIdx != circularOQ->consumerIdx) 2981 { 2982 SA_DBG1(("siCheckQs: Out Q %d PI 0x%03x CI 0x%03x (%d) \n",i, 2983 circularOQ->producerIdx, 2984 circularOQ->consumerIdx, 2985 (circularOQ->producerIdx > circularOQ->consumerIdx ? (circularOQ->producerIdx - circularOQ->consumerIdx) : (circularOQ->numElements - circularOQ->consumerIdx ) + circularOQ->producerIdx))); 2986 2987 } 2988 } 2989 2990 } 2991 GLOBAL void siPciCpyMem(agsaRoot_t *agRoot, 2992 bit32 soffset, 2993 const void *dst, 2994 bit32 DWcount, 2995 bit32 busBaseNumber 2996 ) 2997 { 2998 bit32 i, val,offset; 2999 bit32 *dst1; 3000 3001 dst1 = (bit32 *)dst; 3002 3003 SA_DBG1(("siPciCpyMem:copy DWcount %d from offset 0x%x to %p\n",DWcount,soffset,dst)); 3004 3005 for (i= 0; i < DWcount; i+=4,dst1++) 3006 { 3007 offset = (soffset + i / 4); 3008 SA_ASSERT( (offset < (64 * 1024)), "siPciCpyMem offset too large"); 3009 if(offset < (64 * 1024)) 3010 { 3011 val = ossaHwRegReadExt(agRoot, busBaseNumber, offset); 3012 *dst1 = BIT32_TO_LEBIT32(val); 3013 } 3014 } 3015 3016 return; 3017 } 3018