xref: /freebsd/sys/dev/pci/pcivar.h (revision f5e9c916afed4a948fe5c03bfaee038d165e12ab)
1 /*-
2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  *
28  */
29 
30 #ifndef _PCIVAR_H_
31 #define	_PCIVAR_H_
32 
33 #include <sys/queue.h>
34 
35 /* some PCI bus constants */
36 #define	PCI_MAXMAPS_0	6	/* max. no. of memory/port maps */
37 #define	PCI_MAXMAPS_1	2	/* max. no. of maps for PCI to PCI bridge */
38 #define	PCI_MAXMAPS_2	1	/* max. no. of maps for CardBus bridge */
39 
40 typedef uint64_t pci_addr_t;
41 
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44     uint8_t	br_seclat;
45     uint8_t	br_subbus;
46     uint8_t	br_secbus;
47     uint8_t	br_pribus;
48     uint16_t	br_control;
49 };
50 
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53     uint16_t	pp_cap;		/* PCI power management capabilities */
54     uint8_t	pp_status;	/* conf. space addr. of PM control/status reg */
55     uint8_t	pp_bse;		/* conf. space addr. of PM BSE reg */
56     uint8_t	pp_data;	/* conf. space addr. of PM data reg */
57 };
58 
59 struct pci_map {
60     pci_addr_t	pm_value;	/* Raw BAR value */
61     pci_addr_t	pm_size;
62     uint16_t	pm_reg;
63     STAILQ_ENTRY(pci_map) pm_link;
64 };
65 
66 struct vpd_readonly {
67     char	keyword[2];
68     char	*value;
69     int		len;
70 };
71 
72 struct vpd_write {
73     char	keyword[2];
74     char	*value;
75     int 	start;
76     int 	len;
77 };
78 
79 struct pcicfg_vpd {
80     uint8_t	vpd_reg;	/* base register, + 2 for addr, + 4 data */
81     char	vpd_cached;
82     char	*vpd_ident;	/* string identifier */
83     int 	vpd_rocnt;
84     struct vpd_readonly *vpd_ros;
85     int 	vpd_wcnt;
86     struct vpd_write *vpd_w;
87 };
88 
89 /* Interesting values for PCI MSI */
90 struct pcicfg_msi {
91     uint16_t	msi_ctrl;	/* Message Control */
92     uint8_t	msi_location;	/* Offset of MSI capability registers. */
93     uint8_t	msi_msgnum;	/* Number of messages */
94     int		msi_alloc;	/* Number of allocated messages. */
95     uint64_t	msi_addr;	/* Contents of address register. */
96     uint16_t	msi_data;	/* Contents of data register. */
97     u_int	msi_handlers;
98 };
99 
100 /* Interesting values for PCI MSI-X */
101 struct msix_vector {
102     uint64_t	mv_address;	/* Contents of address register. */
103     uint32_t	mv_data;	/* Contents of data register. */
104     int		mv_irq;
105 };
106 
107 struct msix_table_entry {
108     u_int	mte_vector;	/* 1-based index into msix_vectors array. */
109     u_int	mte_handlers;
110 };
111 
112 struct pcicfg_msix {
113     uint16_t	msix_ctrl;	/* Message Control */
114     uint16_t	msix_msgnum;	/* Number of messages */
115     uint8_t	msix_location;	/* Offset of MSI-X capability registers. */
116     uint8_t	msix_table_bar;	/* BAR containing vector table. */
117     uint8_t	msix_pba_bar;	/* BAR containing PBA. */
118     uint32_t	msix_table_offset;
119     uint32_t	msix_pba_offset;
120     int		msix_alloc;	/* Number of allocated vectors. */
121     int		msix_table_len;	/* Length of virtual table. */
122     struct msix_table_entry *msix_table; /* Virtual table. */
123     struct msix_vector *msix_vectors;	/* Array of allocated vectors. */
124     struct resource *msix_table_res;	/* Resource containing vector table. */
125     struct resource *msix_pba_res;	/* Resource containing PBA. */
126 };
127 
128 /* Interesting values for HyperTransport */
129 struct pcicfg_ht {
130     uint8_t	ht_slave;	/* Non-zero if device is an HT slave. */
131     uint8_t	ht_msimap;	/* Offset of MSI mapping cap registers. */
132     uint16_t	ht_msictrl;	/* MSI mapping control */
133     uint64_t	ht_msiaddr;	/* MSI mapping base address */
134 };
135 
136 /* Interesting values for PCI-express */
137 struct pcicfg_pcie {
138     uint8_t	pcie_location;	/* Offset of PCI-e capability registers. */
139     uint8_t	pcie_type;	/* Device type. */
140     uint16_t	pcie_flags;	/* Device capabilities register. */
141     uint16_t	pcie_device_ctl; /* Device control register. */
142     uint16_t	pcie_link_ctl;	/* Link control register. */
143     uint16_t	pcie_slot_ctl;	/* Slot control register. */
144     uint16_t	pcie_root_ctl;	/* Root control register. */
145     uint16_t	pcie_device_ctl2; /* Second device control register. */
146     uint16_t	pcie_link_ctl2;	/* Second link control register. */
147     uint16_t	pcie_slot_ctl2;	/* Second slot control register. */
148 };
149 
150 struct pcicfg_pcix {
151     uint16_t	pcix_command;
152     uint8_t	pcix_location;	/* Offset of PCI-X capability registers. */
153 };
154 
155 struct pcicfg_vf {
156        int index;
157 };
158 
159 struct pci_ea_entry {
160     int		eae_bei;
161     uint32_t	eae_flags;
162     uint64_t	eae_base;
163     uint64_t	eae_max_offset;
164     uint32_t	eae_cfg_offset;
165     STAILQ_ENTRY(pci_ea_entry) eae_link;
166 };
167 
168 struct pcicfg_ea {
169     int ea_location;	/* Structure offset in Configuration Header */
170     STAILQ_HEAD(, pci_ea_entry) ea_entries;	/* EA entries */
171 };
172 
173 #define	PCICFG_VF	0x0001 /* Device is an SR-IOV Virtual Function */
174 
175 /* config header information common to all header types */
176 typedef struct pcicfg {
177     struct device *dev;		/* device which owns this */
178 
179     STAILQ_HEAD(, pci_map) maps; /* BARs */
180 
181     uint16_t	subvendor;	/* card vendor ID */
182     uint16_t	subdevice;	/* card device ID, assigned by card vendor */
183     uint16_t	vendor;		/* chip vendor ID */
184     uint16_t	device;		/* chip device ID, assigned by chip vendor */
185 
186     uint16_t	cmdreg;		/* disable/enable chip and PCI options */
187     uint16_t	statreg;	/* supported PCI features and error state */
188 
189     uint8_t	baseclass;	/* chip PCI class */
190     uint8_t	subclass;	/* chip PCI subclass */
191     uint8_t	progif;		/* chip PCI programming interface */
192     uint8_t	revid;		/* chip revision ID */
193 
194     uint8_t	hdrtype;	/* chip config header type */
195     uint8_t	cachelnsz;	/* cache line size in 4byte units */
196     uint8_t	intpin;		/* PCI interrupt pin */
197     uint8_t	intline;	/* interrupt line (IRQ for PC arch) */
198 
199     uint8_t	mingnt;		/* min. useful bus grant time in 250ns units */
200     uint8_t	maxlat;		/* max. tolerated bus grant latency in 250ns */
201     uint8_t	lattimer;	/* latency timer in units of 30ns bus cycles */
202 
203     uint8_t	mfdev;		/* multi-function device (from hdrtype reg) */
204     uint8_t	nummaps;	/* actual number of PCI maps used */
205 
206     uint32_t	domain;		/* PCI domain */
207     uint8_t	bus;		/* config space bus address */
208     uint8_t	slot;		/* config space slot address */
209     uint8_t	func;		/* config space function number */
210 
211     uint32_t	flags;		/* flags defined above */
212     size_t	devinfo_size;	/* Size of devinfo for this bus type. */
213 
214     struct pcicfg_bridge bridge; /* Bridges */
215     struct pcicfg_pp pp;	/* Power management */
216     struct pcicfg_vpd vpd;	/* Vital product data */
217     struct pcicfg_msi msi;	/* PCI MSI */
218     struct pcicfg_msix msix;	/* PCI MSI-X */
219     struct pcicfg_ht ht;	/* HyperTransport */
220     struct pcicfg_pcie pcie;	/* PCI Express */
221     struct pcicfg_pcix pcix;	/* PCI-X */
222     struct pcicfg_iov *iov;	/* SR-IOV */
223     struct pcicfg_vf vf;	/* SR-IOV Virtual Function */
224     struct pcicfg_ea ea;	/* Enhanced Allocation */
225 } pcicfgregs;
226 
227 /* additional type 1 device config header information (PCI to PCI bridge) */
228 
229 typedef struct {
230     pci_addr_t	pmembase;	/* base address of prefetchable memory */
231     pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */
232     uint32_t	membase;	/* base address of memory window */
233     uint32_t	memlimit;	/* topmost address of memory window */
234     uint32_t	iobase;		/* base address of port window */
235     uint32_t	iolimit;	/* topmost address of port window */
236     uint16_t	secstat;	/* secondary bus status register */
237     uint16_t	bridgectl;	/* bridge control register */
238     uint8_t	seclat;		/* CardBus latency timer */
239 } pcih1cfgregs;
240 
241 /* additional type 2 device config header information (CardBus bridge) */
242 
243 typedef struct {
244     uint32_t	membase0;	/* base address of memory window */
245     uint32_t	memlimit0;	/* topmost address of memory window */
246     uint32_t	membase1;	/* base address of memory window */
247     uint32_t	memlimit1;	/* topmost address of memory window */
248     uint32_t	iobase0;	/* base address of port window */
249     uint32_t	iolimit0;	/* topmost address of port window */
250     uint32_t	iobase1;	/* base address of port window */
251     uint32_t	iolimit1;	/* topmost address of port window */
252     uint32_t	pccardif;	/* PC Card 16bit IF legacy more base addr. */
253     uint16_t	secstat;	/* secondary bus status register */
254     uint16_t	bridgectl;	/* bridge control register */
255     uint8_t	seclat;		/* CardBus latency timer */
256 } pcih2cfgregs;
257 
258 extern uint32_t pci_numdevs;
259 
260 /* Only if the prerequisites are present */
261 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
262 struct pci_devinfo {
263         STAILQ_ENTRY(pci_devinfo) pci_links;
264 	struct resource_list resources;
265 	pcicfgregs		cfg;
266 	struct pci_conf		conf;
267 };
268 #endif
269 
270 #ifdef _SYS_BUS_H_
271 
272 #include "pci_if.h"
273 
274 enum pci_device_ivars {
275     PCI_IVAR_SUBVENDOR,
276     PCI_IVAR_SUBDEVICE,
277     PCI_IVAR_VENDOR,
278     PCI_IVAR_DEVICE,
279     PCI_IVAR_DEVID,
280     PCI_IVAR_CLASS,
281     PCI_IVAR_SUBCLASS,
282     PCI_IVAR_PROGIF,
283     PCI_IVAR_REVID,
284     PCI_IVAR_INTPIN,
285     PCI_IVAR_IRQ,
286     PCI_IVAR_DOMAIN,
287     PCI_IVAR_BUS,
288     PCI_IVAR_SLOT,
289     PCI_IVAR_FUNCTION,
290     PCI_IVAR_ETHADDR,
291     PCI_IVAR_CMDREG,
292     PCI_IVAR_CACHELNSZ,
293     PCI_IVAR_MINGNT,
294     PCI_IVAR_MAXLAT,
295     PCI_IVAR_LATTIMER
296 };
297 
298 /*
299  * Simplified accessors for pci devices
300  */
301 #define	PCI_ACCESSOR(var, ivar, type)					\
302 	__BUS_ACCESSOR(pci, var, PCI, ivar, type)
303 
304 PCI_ACCESSOR(subvendor,		SUBVENDOR,	uint16_t)
305 PCI_ACCESSOR(subdevice,		SUBDEVICE,	uint16_t)
306 PCI_ACCESSOR(vendor,		VENDOR,		uint16_t)
307 PCI_ACCESSOR(device,		DEVICE,		uint16_t)
308 PCI_ACCESSOR(devid,		DEVID,		uint32_t)
309 PCI_ACCESSOR(class,		CLASS,		uint8_t)
310 PCI_ACCESSOR(subclass,		SUBCLASS,	uint8_t)
311 PCI_ACCESSOR(progif,		PROGIF,		uint8_t)
312 PCI_ACCESSOR(revid,		REVID,		uint8_t)
313 PCI_ACCESSOR(intpin,		INTPIN,		uint8_t)
314 PCI_ACCESSOR(irq,		IRQ,		uint8_t)
315 PCI_ACCESSOR(domain,		DOMAIN,		uint32_t)
316 PCI_ACCESSOR(bus,		BUS,		uint8_t)
317 PCI_ACCESSOR(slot,		SLOT,		uint8_t)
318 PCI_ACCESSOR(function,		FUNCTION,	uint8_t)
319 PCI_ACCESSOR(ether,		ETHADDR,	uint8_t *)
320 PCI_ACCESSOR(cmdreg,		CMDREG,		uint8_t)
321 PCI_ACCESSOR(cachelnsz,		CACHELNSZ,	uint8_t)
322 PCI_ACCESSOR(mingnt,		MINGNT,		uint8_t)
323 PCI_ACCESSOR(maxlat,		MAXLAT,		uint8_t)
324 PCI_ACCESSOR(lattimer,		LATTIMER,	uint8_t)
325 
326 #undef PCI_ACCESSOR
327 
328 /*
329  * Operations on configuration space.
330  */
331 static __inline uint32_t
332 pci_read_config(device_t dev, int reg, int width)
333 {
334     return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
335 }
336 
337 static __inline void
338 pci_write_config(device_t dev, int reg, uint32_t val, int width)
339 {
340     PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
341 }
342 
343 /*
344  * Ivars for pci bridges.
345  */
346 
347 /*typedef enum pci_device_ivars pcib_device_ivars;*/
348 enum pcib_device_ivars {
349 	PCIB_IVAR_DOMAIN,
350 	PCIB_IVAR_BUS
351 };
352 
353 #define	PCIB_ACCESSOR(var, ivar, type)					 \
354     __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
355 
356 PCIB_ACCESSOR(domain,		DOMAIN,		uint32_t)
357 PCIB_ACCESSOR(bus,		BUS,		uint32_t)
358 
359 #undef PCIB_ACCESSOR
360 
361 /*
362  * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
363  * on i386 or other platforms should be mapped out in the MD pcireadconf
364  * code and not here, since the only MI invalid IRQ is 255.
365  */
366 #define	PCI_INVALID_IRQ		255
367 #define	PCI_INTERRUPT_VALID(x)	((x) != PCI_INVALID_IRQ)
368 
369 /*
370  * Convenience functions.
371  *
372  * These should be used in preference to manually manipulating
373  * configuration space.
374  */
375 static __inline int
376 pci_enable_busmaster(device_t dev)
377 {
378     return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
379 }
380 
381 static __inline int
382 pci_disable_busmaster(device_t dev)
383 {
384     return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
385 }
386 
387 static __inline int
388 pci_enable_io(device_t dev, int space)
389 {
390     return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
391 }
392 
393 static __inline int
394 pci_disable_io(device_t dev, int space)
395 {
396     return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
397 }
398 
399 static __inline int
400 pci_get_vpd_ident(device_t dev, const char **identptr)
401 {
402     return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
403 }
404 
405 static __inline int
406 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
407 {
408     return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
409 }
410 
411 /*
412  * Check if the address range falls within the VGA defined address range(s)
413  */
414 static __inline int
415 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
416 {
417 
418 	return (((start >= 0x3b0 && end <= 0x3bb) ||
419 	    (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
420 }
421 
422 static __inline int
423 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
424 {
425 
426 	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
427 }
428 
429 /*
430  * PCI power states are as defined by ACPI:
431  *
432  * D0	State in which device is on and running.  It is receiving full
433  *	power from the system and delivering full functionality to the user.
434  * D1	Class-specific low-power state in which device context may or may not
435  *	be lost.  Buses in D1 cannot do anything to the bus that would force
436  *	devices on that bus to lose context.
437  * D2	Class-specific low-power state in which device context may or may
438  *	not be lost.  Attains greater power savings than D1.  Buses in D2
439  *	can cause devices on that bus to lose some context.  Devices in D2
440  *	must be prepared for the bus to be in D2 or higher.
441  * D3	State in which the device is off and not running.  Device context is
442  *	lost.  Power can be removed from the device.
443  */
444 #define	PCI_POWERSTATE_D0	0
445 #define	PCI_POWERSTATE_D1	1
446 #define	PCI_POWERSTATE_D2	2
447 #define	PCI_POWERSTATE_D3	3
448 #define	PCI_POWERSTATE_UNKNOWN	-1
449 
450 static __inline int
451 pci_set_powerstate(device_t dev, int state)
452 {
453     return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
454 }
455 
456 static __inline int
457 pci_get_powerstate(device_t dev)
458 {
459     return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
460 }
461 
462 static __inline int
463 pci_find_cap(device_t dev, int capability, int *capreg)
464 {
465     return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
466 }
467 
468 static __inline int
469 pci_find_extcap(device_t dev, int capability, int *capreg)
470 {
471     return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
472 }
473 
474 static __inline int
475 pci_find_htcap(device_t dev, int capability, int *capreg)
476 {
477     return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
478 }
479 
480 static __inline int
481 pci_alloc_msi(device_t dev, int *count)
482 {
483     return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
484 }
485 
486 static __inline int
487 pci_alloc_msix(device_t dev, int *count)
488 {
489     return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
490 }
491 
492 static __inline void
493 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
494 {
495     PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
496 }
497 
498 static __inline void
499 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
500 {
501     PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
502 }
503 
504 static __inline void
505 pci_disable_msi(device_t dev)
506 {
507     PCI_DISABLE_MSI(device_get_parent(dev), dev);
508 }
509 
510 static __inline int
511 pci_remap_msix(device_t dev, int count, const u_int *vectors)
512 {
513     return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
514 }
515 
516 static __inline int
517 pci_release_msi(device_t dev)
518 {
519     return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
520 }
521 
522 static __inline int
523 pci_msi_count(device_t dev)
524 {
525     return (PCI_MSI_COUNT(device_get_parent(dev), dev));
526 }
527 
528 static __inline int
529 pci_msix_count(device_t dev)
530 {
531     return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
532 }
533 
534 static __inline int
535 pci_msix_pba_bar(device_t dev)
536 {
537     return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
538 }
539 
540 static __inline int
541 pci_msix_table_bar(device_t dev)
542 {
543     return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
544 }
545 
546 static __inline uint16_t
547 pci_get_rid(device_t dev)
548 {
549 	return (PCI_GET_RID(device_get_parent(dev), dev));
550 }
551 
552 static __inline void
553 pci_child_added(device_t dev)
554 {
555 
556     return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
557 }
558 
559 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
560 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
561 device_t pci_find_device(uint16_t, uint16_t);
562 device_t pci_find_class(uint8_t class, uint8_t subclass);
563 
564 /* Can be used by drivers to manage the MSI-X table. */
565 int	pci_pending_msix(device_t dev, u_int index);
566 
567 int	pci_msi_device_blacklisted(device_t dev);
568 int	pci_msix_device_blacklisted(device_t dev);
569 
570 void	pci_ht_map_msi(device_t dev, uint64_t addr);
571 
572 device_t pci_find_pcie_root_port(device_t dev);
573 int	pci_get_max_read_req(device_t dev);
574 void	pci_restore_state(device_t dev);
575 void	pci_save_state(device_t dev);
576 int	pci_set_max_read_req(device_t dev, int size);
577 uint32_t pcie_read_config(device_t dev, int reg, int width);
578 void	pcie_write_config(device_t dev, int reg, uint32_t value, int width);
579 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
580 	    uint32_t value, int width);
581 
582 
583 #ifdef BUS_SPACE_MAXADDR
584 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
585 #define	PCI_DMA_BOUNDARY	0x100000000
586 #else
587 #define	PCI_DMA_BOUNDARY	0
588 #endif
589 #endif
590 
591 #endif	/* _SYS_BUS_H_ */
592 
593 /*
594  * cdev switch for control device, initialised in generic PCI code
595  */
596 extern struct cdevsw pcicdev;
597 
598 /*
599  * List of all PCI devices, generation count for the list.
600  */
601 STAILQ_HEAD(devlist, pci_devinfo);
602 
603 extern struct devlist	pci_devq;
604 extern uint32_t	pci_generation;
605 
606 struct pci_map *pci_find_bar(device_t dev, int reg);
607 int	pci_bar_enabled(device_t dev, struct pci_map *pm);
608 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
609 
610 #define	VGA_PCI_BIOS_SHADOW_ADDR	0xC0000
611 #define	VGA_PCI_BIOS_SHADOW_SIZE	131072
612 
613 int	vga_pci_is_boot_display(device_t dev);
614 void *	vga_pci_map_bios(device_t dev, size_t *size);
615 void	vga_pci_unmap_bios(device_t dev, void *bios);
616 int	vga_pci_repost(device_t dev);
617 
618 #endif /* _PCIVAR_H_ */
619