1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 37 #define PCI_BUSMAX 255 /* highest supported bus number */ 38 #define PCI_SLOTMAX 31 /* highest supported slot number */ 39 #define PCI_FUNCMAX 7 /* highest supported function number */ 40 #define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48 #ifdef PCI_A64 49 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50 #else 51 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52 #endif 53 54 /* config header information common to all header types */ 55 56 typedef struct pcicfg { 57 struct device *dev; /* device which owns this */ 58 void *hdrspec; /* pointer to header type specific data */ 59 60 u_int16_t subvendor; /* card vendor ID */ 61 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 62 u_int16_t vendor; /* chip vendor ID */ 63 u_int16_t device; /* chip device ID, assigned by chip vendor */ 64 65 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 66 u_int16_t statreg; /* supported PCI features and error state */ 67 68 u_int8_t baseclass; /* chip PCI class */ 69 u_int8_t subclass; /* chip PCI subclass */ 70 u_int8_t progif; /* chip PCI programming interface */ 71 u_int8_t revid; /* chip revision ID */ 72 73 u_int8_t hdrtype; /* chip config header type */ 74 u_int8_t cachelnsz; /* cache line size in 4byte units */ 75 u_int8_t intpin; /* PCI interrupt pin */ 76 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 77 78 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 79 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 80 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 81 82 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 83 u_int8_t nummaps; /* actual number of PCI maps used */ 84 85 u_int8_t hose; /* hose which bus is attached to */ 86 u_int8_t bus; /* config space bus address */ 87 u_int8_t slot; /* config space slot address */ 88 u_int8_t func; /* config space function number */ 89 90 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 91 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 92 } pcicfgregs; 93 94 /* additional type 1 device config header information (PCI to PCI bridge) */ 95 96 #ifdef PCI_A64 97 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 98 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 99 #else 100 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 101 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 102 #endif /* PCI_A64 */ 103 104 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 105 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 106 107 typedef struct { 108 pci_addr_t pmembase; /* base address of prefetchable memory */ 109 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 110 u_int32_t membase; /* base address of memory window */ 111 u_int32_t memlimit; /* topmost address of memory window */ 112 u_int32_t iobase; /* base address of port window */ 113 u_int32_t iolimit; /* topmost address of port window */ 114 u_int16_t secstat; /* secondary bus status register */ 115 u_int16_t bridgectl; /* bridge control register */ 116 u_int8_t seclat; /* CardBus latency timer */ 117 } pcih1cfgregs; 118 119 /* additional type 2 device config header information (CardBus bridge) */ 120 121 typedef struct { 122 u_int32_t membase0; /* base address of memory window */ 123 u_int32_t memlimit0; /* topmost address of memory window */ 124 u_int32_t membase1; /* base address of memory window */ 125 u_int32_t memlimit1; /* topmost address of memory window */ 126 u_int32_t iobase0; /* base address of port window */ 127 u_int32_t iolimit0; /* topmost address of port window */ 128 u_int32_t iobase1; /* base address of port window */ 129 u_int32_t iolimit1; /* topmost address of port window */ 130 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 131 u_int16_t secstat; /* secondary bus status register */ 132 u_int16_t bridgectl; /* bridge control register */ 133 u_int8_t seclat; /* CardBus latency timer */ 134 } pcih2cfgregs; 135 136 extern u_int32_t pci_numdevs; 137 138 /* Only if the prerequisites are present */ 139 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 140 struct pci_devinfo { 141 STAILQ_ENTRY(pci_devinfo) pci_links; 142 struct resource_list resources; 143 pcicfgregs cfg; 144 struct pci_conf conf; 145 }; 146 #endif 147 148 /* externally visible functions */ 149 150 const char *pci_ata_match(struct device *dev); 151 const char *pci_usb_match(struct device *dev); 152 const char *pci_vga_match(struct device *dev); 153 const char *pci_chip_match(struct device *dev); 154 155 /* low level PCI config register functions provided by pcibus.c */ 156 157 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 158 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 159 #ifdef __alpha__ 160 vm_offset_t pci_cvt_to_dense (vm_offset_t); 161 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 162 #endif /* __alpha__ */ 163 164 /* low level devlist operations for the 2.2 compatibility code in pci.c */ 165 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 166 167 #ifdef _SYS_BUS_H_ 168 169 #include "pci_if.h" 170 171 /* 172 * Define pci-specific resource flags for accessing memory via dense 173 * or bwx memory spaces. These flags are ignored on i386. 174 */ 175 #define PCI_RF_DENSE 0x10000 176 #define PCI_RF_BWX 0x20000 177 178 enum pci_device_ivars { 179 PCI_IVAR_SUBVENDOR, 180 PCI_IVAR_SUBDEVICE, 181 PCI_IVAR_VENDOR, 182 PCI_IVAR_DEVICE, 183 PCI_IVAR_DEVID, 184 PCI_IVAR_CLASS, 185 PCI_IVAR_SUBCLASS, 186 PCI_IVAR_PROGIF, 187 PCI_IVAR_REVID, 188 PCI_IVAR_INTPIN, 189 PCI_IVAR_IRQ, 190 PCI_IVAR_BUS, 191 PCI_IVAR_SLOT, 192 PCI_IVAR_FUNCTION, 193 PCI_IVAR_SECONDARYBUS, 194 PCI_IVAR_SUBORDINATEBUS, 195 PCI_IVAR_HOSE, 196 }; 197 198 /* 199 * Simplified accessors for pci devices 200 */ 201 #define PCI_ACCESSOR(A, B, T) \ 202 \ 203 static __inline T pci_get_ ## A(device_t dev) \ 204 { \ 205 uintptr_t v; \ 206 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 207 return (T) v; \ 208 } \ 209 \ 210 static __inline void pci_set_ ## A(device_t dev, T t) \ 211 { \ 212 u_long v = (u_long) t; \ 213 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 214 } 215 216 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 217 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 218 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 219 PCI_ACCESSOR(device, DEVICE, u_int16_t) 220 PCI_ACCESSOR(devid, DEVID, u_int32_t) 221 PCI_ACCESSOR(class, CLASS, u_int8_t) 222 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 223 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 224 PCI_ACCESSOR(revid, REVID, u_int8_t) 225 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 226 PCI_ACCESSOR(irq, IRQ, u_int8_t) 227 PCI_ACCESSOR(bus, BUS, u_int8_t) 228 PCI_ACCESSOR(slot, SLOT, u_int8_t) 229 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 230 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 231 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 232 PCI_ACCESSOR(hose, HOSE, u_int32_t) 233 234 static __inline u_int32_t 235 pci_read_config(device_t dev, int reg, int width) 236 { 237 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 238 } 239 240 static __inline void 241 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 242 { 243 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 244 } 245 246 /* 247 * Ivars for pci bridges. 248 */ 249 250 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 251 enum pcib_device_ivars { 252 PCIB_IVAR_HOSE, 253 }; 254 255 #define PCIB_ACCESSOR(A, B, T) \ 256 \ 257 static __inline T pcib_get_ ## A(device_t dev) \ 258 { \ 259 uintptr_t v; \ 260 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 261 return (T) v; \ 262 } \ 263 \ 264 static __inline void pcib_set_ ## A(device_t dev, T t) \ 265 { \ 266 u_long v = (u_long) t; \ 267 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 268 } 269 270 PCIB_ACCESSOR(hose, HOSE, u_int32_t) 271 272 #endif 273 274 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 275 276 #if defined(_KERNEL) && !defined(KLD_MODULE) 277 #include "opt_compat_oldpci.h" 278 #endif 279 280 #ifdef COMPAT_OLDPCI 281 282 /* all this is going some day */ 283 284 typedef pcicfgregs *pcici_t; 285 typedef unsigned pcidi_t; 286 typedef void pci_inthand_t(void *arg); 287 288 #define pci_max_burst_len (3) 289 290 /* just copied from old PCI code for now ... */ 291 292 struct pci_device { 293 char* pd_name; 294 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 295 void (*pd_attach) (pcici_t tag, int unit); 296 u_long *pd_count; 297 int (*pd_shutdown) (int, int); 298 }; 299 300 #ifdef __i386__ 301 typedef u_short pci_port_t; 302 #else 303 typedef u_int pci_port_t; 304 #endif 305 306 u_long pci_conf_read (pcici_t tag, u_long reg); 307 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 308 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 309 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 310 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 311 intrmask_t *maskptr); 312 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 313 intrmask_t *maskptr, u_int flags); 314 int pci_unmap_int (pcici_t tag); 315 316 pcici_t pci_get_parent_from_tag(pcici_t tag); 317 int pci_get_bus_from_tag(pcici_t tag); 318 319 struct module; 320 int compat_pci_handler (struct module *, int, void *); 321 #define COMPAT_PCI_DRIVER(name, pcidata) \ 322 static moduledata_t name##_mod = { \ 323 #name, \ 324 compat_pci_handler, \ 325 &pcidata \ 326 }; \ 327 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 328 #endif /* COMPAT_OLDPCI */ 329 330 #endif /* _PCIVAR_H_ */ 331