1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 37 #define PCI_BUSMAX 255 /* highest supported bus number */ 38 #define PCI_SLOTMAX 31 /* highest supported slot number */ 39 #define PCI_FUNCMAX 7 /* highest supported function number */ 40 #define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48 #ifdef PCI_A64 49 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50 #else 51 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52 #endif 53 54 /* config header information common to all header types */ 55 56 typedef struct pcicfg { 57 struct device *dev; /* device which owns this */ 58 59 u_int16_t subvendor; /* card vendor ID */ 60 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 61 u_int16_t vendor; /* chip vendor ID */ 62 u_int16_t device; /* chip device ID, assigned by chip vendor */ 63 64 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 65 u_int16_t statreg; /* supported PCI features and error state */ 66 67 u_int8_t baseclass; /* chip PCI class */ 68 u_int8_t subclass; /* chip PCI subclass */ 69 u_int8_t progif; /* chip PCI programming interface */ 70 u_int8_t revid; /* chip revision ID */ 71 72 u_int8_t hdrtype; /* chip config header type */ 73 u_int8_t cachelnsz; /* cache line size in 4byte units */ 74 u_int8_t intpin; /* PCI interrupt pin */ 75 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 76 77 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 78 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 79 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 80 81 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 82 u_int8_t nummaps; /* actual number of PCI maps used */ 83 84 u_int8_t bus; /* config space bus address */ 85 u_int8_t slot; /* config space slot address */ 86 u_int8_t func; /* config space function number */ 87 88 u_int16_t pp_cap; /* PCI power management capabilities */ 89 u_int8_t pp_status; /* config space address of PCI power status reg */ 90 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 91 u_int8_t pp_data; /* config space address of PCI power data reg */ 92 93 } pcicfgregs; 94 95 /* additional type 1 device config header information (PCI to PCI bridge) */ 96 97 #ifdef PCI_A64 98 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 99 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 100 #else 101 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 102 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 103 #endif /* PCI_A64 */ 104 105 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 106 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 107 108 typedef struct { 109 pci_addr_t pmembase; /* base address of prefetchable memory */ 110 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 111 u_int32_t membase; /* base address of memory window */ 112 u_int32_t memlimit; /* topmost address of memory window */ 113 u_int32_t iobase; /* base address of port window */ 114 u_int32_t iolimit; /* topmost address of port window */ 115 u_int16_t secstat; /* secondary bus status register */ 116 u_int16_t bridgectl; /* bridge control register */ 117 u_int8_t seclat; /* CardBus latency timer */ 118 } pcih1cfgregs; 119 120 /* additional type 2 device config header information (CardBus bridge) */ 121 122 typedef struct { 123 u_int32_t membase0; /* base address of memory window */ 124 u_int32_t memlimit0; /* topmost address of memory window */ 125 u_int32_t membase1; /* base address of memory window */ 126 u_int32_t memlimit1; /* topmost address of memory window */ 127 u_int32_t iobase0; /* base address of port window */ 128 u_int32_t iolimit0; /* topmost address of port window */ 129 u_int32_t iobase1; /* base address of port window */ 130 u_int32_t iolimit1; /* topmost address of port window */ 131 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 132 u_int16_t secstat; /* secondary bus status register */ 133 u_int16_t bridgectl; /* bridge control register */ 134 u_int8_t seclat; /* CardBus latency timer */ 135 } pcih2cfgregs; 136 137 extern u_int32_t pci_numdevs; 138 139 /* Only if the prerequisites are present */ 140 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 141 struct pci_devinfo { 142 STAILQ_ENTRY(pci_devinfo) pci_links; 143 struct resource_list resources; 144 pcicfgregs cfg; 145 struct pci_conf conf; 146 }; 147 #endif 148 149 #ifdef __alpha__ 150 vm_offset_t pci_cvt_to_dense (vm_offset_t); 151 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 152 #endif /* __alpha__ */ 153 154 #ifdef _SYS_BUS_H_ 155 156 #include "pci_if.h" 157 158 /* 159 * Define pci-specific resource flags for accessing memory via dense 160 * or bwx memory spaces. These flags are ignored on i386. 161 */ 162 #define PCI_RF_DENSE 0x10000 163 #define PCI_RF_BWX 0x20000 164 165 enum pci_device_ivars { 166 PCI_IVAR_SUBVENDOR, 167 PCI_IVAR_SUBDEVICE, 168 PCI_IVAR_VENDOR, 169 PCI_IVAR_DEVICE, 170 PCI_IVAR_DEVID, 171 PCI_IVAR_CLASS, 172 PCI_IVAR_SUBCLASS, 173 PCI_IVAR_PROGIF, 174 PCI_IVAR_REVID, 175 PCI_IVAR_INTPIN, 176 PCI_IVAR_IRQ, 177 PCI_IVAR_BUS, 178 PCI_IVAR_SLOT, 179 PCI_IVAR_FUNCTION, 180 }; 181 182 /* 183 * Simplified accessors for pci devices 184 */ 185 #define PCI_ACCESSOR(var, ivar, type) \ 186 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 187 188 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 189 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 190 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 191 PCI_ACCESSOR(device, DEVICE, u_int16_t) 192 PCI_ACCESSOR(devid, DEVID, u_int32_t) 193 PCI_ACCESSOR(class, CLASS, u_int8_t) 194 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 195 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 196 PCI_ACCESSOR(revid, REVID, u_int8_t) 197 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 198 PCI_ACCESSOR(irq, IRQ, u_int8_t) 199 PCI_ACCESSOR(bus, BUS, u_int8_t) 200 PCI_ACCESSOR(slot, SLOT, u_int8_t) 201 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 202 203 #undef PCI_ACCESSOR 204 205 /* 206 * Operations on configuration space. 207 */ 208 static __inline u_int32_t 209 pci_read_config(device_t dev, int reg, int width) 210 { 211 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 212 } 213 214 static __inline void 215 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 216 { 217 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 218 } 219 220 /* 221 * Ivars for pci bridges. 222 */ 223 224 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 225 enum pcib_device_ivars { 226 PCIB_IVAR_BUS 227 }; 228 229 #define PCIB_ACCESSOR(A, B, T) \ 230 \ 231 static __inline T pcib_get_ ## A(device_t dev) \ 232 { \ 233 uintptr_t v; \ 234 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 235 return (T) v; \ 236 } \ 237 \ 238 static __inline void pcib_set_ ## A(device_t dev, T t) \ 239 { \ 240 uintptr_t v = (uintptr_t) t; \ 241 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 242 } 243 244 PCIB_ACCESSOR(bus, BUS, u_int32_t) 245 246 #undef PCIB_ACCESSOR 247 248 /* 249 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 250 * on i386 or other platforms should be mapped out in the MD pcireadconf 251 * code and not here, since the only MI invalid IRQ is 255. 252 */ 253 #define PCI_INVALID_IRQ 255 254 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 255 256 /* 257 * Convenience functions. 258 * 259 * These should be used in preference to manually manipulating 260 * configuration space. 261 */ 262 static __inline void 263 pci_enable_busmaster(device_t dev) 264 { 265 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 266 } 267 268 static __inline void 269 pci_disable_busmaster(device_t dev) 270 { 271 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 272 } 273 274 static __inline void 275 pci_enable_io(device_t dev, int space) 276 { 277 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 278 } 279 280 static __inline void 281 pci_disable_io(device_t dev, int space) 282 { 283 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 284 } 285 286 /* 287 * PCI power states are as defined by ACPI: 288 * 289 * D0 State in which device is on and running. It is receiving full 290 * power from the system and delivering full functionality to the user. 291 * D1 Class-specific low-power state in which device context may or may not 292 * be lost. Buses in D1 cannot do anything to the bus that would force 293 * devices on that bus to loose context. 294 * D2 Class-specific low-power state in which device context may or may 295 * not be lost. Attains greater power savings than D1. Buses in D2 296 * can cause devices on that bus to loose some context. Devices in D2 297 * must be prepared for the bus to be in D2 or higher. 298 * D3 State in which the device is off and not running. Device context is 299 * lost. Power can be removed from the device. 300 */ 301 #define PCI_POWERSTATE_D0 0 302 #define PCI_POWERSTATE_D1 1 303 #define PCI_POWERSTATE_D2 2 304 #define PCI_POWERSTATE_D3 3 305 #define PCI_POWERSTATE_UNKNOWN -1 306 307 static __inline int 308 pci_set_powerstate(device_t dev, int state) 309 { 310 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 311 } 312 313 static __inline int 314 pci_get_powerstate(device_t dev) 315 { 316 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 317 } 318 319 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 320 device_t pci_find_device(u_int16_t, u_int16_t); 321 #endif /* _SYS_BUS_H_ */ 322 323 /* 324 * cdev switch for control device, initialised in generic PCI code 325 */ 326 extern struct cdevsw pcicdev; 327 328 /* 329 * List of all PCI devices, generation count for the list. 330 */ 331 STAILQ_HEAD(devlist, pci_devinfo); 332 333 extern struct devlist pci_devq; 334 extern u_int32_t pci_generation; 335 336 #endif /* _PCIVAR_H_ */ 337