1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 37 #define PCI_BUSMAX 255 /* highest supported bus number */ 38 #define PCI_SLOTMAX 31 /* highest supported slot number */ 39 #define PCI_FUNCMAX 7 /* highest supported function number */ 40 #define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46 typedef uint64_t pci_addr_t; 47 48 /* Interesting values for PCI power management */ 49 struct pcicfg_pp { 50 uint16_t pp_cap; /* PCI power management capabilities */ 51 uint8_t pp_status; /* config space address of PCI power status reg */ 52 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 53 uint8_t pp_data; /* config space address of PCI power data reg */ 54 }; 55 56 struct vpd_readonly { 57 char keyword[2]; 58 char *value; 59 }; 60 61 struct vpd_write { 62 char keyword[2]; 63 char *value; 64 int start; 65 int len; 66 }; 67 68 struct pcicfg_vpd { 69 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 70 char *vpd_ident; /* string identifier */ 71 int vpd_rocnt; 72 struct vpd_readonly *vpd_ros; 73 int vpd_wcnt; 74 struct vpd_write *vpd_w; 75 }; 76 77 /* Interesting values for PCI MSI */ 78 struct pcicfg_msi { 79 uint16_t msi_ctrl; /* Message Control */ 80 uint8_t msi_msgnum; /* Number of messages */ 81 uint16_t msi_data; /* Location of MSI data word */ 82 }; 83 84 /* config header information common to all header types */ 85 typedef struct pcicfg { 86 struct device *dev; /* device which owns this */ 87 88 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 89 uint32_t bios; /* BIOS mapping */ 90 91 uint16_t subvendor; /* card vendor ID */ 92 uint16_t subdevice; /* card device ID, assigned by card vendor */ 93 uint16_t vendor; /* chip vendor ID */ 94 uint16_t device; /* chip device ID, assigned by chip vendor */ 95 96 uint16_t cmdreg; /* disable/enable chip and PCI options */ 97 uint16_t statreg; /* supported PCI features and error state */ 98 99 uint8_t baseclass; /* chip PCI class */ 100 uint8_t subclass; /* chip PCI subclass */ 101 uint8_t progif; /* chip PCI programming interface */ 102 uint8_t revid; /* chip revision ID */ 103 104 uint8_t hdrtype; /* chip config header type */ 105 uint8_t cachelnsz; /* cache line size in 4byte units */ 106 uint8_t intpin; /* PCI interrupt pin */ 107 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 108 109 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 110 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 111 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 112 113 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 114 uint8_t nummaps; /* actual number of PCI maps used */ 115 116 uint8_t bus; /* config space bus address */ 117 uint8_t slot; /* config space slot address */ 118 uint8_t func; /* config space function number */ 119 120 struct pcicfg_pp pp; /* pci power management */ 121 struct pcicfg_vpd vpd; /* pci vital product data */ 122 struct pcicfg_msi msi; /* pci msi */ 123 } pcicfgregs; 124 125 /* additional type 1 device config header information (PCI to PCI bridge) */ 126 127 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 128 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 129 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 130 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 131 132 typedef struct { 133 pci_addr_t pmembase; /* base address of prefetchable memory */ 134 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 135 uint32_t membase; /* base address of memory window */ 136 uint32_t memlimit; /* topmost address of memory window */ 137 uint32_t iobase; /* base address of port window */ 138 uint32_t iolimit; /* topmost address of port window */ 139 uint16_t secstat; /* secondary bus status register */ 140 uint16_t bridgectl; /* bridge control register */ 141 uint8_t seclat; /* CardBus latency timer */ 142 } pcih1cfgregs; 143 144 /* additional type 2 device config header information (CardBus bridge) */ 145 146 typedef struct { 147 uint32_t membase0; /* base address of memory window */ 148 uint32_t memlimit0; /* topmost address of memory window */ 149 uint32_t membase1; /* base address of memory window */ 150 uint32_t memlimit1; /* topmost address of memory window */ 151 uint32_t iobase0; /* base address of port window */ 152 uint32_t iolimit0; /* topmost address of port window */ 153 uint32_t iobase1; /* base address of port window */ 154 uint32_t iolimit1; /* topmost address of port window */ 155 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 156 uint16_t secstat; /* secondary bus status register */ 157 uint16_t bridgectl; /* bridge control register */ 158 uint8_t seclat; /* CardBus latency timer */ 159 } pcih2cfgregs; 160 161 extern uint32_t pci_numdevs; 162 163 /* Only if the prerequisites are present */ 164 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 165 struct pci_devinfo { 166 STAILQ_ENTRY(pci_devinfo) pci_links; 167 struct resource_list resources; 168 pcicfgregs cfg; 169 struct pci_conf conf; 170 }; 171 #endif 172 173 #ifdef _SYS_BUS_H_ 174 175 #include "pci_if.h" 176 177 /* 178 * Define pci-specific resource flags for accessing memory via dense 179 * or bwx memory spaces. These flags are ignored on i386. 180 */ 181 #define PCI_RF_DENSE 0x10000 182 #define PCI_RF_BWX 0x20000 183 184 enum pci_device_ivars { 185 PCI_IVAR_SUBVENDOR, 186 PCI_IVAR_SUBDEVICE, 187 PCI_IVAR_VENDOR, 188 PCI_IVAR_DEVICE, 189 PCI_IVAR_DEVID, 190 PCI_IVAR_CLASS, 191 PCI_IVAR_SUBCLASS, 192 PCI_IVAR_PROGIF, 193 PCI_IVAR_REVID, 194 PCI_IVAR_INTPIN, 195 PCI_IVAR_IRQ, 196 PCI_IVAR_BUS, 197 PCI_IVAR_SLOT, 198 PCI_IVAR_FUNCTION, 199 PCI_IVAR_ETHADDR, 200 PCI_IVAR_CMDREG, 201 PCI_IVAR_CACHELNSZ, 202 PCI_IVAR_MINGNT, 203 PCI_IVAR_MAXLAT, 204 PCI_IVAR_LATTIMER, 205 }; 206 207 /* 208 * Simplified accessors for pci devices 209 */ 210 #define PCI_ACCESSOR(var, ivar, type) \ 211 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 212 213 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 214 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 215 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 216 PCI_ACCESSOR(device, DEVICE, uint16_t) 217 PCI_ACCESSOR(devid, DEVID, uint32_t) 218 PCI_ACCESSOR(class, CLASS, uint8_t) 219 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 220 PCI_ACCESSOR(progif, PROGIF, uint8_t) 221 PCI_ACCESSOR(revid, REVID, uint8_t) 222 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 223 PCI_ACCESSOR(irq, IRQ, uint8_t) 224 PCI_ACCESSOR(bus, BUS, uint8_t) 225 PCI_ACCESSOR(slot, SLOT, uint8_t) 226 PCI_ACCESSOR(function, FUNCTION, uint8_t) 227 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 228 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 229 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 230 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 231 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 232 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 233 234 #undef PCI_ACCESSOR 235 236 /* 237 * Operations on configuration space. 238 */ 239 static __inline uint32_t 240 pci_read_config(device_t dev, int reg, int width) 241 { 242 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 243 } 244 245 static __inline void 246 pci_write_config(device_t dev, int reg, uint32_t val, int width) 247 { 248 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 249 } 250 251 /* 252 * Ivars for pci bridges. 253 */ 254 255 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 256 enum pcib_device_ivars { 257 PCIB_IVAR_BUS 258 }; 259 260 #define PCIB_ACCESSOR(var, ivar, type) \ 261 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 262 263 PCIB_ACCESSOR(bus, BUS, uint32_t) 264 265 #undef PCIB_ACCESSOR 266 267 /* 268 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 269 * on i386 or other platforms should be mapped out in the MD pcireadconf 270 * code and not here, since the only MI invalid IRQ is 255. 271 */ 272 #define PCI_INVALID_IRQ 255 273 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 274 275 /* 276 * Convenience functions. 277 * 278 * These should be used in preference to manually manipulating 279 * configuration space. 280 */ 281 static __inline int 282 pci_enable_busmaster(device_t dev) 283 { 284 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 285 } 286 287 static __inline int 288 pci_disable_busmaster(device_t dev) 289 { 290 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 291 } 292 293 static __inline int 294 pci_enable_io(device_t dev, int space) 295 { 296 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 297 } 298 299 static __inline int 300 pci_disable_io(device_t dev, int space) 301 { 302 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 303 } 304 305 static __inline int 306 pci_get_vpd_ident(device_t dev, const char **identptr) 307 { 308 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 309 } 310 311 static __inline int 312 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 313 { 314 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 315 } 316 317 /* 318 * Check if the address range falls within the VGA defined address range(s) 319 */ 320 static __inline int 321 pci_is_vga_ioport_range(u_long start, u_long end) 322 { 323 324 return (((start >= 0x3b0 && end <= 0x3bb) || 325 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 326 } 327 328 static __inline int 329 pci_is_vga_memory_range(u_long start, u_long end) 330 { 331 332 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 333 } 334 335 /* 336 * PCI power states are as defined by ACPI: 337 * 338 * D0 State in which device is on and running. It is receiving full 339 * power from the system and delivering full functionality to the user. 340 * D1 Class-specific low-power state in which device context may or may not 341 * be lost. Buses in D1 cannot do anything to the bus that would force 342 * devices on that bus to lose context. 343 * D2 Class-specific low-power state in which device context may or may 344 * not be lost. Attains greater power savings than D1. Buses in D2 345 * can cause devices on that bus to lose some context. Devices in D2 346 * must be prepared for the bus to be in D2 or higher. 347 * D3 State in which the device is off and not running. Device context is 348 * lost. Power can be removed from the device. 349 */ 350 #define PCI_POWERSTATE_D0 0 351 #define PCI_POWERSTATE_D1 1 352 #define PCI_POWERSTATE_D2 2 353 #define PCI_POWERSTATE_D3 3 354 #define PCI_POWERSTATE_UNKNOWN -1 355 356 static __inline int 357 pci_set_powerstate(device_t dev, int state) 358 { 359 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 360 } 361 362 static __inline int 363 pci_get_powerstate(device_t dev) 364 { 365 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 366 } 367 368 static __inline int 369 pci_find_extcap(device_t dev, int capability, int *capreg) 370 { 371 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 372 } 373 374 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 375 device_t pci_find_device(uint16_t, uint16_t); 376 #endif /* _SYS_BUS_H_ */ 377 378 /* 379 * cdev switch for control device, initialised in generic PCI code 380 */ 381 extern struct cdevsw pcicdev; 382 383 /* 384 * List of all PCI devices, generation count for the list. 385 */ 386 STAILQ_HEAD(devlist, pci_devinfo); 387 388 extern struct devlist pci_devq; 389 extern uint32_t pci_generation; 390 391 #endif /* _PCIVAR_H_ */ 392