1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40 typedef uint64_t pci_addr_t; 41 42 struct nvlist; 43 44 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */ 45 struct pcicfg_bridge { 46 uint8_t br_seclat; 47 uint8_t br_subbus; 48 uint8_t br_secbus; 49 uint8_t br_pribus; 50 uint16_t br_control; 51 }; 52 53 /* Interesting values for PCI power management */ 54 struct pcicfg_pp { 55 uint16_t pp_cap; /* PCI power management capabilities */ 56 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 57 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 58 uint8_t pp_data; /* conf. space addr. of PM data reg */ 59 }; 60 61 struct pci_map { 62 pci_addr_t pm_value; /* Raw BAR value */ 63 pci_addr_t pm_size; 64 uint16_t pm_reg; 65 STAILQ_ENTRY(pci_map) pm_link; 66 }; 67 68 struct vpd_readonly { 69 char keyword[2]; 70 char *value; 71 int len; 72 }; 73 74 struct vpd_write { 75 char keyword[2]; 76 char *value; 77 int start; 78 int len; 79 }; 80 81 struct pcicfg_vpd { 82 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 83 char vpd_cached; 84 char *vpd_ident; /* string identifier */ 85 int vpd_rocnt; 86 struct vpd_readonly *vpd_ros; 87 int vpd_wcnt; 88 struct vpd_write *vpd_w; 89 }; 90 91 /* Interesting values for PCI MSI */ 92 struct pcicfg_msi { 93 uint16_t msi_ctrl; /* Message Control */ 94 uint8_t msi_location; /* Offset of MSI capability registers. */ 95 uint8_t msi_msgnum; /* Number of messages */ 96 int msi_alloc; /* Number of allocated messages. */ 97 uint64_t msi_addr; /* Contents of address register. */ 98 uint16_t msi_data; /* Contents of data register. */ 99 u_int msi_handlers; 100 }; 101 102 /* Interesting values for PCI MSI-X */ 103 struct msix_vector { 104 uint64_t mv_address; /* Contents of address register. */ 105 uint32_t mv_data; /* Contents of data register. */ 106 int mv_irq; 107 }; 108 109 struct msix_table_entry { 110 u_int mte_vector; /* 1-based index into msix_vectors array. */ 111 u_int mte_handlers; 112 }; 113 114 struct pcicfg_msix { 115 uint16_t msix_ctrl; /* Message Control */ 116 uint16_t msix_msgnum; /* Number of messages */ 117 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 118 uint8_t msix_table_bar; /* BAR containing vector table. */ 119 uint8_t msix_pba_bar; /* BAR containing PBA. */ 120 uint32_t msix_table_offset; 121 uint32_t msix_pba_offset; 122 int msix_alloc; /* Number of allocated vectors. */ 123 int msix_table_len; /* Length of virtual table. */ 124 struct msix_table_entry *msix_table; /* Virtual table. */ 125 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 126 struct resource *msix_table_res; /* Resource containing vector table. */ 127 struct resource *msix_pba_res; /* Resource containing PBA. */ 128 }; 129 130 /* Interesting values for HyperTransport */ 131 struct pcicfg_ht { 132 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 133 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 134 uint16_t ht_msictrl; /* MSI mapping control */ 135 uint64_t ht_msiaddr; /* MSI mapping base address */ 136 }; 137 138 /* Interesting values for PCI-express */ 139 struct pcicfg_pcie { 140 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 141 uint8_t pcie_type; /* Device type. */ 142 uint16_t pcie_flags; /* Device capabilities register. */ 143 uint16_t pcie_device_ctl; /* Device control register. */ 144 uint16_t pcie_link_ctl; /* Link control register. */ 145 uint16_t pcie_slot_ctl; /* Slot control register. */ 146 uint16_t pcie_root_ctl; /* Root control register. */ 147 uint16_t pcie_device_ctl2; /* Second device control register. */ 148 uint16_t pcie_link_ctl2; /* Second link control register. */ 149 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 150 }; 151 152 struct pcicfg_pcix { 153 uint16_t pcix_command; 154 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 155 }; 156 157 struct pcicfg_vf { 158 int index; 159 }; 160 161 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 162 163 /* config header information common to all header types */ 164 typedef struct pcicfg { 165 struct device *dev; /* device which owns this */ 166 167 STAILQ_HEAD(, pci_map) maps; /* BARs */ 168 169 uint16_t subvendor; /* card vendor ID */ 170 uint16_t subdevice; /* card device ID, assigned by card vendor */ 171 uint16_t vendor; /* chip vendor ID */ 172 uint16_t device; /* chip device ID, assigned by chip vendor */ 173 174 uint16_t cmdreg; /* disable/enable chip and PCI options */ 175 uint16_t statreg; /* supported PCI features and error state */ 176 177 uint8_t baseclass; /* chip PCI class */ 178 uint8_t subclass; /* chip PCI subclass */ 179 uint8_t progif; /* chip PCI programming interface */ 180 uint8_t revid; /* chip revision ID */ 181 182 uint8_t hdrtype; /* chip config header type */ 183 uint8_t cachelnsz; /* cache line size in 4byte units */ 184 uint8_t intpin; /* PCI interrupt pin */ 185 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 186 187 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 188 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 189 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 190 191 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 192 uint8_t nummaps; /* actual number of PCI maps used */ 193 194 uint32_t domain; /* PCI domain */ 195 uint8_t bus; /* config space bus address */ 196 uint8_t slot; /* config space slot address */ 197 uint8_t func; /* config space function number */ 198 199 uint32_t flags; /* flags defined above */ 200 size_t devinfo_size; /* Size of devinfo for this bus type. */ 201 202 struct pcicfg_bridge bridge; /* Bridges */ 203 struct pcicfg_pp pp; /* Power management */ 204 struct pcicfg_vpd vpd; /* Vital product data */ 205 struct pcicfg_msi msi; /* PCI MSI */ 206 struct pcicfg_msix msix; /* PCI MSI-X */ 207 struct pcicfg_ht ht; /* HyperTransport */ 208 struct pcicfg_pcie pcie; /* PCI Express */ 209 struct pcicfg_pcix pcix; /* PCI-X */ 210 struct pcicfg_iov *iov; /* SR-IOV */ 211 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 212 } pcicfgregs; 213 214 /* additional type 1 device config header information (PCI to PCI bridge) */ 215 216 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 217 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 218 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 219 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 220 221 typedef struct { 222 pci_addr_t pmembase; /* base address of prefetchable memory */ 223 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 224 uint32_t membase; /* base address of memory window */ 225 uint32_t memlimit; /* topmost address of memory window */ 226 uint32_t iobase; /* base address of port window */ 227 uint32_t iolimit; /* topmost address of port window */ 228 uint16_t secstat; /* secondary bus status register */ 229 uint16_t bridgectl; /* bridge control register */ 230 uint8_t seclat; /* CardBus latency timer */ 231 } pcih1cfgregs; 232 233 /* additional type 2 device config header information (CardBus bridge) */ 234 235 typedef struct { 236 uint32_t membase0; /* base address of memory window */ 237 uint32_t memlimit0; /* topmost address of memory window */ 238 uint32_t membase1; /* base address of memory window */ 239 uint32_t memlimit1; /* topmost address of memory window */ 240 uint32_t iobase0; /* base address of port window */ 241 uint32_t iolimit0; /* topmost address of port window */ 242 uint32_t iobase1; /* base address of port window */ 243 uint32_t iolimit1; /* topmost address of port window */ 244 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 245 uint16_t secstat; /* secondary bus status register */ 246 uint16_t bridgectl; /* bridge control register */ 247 uint8_t seclat; /* CardBus latency timer */ 248 } pcih2cfgregs; 249 250 extern uint32_t pci_numdevs; 251 252 /* Only if the prerequisites are present */ 253 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 254 struct pci_devinfo { 255 STAILQ_ENTRY(pci_devinfo) pci_links; 256 struct resource_list resources; 257 pcicfgregs cfg; 258 struct pci_conf conf; 259 }; 260 #endif 261 262 #ifdef _SYS_BUS_H_ 263 264 #include "pci_if.h" 265 266 enum pci_device_ivars { 267 PCI_IVAR_SUBVENDOR, 268 PCI_IVAR_SUBDEVICE, 269 PCI_IVAR_VENDOR, 270 PCI_IVAR_DEVICE, 271 PCI_IVAR_DEVID, 272 PCI_IVAR_CLASS, 273 PCI_IVAR_SUBCLASS, 274 PCI_IVAR_PROGIF, 275 PCI_IVAR_REVID, 276 PCI_IVAR_INTPIN, 277 PCI_IVAR_IRQ, 278 PCI_IVAR_DOMAIN, 279 PCI_IVAR_BUS, 280 PCI_IVAR_SLOT, 281 PCI_IVAR_FUNCTION, 282 PCI_IVAR_ETHADDR, 283 PCI_IVAR_CMDREG, 284 PCI_IVAR_CACHELNSZ, 285 PCI_IVAR_MINGNT, 286 PCI_IVAR_MAXLAT, 287 PCI_IVAR_LATTIMER 288 }; 289 290 /* 291 * Simplified accessors for pci devices 292 */ 293 #define PCI_ACCESSOR(var, ivar, type) \ 294 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 295 296 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 297 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 298 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 299 PCI_ACCESSOR(device, DEVICE, uint16_t) 300 PCI_ACCESSOR(devid, DEVID, uint32_t) 301 PCI_ACCESSOR(class, CLASS, uint8_t) 302 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 303 PCI_ACCESSOR(progif, PROGIF, uint8_t) 304 PCI_ACCESSOR(revid, REVID, uint8_t) 305 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 306 PCI_ACCESSOR(irq, IRQ, uint8_t) 307 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 308 PCI_ACCESSOR(bus, BUS, uint8_t) 309 PCI_ACCESSOR(slot, SLOT, uint8_t) 310 PCI_ACCESSOR(function, FUNCTION, uint8_t) 311 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 312 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 313 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 314 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 315 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 316 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 317 318 #undef PCI_ACCESSOR 319 320 /* 321 * Operations on configuration space. 322 */ 323 static __inline uint32_t 324 pci_read_config(device_t dev, int reg, int width) 325 { 326 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 327 } 328 329 static __inline void 330 pci_write_config(device_t dev, int reg, uint32_t val, int width) 331 { 332 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 333 } 334 335 /* 336 * Ivars for pci bridges. 337 */ 338 339 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 340 enum pcib_device_ivars { 341 PCIB_IVAR_DOMAIN, 342 PCIB_IVAR_BUS 343 }; 344 345 #define PCIB_ACCESSOR(var, ivar, type) \ 346 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 347 348 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 349 PCIB_ACCESSOR(bus, BUS, uint32_t) 350 351 #undef PCIB_ACCESSOR 352 353 /* 354 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 355 * on i386 or other platforms should be mapped out in the MD pcireadconf 356 * code and not here, since the only MI invalid IRQ is 255. 357 */ 358 #define PCI_INVALID_IRQ 255 359 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 360 361 /* 362 * Convenience functions. 363 * 364 * These should be used in preference to manually manipulating 365 * configuration space. 366 */ 367 static __inline int 368 pci_enable_busmaster(device_t dev) 369 { 370 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 371 } 372 373 static __inline int 374 pci_disable_busmaster(device_t dev) 375 { 376 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 377 } 378 379 static __inline int 380 pci_enable_io(device_t dev, int space) 381 { 382 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 383 } 384 385 static __inline int 386 pci_disable_io(device_t dev, int space) 387 { 388 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 389 } 390 391 static __inline int 392 pci_get_vpd_ident(device_t dev, const char **identptr) 393 { 394 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 395 } 396 397 static __inline int 398 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 399 { 400 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 401 } 402 403 /* 404 * Check if the address range falls within the VGA defined address range(s) 405 */ 406 static __inline int 407 pci_is_vga_ioport_range(u_long start, u_long end) 408 { 409 410 return (((start >= 0x3b0 && end <= 0x3bb) || 411 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 412 } 413 414 static __inline int 415 pci_is_vga_memory_range(u_long start, u_long end) 416 { 417 418 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 419 } 420 421 /* 422 * PCI power states are as defined by ACPI: 423 * 424 * D0 State in which device is on and running. It is receiving full 425 * power from the system and delivering full functionality to the user. 426 * D1 Class-specific low-power state in which device context may or may not 427 * be lost. Buses in D1 cannot do anything to the bus that would force 428 * devices on that bus to lose context. 429 * D2 Class-specific low-power state in which device context may or may 430 * not be lost. Attains greater power savings than D1. Buses in D2 431 * can cause devices on that bus to lose some context. Devices in D2 432 * must be prepared for the bus to be in D2 or higher. 433 * D3 State in which the device is off and not running. Device context is 434 * lost. Power can be removed from the device. 435 */ 436 #define PCI_POWERSTATE_D0 0 437 #define PCI_POWERSTATE_D1 1 438 #define PCI_POWERSTATE_D2 2 439 #define PCI_POWERSTATE_D3 3 440 #define PCI_POWERSTATE_UNKNOWN -1 441 442 static __inline int 443 pci_set_powerstate(device_t dev, int state) 444 { 445 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 446 } 447 448 static __inline int 449 pci_get_powerstate(device_t dev) 450 { 451 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 452 } 453 454 static __inline int 455 pci_find_cap(device_t dev, int capability, int *capreg) 456 { 457 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 458 } 459 460 static __inline int 461 pci_find_extcap(device_t dev, int capability, int *capreg) 462 { 463 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 464 } 465 466 static __inline int 467 pci_find_htcap(device_t dev, int capability, int *capreg) 468 { 469 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 470 } 471 472 static __inline int 473 pci_alloc_msi(device_t dev, int *count) 474 { 475 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 476 } 477 478 static __inline int 479 pci_alloc_msix(device_t dev, int *count) 480 { 481 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 482 } 483 484 static __inline void 485 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 486 { 487 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 488 } 489 490 static __inline void 491 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 492 { 493 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 494 } 495 496 static __inline void 497 pci_disable_msi(device_t dev) 498 { 499 PCI_DISABLE_MSI(device_get_parent(dev), dev); 500 } 501 502 static __inline int 503 pci_remap_msix(device_t dev, int count, const u_int *vectors) 504 { 505 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 506 } 507 508 static __inline int 509 pci_release_msi(device_t dev) 510 { 511 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 512 } 513 514 static __inline int 515 pci_msi_count(device_t dev) 516 { 517 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 518 } 519 520 static __inline int 521 pci_msix_count(device_t dev) 522 { 523 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 524 } 525 526 static __inline uint16_t 527 pci_get_rid(device_t dev) 528 { 529 return (PCI_GET_RID(device_get_parent(dev), dev)); 530 } 531 532 static __inline void 533 pci_child_added(device_t dev) 534 { 535 536 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 537 } 538 539 static __inline int 540 pci_iov_attach(device_t dev, struct nvlist *pf_schema, struct nvlist *vf_schema) 541 { 542 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema, 543 vf_schema)); 544 } 545 546 static __inline int 547 pci_iov_detach(device_t dev) 548 { 549 return (PCI_IOV_DETACH(device_get_parent(dev), dev)); 550 } 551 552 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 553 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 554 device_t pci_find_device(uint16_t, uint16_t); 555 device_t pci_find_class(uint8_t class, uint8_t subclass); 556 557 /* Can be used by drivers to manage the MSI-X table. */ 558 int pci_pending_msix(device_t dev, u_int index); 559 560 int pci_msi_device_blacklisted(device_t dev); 561 int pci_msix_device_blacklisted(device_t dev); 562 563 void pci_ht_map_msi(device_t dev, uint64_t addr); 564 565 int pci_get_max_read_req(device_t dev); 566 void pci_restore_state(device_t dev); 567 void pci_save_state(device_t dev); 568 int pci_set_max_read_req(device_t dev, int size); 569 570 571 #ifdef BUS_SPACE_MAXADDR 572 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 573 #define PCI_DMA_BOUNDARY 0x100000000 574 #else 575 #define PCI_DMA_BOUNDARY 0 576 #endif 577 #endif 578 579 #endif /* _SYS_BUS_H_ */ 580 581 /* 582 * cdev switch for control device, initialised in generic PCI code 583 */ 584 extern struct cdevsw pcicdev; 585 586 /* 587 * List of all PCI devices, generation count for the list. 588 */ 589 STAILQ_HEAD(devlist, pci_devinfo); 590 591 extern struct devlist pci_devq; 592 extern uint32_t pci_generation; 593 594 struct pci_map *pci_find_bar(device_t dev, int reg); 595 int pci_bar_enabled(device_t dev, struct pci_map *pm); 596 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 597 598 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 599 #define VGA_PCI_BIOS_SHADOW_SIZE 131072 600 601 int vga_pci_is_boot_display(device_t dev); 602 void * vga_pci_map_bios(device_t dev, size_t *size); 603 void vga_pci_unmap_bios(device_t dev, void *bios); 604 int vga_pci_repost(device_t dev); 605 606 #endif /* _PCIVAR_H_ */ 607