1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 37 #define PCI_BUSMAX 255 /* highest supported bus number */ 38 #define PCI_SLOTMAX 31 /* highest supported slot number */ 39 #define PCI_FUNCMAX 7 /* highest supported function number */ 40 #define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48 #ifdef PCI_A64 49 typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 50 #else 51 typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 52 #endif 53 54 /* Interesting values for PCI power management */ 55 struct pcicfg_pp { 56 uint16_t pp_cap; /* PCI power management capabilities */ 57 uint8_t pp_status; /* config space address of PCI power status reg */ 58 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 59 uint8_t pp_data; /* config space address of PCI power data reg */ 60 }; 61 62 struct vpd_readonly { 63 char keyword[2]; 64 char *value; 65 }; 66 67 struct vpd_write { 68 char keyword[2]; 69 char *value; 70 int start; 71 int len; 72 }; 73 74 struct pcicfg_vpd { 75 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 76 char *vpd_ident; /* string identifier */ 77 int vpd_rocnt; 78 struct vpd_readonly *vpd_ros; 79 int vpd_wcnt; 80 struct vpd_write *vpd_w; 81 }; 82 83 /* Interesting values for PCI MSI */ 84 struct pcicfg_msi { 85 uint16_t msi_ctrl; /* Message Control */ 86 uint8_t msi_msgnum; /* Number of messages */ 87 uint16_t msi_data; /* Location of MSI data word */ 88 }; 89 90 /* config header information common to all header types */ 91 typedef struct pcicfg { 92 struct device *dev; /* device which owns this */ 93 94 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 95 uint32_t bios; /* BIOS mapping */ 96 97 uint16_t subvendor; /* card vendor ID */ 98 uint16_t subdevice; /* card device ID, assigned by card vendor */ 99 uint16_t vendor; /* chip vendor ID */ 100 uint16_t device; /* chip device ID, assigned by chip vendor */ 101 102 uint16_t cmdreg; /* disable/enable chip and PCI options */ 103 uint16_t statreg; /* supported PCI features and error state */ 104 105 uint8_t baseclass; /* chip PCI class */ 106 uint8_t subclass; /* chip PCI subclass */ 107 uint8_t progif; /* chip PCI programming interface */ 108 uint8_t revid; /* chip revision ID */ 109 110 uint8_t hdrtype; /* chip config header type */ 111 uint8_t cachelnsz; /* cache line size in 4byte units */ 112 uint8_t intpin; /* PCI interrupt pin */ 113 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 114 115 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 116 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 117 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 118 119 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 120 uint8_t nummaps; /* actual number of PCI maps used */ 121 122 uint8_t bus; /* config space bus address */ 123 uint8_t slot; /* config space slot address */ 124 uint8_t func; /* config space function number */ 125 126 struct pcicfg_pp pp; /* pci power management */ 127 struct pcicfg_vpd vpd; /* pci vital product data */ 128 struct pcicfg_msi msi; /* pci msi */ 129 } pcicfgregs; 130 131 /* additional type 1 device config header information (PCI to PCI bridge) */ 132 133 #ifdef PCI_A64 134 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 135 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 136 #else 137 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 138 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 139 #endif /* PCI_A64 */ 140 141 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 142 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 143 144 typedef struct { 145 pci_addr_t pmembase; /* base address of prefetchable memory */ 146 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 147 uint32_t membase; /* base address of memory window */ 148 uint32_t memlimit; /* topmost address of memory window */ 149 uint32_t iobase; /* base address of port window */ 150 uint32_t iolimit; /* topmost address of port window */ 151 uint16_t secstat; /* secondary bus status register */ 152 uint16_t bridgectl; /* bridge control register */ 153 uint8_t seclat; /* CardBus latency timer */ 154 } pcih1cfgregs; 155 156 /* additional type 2 device config header information (CardBus bridge) */ 157 158 typedef struct { 159 uint32_t membase0; /* base address of memory window */ 160 uint32_t memlimit0; /* topmost address of memory window */ 161 uint32_t membase1; /* base address of memory window */ 162 uint32_t memlimit1; /* topmost address of memory window */ 163 uint32_t iobase0; /* base address of port window */ 164 uint32_t iolimit0; /* topmost address of port window */ 165 uint32_t iobase1; /* base address of port window */ 166 uint32_t iolimit1; /* topmost address of port window */ 167 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 168 uint16_t secstat; /* secondary bus status register */ 169 uint16_t bridgectl; /* bridge control register */ 170 uint8_t seclat; /* CardBus latency timer */ 171 } pcih2cfgregs; 172 173 extern uint32_t pci_numdevs; 174 175 /* Only if the prerequisites are present */ 176 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 177 struct pci_devinfo { 178 STAILQ_ENTRY(pci_devinfo) pci_links; 179 struct resource_list resources; 180 pcicfgregs cfg; 181 struct pci_conf conf; 182 }; 183 #endif 184 185 #ifdef _SYS_BUS_H_ 186 187 #include "pci_if.h" 188 189 /* 190 * Define pci-specific resource flags for accessing memory via dense 191 * or bwx memory spaces. These flags are ignored on i386. 192 */ 193 #define PCI_RF_DENSE 0x10000 194 #define PCI_RF_BWX 0x20000 195 196 enum pci_device_ivars { 197 PCI_IVAR_SUBVENDOR, 198 PCI_IVAR_SUBDEVICE, 199 PCI_IVAR_VENDOR, 200 PCI_IVAR_DEVICE, 201 PCI_IVAR_DEVID, 202 PCI_IVAR_CLASS, 203 PCI_IVAR_SUBCLASS, 204 PCI_IVAR_PROGIF, 205 PCI_IVAR_REVID, 206 PCI_IVAR_INTPIN, 207 PCI_IVAR_IRQ, 208 PCI_IVAR_BUS, 209 PCI_IVAR_SLOT, 210 PCI_IVAR_FUNCTION, 211 PCI_IVAR_ETHADDR, 212 PCI_IVAR_CMDREG, 213 PCI_IVAR_CACHELNSZ, 214 PCI_IVAR_MINGNT, 215 PCI_IVAR_MAXLAT, 216 PCI_IVAR_LATTIMER, 217 }; 218 219 /* 220 * Simplified accessors for pci devices 221 */ 222 #define PCI_ACCESSOR(var, ivar, type) \ 223 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 224 225 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 226 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 227 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 228 PCI_ACCESSOR(device, DEVICE, uint16_t) 229 PCI_ACCESSOR(devid, DEVID, uint32_t) 230 PCI_ACCESSOR(class, CLASS, uint8_t) 231 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 232 PCI_ACCESSOR(progif, PROGIF, uint8_t) 233 PCI_ACCESSOR(revid, REVID, uint8_t) 234 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 235 PCI_ACCESSOR(irq, IRQ, uint8_t) 236 PCI_ACCESSOR(bus, BUS, uint8_t) 237 PCI_ACCESSOR(slot, SLOT, uint8_t) 238 PCI_ACCESSOR(function, FUNCTION, uint8_t) 239 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 240 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 241 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 242 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 243 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 244 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 245 246 #undef PCI_ACCESSOR 247 248 /* 249 * Operations on configuration space. 250 */ 251 static __inline uint32_t 252 pci_read_config(device_t dev, int reg, int width) 253 { 254 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 255 } 256 257 static __inline void 258 pci_write_config(device_t dev, int reg, uint32_t val, int width) 259 { 260 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 261 } 262 263 /* 264 * Ivars for pci bridges. 265 */ 266 267 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 268 enum pcib_device_ivars { 269 PCIB_IVAR_BUS 270 }; 271 272 #define PCIB_ACCESSOR(var, ivar, type) \ 273 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 274 275 PCIB_ACCESSOR(bus, BUS, uint32_t) 276 277 #undef PCIB_ACCESSOR 278 279 /* 280 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 281 * on i386 or other platforms should be mapped out in the MD pcireadconf 282 * code and not here, since the only MI invalid IRQ is 255. 283 */ 284 #define PCI_INVALID_IRQ 255 285 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 286 287 /* 288 * Convenience functions. 289 * 290 * These should be used in preference to manually manipulating 291 * configuration space. 292 */ 293 static __inline int 294 pci_enable_busmaster(device_t dev) 295 { 296 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 297 } 298 299 static __inline int 300 pci_disable_busmaster(device_t dev) 301 { 302 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 303 } 304 305 static __inline int 306 pci_enable_io(device_t dev, int space) 307 { 308 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 309 } 310 311 static __inline int 312 pci_disable_io(device_t dev, int space) 313 { 314 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 315 } 316 317 static __inline int 318 pci_get_vpd_ident(device_t dev, const char **identptr) 319 { 320 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 321 } 322 323 static __inline int 324 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 325 { 326 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 327 } 328 329 /* 330 * Check if the address range falls within the VGA defined address range(s) 331 */ 332 static __inline int 333 pci_is_vga_ioport_range(u_long start, u_long end) 334 { 335 336 return (((start >= 0x3b0 && end <= 0x3bb) || 337 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 338 } 339 340 static __inline int 341 pci_is_vga_memory_range(u_long start, u_long end) 342 { 343 344 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 345 } 346 347 /* 348 * PCI power states are as defined by ACPI: 349 * 350 * D0 State in which device is on and running. It is receiving full 351 * power from the system and delivering full functionality to the user. 352 * D1 Class-specific low-power state in which device context may or may not 353 * be lost. Buses in D1 cannot do anything to the bus that would force 354 * devices on that bus to lose context. 355 * D2 Class-specific low-power state in which device context may or may 356 * not be lost. Attains greater power savings than D1. Buses in D2 357 * can cause devices on that bus to lose some context. Devices in D2 358 * must be prepared for the bus to be in D2 or higher. 359 * D3 State in which the device is off and not running. Device context is 360 * lost. Power can be removed from the device. 361 */ 362 #define PCI_POWERSTATE_D0 0 363 #define PCI_POWERSTATE_D1 1 364 #define PCI_POWERSTATE_D2 2 365 #define PCI_POWERSTATE_D3 3 366 #define PCI_POWERSTATE_UNKNOWN -1 367 368 static __inline int 369 pci_set_powerstate(device_t dev, int state) 370 { 371 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 372 } 373 374 static __inline int 375 pci_get_powerstate(device_t dev) 376 { 377 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 378 } 379 380 static __inline int 381 pci_find_extcap(device_t dev, int capability, int *capreg) 382 { 383 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 384 } 385 386 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 387 device_t pci_find_device(uint16_t, uint16_t); 388 #endif /* _SYS_BUS_H_ */ 389 390 /* 391 * cdev switch for control device, initialised in generic PCI code 392 */ 393 extern struct cdevsw pcicdev; 394 395 /* 396 * List of all PCI devices, generation count for the list. 397 */ 398 STAILQ_HEAD(devlist, pci_devinfo); 399 400 extern struct devlist pci_devq; 401 extern uint32_t pci_generation; 402 403 #endif /* _PCIVAR_H_ */ 404