1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 37 #define PCI_BUSMAX 255 /* highest supported bus number */ 38 #define PCI_SLOTMAX 31 /* highest supported slot number */ 39 #define PCI_FUNCMAX 7 /* highest supported function number */ 40 #define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48 #ifdef PCI_A64 49 typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 50 #else 51 typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 52 #endif 53 54 /* Interesting values for PCI power management */ 55 struct pcicfg_pp { 56 uint16_t pp_cap; /* PCI power management capabilities */ 57 uint8_t pp_status; /* config space address of PCI power status reg */ 58 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 59 uint8_t pp_data; /* config space address of PCI power data reg */ 60 }; 61 62 /* Interesting values for PCI MSI */ 63 struct pcicfg_msi { 64 uint16_t msi_ctrl; /* Message Control */ 65 uint8_t msi_msgnum; /* Number of messages */ 66 uint16_t msi_data; /* Location of MSI data word */ 67 }; 68 69 /* config header information common to all header types */ 70 71 typedef struct pcicfg { 72 struct device *dev; /* device which owns this */ 73 74 uint16_t subvendor; /* card vendor ID */ 75 uint16_t subdevice; /* card device ID, assigned by card vendor */ 76 uint16_t vendor; /* chip vendor ID */ 77 uint16_t device; /* chip device ID, assigned by chip vendor */ 78 79 uint16_t cmdreg; /* disable/enable chip and PCI options */ 80 uint16_t statreg; /* supported PCI features and error state */ 81 82 uint8_t baseclass; /* chip PCI class */ 83 uint8_t subclass; /* chip PCI subclass */ 84 uint8_t progif; /* chip PCI programming interface */ 85 uint8_t revid; /* chip revision ID */ 86 87 uint8_t hdrtype; /* chip config header type */ 88 uint8_t cachelnsz; /* cache line size in 4byte units */ 89 uint8_t intpin; /* PCI interrupt pin */ 90 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 91 92 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 93 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 94 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 95 96 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 97 uint8_t nummaps; /* actual number of PCI maps used */ 98 99 uint8_t bus; /* config space bus address */ 100 uint8_t slot; /* config space slot address */ 101 uint8_t func; /* config space function number */ 102 103 struct pcicfg_pp pp; /* pci power management */ 104 struct pcicfg_msi msi; /* pci msi */ 105 } pcicfgregs; 106 107 /* additional type 1 device config header information (PCI to PCI bridge) */ 108 109 #ifdef PCI_A64 110 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 111 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 112 #else 113 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 114 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 115 #endif /* PCI_A64 */ 116 117 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 118 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 119 120 typedef struct { 121 pci_addr_t pmembase; /* base address of prefetchable memory */ 122 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 123 uint32_t membase; /* base address of memory window */ 124 uint32_t memlimit; /* topmost address of memory window */ 125 uint32_t iobase; /* base address of port window */ 126 uint32_t iolimit; /* topmost address of port window */ 127 uint16_t secstat; /* secondary bus status register */ 128 uint16_t bridgectl; /* bridge control register */ 129 uint8_t seclat; /* CardBus latency timer */ 130 } pcih1cfgregs; 131 132 /* additional type 2 device config header information (CardBus bridge) */ 133 134 typedef struct { 135 uint32_t membase0; /* base address of memory window */ 136 uint32_t memlimit0; /* topmost address of memory window */ 137 uint32_t membase1; /* base address of memory window */ 138 uint32_t memlimit1; /* topmost address of memory window */ 139 uint32_t iobase0; /* base address of port window */ 140 uint32_t iolimit0; /* topmost address of port window */ 141 uint32_t iobase1; /* base address of port window */ 142 uint32_t iolimit1; /* topmost address of port window */ 143 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 144 uint16_t secstat; /* secondary bus status register */ 145 uint16_t bridgectl; /* bridge control register */ 146 uint8_t seclat; /* CardBus latency timer */ 147 } pcih2cfgregs; 148 149 extern uint32_t pci_numdevs; 150 151 /* Only if the prerequisites are present */ 152 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 153 struct pci_devinfo { 154 STAILQ_ENTRY(pci_devinfo) pci_links; 155 struct resource_list resources; 156 pcicfgregs cfg; 157 struct pci_conf conf; 158 }; 159 #endif 160 161 #ifdef __alpha__ 162 vm_offset_t pci_cvt_to_dense (vm_offset_t); 163 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 164 #endif /* __alpha__ */ 165 166 #ifdef _SYS_BUS_H_ 167 168 #include "pci_if.h" 169 170 /* 171 * Define pci-specific resource flags for accessing memory via dense 172 * or bwx memory spaces. These flags are ignored on i386. 173 */ 174 #define PCI_RF_DENSE 0x10000 175 #define PCI_RF_BWX 0x20000 176 177 enum pci_device_ivars { 178 PCI_IVAR_SUBVENDOR, 179 PCI_IVAR_SUBDEVICE, 180 PCI_IVAR_VENDOR, 181 PCI_IVAR_DEVICE, 182 PCI_IVAR_DEVID, 183 PCI_IVAR_CLASS, 184 PCI_IVAR_SUBCLASS, 185 PCI_IVAR_PROGIF, 186 PCI_IVAR_REVID, 187 PCI_IVAR_INTPIN, 188 PCI_IVAR_IRQ, 189 PCI_IVAR_BUS, 190 PCI_IVAR_SLOT, 191 PCI_IVAR_FUNCTION, 192 PCI_IVAR_ETHADDR, 193 }; 194 195 /* 196 * Simplified accessors for pci devices 197 */ 198 #define PCI_ACCESSOR(var, ivar, type) \ 199 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 200 201 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 202 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 203 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 204 PCI_ACCESSOR(device, DEVICE, uint16_t) 205 PCI_ACCESSOR(devid, DEVID, uint32_t) 206 PCI_ACCESSOR(class, CLASS, uint8_t) 207 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 208 PCI_ACCESSOR(progif, PROGIF, uint8_t) 209 PCI_ACCESSOR(revid, REVID, uint8_t) 210 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 211 PCI_ACCESSOR(irq, IRQ, uint8_t) 212 PCI_ACCESSOR(bus, BUS, uint8_t) 213 PCI_ACCESSOR(slot, SLOT, uint8_t) 214 PCI_ACCESSOR(function, FUNCTION, uint8_t) 215 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 216 217 #undef PCI_ACCESSOR 218 219 /* 220 * Operations on configuration space. 221 */ 222 static __inline uint32_t 223 pci_read_config(device_t dev, int reg, int width) 224 { 225 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 226 } 227 228 static __inline void 229 pci_write_config(device_t dev, int reg, uint32_t val, int width) 230 { 231 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 232 } 233 234 /* 235 * Ivars for pci bridges. 236 */ 237 238 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 239 enum pcib_device_ivars { 240 PCIB_IVAR_BUS 241 }; 242 243 #define PCIB_ACCESSOR(var, ivar, type) \ 244 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 245 246 PCIB_ACCESSOR(bus, BUS, uint32_t) 247 248 #undef PCIB_ACCESSOR 249 250 /* 251 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 252 * on i386 or other platforms should be mapped out in the MD pcireadconf 253 * code and not here, since the only MI invalid IRQ is 255. 254 */ 255 #define PCI_INVALID_IRQ 255 256 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 257 258 /* 259 * Convenience functions. 260 * 261 * These should be used in preference to manually manipulating 262 * configuration space. 263 */ 264 static __inline int 265 pci_enable_busmaster(device_t dev) 266 { 267 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 268 } 269 270 static __inline int 271 pci_disable_busmaster(device_t dev) 272 { 273 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 274 } 275 276 static __inline int 277 pci_enable_io(device_t dev, int space) 278 { 279 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 280 } 281 282 static __inline int 283 pci_disable_io(device_t dev, int space) 284 { 285 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 286 } 287 288 /* 289 * PCI power states are as defined by ACPI: 290 * 291 * D0 State in which device is on and running. It is receiving full 292 * power from the system and delivering full functionality to the user. 293 * D1 Class-specific low-power state in which device context may or may not 294 * be lost. Buses in D1 cannot do anything to the bus that would force 295 * devices on that bus to loose context. 296 * D2 Class-specific low-power state in which device context may or may 297 * not be lost. Attains greater power savings than D1. Buses in D2 298 * can cause devices on that bus to loose some context. Devices in D2 299 * must be prepared for the bus to be in D2 or higher. 300 * D3 State in which the device is off and not running. Device context is 301 * lost. Power can be removed from the device. 302 */ 303 #define PCI_POWERSTATE_D0 0 304 #define PCI_POWERSTATE_D1 1 305 #define PCI_POWERSTATE_D2 2 306 #define PCI_POWERSTATE_D3 3 307 #define PCI_POWERSTATE_UNKNOWN -1 308 309 static __inline int 310 pci_set_powerstate(device_t dev, int state) 311 { 312 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 313 } 314 315 static __inline int 316 pci_get_powerstate(device_t dev) 317 { 318 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 319 } 320 321 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 322 device_t pci_find_device(uint16_t, uint16_t); 323 #endif /* _SYS_BUS_H_ */ 324 325 /* 326 * cdev switch for control device, initialised in generic PCI code 327 */ 328 extern struct cdevsw pcicdev; 329 330 /* 331 * List of all PCI devices, generation count for the list. 332 */ 333 STAILQ_HEAD(devlist, pci_devinfo); 334 335 extern struct devlist pci_devq; 336 extern uint32_t pci_generation; 337 338 #endif /* _PCIVAR_H_ */ 339