1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 1997, Stefan Esser <se@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _PCIVAR_H_ 30 #define _PCIVAR_H_ 31 32 #include <sys/queue.h> 33 #include <sys/_eventhandler.h> 34 35 /* some PCI bus constants */ 36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40 typedef uint64_t pci_addr_t; 41 42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */ 43 struct pcicfg_bridge { 44 uint8_t br_seclat; 45 uint8_t br_subbus; 46 uint8_t br_secbus; 47 uint8_t br_pribus; 48 uint16_t br_control; 49 }; 50 51 /* Interesting values for PCI power management */ 52 struct pcicfg_pp { 53 uint16_t pp_cap; /* PCI power management capabilities */ 54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 56 uint8_t pp_data; /* conf. space addr. of PM data reg */ 57 }; 58 59 struct pci_map { 60 pci_addr_t pm_value; /* Raw BAR value */ 61 pci_addr_t pm_size; 62 uint16_t pm_reg; 63 STAILQ_ENTRY(pci_map) pm_link; 64 }; 65 66 struct vpd_readonly { 67 char keyword[2]; 68 char *value; 69 int len; 70 }; 71 72 struct vpd_write { 73 char keyword[2]; 74 char *value; 75 int start; 76 int len; 77 }; 78 79 struct pcicfg_vpd { 80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 81 char vpd_cached; 82 char *vpd_ident; /* string identifier */ 83 int vpd_rocnt; 84 struct vpd_readonly *vpd_ros; 85 int vpd_wcnt; 86 struct vpd_write *vpd_w; 87 }; 88 89 /* Interesting values for PCI MSI */ 90 struct pcicfg_msi { 91 uint16_t msi_ctrl; /* Message Control */ 92 uint8_t msi_location; /* Offset of MSI capability registers. */ 93 int msi_alloc; /* Number of allocated messages. */ 94 uint64_t msi_addr; /* Contents of address register. */ 95 uint16_t msi_data; /* Contents of data register. */ 96 u_int msi_handlers; 97 }; 98 99 /* Interesting values for PCI MSI-X */ 100 struct msix_vector { 101 uint64_t mv_address; /* Contents of address register. */ 102 uint32_t mv_data; /* Contents of data register. */ 103 int mv_irq; 104 }; 105 106 struct msix_table_entry { 107 u_int mte_vector; /* 1-based index into msix_vectors array. */ 108 u_int mte_handlers; 109 }; 110 111 struct pcicfg_msix { 112 uint16_t msix_ctrl; /* Message Control */ 113 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 114 uint8_t msix_table_bar; /* BAR containing vector table. */ 115 uint8_t msix_pba_bar; /* BAR containing PBA. */ 116 uint32_t msix_table_offset; 117 uint32_t msix_pba_offset; 118 u_int msix_alloc; /* Number of allocated vectors. */ 119 u_int msix_table_len; /* Length of virtual table. */ 120 struct msix_table_entry *msix_table; /* Virtual table. */ 121 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 122 struct resource *msix_table_res; /* Resource containing vector table. */ 123 struct resource *msix_pba_res; /* Resource containing PBA. */ 124 }; 125 126 struct pci_id_ofw_iommu { 127 uint32_t id; 128 uint32_t xref; 129 }; 130 131 /* Interesting values for HyperTransport */ 132 struct pcicfg_ht { 133 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 134 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 135 uint16_t ht_msictrl; /* MSI mapping control */ 136 uint64_t ht_msiaddr; /* MSI mapping base address */ 137 }; 138 139 /* Interesting values for PCI-express */ 140 struct pcicfg_pcie { 141 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 142 uint8_t pcie_type; /* Device type. */ 143 uint16_t pcie_flags; /* Device capabilities register. */ 144 uint16_t pcie_device_ctl; /* Device control register. */ 145 uint16_t pcie_link_ctl; /* Link control register. */ 146 uint16_t pcie_slot_ctl; /* Slot control register. */ 147 uint16_t pcie_root_ctl; /* Root control register. */ 148 uint16_t pcie_device_ctl2; /* Second device control register. */ 149 uint16_t pcie_link_ctl2; /* Second link control register. */ 150 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 151 }; 152 153 struct pcicfg_pcix { 154 uint16_t pcix_command; 155 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 156 }; 157 158 struct pcicfg_vf { 159 int index; 160 }; 161 162 struct pci_ea_entry { 163 int eae_bei; 164 uint32_t eae_flags; 165 uint64_t eae_base; 166 uint64_t eae_max_offset; 167 uint32_t eae_cfg_offset; 168 STAILQ_ENTRY(pci_ea_entry) eae_link; 169 }; 170 171 struct pcicfg_ea { 172 int ea_location; /* Structure offset in Configuration Header */ 173 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */ 174 }; 175 176 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 177 178 /* config header information common to all header types */ 179 typedef struct pcicfg { 180 device_t dev; /* device which owns this */ 181 182 STAILQ_HEAD(, pci_map) maps; /* BARs */ 183 184 uint16_t subvendor; /* card vendor ID */ 185 uint16_t subdevice; /* card device ID, assigned by card vendor */ 186 uint16_t vendor; /* chip vendor ID */ 187 uint16_t device; /* chip device ID, assigned by chip vendor */ 188 189 uint16_t cmdreg; /* disable/enable chip and PCI options */ 190 uint16_t statreg; /* supported PCI features and error state */ 191 192 uint8_t baseclass; /* chip PCI class */ 193 uint8_t subclass; /* chip PCI subclass */ 194 uint8_t progif; /* chip PCI programming interface */ 195 uint8_t revid; /* chip revision ID */ 196 197 uint8_t hdrtype; /* chip config header type */ 198 uint8_t cachelnsz; /* cache line size in 4byte units */ 199 uint8_t intpin; /* PCI interrupt pin */ 200 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 201 202 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 203 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 204 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 205 206 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 207 uint8_t nummaps; /* actual number of PCI maps used */ 208 209 uint32_t domain; /* PCI domain */ 210 uint8_t bus; /* config space bus address */ 211 uint8_t slot; /* config space slot address */ 212 uint8_t func; /* config space function number */ 213 214 uint32_t flags; /* flags defined above */ 215 216 struct pcicfg_bridge bridge; /* Bridges */ 217 struct pcicfg_pp pp; /* Power management */ 218 struct pcicfg_vpd vpd; /* Vital product data */ 219 struct pcicfg_msi msi; /* PCI MSI */ 220 struct pcicfg_msix msix; /* PCI MSI-X */ 221 struct pcicfg_ht ht; /* HyperTransport */ 222 struct pcicfg_pcie pcie; /* PCI Express */ 223 struct pcicfg_pcix pcix; /* PCI-X */ 224 struct pcicfg_iov *iov; /* SR-IOV */ 225 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 226 struct pcicfg_ea ea; /* Enhanced Allocation */ 227 } pcicfgregs; 228 229 /* additional type 1 device config header information (PCI to PCI bridge) */ 230 231 typedef struct { 232 pci_addr_t pmembase; /* base address of prefetchable memory */ 233 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 234 uint32_t membase; /* base address of memory window */ 235 uint32_t memlimit; /* topmost address of memory window */ 236 uint32_t iobase; /* base address of port window */ 237 uint32_t iolimit; /* topmost address of port window */ 238 uint16_t secstat; /* secondary bus status register */ 239 uint16_t bridgectl; /* bridge control register */ 240 uint8_t seclat; /* CardBus latency timer */ 241 } pcih1cfgregs; 242 243 /* additional type 2 device config header information (CardBus bridge) */ 244 245 typedef struct { 246 uint32_t membase0; /* base address of memory window */ 247 uint32_t memlimit0; /* topmost address of memory window */ 248 uint32_t membase1; /* base address of memory window */ 249 uint32_t memlimit1; /* topmost address of memory window */ 250 uint32_t iobase0; /* base address of port window */ 251 uint32_t iolimit0; /* topmost address of port window */ 252 uint32_t iobase1; /* base address of port window */ 253 uint32_t iolimit1; /* topmost address of port window */ 254 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 255 uint16_t secstat; /* secondary bus status register */ 256 uint16_t bridgectl; /* bridge control register */ 257 uint8_t seclat; /* CardBus latency timer */ 258 } pcih2cfgregs; 259 260 extern uint32_t pci_numdevs; 261 extern int pci_enable_aspm; 262 263 /* 264 * The bitfield has to be stable and match the fields below (so that 265 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't 266 * use enums or #define constants because then the macros for subsetting matches 267 * wouldn't work. These tables are parsed by devmatch and others to connect 268 * modules with devices on the PCI bus. 269 */ 270 struct pci_device_table { 271 #if BYTE_ORDER == LITTLE_ENDIAN 272 uint16_t 273 match_flag_vendor:1, 274 match_flag_device:1, 275 match_flag_subvendor:1, 276 match_flag_subdevice:1, 277 match_flag_class:1, 278 match_flag_subclass:1, 279 match_flag_revid:1, 280 match_flag_unused:9; 281 #else 282 uint16_t 283 match_flag_unused:9, 284 match_flag_revid:1, 285 match_flag_subclass:1, 286 match_flag_class:1, 287 match_flag_subdevice:1, 288 match_flag_subvendor:1, 289 match_flag_device:1, 290 match_flag_vendor:1; 291 #endif 292 uint16_t vendor; 293 uint16_t device; 294 uint16_t subvendor; 295 uint16_t subdevice; 296 uint16_t class_id; 297 uint16_t subclass; 298 uint16_t revid; 299 uint16_t unused; 300 uintptr_t driver_data; 301 char *descr; 302 }; 303 304 #define PCI_DEV(v, d) \ 305 .match_flag_vendor = 1, .vendor = (v), \ 306 .match_flag_device = 1, .device = (d) 307 #define PCI_SUBDEV(sv, sd) \ 308 .match_flag_subvendor = 1, .subvendor = (sv), \ 309 .match_flag_subdevice = 1, .subdevice = (sd) 310 #define PCI_CLASS(x) \ 311 .match_flag_class = 1, .class_id = (x) 312 #define PCI_SUBCLASS(x) \ 313 .match_flag_subclass = 1, .subclass = (x) 314 #define PCI_REVID(x) \ 315 .match_flag_revid = 1, .revid = (x) 316 #define PCI_DESCR(x) \ 317 .descr = (x) 318 #define PCI_PNP_STR \ 319 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \ 320 "U16:class;U16:subclass;U16:revid;" 321 #define PCI_PNP_INFO(table) \ 322 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \ 323 sizeof(table) / sizeof(table[0])) 324 325 const struct pci_device_table *pci_match_device(device_t child, 326 const struct pci_device_table *id, size_t nelt); 327 #define PCI_MATCH(child, table) \ 328 pci_match_device(child, (table), nitems(table)); 329 330 /* Only if the prerequisites are present */ 331 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 332 struct pci_devinfo { 333 STAILQ_ENTRY(pci_devinfo) pci_links; 334 struct resource_list resources; 335 pcicfgregs cfg; 336 struct pci_conf conf; 337 }; 338 #endif 339 340 #ifdef _SYS_BUS_H_ 341 342 #include "pci_if.h" 343 344 enum pci_device_ivars { 345 PCI_IVAR_SUBVENDOR, 346 PCI_IVAR_SUBDEVICE, 347 PCI_IVAR_VENDOR, 348 PCI_IVAR_DEVICE, 349 PCI_IVAR_DEVID, 350 PCI_IVAR_CLASS, 351 PCI_IVAR_SUBCLASS, 352 PCI_IVAR_PROGIF, 353 PCI_IVAR_REVID, 354 PCI_IVAR_INTPIN, 355 PCI_IVAR_IRQ, 356 PCI_IVAR_DOMAIN, 357 PCI_IVAR_BUS, 358 PCI_IVAR_SLOT, 359 PCI_IVAR_FUNCTION, 360 PCI_IVAR_ETHADDR, 361 PCI_IVAR_CMDREG, 362 PCI_IVAR_CACHELNSZ, 363 PCI_IVAR_MINGNT, 364 PCI_IVAR_MAXLAT, 365 PCI_IVAR_LATTIMER 366 }; 367 368 /* 369 * Simplified accessors for pci devices 370 */ 371 #define PCI_ACCESSOR(var, ivar, type) \ 372 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 373 374 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 375 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 376 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 377 PCI_ACCESSOR(device, DEVICE, uint16_t) 378 PCI_ACCESSOR(devid, DEVID, uint32_t) 379 PCI_ACCESSOR(class, CLASS, uint8_t) 380 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 381 PCI_ACCESSOR(progif, PROGIF, uint8_t) 382 PCI_ACCESSOR(revid, REVID, uint8_t) 383 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 384 PCI_ACCESSOR(irq, IRQ, uint8_t) 385 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 386 PCI_ACCESSOR(bus, BUS, uint8_t) 387 PCI_ACCESSOR(slot, SLOT, uint8_t) 388 PCI_ACCESSOR(function, FUNCTION, uint8_t) 389 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 390 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 391 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 392 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 393 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 394 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 395 396 #undef PCI_ACCESSOR 397 398 /* 399 * Operations on configuration space. 400 */ 401 static __inline uint32_t 402 pci_read_config(device_t dev, int reg, int width) 403 { 404 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 405 } 406 407 static __inline void 408 pci_write_config(device_t dev, int reg, uint32_t val, int width) 409 { 410 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 411 } 412 413 /* 414 * Ivars for pci bridges. 415 */ 416 417 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 418 enum pcib_device_ivars { 419 PCIB_IVAR_DOMAIN, 420 PCIB_IVAR_BUS 421 }; 422 423 #define PCIB_ACCESSOR(var, ivar, type) \ 424 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 425 426 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 427 PCIB_ACCESSOR(bus, BUS, uint32_t) 428 429 #undef PCIB_ACCESSOR 430 431 /* 432 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 433 * on i386 or other platforms should be mapped out in the MD pcireadconf 434 * code and not here, since the only MI invalid IRQ is 255. 435 */ 436 #define PCI_INVALID_IRQ 255 437 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 438 439 /* 440 * Convenience functions. 441 * 442 * These should be used in preference to manually manipulating 443 * configuration space. 444 */ 445 static __inline int 446 pci_enable_busmaster(device_t dev) 447 { 448 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 449 } 450 451 static __inline int 452 pci_disable_busmaster(device_t dev) 453 { 454 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 455 } 456 457 static __inline int 458 pci_enable_io(device_t dev, int space) 459 { 460 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 461 } 462 463 static __inline int 464 pci_disable_io(device_t dev, int space) 465 { 466 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 467 } 468 469 static __inline int 470 pci_get_vpd_ident(device_t dev, const char **identptr) 471 { 472 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 473 } 474 475 static __inline int 476 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 477 { 478 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 479 } 480 481 /* 482 * Check if the address range falls within the VGA defined address range(s) 483 */ 484 static __inline int 485 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end) 486 { 487 488 return (((start >= 0x3b0 && end <= 0x3bb) || 489 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 490 } 491 492 static __inline int 493 pci_is_vga_memory_range(rman_res_t start, rman_res_t end) 494 { 495 496 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 497 } 498 499 /* 500 * PCI power states are as defined by ACPI: 501 * 502 * D0 State in which device is on and running. It is receiving full 503 * power from the system and delivering full functionality to the user. 504 * D1 Class-specific low-power state in which device context may or may not 505 * be lost. Buses in D1 cannot do anything to the bus that would force 506 * devices on that bus to lose context. 507 * D2 Class-specific low-power state in which device context may or may 508 * not be lost. Attains greater power savings than D1. Buses in D2 509 * can cause devices on that bus to lose some context. Devices in D2 510 * must be prepared for the bus to be in D2 or higher. 511 * D3 State in which the device is off and not running. Device context is 512 * lost. Power can be removed from the device. 513 */ 514 #define PCI_POWERSTATE_D0 0 515 #define PCI_POWERSTATE_D1 1 516 #define PCI_POWERSTATE_D2 2 517 #define PCI_POWERSTATE_D3 3 518 #define PCI_POWERSTATE_UNKNOWN -1 519 520 static __inline int 521 pci_set_powerstate(device_t dev, int state) 522 { 523 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 524 } 525 526 static __inline int 527 pci_get_powerstate(device_t dev) 528 { 529 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 530 } 531 532 static __inline int 533 pci_find_cap(device_t dev, int capability, int *capreg) 534 { 535 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 536 } 537 538 static __inline int 539 pci_find_next_cap(device_t dev, int capability, int start, int *capreg) 540 { 541 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start, 542 capreg)); 543 } 544 545 static __inline int 546 pci_find_extcap(device_t dev, int capability, int *capreg) 547 { 548 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 549 } 550 551 static __inline int 552 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg) 553 { 554 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability, 555 start, capreg)); 556 } 557 558 static __inline int 559 pci_find_htcap(device_t dev, int capability, int *capreg) 560 { 561 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 562 } 563 564 static __inline int 565 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg) 566 { 567 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability, 568 start, capreg)); 569 } 570 571 static __inline int 572 pci_alloc_msi(device_t dev, int *count) 573 { 574 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 575 } 576 577 static __inline int 578 pci_alloc_msix(device_t dev, int *count) 579 { 580 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 581 } 582 583 static __inline void 584 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 585 { 586 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 587 } 588 589 static __inline void 590 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 591 { 592 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 593 } 594 595 static __inline void 596 pci_disable_msi(device_t dev) 597 { 598 PCI_DISABLE_MSI(device_get_parent(dev), dev); 599 } 600 601 static __inline int 602 pci_remap_msix(device_t dev, int count, const u_int *vectors) 603 { 604 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 605 } 606 607 static __inline int 608 pci_release_msi(device_t dev) 609 { 610 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 611 } 612 613 static __inline int 614 pci_msi_count(device_t dev) 615 { 616 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 617 } 618 619 static __inline int 620 pci_msix_count(device_t dev) 621 { 622 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 623 } 624 625 static __inline int 626 pci_msix_pba_bar(device_t dev) 627 { 628 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev)); 629 } 630 631 static __inline int 632 pci_msix_table_bar(device_t dev) 633 { 634 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev)); 635 } 636 637 static __inline int 638 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id) 639 { 640 return (PCI_GET_ID(device_get_parent(dev), dev, type, id)); 641 } 642 643 /* 644 * This is the deprecated interface, there is no way to tell the difference 645 * between a failure and a valid value that happens to be the same as the 646 * failure value. 647 */ 648 static __inline uint16_t 649 pci_get_rid(device_t dev) 650 { 651 uintptr_t rid; 652 653 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0) 654 return (0); 655 656 return (rid); 657 } 658 659 static __inline void 660 pci_child_added(device_t dev) 661 { 662 663 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 664 } 665 666 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 667 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 668 device_t pci_find_device(uint16_t, uint16_t); 669 device_t pci_find_class(uint8_t class, uint8_t subclass); 670 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom); 671 device_t pci_find_base_class_from(uint8_t class, device_t devfrom); 672 673 /* Can be used by drivers to manage the MSI-X table. */ 674 int pci_pending_msix(device_t dev, u_int index); 675 676 int pci_msi_device_blacklisted(device_t dev); 677 int pci_msix_device_blacklisted(device_t dev); 678 679 void pci_ht_map_msi(device_t dev, uint64_t addr); 680 681 device_t pci_find_pcie_root_port(device_t dev); 682 int pci_get_relaxed_ordering_enabled(device_t dev); 683 int pci_get_max_payload(device_t dev); 684 int pci_get_max_read_req(device_t dev); 685 void pci_restore_state(device_t dev); 686 void pci_save_state(device_t dev); 687 int pci_set_max_read_req(device_t dev, int size); 688 int pci_power_reset(device_t dev); 689 uint32_t pcie_read_config(device_t dev, int reg, int width); 690 void pcie_write_config(device_t dev, int reg, uint32_t value, int width); 691 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask, 692 uint32_t value, int width); 693 void pcie_apei_error(device_t dev, int sev, uint8_t *aer); 694 bool pcie_flr(device_t dev, u_int max_delay, bool force); 695 int pcie_get_max_completion_timeout(device_t dev); 696 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay); 697 int pcie_link_reset(device_t port, int pcie_location); 698 699 void pci_print_faulted_dev(void); 700 701 #endif /* _SYS_BUS_H_ */ 702 703 /* 704 * cdev switch for control device, initialised in generic PCI code 705 */ 706 extern struct cdevsw pcicdev; 707 708 /* 709 * List of all PCI devices, generation count for the list. 710 */ 711 STAILQ_HEAD(devlist, pci_devinfo); 712 713 extern struct devlist pci_devq; 714 extern uint32_t pci_generation; 715 716 struct pci_map *pci_find_bar(device_t dev, int reg); 717 struct pci_map *pci_first_bar(device_t dev); 718 struct pci_map *pci_next_bar(struct pci_map *pm); 719 int pci_bar_enabled(device_t dev, struct pci_map *pm); 720 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 721 722 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 723 #define VGA_PCI_BIOS_SHADOW_SIZE 131072 724 725 int vga_pci_is_boot_display(device_t dev); 726 void * vga_pci_map_bios(device_t dev, size_t *size); 727 void vga_pci_unmap_bios(device_t dev, void *bios); 728 int vga_pci_repost(device_t dev); 729 730 /** 731 * Global eventhandlers invoked when PCI devices are added or removed 732 * from the system. 733 */ 734 typedef void (*pci_event_fn)(void *arg, device_t dev); 735 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn); 736 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn); 737 738 #endif /* _PCIVAR_H_ */ 739