1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #ifndef PCI_COMPAT 34 #define PCI_COMPAT 35 #endif 36 37 #include <pci/pci_ioctl.h> /* XXX KDM */ 38 #include <sys/queue.h> 39 40 /* some PCI bus constants */ 41 42 #define PCI_BUSMAX 255 /* highest supported bus number */ 43 #define PCI_SLOTMAX 31 /* highest supported slot number */ 44 #define PCI_FUNCMAX 7 /* highest supported function number */ 45 #define PCI_REGMAX 255 /* highest supported config register addr. */ 46 47 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 48 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 49 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 50 51 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 52 53 #ifdef PCI_A64 54 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 55 #else 56 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 57 #endif 58 59 /* config header information common to all header types */ 60 61 typedef struct pcicfg { 62 struct device *dev; /* device which owns this */ 63 void *hdrspec; /* pointer to header type specific data */ 64 65 u_int16_t subvendor; /* card vendor ID */ 66 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 67 u_int16_t vendor; /* chip vendor ID */ 68 u_int16_t device; /* chip device ID, assigned by chip vendor */ 69 70 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 71 u_int16_t statreg; /* supported PCI features and error state */ 72 73 u_int8_t baseclass; /* chip PCI class */ 74 u_int8_t subclass; /* chip PCI subclass */ 75 u_int8_t progif; /* chip PCI programming interface */ 76 u_int8_t revid; /* chip revision ID */ 77 78 u_int8_t hdrtype; /* chip config header type */ 79 u_int8_t cachelnsz; /* cache line size in 4byte units */ 80 u_int8_t intpin; /* PCI interrupt pin */ 81 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 82 83 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 84 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 85 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 86 87 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 88 u_int8_t nummaps; /* actual number of PCI maps used */ 89 90 u_int8_t hose; /* hose which bus is attached to */ 91 u_int8_t bus; /* config space bus address */ 92 u_int8_t slot; /* config space slot address */ 93 u_int8_t func; /* config space function number */ 94 95 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 96 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 97 } pcicfgregs; 98 99 /* additional type 1 device config header information (PCI to PCI bridge) */ 100 101 #ifdef PCI_A64 102 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 103 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 104 #else 105 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 106 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 107 #endif /* PCI_A64 */ 108 109 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 110 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 111 112 typedef struct { 113 pci_addr_t pmembase; /* base address of prefetchable memory */ 114 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 115 u_int32_t membase; /* base address of memory window */ 116 u_int32_t memlimit; /* topmost address of memory window */ 117 u_int32_t iobase; /* base address of port window */ 118 u_int32_t iolimit; /* topmost address of port window */ 119 u_int16_t secstat; /* secondary bus status register */ 120 u_int16_t bridgectl; /* bridge control register */ 121 u_int8_t seclat; /* CardBus latency timer */ 122 } pcih1cfgregs; 123 124 /* additional type 2 device config header information (CardBus bridge) */ 125 126 typedef struct { 127 u_int32_t membase0; /* base address of memory window */ 128 u_int32_t memlimit0; /* topmost address of memory window */ 129 u_int32_t membase1; /* base address of memory window */ 130 u_int32_t memlimit1; /* topmost address of memory window */ 131 u_int32_t iobase0; /* base address of port window */ 132 u_int32_t iolimit0; /* topmost address of port window */ 133 u_int32_t iobase1; /* base address of port window */ 134 u_int32_t iolimit1; /* topmost address of port window */ 135 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 136 u_int16_t secstat; /* secondary bus status register */ 137 u_int16_t bridgectl; /* bridge control register */ 138 u_int8_t seclat; /* CardBus latency timer */ 139 } pcih2cfgregs; 140 141 /* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 142 143 typedef struct pciattach { 144 int unit; 145 int pcibushigh; 146 struct pciattach *next; 147 } pciattach; 148 149 extern u_int32_t pci_numdevs; 150 151 152 /* externally visible functions */ 153 154 const char *ide_pci_match(struct device *dev); 155 156 /* low level PCI config register functions provided by pcibus.c */ 157 158 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 159 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 160 #ifdef __alpha__ 161 vm_offset_t pci_cvt_to_dense (vm_offset_t); 162 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 163 #endif /* __alpha__ */ 164 165 /* low level devlist operations for the 2.2 compatibility code in pci.c */ 166 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 167 168 #ifdef _SYS_BUS_H_ 169 170 #include "pci_if.h" 171 172 /* 173 * Define pci-specific resource flags for accessing memory via dense 174 * or bwx memory spaces. These flags are ignored on i386. 175 */ 176 #define PCI_RF_DENSE 0x10000 177 #define PCI_RF_BWX 0x20000 178 179 enum pci_device_ivars { 180 PCI_IVAR_SUBVENDOR, 181 PCI_IVAR_SUBDEVICE, 182 PCI_IVAR_VENDOR, 183 PCI_IVAR_DEVICE, 184 PCI_IVAR_DEVID, 185 PCI_IVAR_CLASS, 186 PCI_IVAR_SUBCLASS, 187 PCI_IVAR_PROGIF, 188 PCI_IVAR_REVID, 189 PCI_IVAR_INTPIN, 190 PCI_IVAR_IRQ, 191 PCI_IVAR_BUS, 192 PCI_IVAR_SLOT, 193 PCI_IVAR_FUNCTION, 194 PCI_IVAR_SECONDARYBUS, 195 PCI_IVAR_SUBORDINATEBUS, 196 PCI_IVAR_HOSE, 197 }; 198 199 /* 200 * Simplified accessors for pci devices 201 */ 202 #define PCI_ACCESSOR(A, B, T) \ 203 \ 204 static __inline T pci_get_ ## A(device_t dev) \ 205 { \ 206 uintptr_t v; \ 207 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 208 return (T) v; \ 209 } \ 210 \ 211 static __inline void pci_set_ ## A(device_t dev, T t) \ 212 { \ 213 u_long v = (u_long) t; \ 214 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 215 } 216 217 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 218 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 219 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 220 PCI_ACCESSOR(device, DEVICE, u_int16_t) 221 PCI_ACCESSOR(devid, DEVID, u_int32_t) 222 PCI_ACCESSOR(class, CLASS, u_int8_t) 223 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 224 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 225 PCI_ACCESSOR(revid, REVID, u_int8_t) 226 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 227 PCI_ACCESSOR(irq, IRQ, u_int8_t) 228 PCI_ACCESSOR(bus, BUS, u_int8_t) 229 PCI_ACCESSOR(slot, SLOT, u_int8_t) 230 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 231 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 232 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 233 PCI_ACCESSOR(hose, HOSE, u_int32_t) 234 235 static __inline u_int32_t 236 pci_read_config(device_t dev, int reg, int width) 237 { 238 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 239 } 240 241 static __inline void 242 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 243 { 244 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 245 } 246 247 /* 248 * Ivars for pci bridges. 249 */ 250 251 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 252 enum pcib_device_ivars { 253 PCIB_IVAR_HOSE, 254 }; 255 256 #define PCIB_ACCESSOR(A, B, T) \ 257 \ 258 static __inline T pcib_get_ ## A(device_t dev) \ 259 { \ 260 uintptr_t v; \ 261 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 262 return (T) v; \ 263 } \ 264 \ 265 static __inline void pcib_set_ ## A(device_t dev, T t) \ 266 { \ 267 u_long v = (u_long) t; \ 268 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 269 } 270 271 PCIB_ACCESSOR(hose, HOSE, u_int32_t) 272 273 #endif 274 275 /* for compatibility to FreeBSD-2.2 version of PCI code */ 276 277 #ifdef PCI_COMPAT 278 279 typedef pcicfgregs *pcici_t; 280 typedef unsigned pcidi_t; 281 typedef void pci_inthand_t(void *arg); 282 283 #define pci_max_burst_len (3) 284 285 /* just copied from old PCI code for now ... */ 286 287 extern int pci_mechanism; 288 289 struct pci_device { 290 char* pd_name; 291 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 292 void (*pd_attach) (pcici_t tag, int unit); 293 u_long *pd_count; 294 int (*pd_shutdown) (int, int); 295 }; 296 297 #ifdef __i386__ 298 typedef u_short pci_port_t; 299 #else 300 typedef u_int pci_port_t; 301 #endif 302 303 u_long pci_conf_read (pcici_t tag, u_long reg); 304 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 305 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 306 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 307 int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 308 int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 309 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 310 intrmask_t *maskptr); 311 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 312 intrmask_t *maskptr, u_int flags); 313 int pci_unmap_int (pcici_t tag); 314 315 pcici_t pci_get_parent_from_tag(pcici_t tag); 316 int pci_get_bus_from_tag(pcici_t tag); 317 318 struct module; 319 int compat_pci_handler (struct module *, int, void *); 320 #define COMPAT_PCI_DRIVER(name, pcidata) \ 321 static moduledata_t name##_mod = { \ 322 #name, \ 323 compat_pci_handler, \ 324 &pcidata \ 325 }; \ 326 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 327 328 329 #endif /* PCI_COMPAT */ 330 #endif /* _PCIVAR_H_ */ 331