1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pcivar.h,v 1.22 1998/10/06 14:18:40 dfr Exp $ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #ifndef PCI_COMPAT 34 #define PCI_COMPAT 35 #endif 36 37 #include <pci/pci_ioctl.h> /* XXX KDM */ 38 #include <sys/queue.h> 39 40 /* some PCI bus constants */ 41 42 #define PCI_BUSMAX 255 /* highest supported bus number */ 43 #define PCI_SLOTMAX 31 /* highest supported slot number */ 44 #define PCI_FUNCMAX 7 /* highest supported function number */ 45 #define PCI_REGMAX 255 /* highest supported config register addr. */ 46 47 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 48 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 49 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 50 51 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 52 53 #ifdef PCI_A64 54 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 55 #else 56 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 57 #endif 58 59 /* map register information */ 60 61 typedef struct { 62 u_int32_t base; 63 u_int8_t type; 64 #define PCI_MAPMEM 0x01 /* memory map */ 65 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 66 #define PCI_MAPPORT 0x04 /* port map */ 67 u_int8_t ln2size; 68 u_int8_t ln2range; 69 /* u_int8_t dummy;*/ 70 } pcimap; 71 72 /* config header information common to all header types */ 73 74 typedef struct pcicfg { 75 pcimap *map; /* pointer to array of PCI maps */ 76 void *hdrspec; /* pointer to header type specific data */ 77 78 u_int16_t subvendor; /* card vendor ID */ 79 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 80 u_int16_t vendor; /* chip vendor ID */ 81 u_int16_t device; /* chip device ID, assigned by chip vendor */ 82 83 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 84 u_int16_t statreg; /* supported PCI features and error state */ 85 86 u_int8_t baseclass; /* chip PCI class */ 87 u_int8_t subclass; /* chip PCI subclass */ 88 u_int8_t progif; /* chip PCI programming interface */ 89 u_int8_t revid; /* chip revision ID */ 90 91 u_int8_t hdrtype; /* chip config header type */ 92 u_int8_t cachelnsz; /* cache line size in 4byte units */ 93 u_int8_t intpin; /* PCI interrupt pin */ 94 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 95 96 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 97 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 98 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 99 100 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 101 u_int8_t nummaps; /* actual number of PCI maps used */ 102 103 u_int8_t bus; /* config space bus address */ 104 u_int8_t slot; /* config space slot address */ 105 u_int8_t func; /* config space function number */ 106 107 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 108 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 109 } pcicfgregs; 110 111 /* additional type 1 device config header information (PCI to PCI bridge) */ 112 113 #ifdef PCI_A64 114 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 115 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 116 #else 117 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 118 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 119 #endif /* PCI_A64 */ 120 121 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 122 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 123 124 typedef struct { 125 pci_addr_t pmembase; /* base address of prefetchable memory */ 126 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 127 u_int32_t membase; /* base address of memory window */ 128 u_int32_t memlimit; /* topmost address of memory window */ 129 u_int32_t iobase; /* base address of port window */ 130 u_int32_t iolimit; /* topmost address of port window */ 131 u_int16_t secstat; /* secondary bus status register */ 132 u_int16_t bridgectl; /* bridge control register */ 133 u_int8_t seclat; /* CardBus latency timer */ 134 } pcih1cfgregs; 135 136 /* additional type 2 device config header information (CardBus bridge) */ 137 138 typedef struct { 139 u_int32_t membase0; /* base address of memory window */ 140 u_int32_t memlimit0; /* topmost address of memory window */ 141 u_int32_t membase1; /* base address of memory window */ 142 u_int32_t memlimit1; /* topmost address of memory window */ 143 u_int32_t iobase0; /* base address of port window */ 144 u_int32_t iolimit0; /* topmost address of port window */ 145 u_int32_t iobase1; /* base address of port window */ 146 u_int32_t iolimit1; /* topmost address of port window */ 147 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 148 u_int16_t secstat; /* secondary bus status register */ 149 u_int16_t bridgectl; /* bridge control register */ 150 u_int8_t seclat; /* CardBus latency timer */ 151 } pcih2cfgregs; 152 153 /* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 154 155 typedef struct pciattach { 156 int unit; 157 int pcibushigh; 158 struct pciattach *next; 159 } pciattach; 160 161 struct pci_devinfo { 162 STAILQ_ENTRY(pci_devinfo) pci_links; 163 struct pci_device *device; /* should this be ifdefed? */ 164 pcicfgregs cfg; 165 struct pci_conf conf; 166 }; 167 168 extern u_int32_t pci_numdevs; 169 170 171 /* externally visible functions */ 172 173 int pci_probe (pciattach *attach); 174 void pci_drvattach(struct pci_devinfo *dinfo); 175 176 /* low level PCI config register functions provided by pcibus.c */ 177 178 int pci_cfgopen (void); 179 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 180 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 181 #ifdef __alpha__ 182 vm_offset_t pci_cvt_to_dense (vm_offset_t); 183 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 184 #endif /* __alpha__ */ 185 /* for compatibility to FreeBSD-2.2 version of PCI code */ 186 187 #ifdef PCI_COMPAT 188 189 typedef pcicfgregs *pcici_t; 190 typedef unsigned pcidi_t; 191 typedef void pci_inthand_t(void *arg); 192 193 #define pci_max_burst_len (3) 194 195 /* just copied from old PCI code for now ... */ 196 197 extern struct linker_set pcidevice_set; 198 extern int pci_mechanism; 199 200 struct pci_device { 201 char* pd_name; 202 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 203 void (*pd_attach) (pcici_t tag, int unit); 204 u_long *pd_count; 205 int (*pd_shutdown) (int, int); 206 }; 207 208 struct pci_lkm { 209 struct pci_device *dvp; 210 struct pci_lkm *next; 211 }; 212 213 #ifdef __i386__ 214 typedef u_short pci_port_t; 215 #else 216 typedef u_int pci_port_t; 217 #endif 218 219 u_long pci_conf_read (pcici_t tag, u_long reg); 220 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 221 void pci_configure (void); 222 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 223 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 224 int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 225 int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 226 int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); 227 int pci_unmap_int (pcici_t tag); 228 int pci_register_lkm (struct pci_device *dvp, int if_revision); 229 230 #endif /* PCI_COMPAT */ 231 #endif /* _PCIVAR_H_ */ 232