1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #include <sys/queue.h> 34 35 /* some PCI bus constants */ 36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40 typedef uint64_t pci_addr_t; 41 42 struct nvlist; 43 44 /* Interesting values for PCI power management */ 45 struct pcicfg_pp { 46 uint16_t pp_cap; /* PCI power management capabilities */ 47 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 48 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 49 uint8_t pp_data; /* conf. space addr. of PM data reg */ 50 }; 51 52 struct pci_map { 53 pci_addr_t pm_value; /* Raw BAR value */ 54 pci_addr_t pm_size; 55 uint16_t pm_reg; 56 STAILQ_ENTRY(pci_map) pm_link; 57 }; 58 59 struct vpd_readonly { 60 char keyword[2]; 61 char *value; 62 int len; 63 }; 64 65 struct vpd_write { 66 char keyword[2]; 67 char *value; 68 int start; 69 int len; 70 }; 71 72 struct pcicfg_vpd { 73 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 74 char vpd_cached; 75 char *vpd_ident; /* string identifier */ 76 int vpd_rocnt; 77 struct vpd_readonly *vpd_ros; 78 int vpd_wcnt; 79 struct vpd_write *vpd_w; 80 }; 81 82 /* Interesting values for PCI MSI */ 83 struct pcicfg_msi { 84 uint16_t msi_ctrl; /* Message Control */ 85 uint8_t msi_location; /* Offset of MSI capability registers. */ 86 uint8_t msi_msgnum; /* Number of messages */ 87 int msi_alloc; /* Number of allocated messages. */ 88 uint64_t msi_addr; /* Contents of address register. */ 89 uint16_t msi_data; /* Contents of data register. */ 90 u_int msi_handlers; 91 }; 92 93 /* Interesting values for PCI MSI-X */ 94 struct msix_vector { 95 uint64_t mv_address; /* Contents of address register. */ 96 uint32_t mv_data; /* Contents of data register. */ 97 int mv_irq; 98 }; 99 100 struct msix_table_entry { 101 u_int mte_vector; /* 1-based index into msix_vectors array. */ 102 u_int mte_handlers; 103 }; 104 105 struct pcicfg_msix { 106 uint16_t msix_ctrl; /* Message Control */ 107 uint16_t msix_msgnum; /* Number of messages */ 108 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 109 uint8_t msix_table_bar; /* BAR containing vector table. */ 110 uint8_t msix_pba_bar; /* BAR containing PBA. */ 111 uint32_t msix_table_offset; 112 uint32_t msix_pba_offset; 113 int msix_alloc; /* Number of allocated vectors. */ 114 int msix_table_len; /* Length of virtual table. */ 115 struct msix_table_entry *msix_table; /* Virtual table. */ 116 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 117 struct resource *msix_table_res; /* Resource containing vector table. */ 118 struct resource *msix_pba_res; /* Resource containing PBA. */ 119 }; 120 121 /* Interesting values for HyperTransport */ 122 struct pcicfg_ht { 123 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 124 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 125 uint16_t ht_msictrl; /* MSI mapping control */ 126 uint64_t ht_msiaddr; /* MSI mapping base address */ 127 }; 128 129 /* Interesting values for PCI-express */ 130 struct pcicfg_pcie { 131 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 132 uint8_t pcie_type; /* Device type. */ 133 uint16_t pcie_flags; /* Device capabilities register. */ 134 uint16_t pcie_device_ctl; /* Device control register. */ 135 uint16_t pcie_link_ctl; /* Link control register. */ 136 uint16_t pcie_slot_ctl; /* Slot control register. */ 137 uint16_t pcie_root_ctl; /* Root control register. */ 138 uint16_t pcie_device_ctl2; /* Second device control register. */ 139 uint16_t pcie_link_ctl2; /* Second link control register. */ 140 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 141 }; 142 143 struct pcicfg_pcix { 144 uint16_t pcix_command; 145 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 146 }; 147 148 struct pcicfg_vf { 149 int index; 150 }; 151 152 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 153 154 /* config header information common to all header types */ 155 typedef struct pcicfg { 156 struct device *dev; /* device which owns this */ 157 158 STAILQ_HEAD(, pci_map) maps; /* BARs */ 159 160 uint16_t subvendor; /* card vendor ID */ 161 uint16_t subdevice; /* card device ID, assigned by card vendor */ 162 uint16_t vendor; /* chip vendor ID */ 163 uint16_t device; /* chip device ID, assigned by chip vendor */ 164 165 uint16_t cmdreg; /* disable/enable chip and PCI options */ 166 uint16_t statreg; /* supported PCI features and error state */ 167 168 uint8_t baseclass; /* chip PCI class */ 169 uint8_t subclass; /* chip PCI subclass */ 170 uint8_t progif; /* chip PCI programming interface */ 171 uint8_t revid; /* chip revision ID */ 172 173 uint8_t hdrtype; /* chip config header type */ 174 uint8_t cachelnsz; /* cache line size in 4byte units */ 175 uint8_t intpin; /* PCI interrupt pin */ 176 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 177 178 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 179 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 180 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 181 182 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 183 uint8_t nummaps; /* actual number of PCI maps used */ 184 185 uint32_t domain; /* PCI domain */ 186 uint8_t bus; /* config space bus address */ 187 uint8_t slot; /* config space slot address */ 188 uint8_t func; /* config space function number */ 189 190 uint32_t flags; /* flags defined above */ 191 size_t devinfo_size; /* Size of devinfo for this bus type. */ 192 193 struct pcicfg_pp pp; /* Power management */ 194 struct pcicfg_vpd vpd; /* Vital product data */ 195 struct pcicfg_msi msi; /* PCI MSI */ 196 struct pcicfg_msix msix; /* PCI MSI-X */ 197 struct pcicfg_ht ht; /* HyperTransport */ 198 struct pcicfg_pcie pcie; /* PCI Express */ 199 struct pcicfg_pcix pcix; /* PCI-X */ 200 struct pcicfg_iov *iov; /* SR-IOV */ 201 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 202 } pcicfgregs; 203 204 /* additional type 1 device config header information (PCI to PCI bridge) */ 205 206 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 207 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 208 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 209 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 210 211 typedef struct { 212 pci_addr_t pmembase; /* base address of prefetchable memory */ 213 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 214 uint32_t membase; /* base address of memory window */ 215 uint32_t memlimit; /* topmost address of memory window */ 216 uint32_t iobase; /* base address of port window */ 217 uint32_t iolimit; /* topmost address of port window */ 218 uint16_t secstat; /* secondary bus status register */ 219 uint16_t bridgectl; /* bridge control register */ 220 uint8_t seclat; /* CardBus latency timer */ 221 } pcih1cfgregs; 222 223 /* additional type 2 device config header information (CardBus bridge) */ 224 225 typedef struct { 226 uint32_t membase0; /* base address of memory window */ 227 uint32_t memlimit0; /* topmost address of memory window */ 228 uint32_t membase1; /* base address of memory window */ 229 uint32_t memlimit1; /* topmost address of memory window */ 230 uint32_t iobase0; /* base address of port window */ 231 uint32_t iolimit0; /* topmost address of port window */ 232 uint32_t iobase1; /* base address of port window */ 233 uint32_t iolimit1; /* topmost address of port window */ 234 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 235 uint16_t secstat; /* secondary bus status register */ 236 uint16_t bridgectl; /* bridge control register */ 237 uint8_t seclat; /* CardBus latency timer */ 238 } pcih2cfgregs; 239 240 extern uint32_t pci_numdevs; 241 242 /* Only if the prerequisites are present */ 243 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 244 struct pci_devinfo { 245 STAILQ_ENTRY(pci_devinfo) pci_links; 246 struct resource_list resources; 247 pcicfgregs cfg; 248 struct pci_conf conf; 249 }; 250 #endif 251 252 #ifdef _SYS_BUS_H_ 253 254 #include "pci_if.h" 255 256 enum pci_device_ivars { 257 PCI_IVAR_SUBVENDOR, 258 PCI_IVAR_SUBDEVICE, 259 PCI_IVAR_VENDOR, 260 PCI_IVAR_DEVICE, 261 PCI_IVAR_DEVID, 262 PCI_IVAR_CLASS, 263 PCI_IVAR_SUBCLASS, 264 PCI_IVAR_PROGIF, 265 PCI_IVAR_REVID, 266 PCI_IVAR_INTPIN, 267 PCI_IVAR_IRQ, 268 PCI_IVAR_DOMAIN, 269 PCI_IVAR_BUS, 270 PCI_IVAR_SLOT, 271 PCI_IVAR_FUNCTION, 272 PCI_IVAR_ETHADDR, 273 PCI_IVAR_CMDREG, 274 PCI_IVAR_CACHELNSZ, 275 PCI_IVAR_MINGNT, 276 PCI_IVAR_MAXLAT, 277 PCI_IVAR_LATTIMER 278 }; 279 280 /* 281 * Simplified accessors for pci devices 282 */ 283 #define PCI_ACCESSOR(var, ivar, type) \ 284 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 285 286 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 287 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 288 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 289 PCI_ACCESSOR(device, DEVICE, uint16_t) 290 PCI_ACCESSOR(devid, DEVID, uint32_t) 291 PCI_ACCESSOR(class, CLASS, uint8_t) 292 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 293 PCI_ACCESSOR(progif, PROGIF, uint8_t) 294 PCI_ACCESSOR(revid, REVID, uint8_t) 295 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 296 PCI_ACCESSOR(irq, IRQ, uint8_t) 297 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 298 PCI_ACCESSOR(bus, BUS, uint8_t) 299 PCI_ACCESSOR(slot, SLOT, uint8_t) 300 PCI_ACCESSOR(function, FUNCTION, uint8_t) 301 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 302 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 303 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 304 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 305 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 306 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 307 308 #undef PCI_ACCESSOR 309 310 /* 311 * Operations on configuration space. 312 */ 313 static __inline uint32_t 314 pci_read_config(device_t dev, int reg, int width) 315 { 316 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 317 } 318 319 static __inline void 320 pci_write_config(device_t dev, int reg, uint32_t val, int width) 321 { 322 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 323 } 324 325 /* 326 * Ivars for pci bridges. 327 */ 328 329 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 330 enum pcib_device_ivars { 331 PCIB_IVAR_DOMAIN, 332 PCIB_IVAR_BUS 333 }; 334 335 #define PCIB_ACCESSOR(var, ivar, type) \ 336 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 337 338 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 339 PCIB_ACCESSOR(bus, BUS, uint32_t) 340 341 #undef PCIB_ACCESSOR 342 343 /* 344 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 345 * on i386 or other platforms should be mapped out in the MD pcireadconf 346 * code and not here, since the only MI invalid IRQ is 255. 347 */ 348 #define PCI_INVALID_IRQ 255 349 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 350 351 /* 352 * Convenience functions. 353 * 354 * These should be used in preference to manually manipulating 355 * configuration space. 356 */ 357 static __inline int 358 pci_enable_busmaster(device_t dev) 359 { 360 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 361 } 362 363 static __inline int 364 pci_disable_busmaster(device_t dev) 365 { 366 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 367 } 368 369 static __inline int 370 pci_enable_io(device_t dev, int space) 371 { 372 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 373 } 374 375 static __inline int 376 pci_disable_io(device_t dev, int space) 377 { 378 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 379 } 380 381 static __inline int 382 pci_get_vpd_ident(device_t dev, const char **identptr) 383 { 384 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 385 } 386 387 static __inline int 388 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 389 { 390 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 391 } 392 393 /* 394 * Check if the address range falls within the VGA defined address range(s) 395 */ 396 static __inline int 397 pci_is_vga_ioport_range(u_long start, u_long end) 398 { 399 400 return (((start >= 0x3b0 && end <= 0x3bb) || 401 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 402 } 403 404 static __inline int 405 pci_is_vga_memory_range(u_long start, u_long end) 406 { 407 408 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 409 } 410 411 /* 412 * PCI power states are as defined by ACPI: 413 * 414 * D0 State in which device is on and running. It is receiving full 415 * power from the system and delivering full functionality to the user. 416 * D1 Class-specific low-power state in which device context may or may not 417 * be lost. Buses in D1 cannot do anything to the bus that would force 418 * devices on that bus to lose context. 419 * D2 Class-specific low-power state in which device context may or may 420 * not be lost. Attains greater power savings than D1. Buses in D2 421 * can cause devices on that bus to lose some context. Devices in D2 422 * must be prepared for the bus to be in D2 or higher. 423 * D3 State in which the device is off and not running. Device context is 424 * lost. Power can be removed from the device. 425 */ 426 #define PCI_POWERSTATE_D0 0 427 #define PCI_POWERSTATE_D1 1 428 #define PCI_POWERSTATE_D2 2 429 #define PCI_POWERSTATE_D3 3 430 #define PCI_POWERSTATE_UNKNOWN -1 431 432 static __inline int 433 pci_set_powerstate(device_t dev, int state) 434 { 435 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 436 } 437 438 static __inline int 439 pci_get_powerstate(device_t dev) 440 { 441 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 442 } 443 444 static __inline int 445 pci_find_cap(device_t dev, int capability, int *capreg) 446 { 447 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 448 } 449 450 static __inline int 451 pci_find_extcap(device_t dev, int capability, int *capreg) 452 { 453 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 454 } 455 456 static __inline int 457 pci_find_htcap(device_t dev, int capability, int *capreg) 458 { 459 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 460 } 461 462 static __inline int 463 pci_alloc_msi(device_t dev, int *count) 464 { 465 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 466 } 467 468 static __inline int 469 pci_alloc_msix(device_t dev, int *count) 470 { 471 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 472 } 473 474 static __inline void 475 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 476 { 477 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 478 } 479 480 static __inline void 481 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 482 { 483 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 484 } 485 486 static __inline void 487 pci_disable_msi(device_t dev) 488 { 489 PCI_DISABLE_MSI(device_get_parent(dev), dev); 490 } 491 492 static __inline int 493 pci_remap_msix(device_t dev, int count, const u_int *vectors) 494 { 495 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 496 } 497 498 static __inline int 499 pci_release_msi(device_t dev) 500 { 501 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 502 } 503 504 static __inline int 505 pci_msi_count(device_t dev) 506 { 507 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 508 } 509 510 static __inline int 511 pci_msix_count(device_t dev) 512 { 513 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 514 } 515 516 static __inline uint16_t 517 pci_get_rid(device_t dev) 518 { 519 return (PCI_GET_RID(device_get_parent(dev), dev)); 520 } 521 522 static __inline void 523 pci_child_added(device_t dev) 524 { 525 526 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 527 } 528 529 static __inline int 530 pci_iov_attach(device_t dev, struct nvlist *pf_schema, struct nvlist *vf_schema) 531 { 532 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema, 533 vf_schema)); 534 } 535 536 static __inline int 537 pci_iov_detach(device_t dev) 538 { 539 return (PCI_IOV_DETACH(device_get_parent(dev), dev)); 540 } 541 542 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 543 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 544 device_t pci_find_device(uint16_t, uint16_t); 545 device_t pci_find_class(uint8_t class, uint8_t subclass); 546 547 /* Can be used by drivers to manage the MSI-X table. */ 548 int pci_pending_msix(device_t dev, u_int index); 549 550 int pci_msi_device_blacklisted(device_t dev); 551 int pci_msix_device_blacklisted(device_t dev); 552 553 void pci_ht_map_msi(device_t dev, uint64_t addr); 554 555 int pci_get_max_read_req(device_t dev); 556 void pci_restore_state(device_t dev); 557 void pci_save_state(device_t dev); 558 int pci_set_max_read_req(device_t dev, int size); 559 560 561 #ifdef BUS_SPACE_MAXADDR 562 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 563 #define PCI_DMA_BOUNDARY 0x100000000 564 #else 565 #define PCI_DMA_BOUNDARY 0 566 #endif 567 #endif 568 569 #endif /* _SYS_BUS_H_ */ 570 571 /* 572 * cdev switch for control device, initialised in generic PCI code 573 */ 574 extern struct cdevsw pcicdev; 575 576 /* 577 * List of all PCI devices, generation count for the list. 578 */ 579 STAILQ_HEAD(devlist, pci_devinfo); 580 581 extern struct devlist pci_devq; 582 extern uint32_t pci_generation; 583 584 struct pci_map *pci_find_bar(device_t dev, int reg); 585 int pci_bar_enabled(device_t dev, struct pci_map *pm); 586 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 587 588 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 589 #define VGA_PCI_BIOS_SHADOW_SIZE 131072 590 591 int vga_pci_is_boot_display(device_t dev); 592 void * vga_pci_map_bios(device_t dev, size_t *size); 593 void vga_pci_unmap_bios(device_t dev, void *bios); 594 int vga_pci_repost(device_t dev); 595 596 #endif /* _PCIVAR_H_ */ 597