xref: /freebsd/sys/dev/pci/pcivar.h (revision 262e143bd46171a6415a5b28af260a5efa2a3db8)
1 /*-
2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  *
28  */
29 
30 #ifndef _PCIVAR_H_
31 #define _PCIVAR_H_
32 
33 #include <sys/queue.h>
34 
35 /* some PCI bus constants */
36 
37 #define PCI_BUSMAX	255	/* highest supported bus number */
38 #define PCI_SLOTMAX	31	/* highest supported slot number */
39 #define PCI_FUNCMAX	7	/* highest supported function number */
40 #define PCI_REGMAX	255	/* highest supported config register addr. */
41 
42 #define PCI_MAXMAPS_0	6	/* max. no. of memory/port maps */
43 #define PCI_MAXMAPS_1	2	/* max. no. of maps for PCI to PCI bridge */
44 #define PCI_MAXMAPS_2	1	/* max. no. of maps for CardBus bridge */
45 
46 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
47 
48 #ifdef PCI_A64
49 typedef uint64_t pci_addr_t;	/* uint64_t for system with 64bit addresses */
50 #else
51 typedef uint32_t pci_addr_t;	/* uint64_t for system with 64bit addresses */
52 #endif
53 
54 /* Interesting values for PCI power management */
55 struct pcicfg_pp {
56     uint16_t	pp_cap;		/* PCI power management capabilities */
57     uint8_t	pp_status;	/* config space address of PCI power status reg */
58     uint8_t	pp_pmcsr;	/* config space address of PMCSR reg */
59     uint8_t	pp_data;	/* config space address of PCI power data reg */
60 };
61 
62 /* Interesting values for PCI MSI */
63 struct pcicfg_msi {
64     uint16_t	msi_ctrl;	/* Message Control */
65     uint8_t	msi_msgnum;	/* Number of messages */
66     uint16_t	msi_data;	/* Location of MSI data word */
67 };
68 
69 /* config header information common to all header types */
70 typedef struct pcicfg {
71     struct device *dev;		/* device which owns this */
72 
73     uint32_t	bar[PCI_MAXMAPS_0]; /* BARs */
74     uint32_t	bios;		/* BIOS mapping */
75 
76     uint16_t	subvendor;	/* card vendor ID */
77     uint16_t	subdevice;	/* card device ID, assigned by card vendor */
78     uint16_t	vendor;		/* chip vendor ID */
79     uint16_t	device;		/* chip device ID, assigned by chip vendor */
80 
81     uint16_t	cmdreg;		/* disable/enable chip and PCI options */
82     uint16_t	statreg;	/* supported PCI features and error state */
83 
84     uint8_t	baseclass;	/* chip PCI class */
85     uint8_t	subclass;	/* chip PCI subclass */
86     uint8_t	progif;		/* chip PCI programming interface */
87     uint8_t	revid;		/* chip revision ID */
88 
89     uint8_t	hdrtype;	/* chip config header type */
90     uint8_t	cachelnsz;	/* cache line size in 4byte units */
91     uint8_t	intpin;		/* PCI interrupt pin */
92     uint8_t	intline;	/* interrupt line (IRQ for PC arch) */
93 
94     uint8_t	mingnt;		/* min. useful bus grant time in 250ns units */
95     uint8_t	maxlat;		/* max. tolerated bus grant latency in 250ns */
96     uint8_t	lattimer;	/* latency timer in units of 30ns bus cycles */
97 
98     uint8_t	mfdev;		/* multi-function device (from hdrtype reg) */
99     uint8_t	nummaps;	/* actual number of PCI maps used */
100 
101     uint8_t	bus;		/* config space bus address */
102     uint8_t	slot;		/* config space slot address */
103     uint8_t	func;		/* config space function number */
104 
105     struct pcicfg_pp pp;	/* pci power management */
106     struct pcicfg_msi msi;	/* pci msi */
107 } pcicfgregs;
108 
109 /* additional type 1 device config header information (PCI to PCI bridge) */
110 
111 #ifdef PCI_A64
112 #define PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
113 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
114 #else
115 #define PCI_PPBMEMBASE(h,l)  (((l)<<16) & ~0xfffff)
116 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
117 #endif /* PCI_A64 */
118 
119 #define PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
120 #define PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
121 
122 typedef struct {
123     pci_addr_t	pmembase;	/* base address of prefetchable memory */
124     pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */
125     uint32_t	membase;	/* base address of memory window */
126     uint32_t	memlimit;	/* topmost address of memory window */
127     uint32_t	iobase;		/* base address of port window */
128     uint32_t	iolimit;	/* topmost address of port window */
129     uint16_t	secstat;	/* secondary bus status register */
130     uint16_t	bridgectl;	/* bridge control register */
131     uint8_t	seclat;		/* CardBus latency timer */
132 } pcih1cfgregs;
133 
134 /* additional type 2 device config header information (CardBus bridge) */
135 
136 typedef struct {
137     uint32_t	membase0;	/* base address of memory window */
138     uint32_t	memlimit0;	/* topmost address of memory window */
139     uint32_t	membase1;	/* base address of memory window */
140     uint32_t	memlimit1;	/* topmost address of memory window */
141     uint32_t	iobase0;	/* base address of port window */
142     uint32_t	iolimit0;	/* topmost address of port window */
143     uint32_t	iobase1;	/* base address of port window */
144     uint32_t	iolimit1;	/* topmost address of port window */
145     uint32_t	pccardif;	/* PC Card 16bit IF legacy more base addr. */
146     uint16_t	secstat;	/* secondary bus status register */
147     uint16_t	bridgectl;	/* bridge control register */
148     uint8_t	seclat;		/* CardBus latency timer */
149 } pcih2cfgregs;
150 
151 extern uint32_t pci_numdevs;
152 
153 /* Only if the prerequisites are present */
154 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
155 struct pci_devinfo {
156         STAILQ_ENTRY(pci_devinfo) pci_links;
157 	struct resource_list resources;
158 	pcicfgregs		cfg;
159 	struct pci_conf		conf;
160 };
161 #endif
162 
163 #ifdef __alpha__
164 vm_offset_t pci_cvt_to_dense (vm_offset_t);
165 vm_offset_t pci_cvt_to_bwx (vm_offset_t);
166 #endif /* __alpha__ */
167 
168 #ifdef _SYS_BUS_H_
169 
170 #include "pci_if.h"
171 
172 /*
173  * Define pci-specific resource flags for accessing memory via dense
174  * or bwx memory spaces. These flags are ignored on i386.
175  */
176 #define PCI_RF_DENSE	0x10000
177 #define PCI_RF_BWX	0x20000
178 
179 enum pci_device_ivars {
180     PCI_IVAR_SUBVENDOR,
181     PCI_IVAR_SUBDEVICE,
182     PCI_IVAR_VENDOR,
183     PCI_IVAR_DEVICE,
184     PCI_IVAR_DEVID,
185     PCI_IVAR_CLASS,
186     PCI_IVAR_SUBCLASS,
187     PCI_IVAR_PROGIF,
188     PCI_IVAR_REVID,
189     PCI_IVAR_INTPIN,
190     PCI_IVAR_IRQ,
191     PCI_IVAR_BUS,
192     PCI_IVAR_SLOT,
193     PCI_IVAR_FUNCTION,
194     PCI_IVAR_ETHADDR,
195     PCI_IVAR_CMDREG,
196     PCI_IVAR_CACHELNSZ,
197     PCI_IVAR_MINGNT,
198     PCI_IVAR_MAXLAT,
199     PCI_IVAR_LATTIMER,
200 };
201 
202 /*
203  * Simplified accessors for pci devices
204  */
205 #define PCI_ACCESSOR(var, ivar, type)					\
206 	__BUS_ACCESSOR(pci, var, PCI, ivar, type)
207 
208 PCI_ACCESSOR(subvendor,		SUBVENDOR,	uint16_t)
209 PCI_ACCESSOR(subdevice,		SUBDEVICE,	uint16_t)
210 PCI_ACCESSOR(vendor,		VENDOR,		uint16_t)
211 PCI_ACCESSOR(device,		DEVICE,		uint16_t)
212 PCI_ACCESSOR(devid,		DEVID,		uint32_t)
213 PCI_ACCESSOR(class,		CLASS,		uint8_t)
214 PCI_ACCESSOR(subclass,		SUBCLASS,	uint8_t)
215 PCI_ACCESSOR(progif,		PROGIF,		uint8_t)
216 PCI_ACCESSOR(revid,		REVID,		uint8_t)
217 PCI_ACCESSOR(intpin,		INTPIN,		uint8_t)
218 PCI_ACCESSOR(irq,		IRQ,		uint8_t)
219 PCI_ACCESSOR(bus,		BUS,		uint8_t)
220 PCI_ACCESSOR(slot,		SLOT,		uint8_t)
221 PCI_ACCESSOR(function,		FUNCTION,	uint8_t)
222 PCI_ACCESSOR(ether,		ETHADDR,	uint8_t *)
223 PCI_ACCESSOR(cmdreg,		CMDREG,		uint8_t)
224 PCI_ACCESSOR(cachelnsz,		CACHELNSZ,	uint8_t)
225 PCI_ACCESSOR(mingnt,		MINGNT,		uint8_t)
226 PCI_ACCESSOR(maxlat,		MAXLAT,		uint8_t)
227 PCI_ACCESSOR(lattimer,		LATTIMER,	uint8_t)
228 
229 #undef PCI_ACCESSOR
230 
231 /*
232  * Operations on configuration space.
233  */
234 static __inline uint32_t
235 pci_read_config(device_t dev, int reg, int width)
236 {
237     return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
238 }
239 
240 static __inline void
241 pci_write_config(device_t dev, int reg, uint32_t val, int width)
242 {
243     PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
244 }
245 
246 /*
247  * Ivars for pci bridges.
248  */
249 
250 /*typedef enum pci_device_ivars pcib_device_ivars;*/
251 enum pcib_device_ivars {
252 	PCIB_IVAR_BUS
253 };
254 
255 #define PCIB_ACCESSOR(var, ivar, type)					 \
256     __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
257 
258 PCIB_ACCESSOR(bus,		BUS,		uint32_t)
259 
260 #undef PCIB_ACCESSOR
261 
262 /*
263  * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
264  * on i386 or other platforms should be mapped out in the MD pcireadconf
265  * code and not here, since the only MI invalid IRQ is 255.
266  */
267 #define PCI_INVALID_IRQ		255
268 #define PCI_INTERRUPT_VALID(x)	((x) != PCI_INVALID_IRQ)
269 
270 /*
271  * Convenience functions.
272  *
273  * These should be used in preference to manually manipulating
274  * configuration space.
275  */
276 static __inline int
277 pci_enable_busmaster(device_t dev)
278 {
279     return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
280 }
281 
282 static __inline int
283 pci_disable_busmaster(device_t dev)
284 {
285     return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
286 }
287 
288 static __inline int
289 pci_enable_io(device_t dev, int space)
290 {
291     return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
292 }
293 
294 static __inline int
295 pci_disable_io(device_t dev, int space)
296 {
297     return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
298 }
299 
300 /*
301  * Check if the address range falls within the VGA defined address range(s)
302  */
303 static __inline int
304 pci_is_vga_ioport_range(u_long start, u_long end)
305 {
306 
307 	return (((start >= 0x3b0 && end <= 0x3bb) ||
308 	    (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
309 }
310 
311 static __inline int
312 pci_is_vga_memory_range(u_long start, u_long end)
313 {
314 
315 	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
316 }
317 
318 /*
319  * PCI power states are as defined by ACPI:
320  *
321  * D0	State in which device is on and running.  It is receiving full
322  *	power from the system and delivering full functionality to the user.
323  * D1	Class-specific low-power state in which device context may or may not
324  *	be lost.  Buses in D1 cannot do anything to the bus that would force
325  *	devices on that bus to loose context.
326  * D2	Class-specific low-power state in which device context may or may
327  *	not be lost.  Attains greater power savings than D1.  Buses in D2
328  *	can cause devices on that bus to loose some context.  Devices in D2
329  *	must be prepared for the bus to be in D2 or higher.
330  * D3	State in which the device is off and not running.  Device context is
331  *	lost.  Power can be removed from the device.
332  */
333 #define PCI_POWERSTATE_D0	0
334 #define PCI_POWERSTATE_D1	1
335 #define PCI_POWERSTATE_D2	2
336 #define PCI_POWERSTATE_D3	3
337 #define PCI_POWERSTATE_UNKNOWN	-1
338 
339 static __inline int
340 pci_set_powerstate(device_t dev, int state)
341 {
342     return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
343 }
344 
345 static __inline int
346 pci_get_powerstate(device_t dev)
347 {
348     return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
349 }
350 
351 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
352 device_t pci_find_device(uint16_t, uint16_t);
353 #endif	/* _SYS_BUS_H_ */
354 
355 /*
356  * cdev switch for control device, initialised in generic PCI code
357  */
358 extern struct cdevsw pcicdev;
359 
360 /*
361  * List of all PCI devices, generation count for the list.
362  */
363 STAILQ_HEAD(devlist, pci_devinfo);
364 
365 extern struct devlist	pci_devq;
366 extern uint32_t	pci_generation;
367 
368 #endif /* _PCIVAR_H_ */
369