xref: /freebsd/sys/dev/pci/pcivar.h (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*-
2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  *
28  */
29 
30 #ifndef _PCIVAR_H_
31 #define	_PCIVAR_H_
32 
33 #include <sys/queue.h>
34 
35 /* some PCI bus constants */
36 
37 #define	PCI_DOMAINMAX	65535	/* highest supported domain number */
38 #define	PCI_BUSMAX	255	/* highest supported bus number */
39 #define	PCI_SLOTMAX	31	/* highest supported slot number */
40 #define	PCI_FUNCMAX	7	/* highest supported function number */
41 #define	PCI_REGMAX	255	/* highest supported config register addr. */
42 
43 #define	PCI_MAXMAPS_0	6	/* max. no. of memory/port maps */
44 #define	PCI_MAXMAPS_1	2	/* max. no. of maps for PCI to PCI bridge */
45 #define	PCI_MAXMAPS_2	1	/* max. no. of maps for CardBus bridge */
46 
47 typedef uint64_t pci_addr_t;
48 
49 /* Interesting values for PCI power management */
50 struct pcicfg_pp {
51     uint16_t	pp_cap;		/* PCI power management capabilities */
52     uint8_t	pp_status;	/* config space address of PCI power status reg */
53     uint8_t	pp_pmcsr;	/* config space address of PMCSR reg */
54     uint8_t	pp_data;	/* config space address of PCI power data reg */
55 };
56 
57 struct vpd_readonly {
58     char	keyword[2];
59     char	*value;
60 };
61 
62 struct vpd_write {
63     char	keyword[2];
64     char	*value;
65     int 	start;
66     int 	len;
67 };
68 
69 struct pcicfg_vpd {
70     uint8_t	vpd_reg;	/* base register, + 2 for addr, + 4 data */
71     char	vpd_cached;
72     char	*vpd_ident;	/* string identifier */
73     int 	vpd_rocnt;
74     struct vpd_readonly *vpd_ros;
75     int 	vpd_wcnt;
76     struct vpd_write *vpd_w;
77 };
78 
79 /* Interesting values for PCI MSI */
80 struct pcicfg_msi {
81     uint16_t	msi_ctrl;	/* Message Control */
82     uint8_t	msi_location;	/* Offset of MSI capability registers. */
83     uint8_t	msi_msgnum;	/* Number of messages */
84     int		msi_alloc;	/* Number of allocated messages. */
85     uint64_t	msi_addr;	/* Contents of address register. */
86     uint16_t	msi_data;	/* Contents of data register. */
87     u_int	msi_handlers;
88 };
89 
90 /* Interesting values for PCI MSI-X */
91 struct msix_vector {
92     uint64_t	mv_address;	/* Contents of address register. */
93     uint32_t	mv_data;	/* Contents of data register. */
94     int		mv_irq;
95 };
96 
97 struct msix_table_entry {
98     u_int	mte_vector;	/* 1-based index into msix_vectors array. */
99     u_int	mte_handlers;
100 };
101 
102 struct pcicfg_msix {
103     uint16_t	msix_ctrl;	/* Message Control */
104     uint16_t	msix_msgnum;	/* Number of messages */
105     uint8_t	msix_location;	/* Offset of MSI-X capability registers. */
106     uint8_t	msix_table_bar;	/* BAR containing vector table. */
107     uint8_t	msix_pba_bar;	/* BAR containing PBA. */
108     uint32_t	msix_table_offset;
109     uint32_t	msix_pba_offset;
110     int		msix_alloc;	/* Number of allocated vectors. */
111     int		msix_table_len;	/* Length of virtual table. */
112     struct msix_table_entry *msix_table; /* Virtual table. */
113     struct msix_vector *msix_vectors;	/* Array of allocated vectors. */
114     struct resource *msix_table_res;	/* Resource containing vector table. */
115     struct resource *msix_pba_res;	/* Resource containing PBA. */
116 };
117 
118 /* config header information common to all header types */
119 typedef struct pcicfg {
120     struct device *dev;		/* device which owns this */
121 
122     uint32_t	bar[PCI_MAXMAPS_0]; /* BARs */
123     uint32_t	bios;		/* BIOS mapping */
124 
125     uint16_t	subvendor;	/* card vendor ID */
126     uint16_t	subdevice;	/* card device ID, assigned by card vendor */
127     uint16_t	vendor;		/* chip vendor ID */
128     uint16_t	device;		/* chip device ID, assigned by chip vendor */
129 
130     uint16_t	cmdreg;		/* disable/enable chip and PCI options */
131     uint16_t	statreg;	/* supported PCI features and error state */
132 
133     uint8_t	baseclass;	/* chip PCI class */
134     uint8_t	subclass;	/* chip PCI subclass */
135     uint8_t	progif;		/* chip PCI programming interface */
136     uint8_t	revid;		/* chip revision ID */
137 
138     uint8_t	hdrtype;	/* chip config header type */
139     uint8_t	cachelnsz;	/* cache line size in 4byte units */
140     uint8_t	intpin;		/* PCI interrupt pin */
141     uint8_t	intline;	/* interrupt line (IRQ for PC arch) */
142 
143     uint8_t	mingnt;		/* min. useful bus grant time in 250ns units */
144     uint8_t	maxlat;		/* max. tolerated bus grant latency in 250ns */
145     uint8_t	lattimer;	/* latency timer in units of 30ns bus cycles */
146 
147     uint8_t	mfdev;		/* multi-function device (from hdrtype reg) */
148     uint8_t	nummaps;	/* actual number of PCI maps used */
149 
150     uint32_t	domain;		/* PCI domain */
151     uint8_t	bus;		/* config space bus address */
152     uint8_t	slot;		/* config space slot address */
153     uint8_t	func;		/* config space function number */
154 
155     struct pcicfg_pp pp;	/* pci power management */
156     struct pcicfg_vpd vpd;	/* pci vital product data */
157     struct pcicfg_msi msi;	/* pci msi */
158     struct pcicfg_msix msix;	/* pci msi-x */
159 } pcicfgregs;
160 
161 /* additional type 1 device config header information (PCI to PCI bridge) */
162 
163 #define	PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
164 #define	PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
165 #define	PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
166 #define	PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
167 
168 typedef struct {
169     pci_addr_t	pmembase;	/* base address of prefetchable memory */
170     pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */
171     uint32_t	membase;	/* base address of memory window */
172     uint32_t	memlimit;	/* topmost address of memory window */
173     uint32_t	iobase;		/* base address of port window */
174     uint32_t	iolimit;	/* topmost address of port window */
175     uint16_t	secstat;	/* secondary bus status register */
176     uint16_t	bridgectl;	/* bridge control register */
177     uint8_t	seclat;		/* CardBus latency timer */
178 } pcih1cfgregs;
179 
180 /* additional type 2 device config header information (CardBus bridge) */
181 
182 typedef struct {
183     uint32_t	membase0;	/* base address of memory window */
184     uint32_t	memlimit0;	/* topmost address of memory window */
185     uint32_t	membase1;	/* base address of memory window */
186     uint32_t	memlimit1;	/* topmost address of memory window */
187     uint32_t	iobase0;	/* base address of port window */
188     uint32_t	iolimit0;	/* topmost address of port window */
189     uint32_t	iobase1;	/* base address of port window */
190     uint32_t	iolimit1;	/* topmost address of port window */
191     uint32_t	pccardif;	/* PC Card 16bit IF legacy more base addr. */
192     uint16_t	secstat;	/* secondary bus status register */
193     uint16_t	bridgectl;	/* bridge control register */
194     uint8_t	seclat;		/* CardBus latency timer */
195 } pcih2cfgregs;
196 
197 extern uint32_t pci_numdevs;
198 
199 /* Only if the prerequisites are present */
200 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
201 struct pci_devinfo {
202         STAILQ_ENTRY(pci_devinfo) pci_links;
203 	struct resource_list resources;
204 	pcicfgregs		cfg;
205 	struct pci_conf		conf;
206 };
207 #endif
208 
209 #ifdef _SYS_BUS_H_
210 
211 #include "pci_if.h"
212 
213 /*
214  * Define pci-specific resource flags for accessing memory via dense
215  * or bwx memory spaces. These flags are ignored on i386.
216  */
217 #define	PCI_RF_DENSE	0x10000
218 #define	PCI_RF_BWX	0x20000
219 
220 enum pci_device_ivars {
221     PCI_IVAR_SUBVENDOR,
222     PCI_IVAR_SUBDEVICE,
223     PCI_IVAR_VENDOR,
224     PCI_IVAR_DEVICE,
225     PCI_IVAR_DEVID,
226     PCI_IVAR_CLASS,
227     PCI_IVAR_SUBCLASS,
228     PCI_IVAR_PROGIF,
229     PCI_IVAR_REVID,
230     PCI_IVAR_INTPIN,
231     PCI_IVAR_IRQ,
232     PCI_IVAR_DOMAIN,
233     PCI_IVAR_BUS,
234     PCI_IVAR_SLOT,
235     PCI_IVAR_FUNCTION,
236     PCI_IVAR_ETHADDR,
237     PCI_IVAR_CMDREG,
238     PCI_IVAR_CACHELNSZ,
239     PCI_IVAR_MINGNT,
240     PCI_IVAR_MAXLAT,
241     PCI_IVAR_LATTIMER,
242 };
243 
244 /*
245  * Simplified accessors for pci devices
246  */
247 #define	PCI_ACCESSOR(var, ivar, type)					\
248 	__BUS_ACCESSOR(pci, var, PCI, ivar, type)
249 
250 PCI_ACCESSOR(subvendor,		SUBVENDOR,	uint16_t)
251 PCI_ACCESSOR(subdevice,		SUBDEVICE,	uint16_t)
252 PCI_ACCESSOR(vendor,		VENDOR,		uint16_t)
253 PCI_ACCESSOR(device,		DEVICE,		uint16_t)
254 PCI_ACCESSOR(devid,		DEVID,		uint32_t)
255 PCI_ACCESSOR(class,		CLASS,		uint8_t)
256 PCI_ACCESSOR(subclass,		SUBCLASS,	uint8_t)
257 PCI_ACCESSOR(progif,		PROGIF,		uint8_t)
258 PCI_ACCESSOR(revid,		REVID,		uint8_t)
259 PCI_ACCESSOR(intpin,		INTPIN,		uint8_t)
260 PCI_ACCESSOR(irq,		IRQ,		uint8_t)
261 PCI_ACCESSOR(domain,		DOMAIN,		uint32_t)
262 PCI_ACCESSOR(bus,		BUS,		uint8_t)
263 PCI_ACCESSOR(slot,		SLOT,		uint8_t)
264 PCI_ACCESSOR(function,		FUNCTION,	uint8_t)
265 PCI_ACCESSOR(ether,		ETHADDR,	uint8_t *)
266 PCI_ACCESSOR(cmdreg,		CMDREG,		uint8_t)
267 PCI_ACCESSOR(cachelnsz,		CACHELNSZ,	uint8_t)
268 PCI_ACCESSOR(mingnt,		MINGNT,		uint8_t)
269 PCI_ACCESSOR(maxlat,		MAXLAT,		uint8_t)
270 PCI_ACCESSOR(lattimer,		LATTIMER,	uint8_t)
271 
272 #undef PCI_ACCESSOR
273 
274 /*
275  * Operations on configuration space.
276  */
277 static __inline uint32_t
278 pci_read_config(device_t dev, int reg, int width)
279 {
280     return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
281 }
282 
283 static __inline void
284 pci_write_config(device_t dev, int reg, uint32_t val, int width)
285 {
286     PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
287 }
288 
289 /*
290  * Ivars for pci bridges.
291  */
292 
293 /*typedef enum pci_device_ivars pcib_device_ivars;*/
294 enum pcib_device_ivars {
295 	PCIB_IVAR_DOMAIN,
296 	PCIB_IVAR_BUS
297 };
298 
299 #define	PCIB_ACCESSOR(var, ivar, type)					 \
300     __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
301 
302 PCIB_ACCESSOR(domain,		DOMAIN,		uint32_t)
303 PCIB_ACCESSOR(bus,		BUS,		uint32_t)
304 
305 #undef PCIB_ACCESSOR
306 
307 /*
308  * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
309  * on i386 or other platforms should be mapped out in the MD pcireadconf
310  * code and not here, since the only MI invalid IRQ is 255.
311  */
312 #define	PCI_INVALID_IRQ		255
313 #define	PCI_INTERRUPT_VALID(x)	((x) != PCI_INVALID_IRQ)
314 
315 /*
316  * Convenience functions.
317  *
318  * These should be used in preference to manually manipulating
319  * configuration space.
320  */
321 static __inline int
322 pci_enable_busmaster(device_t dev)
323 {
324     return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
325 }
326 
327 static __inline int
328 pci_disable_busmaster(device_t dev)
329 {
330     return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
331 }
332 
333 static __inline int
334 pci_enable_io(device_t dev, int space)
335 {
336     return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
337 }
338 
339 static __inline int
340 pci_disable_io(device_t dev, int space)
341 {
342     return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
343 }
344 
345 static __inline int
346 pci_get_vpd_ident(device_t dev, const char **identptr)
347 {
348     return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
349 }
350 
351 static __inline int
352 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
353 {
354     return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
355 }
356 
357 /*
358  * Check if the address range falls within the VGA defined address range(s)
359  */
360 static __inline int
361 pci_is_vga_ioport_range(u_long start, u_long end)
362 {
363 
364 	return (((start >= 0x3b0 && end <= 0x3bb) ||
365 	    (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
366 }
367 
368 static __inline int
369 pci_is_vga_memory_range(u_long start, u_long end)
370 {
371 
372 	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
373 }
374 
375 /*
376  * PCI power states are as defined by ACPI:
377  *
378  * D0	State in which device is on and running.  It is receiving full
379  *	power from the system and delivering full functionality to the user.
380  * D1	Class-specific low-power state in which device context may or may not
381  *	be lost.  Buses in D1 cannot do anything to the bus that would force
382  *	devices on that bus to lose context.
383  * D2	Class-specific low-power state in which device context may or may
384  *	not be lost.  Attains greater power savings than D1.  Buses in D2
385  *	can cause devices on that bus to lose some context.  Devices in D2
386  *	must be prepared for the bus to be in D2 or higher.
387  * D3	State in which the device is off and not running.  Device context is
388  *	lost.  Power can be removed from the device.
389  */
390 #define	PCI_POWERSTATE_D0	0
391 #define	PCI_POWERSTATE_D1	1
392 #define	PCI_POWERSTATE_D2	2
393 #define	PCI_POWERSTATE_D3	3
394 #define	PCI_POWERSTATE_UNKNOWN	-1
395 
396 static __inline int
397 pci_set_powerstate(device_t dev, int state)
398 {
399     return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
400 }
401 
402 static __inline int
403 pci_get_powerstate(device_t dev)
404 {
405     return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
406 }
407 
408 static __inline int
409 pci_find_extcap(device_t dev, int capability, int *capreg)
410 {
411     return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
412 }
413 
414 static __inline int
415 pci_alloc_msi(device_t dev, int *count)
416 {
417     return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
418 }
419 
420 static __inline int
421 pci_alloc_msix(device_t dev, int *count)
422 {
423     return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
424 }
425 
426 static __inline int
427 pci_remap_msix(device_t dev, int count, const u_int *vectors)
428 {
429     return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
430 }
431 
432 static __inline int
433 pci_release_msi(device_t dev)
434 {
435     return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
436 }
437 
438 static __inline int
439 pci_msi_count(device_t dev)
440 {
441     return (PCI_MSI_COUNT(device_get_parent(dev), dev));
442 }
443 
444 static __inline int
445 pci_msix_count(device_t dev)
446 {
447     return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
448 }
449 
450 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
451 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
452 device_t pci_find_device(uint16_t, uint16_t);
453 
454 /*
455  * Can be used by MD code to request the PCI bus to re-map an MSI or
456  * MSI-X message.
457  */
458 int	pci_remap_msi_irq(device_t dev, u_int irq);
459 
460 /* Can be used by drivers to manage the MSI-X table. */
461 int	pci_pending_msix(device_t dev, u_int index);
462 
463 int	pci_msi_device_blacklisted(device_t dev);
464 
465 #endif	/* _SYS_BUS_H_ */
466 
467 /*
468  * cdev switch for control device, initialised in generic PCI code
469  */
470 extern struct cdevsw pcicdev;
471 
472 /*
473  * List of all PCI devices, generation count for the list.
474  */
475 STAILQ_HEAD(devlist, pci_devinfo);
476 
477 extern struct devlist	pci_devq;
478 extern uint32_t	pci_generation;
479 
480 #endif /* _PCIVAR_H_ */
481