1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 */ 40 41 /* some PCI bus constants */ 42 43 #define PCI_BUSMAX 255 44 #define PCI_SLOTMAX 31 45 #define PCI_FUNCMAX 7 46 #define PCI_REGMAX 255 47 #define PCI_MAXHDRTYPE 2 48 49 /* PCI config header registers for all devices */ 50 51 #define PCIR_DEVVENDOR 0x00 52 #define PCIR_VENDOR 0x00 53 #define PCIR_DEVICE 0x02 54 #define PCIR_COMMAND 0x04 55 #define PCIM_CMD_PORTEN 0x0001 56 #define PCIM_CMD_MEMEN 0x0002 57 #define PCIM_CMD_BUSMASTEREN 0x0004 58 #define PCIM_CMD_SPECIALEN 0x0008 59 #define PCIM_CMD_MWRICEN 0x0010 60 #define PCIM_CMD_PERRESPEN 0x0040 61 #define PCIM_CMD_SERRESPEN 0x0100 62 #define PCIM_CMD_BACKTOBACK 0x0200 63 #define PCIR_STATUS 0x06 64 #define PCIM_STATUS_CAPPRESENT 0x0010 65 #define PCIM_STATUS_66CAPABLE 0x0020 66 #define PCIM_STATUS_BACKTOBACK 0x0080 67 #define PCIM_STATUS_PERRREPORT 0x0100 68 #define PCIM_STATUS_SEL_FAST 0x0000 69 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 70 #define PCIM_STATUS_SEL_SLOW 0x0400 71 #define PCIM_STATUS_SEL_MASK 0x0600 72 #define PCIM_STATUS_STABORT 0x0800 73 #define PCIM_STATUS_RTABORT 0x1000 74 #define PCIM_STATUS_RMABORT 0x2000 75 #define PCIM_STATUS_SERR 0x4000 76 #define PCIM_STATUS_PERR 0x8000 77 #define PCIR_REVID 0x08 78 #define PCIR_PROGIF 0x09 79 #define PCIR_SUBCLASS 0x0a 80 #define PCIR_CLASS 0x0b 81 #define PCIR_CACHELNSZ 0x0c 82 #define PCIR_LATTIMER 0x0d 83 #define PCIR_HDRTYPE 0x0e 84 #define PCIM_HDRTYPE 0x7f 85 #define PCIM_HDRTYPE_NORMAL 0x00 86 #define PCIM_HDRTYPE_BRIDGE 0x01 87 #define PCIM_HDRTYPE_CARDBUS 0x02 88 #define PCIM_MFDEV 0x80 89 #define PCIR_BIST 0x0f 90 91 /* Capability Register Offsets */ 92 93 #define PCICAP_ID 0x0 94 #define PCICAP_NEXTPTR 0x1 95 96 /* Capability Identification Numbers */ 97 98 #define PCIY_PMG 0x01 /* PCI Power Management */ 99 #define PCIY_AGP 0x02 /* AGP */ 100 #define PCIY_VPD 0x03 /* Vital Product Data */ 101 #define PCIY_SLOTID 0x04 /* Slot Identification */ 102 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 103 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 104 #define PCIY_PCIX 0x07 /* PCI-X */ 105 #define PCIY_HT 0x08 /* HyperTransport */ 106 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 107 #define PCIY_DEBUG 0x0a /* Debug port */ 108 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 109 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 110 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 111 #define PCIY_AGP8X 0x0e /* AGP 8x */ 112 #define PCIY_SECDEV 0x0f /* Secure Device */ 113 #define PCIY_EXPRESS 0x10 /* PCI Express */ 114 #define PCIY_MSIX 0x11 /* MSI-X */ 115 116 /* config registers for header type 0 devices */ 117 118 #define PCIR_BARS 0x10 119 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 120 #define PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4) 121 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 122 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 123 #define PCIM_BAR_SPACE 0x00000001 124 #define PCIM_BAR_MEM_SPACE 0 125 #define PCIM_BAR_IO_SPACE 1 126 #define PCIM_BAR_MEM_TYPE 0x00000006 127 #define PCIM_BAR_MEM_32 0 128 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 129 #define PCIM_BAR_MEM_64 4 130 #define PCIM_BAR_MEM_PREFETCH 0x00000008 131 #define PCIM_BAR_MEM_BASE 0xfffffff0 132 #define PCIM_BAR_IO_RESERVED 0x00000002 133 #define PCIM_BAR_IO_BASE 0xfffffffc 134 #define PCIR_CIS 0x28 135 #define PCIM_CIS_ASI_MASK 0x7 136 #define PCIM_CIS_ASI_TUPLE 0 137 #define PCIM_CIS_ASI_BAR0 1 138 #define PCIM_CIS_ASI_BAR1 2 139 #define PCIM_CIS_ASI_BAR2 3 140 #define PCIM_CIS_ASI_BAR3 4 141 #define PCIM_CIS_ASI_BAR4 5 142 #define PCIM_CIS_ASI_BAR5 6 143 #define PCIM_CIS_ASI_ROM 7 144 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 145 #define PCIM_CIS_ROM_MASK 0xf0000000 146 #define PCIR_SUBVEND_0 0x2c 147 #define PCIR_SUBDEV_0 0x2e 148 #define PCIR_BIOS 0x30 149 #define PCIM_BIOS_ENABLE 0x01 150 #define PCIM_BIOS_ADDR_MASK 0xfffff800 151 #define PCIR_CAP_PTR 0x34 152 #define PCIR_INTLINE 0x3c 153 #define PCIR_INTPIN 0x3d 154 #define PCIR_MINGNT 0x3e 155 #define PCIR_MAXLAT 0x3f 156 157 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 158 159 #define PCIR_SECSTAT_1 0x1e 160 161 #define PCIR_PRIBUS_1 0x18 162 #define PCIR_SECBUS_1 0x19 163 #define PCIR_SUBBUS_1 0x1a 164 #define PCIR_SECLAT_1 0x1b 165 166 #define PCIR_IOBASEL_1 0x1c 167 #define PCIR_IOLIMITL_1 0x1d 168 #define PCIR_IOBASEH_1 0x30 169 #define PCIR_IOLIMITH_1 0x32 170 #define PCIM_BRIO_16 0x0 171 #define PCIM_BRIO_32 0x1 172 #define PCIM_BRIO_MASK 0xf 173 174 #define PCIR_MEMBASE_1 0x20 175 #define PCIR_MEMLIMIT_1 0x22 176 177 #define PCIR_PMBASEL_1 0x24 178 #define PCIR_PMLIMITL_1 0x26 179 #define PCIR_PMBASEH_1 0x28 180 #define PCIR_PMLIMITH_1 0x2c 181 182 #define PCIR_BRIDGECTL_1 0x3e 183 184 /* config registers for header type 2 (CardBus) devices */ 185 186 #define PCIR_CAP_PTR_2 0x14 187 #define PCIR_SECSTAT_2 0x16 188 189 #define PCIR_PRIBUS_2 0x18 190 #define PCIR_SECBUS_2 0x19 191 #define PCIR_SUBBUS_2 0x1a 192 #define PCIR_SECLAT_2 0x1b 193 194 #define PCIR_MEMBASE0_2 0x1c 195 #define PCIR_MEMLIMIT0_2 0x20 196 #define PCIR_MEMBASE1_2 0x24 197 #define PCIR_MEMLIMIT1_2 0x28 198 #define PCIR_IOBASE0_2 0x2c 199 #define PCIR_IOLIMIT0_2 0x30 200 #define PCIR_IOBASE1_2 0x34 201 #define PCIR_IOLIMIT1_2 0x38 202 203 #define PCIR_BRIDGECTL_2 0x3e 204 205 #define PCIR_SUBVEND_2 0x40 206 #define PCIR_SUBDEV_2 0x42 207 208 #define PCIR_PCCARDIF_2 0x44 209 210 /* PCI device class, subclass and programming interface definitions */ 211 212 #define PCIC_OLD 0x00 213 #define PCIS_OLD_NONVGA 0x00 214 #define PCIS_OLD_VGA 0x01 215 216 #define PCIC_STORAGE 0x01 217 #define PCIS_STORAGE_SCSI 0x00 218 #define PCIS_STORAGE_IDE 0x01 219 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 220 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 221 #define PCIP_STORAGE_IDE_MODESEC 0x04 222 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 223 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 224 #define PCIS_STORAGE_FLOPPY 0x02 225 #define PCIS_STORAGE_IPI 0x03 226 #define PCIS_STORAGE_RAID 0x04 227 #define PCIS_STORAGE_ATA_ADMA 0x05 228 #define PCIS_STORAGE_SATA 0x06 229 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 230 #define PCIS_STORAGE_SAS 0x07 231 #define PCIS_STORAGE_OTHER 0x80 232 233 #define PCIC_NETWORK 0x02 234 #define PCIS_NETWORK_ETHERNET 0x00 235 #define PCIS_NETWORK_TOKENRING 0x01 236 #define PCIS_NETWORK_FDDI 0x02 237 #define PCIS_NETWORK_ATM 0x03 238 #define PCIS_NETWORK_ISDN 0x04 239 #define PCIS_NETWORK_WORLDFIP 0x05 240 #define PCIS_NETWORK_PICMG 0x06 241 #define PCIS_NETWORK_OTHER 0x80 242 243 #define PCIC_DISPLAY 0x03 244 #define PCIS_DISPLAY_VGA 0x00 245 #define PCIS_DISPLAY_XGA 0x01 246 #define PCIS_DISPLAY_3D 0x02 247 #define PCIS_DISPLAY_OTHER 0x80 248 249 #define PCIC_MULTIMEDIA 0x04 250 #define PCIS_MULTIMEDIA_VIDEO 0x00 251 #define PCIS_MULTIMEDIA_AUDIO 0x01 252 #define PCIS_MULTIMEDIA_TELE 0x02 253 #define PCIS_MULTIMEDIA_OTHER 0x80 254 255 #define PCIC_MEMORY 0x05 256 #define PCIS_MEMORY_RAM 0x00 257 #define PCIS_MEMORY_FLASH 0x01 258 #define PCIS_MEMORY_OTHER 0x80 259 260 #define PCIC_BRIDGE 0x06 261 #define PCIS_BRIDGE_HOST 0x00 262 #define PCIS_BRIDGE_ISA 0x01 263 #define PCIS_BRIDGE_EISA 0x02 264 #define PCIS_BRIDGE_MCA 0x03 265 #define PCIS_BRIDGE_PCI 0x04 266 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 267 #define PCIS_BRIDGE_PCMCIA 0x05 268 #define PCIS_BRIDGE_NUBUS 0x06 269 #define PCIS_BRIDGE_CARDBUS 0x07 270 #define PCIS_BRIDGE_RACEWAY 0x08 271 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 272 #define PCIS_BRIDGE_INFINIBAND 0x0a 273 #define PCIS_BRIDGE_OTHER 0x80 274 275 #define PCIC_SIMPLECOMM 0x07 276 #define PCIS_SIMPLECOMM_UART 0x00 277 #define PCIP_SIMPLECOMM_UART_8250 0x00 278 #define PCIP_SIMPLECOMM_UART_16450A 0x01 279 #define PCIP_SIMPLECOMM_UART_16550A 0x02 280 #define PCIP_SIMPLECOMM_UART_16650A 0x03 281 #define PCIP_SIMPLECOMM_UART_16750A 0x04 282 #define PCIP_SIMPLECOMM_UART_16850A 0x05 283 #define PCIP_SIMPLECOMM_UART_16950A 0x06 284 #define PCIS_SIMPLECOMM_PAR 0x01 285 #define PCIS_SIMPLECOMM_MULSER 0x02 286 #define PCIS_SIMPLECOMM_MODEM 0x03 287 #define PCIS_SIMPLECOMM_GPIB 0x04 288 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 289 #define PCIS_SIMPLECOMM_OTHER 0x80 290 291 #define PCIC_BASEPERIPH 0x08 292 #define PCIS_BASEPERIPH_PIC 0x00 293 #define PCIP_BASEPERIPH_PIC_8259A 0x00 294 #define PCIP_BASEPERIPH_PIC_ISA 0x01 295 #define PCIP_BASEPERIPH_PIC_EISA 0x02 296 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 297 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 298 #define PCIS_BASEPERIPH_DMA 0x01 299 #define PCIS_BASEPERIPH_TIMER 0x02 300 #define PCIS_BASEPERIPH_RTC 0x03 301 #define PCIS_BASEPERIPH_PCIHOT 0x04 302 #define PCIS_BASEPERIPH_SDHC 0x05 303 #define PCIS_BASEPERIPH_OTHER 0x80 304 305 #define PCIC_INPUTDEV 0x09 306 #define PCIS_INPUTDEV_KEYBOARD 0x00 307 #define PCIS_INPUTDEV_DIGITIZER 0x01 308 #define PCIS_INPUTDEV_MOUSE 0x02 309 #define PCIS_INPUTDEV_SCANNER 0x03 310 #define PCIS_INPUTDEV_GAMEPORT 0x04 311 #define PCIS_INPUTDEV_OTHER 0x80 312 313 #define PCIC_DOCKING 0x0a 314 #define PCIS_DOCKING_GENERIC 0x00 315 #define PCIS_DOCKING_OTHER 0x80 316 317 #define PCIC_PROCESSOR 0x0b 318 #define PCIS_PROCESSOR_386 0x00 319 #define PCIS_PROCESSOR_486 0x01 320 #define PCIS_PROCESSOR_PENTIUM 0x02 321 #define PCIS_PROCESSOR_ALPHA 0x10 322 #define PCIS_PROCESSOR_POWERPC 0x20 323 #define PCIS_PROCESSOR_MIPS 0x30 324 #define PCIS_PROCESSOR_COPROC 0x40 325 326 #define PCIC_SERIALBUS 0x0c 327 #define PCIS_SERIALBUS_FW 0x00 328 #define PCIS_SERIALBUS_ACCESS 0x01 329 #define PCIS_SERIALBUS_SSA 0x02 330 #define PCIS_SERIALBUS_USB 0x03 331 #define PCIP_SERIALBUS_USB_UHCI 0x00 332 #define PCIP_SERIALBUS_USB_OHCI 0x10 333 #define PCIP_SERIALBUS_USB_EHCI 0x20 334 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 335 #define PCIS_SERIALBUS_FC 0x04 336 #define PCIS_SERIALBUS_SMBUS 0x05 337 #define PCIS_SERIALBUS_INFINIBAND 0x06 338 #define PCIS_SERIALBUS_IPMI 0x07 339 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 340 #define PCIP_SERIALBUS_IPMI_KCS 0x01 341 #define PCIP_SERIALBUS_IPMI_BT 0x02 342 #define PCIS_SERIALBUS_SERCOS 0x08 343 #define PCIS_SERIALBUS_CANBUS 0x09 344 345 #define PCIC_WIRELESS 0x0d 346 #define PCIS_WIRELESS_IRDA 0x00 347 #define PCIS_WIRELESS_IR 0x01 348 #define PCIS_WIRELESS_RF 0x10 349 #define PCIS_WIRELESS_BLUETOOTH 0x11 350 #define PCIS_WIRELESS_BROADBAND 0x12 351 #define PCIS_WIRELESS_80211A 0x20 352 #define PCIS_WIRELESS_80211B 0x21 353 #define PCIS_WIRELESS_OTHER 0x80 354 355 #define PCIC_INTELLIIO 0x0e 356 #define PCIS_INTELLIIO_I2O 0x00 357 358 #define PCIC_SATCOM 0x0f 359 #define PCIS_SATCOM_TV 0x01 360 #define PCIS_SATCOM_AUDIO 0x02 361 #define PCIS_SATCOM_VOICE 0x03 362 #define PCIS_SATCOM_DATA 0x04 363 364 #define PCIC_CRYPTO 0x10 365 #define PCIS_CRYPTO_NETCOMP 0x00 366 #define PCIS_CRYPTO_ENTERTAIN 0x10 367 #define PCIS_CRYPTO_OTHER 0x80 368 369 #define PCIC_DASP 0x11 370 #define PCIS_DASP_DPIO 0x00 371 #define PCIS_DASP_PERFCNTRS 0x01 372 #define PCIS_DASP_COMM_SYNC 0x10 373 #define PCIS_DASP_MGMT_CARD 0x20 374 #define PCIS_DASP_OTHER 0x80 375 376 #define PCIC_OTHER 0xff 377 378 /* Bridge Control Values. */ 379 #define PCIB_BCR_PERR_ENABLE 0x0001 380 #define PCIB_BCR_SERR_ENABLE 0x0002 381 #define PCIB_BCR_ISA_ENABLE 0x0004 382 #define PCIB_BCR_VGA_ENABLE 0x0008 383 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 384 #define PCIB_BCR_SECBUS_RESET 0x0040 385 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 386 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 387 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 388 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 389 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 390 391 /* PCI power manangement */ 392 #define PCIR_POWER_CAP 0x2 393 #define PCIM_PCAP_SPEC 0x0007 394 #define PCIM_PCAP_PMEREQCLK 0x0008 395 #define PCIM_PCAP_PMEREQPWR 0x0010 396 #define PCIM_PCAP_DEVSPECINIT 0x0020 397 #define PCIM_PCAP_DYNCLOCK 0x0040 398 #define PCIM_PCAP_SECCLOCK 0x00c0 399 #define PCIM_PCAP_CLOCKMASK 0x00c0 400 #define PCIM_PCAP_REQFULLCLOCK 0x0100 401 #define PCIM_PCAP_D1SUPP 0x0200 402 #define PCIM_PCAP_D2SUPP 0x0400 403 #define PCIM_PCAP_D0PME 0x1000 404 #define PCIM_PCAP_D1PME 0x2000 405 #define PCIM_PCAP_D2PME 0x4000 406 407 #define PCIR_POWER_STATUS 0x4 408 #define PCIM_PSTAT_D0 0x0000 409 #define PCIM_PSTAT_D1 0x0001 410 #define PCIM_PSTAT_D2 0x0002 411 #define PCIM_PSTAT_D3 0x0003 412 #define PCIM_PSTAT_DMASK 0x0003 413 #define PCIM_PSTAT_REPENABLE 0x0010 414 #define PCIM_PSTAT_PMEENABLE 0x0100 415 #define PCIM_PSTAT_D0POWER 0x0000 416 #define PCIM_PSTAT_D1POWER 0x0200 417 #define PCIM_PSTAT_D2POWER 0x0400 418 #define PCIM_PSTAT_D3POWER 0x0600 419 #define PCIM_PSTAT_D0HEAT 0x0800 420 #define PCIM_PSTAT_D1HEAT 0x1000 421 #define PCIM_PSTAT_D2HEAT 0x1200 422 #define PCIM_PSTAT_D3HEAT 0x1400 423 #define PCIM_PSTAT_DATAUNKN 0x0000 424 #define PCIM_PSTAT_DATADIV10 0x2000 425 #define PCIM_PSTAT_DATADIV100 0x4000 426 #define PCIM_PSTAT_DATADIV1000 0x6000 427 #define PCIM_PSTAT_DATADIVMASK 0x6000 428 #define PCIM_PSTAT_PME 0x8000 429 430 #define PCIR_POWER_PMCSR 0x6 431 #define PCIM_PMCSR_DCLOCK 0x10 432 #define PCIM_PMCSR_B2SUPP 0x20 433 #define PCIM_BMCSR_B3SUPP 0x40 434 #define PCIM_BMCSR_BPCE 0x80 435 436 #define PCIR_POWER_DATA 0x7 437 438 /* VPD capability registers */ 439 #define PCIR_VPD_ADDR 0x2 440 #define PCIR_VPD_DATA 0x4 441 442 /* PCI Message Signalled Interrupts (MSI) */ 443 #define PCIR_MSI_CTRL 0x2 444 #define PCIM_MSICTRL_VECTOR 0x0100 445 #define PCIM_MSICTRL_64BIT 0x0080 446 #define PCIM_MSICTRL_MME_MASK 0x0070 447 #define PCIM_MSICTRL_MME_1 0x0000 448 #define PCIM_MSICTRL_MME_2 0x0010 449 #define PCIM_MSICTRL_MME_4 0x0020 450 #define PCIM_MSICTRL_MME_8 0x0030 451 #define PCIM_MSICTRL_MME_16 0x0040 452 #define PCIM_MSICTRL_MME_32 0x0050 453 #define PCIM_MSICTRL_MMC_MASK 0x000E 454 #define PCIM_MSICTRL_MMC_1 0x0000 455 #define PCIM_MSICTRL_MMC_2 0x0002 456 #define PCIM_MSICTRL_MMC_4 0x0004 457 #define PCIM_MSICTRL_MMC_8 0x0006 458 #define PCIM_MSICTRL_MMC_16 0x0008 459 #define PCIM_MSICTRL_MMC_32 0x000A 460 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 461 #define PCIR_MSI_ADDR 0x4 462 #define PCIR_MSI_ADDR_HIGH 0x8 463 #define PCIR_MSI_DATA 0x8 464 #define PCIR_MSI_DATA_64BIT 0xc 465 #define PCIR_MSI_MASK 0x10 466 #define PCIR_MSI_PENDING 0x14 467 468 /* PCI-X definitions */ 469 470 /* For header type 0 devices */ 471 #define PCIXR_COMMAND 0x2 472 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 473 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 474 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 475 #define PCIXM_COMMAND_MAX_READ_512 0x0000 476 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 477 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 478 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 479 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 480 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 481 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 482 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 483 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 484 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 485 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 486 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 487 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 488 #define PCIXM_COMMAND_VERSION 0x3000 489 #define PCIXR_STATUS 0x4 490 #define PCIXM_STATUS_DEVFN 0x000000FF 491 #define PCIXM_STATUS_BUS 0x0000FF00 492 #define PCIXM_STATUS_64BIT 0x00010000 493 #define PCIXM_STATUS_133CAP 0x00020000 494 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 495 #define PCIXM_STATUS_UNEXP_SC 0x00080000 496 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 497 #define PCIXM_STATUS_MAX_READ 0x00600000 498 #define PCIXM_STATUS_MAX_READ_512 0x00000000 499 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 500 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 501 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 502 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 503 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 504 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 505 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 506 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 507 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 508 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 509 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 510 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 511 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 512 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 513 #define PCIXM_STATUS_266CAP 0x40000000 514 #define PCIXM_STATUS_533CAP 0x80000000 515 516 /* For header type 1 devices (PCI-X bridges) */ 517 #define PCIXR_SEC_STATUS 0x2 518 #define PCIXM_SEC_STATUS_64BIT 0x0001 519 #define PCIXM_SEC_STATUS_133CAP 0x0002 520 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 521 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 522 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 523 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 524 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 525 #define PCIXM_SEC_STATUS_VERSION 0x3000 526 #define PCIXM_SEC_STATUS_266CAP 0x4000 527 #define PCIXM_SEC_STATUS_533CAP 0x8000 528 #define PCIXR_BRIDGE_STATUS 0x4 529 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 530 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 531 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 532 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 533 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 534 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 535 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 536 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 537 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 538 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 539 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 540 541 /* HT (HyperTransport) Capability definitions */ 542 #define PCIR_HT_COMMAND 0x2 543 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 544 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 545 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 546 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 547 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 548 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 549 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 550 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 551 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 552 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 553 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 554 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 555 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 556 557 /* HT MSI Mapping Capability definitions. */ 558 #define PCIM_HTCMD_MSI_ENABLE 0x0001 559 #define PCIR_HTMSI_ADDRESS_LO 0x4 560 #define PCIR_HTMSI_ADDRESS_HI 0x8 561 562 /* PCI Vendor capability definitions */ 563 #define PCIR_VENDOR_LENGTH 0x2 564 #define PCIR_VENDOR_DATA 0x3 565 566 /* PCI EHCI Debug Port definitions */ 567 #define PCIR_DEBUG_PORT 0x2 568 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 569 #define PCIM_DEBUG_PORT_BAR 0xe000 570 571 /* PCI-PCI Bridge Subvendor definitions */ 572 #define PCIR_SUBVENDCAP_ID 0x4 573 574 /* PCI Express definitions */ 575 #define PCIR_EXPRESS_FLAGS 0x2 576 #define PCIM_EXP_FLAGS_VERSION 0x000F 577 #define PCIM_EXP_FLAGS_TYPE 0x00F0 578 #define PCIM_EXP_TYPE_ENDPOINT 0x0000 579 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 580 #define PCIM_EXP_TYPE_ROOT_PORT 0x0040 581 #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 582 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 583 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 584 #define PCIM_EXP_FLAGS_SLOT 0x0100 585 #define PCIM_EXP_FLAGS_IRQ 0x3e00 586 587 /* MSI-X definitions */ 588 #define PCIR_MSIX_CTRL 0x2 589 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 590 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 591 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 592 #define PCIR_MSIX_TABLE 0x4 593 #define PCIR_MSIX_PBA 0x8 594 #define PCIM_MSIX_BIR_MASK 0x7 595 #define PCIM_MSIX_BIR_BAR_10 0 596 #define PCIM_MSIX_BIR_BAR_14 1 597 #define PCIM_MSIX_BIR_BAR_18 2 598 #define PCIM_MSIX_BIR_BAR_1C 3 599 #define PCIM_MSIX_BIR_BAR_20 4 600 #define PCIM_MSIX_BIR_BAR_24 5 601 #define PCIM_MSIX_VCTRL_MASK 0x1 602