1 #ifndef PCI_COMPAT 2 #define PCI_COMPAT 3 #endif 4 /* 5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 /* 34 * PCIM_xxx: mask to locate subfield in register 35 * PCIR_xxx: config register offset 36 * PCIC_xxx: device class 37 * PCIS_xxx: device subclass 38 * PCIP_xxx: device programming interface 39 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 40 * PCID_xxx: device ID 41 */ 42 43 /* some PCI bus constants */ 44 45 #define PCI_BUSMAX 255 46 #define PCI_SLOTMAX 31 47 #define PCI_FUNCMAX 7 48 #define PCI_REGMAX 255 49 50 /* PCI config header registers for all devices */ 51 52 #define PCIR_DEVVENDOR 0x00 53 #define PCIR_VENDOR 0x00 54 #define PCIR_DEVICE 0x02 55 #define PCIR_COMMAND 0x04 56 #define PCIM_CMD_PORTEN 0x0001 57 #define PCIM_CMD_MEMEN 0x0002 58 #define PCIM_CMD_BUSMASTEREN 0x0004 59 #define PCIM_CMD_PERRESPEN 0x0040 60 #define PCIR_STATUS 0x06 61 #define PCIR_REVID 0x08 62 #define PCIR_PROGIF 0x09 63 #define PCIR_SUBCLASS 0x0a 64 #define PCIR_CLASS 0x0b 65 #define PCIR_CACHELNSZ 0x0c 66 #define PCIR_LATTIMER 0x0d 67 #define PCIR_HEADERTYPE 0x0e 68 #define PCIM_MFDEV 0x80 69 #define PCIR_BIST 0x0f 70 71 /* config registers for header type 0 devices */ 72 73 #define PCIR_MAPS 0x10 74 #define PCIR_CARDBUSCIS 0x28 75 #define PCIR_SUBVEND_0 0x2c 76 #define PCIR_SUBDEV_0 0x2e 77 #define PCIR_BIOS 0x30 78 #define PCIM_BIOS_ENABLE 0x01 79 #define PCIR_INTLINE 0x3c 80 #define PCIR_INTPIN 0x3d 81 #define PCIR_MINGNT 0x3e 82 #define PCIR_MAXLAT 0x3f 83 84 /* config registers for header type 1 devices */ 85 86 #define PCIR_SECSTAT_1 0 /**/ 87 88 #define PCIR_PRIBUS_1 0x18 89 #define PCIR_SECBUS_1 0x19 90 #define PCIR_SUBBUS_1 0x1a 91 #define PCIR_SECLAT_1 0x1b 92 93 #define PCIR_IOBASEL_1 0x1c 94 #define PCIR_IOLIMITL_1 0x1d 95 #define PCIR_IOBASEH_1 0 /**/ 96 #define PCIR_IOLIMITH_1 0 /**/ 97 98 #define PCIR_MEMBASE_1 0x20 99 #define PCIR_MEMLIMIT_1 0x22 100 101 #define PCIR_PMBASEL_1 0x24 102 #define PCIR_PMLIMITL_1 0x26 103 #define PCIR_PMBASEH_1 0 /**/ 104 #define PCIR_PMLIMITH_1 0 /**/ 105 106 #define PCIR_BRIDGECTL_1 0 /**/ 107 108 #define PCIR_SUBVEND_1 0x34 109 #define PCIR_SUBDEV_1 0x36 110 111 /* config registers for header type 2 devices */ 112 113 #define PCIR_SECSTAT_2 0x16 114 115 #define PCIR_PRIBUS_2 0x18 116 #define PCIR_SECBUS_2 0x19 117 #define PCIR_SUBBUS_2 0x1a 118 #define PCIR_SECLAT_2 0x1b 119 120 #define PCIR_MEMBASE0_2 0x1c 121 #define PCIR_MEMLIMIT0_2 0x20 122 #define PCIR_MEMBASE1_2 0x24 123 #define PCIR_MEMLIMIT1_2 0x28 124 #define PCIR_IOBASE0_2 0x2c 125 #define PCIR_IOLIMIT0_2 0x30 126 #define PCIR_IOBASE1_2 0x34 127 #define PCIR_IOLIMIT1_2 0x38 128 129 #define PCIR_BRIDGECTL_2 0x3e 130 131 #define PCIR_SUBVEND_2 0x40 132 #define PCIR_SUBDEV_2 0x42 133 134 #define PCIR_PCCARDIF_2 0x44 135 136 /* PCI device class, subclass and programming interface definitions */ 137 138 #define PCIC_OLD 0x00 139 #define PCIS_OLD_NONVGA 0x00 140 #define PCIS_OLD_VGA 0x01 141 142 #define PCIC_STORAGE 0x01 143 #define PCIS_STORAGE_SCSI 0x00 144 #define PCIS_STORAGE_IDE 0x01 145 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 146 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 147 #define PCIP_STORAGE_IDE_MODESEC 0x04 148 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 149 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 150 #define PCIS_STORAGE_FLOPPY 0x02 151 #define PCIS_STORAGE_IPI 0x03 152 #define PCIS_STORAGE_RAID 0x04 153 #define PCIS_STORAGE_OTHER 0x80 154 155 #define PCIC_NETWORK 0x02 156 #define PCIS_NETWORK_ETHERNET 0x00 157 #define PCIS_NETWORK_TOKENRING 0x01 158 #define PCIS_NETWORK_FDDI 0x02 159 #define PCIS_NETWORK_ATM 0x03 160 #define PCIS_NETWORK_OTHER 0x80 161 162 #define PCIC_DISPLAY 0x03 163 #define PCIS_DISPLAY_VGA 0x00 164 #define PCIS_DISPLAY_XGA 0x01 165 #define PCIS_DISPLAY_OTHER 0x80 166 167 #define PCIC_MULTIMEDIA 0x04 168 #define PCIS_MULTIMEDIA_VIDEO 0x00 169 #define PCIS_MULTIMEDIA_AUDIO 0x01 170 #define PCIS_MULTIMEDIA_OTHER 0x80 171 172 #define PCIC_MEMORY 0x05 173 #define PCIS_MEMORY_RAM 0x00 174 #define PCIS_MEMORY_FLASH 0x01 175 #define PCIS_MEMORY_OTHER 0x80 176 177 #define PCIC_BRIDGE 0x06 178 #define PCIS_BRIDGE_HOST 0x00 179 #define PCIS_BRIDGE_ISA 0x01 180 #define PCIS_BRIDGE_EISA 0x02 181 #define PCIS_BRIDGE_MCA 0x03 182 #define PCIS_BRIDGE_PCI 0x04 183 #define PCIS_BRIDGE_PCMCIA 0x05 184 #define PCIS_BRIDGE_NUBUS 0x06 185 #define PCIS_BRIDGE_CARDBUS 0x07 186 #define PCIS_BRIDGE_OTHER 0x80 187 188 #define PCIC_SIMPLECOMM 0x07 189 #define PCIS_SIMPLECOMM_UART 0x00 190 #define PCIP_SIMPLECOMM_UART_16550A 0x02 191 #define PCIS_SIMPLECOMM_PAR 0x01 192 #define PCIS_SIMPLECOMM_OTHER 0x80 193 194 #define PCIC_BASEPERIPH 0x08 195 #define PCIS_BASEPERIPH_PIC 0x00 196 #define PCIS_BASEPERIPH_DMA 0x01 197 #define PCIS_BASEPERIPH_TIMER 0x02 198 #define PCIS_BASEPERIPH_RTC 0x03 199 #define PCIS_BASEPERIPH_OTHER 0x80 200 201 #define PCIC_INPUTDEV 0x09 202 #define PCIS_INPUTDEV_KEYBOARD 0x00 203 #define PCIS_INPUTDEV_DIGITIZER 0x01 204 #define PCIS_INPUTDEV_MOUSE 0x02 205 #define PCIS_INPUTDEV_OTHER 0x80 206 207 #define PCIC_DOCKING 0x0a 208 #define PCIS_DOCKING_GENERIC 0x00 209 #define PCIS_DOCKING_OTHER 0x80 210 211 #define PCIC_PROCESSOR 0x0b 212 #define PCIS_PROCESSOR_386 0x00 213 #define PCIS_PROCESSOR_486 0x01 214 #define PCIS_PROCESSOR_PENTIUM 0x02 215 #define PCIS_PROCESSOR_ALPHA 0x10 216 #define PCIS_PROCESSOR_POWERPC 0x20 217 #define PCIS_PROCESSOR_COPROC 0x40 218 219 #define PCIC_SERIALBUS 0x0c 220 #define PCIS_SERIALBUS_FW 0x00 221 #define PCIS_SERIALBUS_ACCESS 0x01 222 #define PCIS_SERIALBUS_SSA 0x02 223 #define PCIS_SERIALBUS_USB 0x03 224 #define PCIS_SERIALBUS_FC 0x04 225 #define PCIS_SERIALBUS 226 #define PCIS_SERIALBUS 227 228 #define PCIC_OTHER 0xff 229 230 /* some PCI vendor definitions (only used to identify ancient devices !!! */ 231 232 #define PCIV_INTEL 0x8086 233 234 #define PCID_INTEL_SATURN 0x0483 235 #define PCID_INTEL_ORION 0x84c4 236 237 /* for compatibility to FreeBSD-2.2 version of PCI code */ 238 239 #ifdef PCI_COMPAT 240 241 #define PCI_ID_REG 0x00 242 #define PCI_COMMAND_STATUS_REG 0x04 243 #define PCI_COMMAND_IO_ENABLE 0x00000001 244 #define PCI_COMMAND_MEM_ENABLE 0x00000002 245 #define PCI_CLASS_REG 0x08 246 #define PCI_CLASS_MASK 0xff000000 247 #define PCI_SUBCLASS_MASK 0x00ff0000 248 #define PCI_REVISION_MASK 0x000000ff 249 #define PCI_CLASS_PREHISTORIC 0x00000000 250 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 251 #define PCI_CLASS_MASS_STORAGE 0x01000000 252 #define PCI_CLASS_DISPLAY 0x03000000 253 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 254 #define PCI_CLASS_BRIDGE 0x06000000 255 #define PCI_MAP_REG_START 0x10 256 #define PCI_MAP_REG_END 0x28 257 #define PCI_MAP_IO 0x00000001 258 #define PCI_INTERRUPT_REG 0x3c 259 260 #endif /* PCI_COMPAT */ 261