1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42 /* some PCI bus constants */ 43 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44 #define PCI_BUSMAX 255 /* highest supported bus number */ 45 #define PCI_SLOTMAX 31 /* highest supported slot number */ 46 #define PCI_FUNCMAX 7 /* highest supported function number */ 47 #define PCI_REGMAX 255 /* highest supported config register addr. */ 48 #define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49 #define PCI_MAXHDRTYPE 2 50 51 /* PCI config header registers for all devices */ 52 53 #define PCIR_DEVVENDOR 0x00 54 #define PCIR_VENDOR 0x00 55 #define PCIR_DEVICE 0x02 56 #define PCIR_COMMAND 0x04 57 #define PCIM_CMD_PORTEN 0x0001 58 #define PCIM_CMD_MEMEN 0x0002 59 #define PCIM_CMD_BUSMASTEREN 0x0004 60 #define PCIM_CMD_SPECIALEN 0x0008 61 #define PCIM_CMD_MWRICEN 0x0010 62 #define PCIM_CMD_PERRESPEN 0x0040 63 #define PCIM_CMD_SERRESPEN 0x0100 64 #define PCIM_CMD_BACKTOBACK 0x0200 65 #define PCIM_CMD_INTxDIS 0x0400 66 #define PCIR_STATUS 0x06 67 #define PCIM_STATUS_INTxSTATE 0x0008 68 #define PCIM_STATUS_CAPPRESENT 0x0010 69 #define PCIM_STATUS_66CAPABLE 0x0020 70 #define PCIM_STATUS_BACKTOBACK 0x0080 71 #define PCIM_STATUS_MDPERR 0x0100 72 #define PCIM_STATUS_SEL_FAST 0x0000 73 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 74 #define PCIM_STATUS_SEL_SLOW 0x0400 75 #define PCIM_STATUS_SEL_MASK 0x0600 76 #define PCIM_STATUS_STABORT 0x0800 77 #define PCIM_STATUS_RTABORT 0x1000 78 #define PCIM_STATUS_RMABORT 0x2000 79 #define PCIM_STATUS_SERR 0x4000 80 #define PCIM_STATUS_PERR 0x8000 81 #define PCIR_REVID 0x08 82 #define PCIR_PROGIF 0x09 83 #define PCIR_SUBCLASS 0x0a 84 #define PCIR_CLASS 0x0b 85 #define PCIR_CACHELNSZ 0x0c 86 #define PCIR_LATTIMER 0x0d 87 #define PCIR_HDRTYPE 0x0e 88 #define PCIM_HDRTYPE 0x7f 89 #define PCIM_HDRTYPE_NORMAL 0x00 90 #define PCIM_HDRTYPE_BRIDGE 0x01 91 #define PCIM_HDRTYPE_CARDBUS 0x02 92 #define PCIM_MFDEV 0x80 93 #define PCIR_BIST 0x0f 94 95 /* Capability Register Offsets */ 96 97 #define PCICAP_ID 0x0 98 #define PCICAP_NEXTPTR 0x1 99 100 /* Capability Identification Numbers */ 101 102 #define PCIY_PMG 0x01 /* PCI Power Management */ 103 #define PCIY_AGP 0x02 /* AGP */ 104 #define PCIY_VPD 0x03 /* Vital Product Data */ 105 #define PCIY_SLOTID 0x04 /* Slot Identification */ 106 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 107 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 108 #define PCIY_PCIX 0x07 /* PCI-X */ 109 #define PCIY_HT 0x08 /* HyperTransport */ 110 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 111 #define PCIY_DEBUG 0x0a /* Debug port */ 112 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 113 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 114 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 115 #define PCIY_AGP8X 0x0e /* AGP 8x */ 116 #define PCIY_SECDEV 0x0f /* Secure Device */ 117 #define PCIY_EXPRESS 0x10 /* PCI Express */ 118 #define PCIY_MSIX 0x11 /* MSI-X */ 119 #define PCIY_SATA 0x12 /* SATA */ 120 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 121 122 /* Extended Capability Register Fields */ 123 124 #define PCIR_EXTCAP 0x100 125 #define PCIM_EXTCAP_ID 0x0000ffff 126 #define PCIM_EXTCAP_VER 0x000f0000 127 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 128 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 129 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 130 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 131 132 /* Extended Capability Identification Numbers */ 133 134 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 135 #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 136 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 137 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 138 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 139 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 140 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 141 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 142 #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 143 #define PCIZ_RCRB 0x000a /* RCRB Header */ 144 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 145 #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 146 #define PCIZ_ACS 0x000d /* Access Control Services */ 147 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 148 #define PCIZ_ATS 0x000f /* Address Translation Services */ 149 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 150 #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 151 #define PCIZ_MULTICAST 0x0012 /* Multicast */ 152 #define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 153 #define PCIZ_AMD 0x0014 /* Reserved for AMD */ 154 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 155 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 156 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 157 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 158 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 159 #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 160 #define PCIZ_PASID 0x001b /* Process Address Space ID */ 161 #define PCIZ_LN_REQ 0x001c /* LN Requester */ 162 #define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 163 #define PCIZ_L1PM 0x001e /* L1 PM Substates */ 164 165 /* config registers for header type 0 devices */ 166 167 #define PCIR_BARS 0x10 168 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 169 #define PCIR_MAX_BAR_0 5 170 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 171 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 172 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 173 #define PCIM_BAR_SPACE 0x00000001 174 #define PCIM_BAR_MEM_SPACE 0 175 #define PCIM_BAR_IO_SPACE 1 176 #define PCIM_BAR_MEM_TYPE 0x00000006 177 #define PCIM_BAR_MEM_32 0 178 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 179 #define PCIM_BAR_MEM_64 4 180 #define PCIM_BAR_MEM_PREFETCH 0x00000008 181 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 182 #define PCIM_BAR_IO_RESERVED 0x00000002 183 #define PCIM_BAR_IO_BASE 0xfffffffc 184 #define PCIR_CIS 0x28 185 #define PCIM_CIS_ASI_MASK 0x00000007 186 #define PCIM_CIS_ASI_CONFIG 0 187 #define PCIM_CIS_ASI_BAR0 1 188 #define PCIM_CIS_ASI_BAR1 2 189 #define PCIM_CIS_ASI_BAR2 3 190 #define PCIM_CIS_ASI_BAR3 4 191 #define PCIM_CIS_ASI_BAR4 5 192 #define PCIM_CIS_ASI_BAR5 6 193 #define PCIM_CIS_ASI_ROM 7 194 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 195 #define PCIM_CIS_ROM_MASK 0xf0000000 196 #define PCIM_CIS_CONFIG_MASK 0xff 197 #define PCIR_SUBVEND_0 0x2c 198 #define PCIR_SUBDEV_0 0x2e 199 #define PCIR_BIOS 0x30 200 #define PCIM_BIOS_ENABLE 0x01 201 #define PCIM_BIOS_ADDR_MASK 0xfffff800 202 #define PCIR_CAP_PTR 0x34 203 #define PCIR_INTLINE 0x3c 204 #define PCIR_INTPIN 0x3d 205 #define PCIR_MINGNT 0x3e 206 #define PCIR_MAXLAT 0x3f 207 208 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 209 210 #define PCIR_MAX_BAR_1 1 211 #define PCIR_SECSTAT_1 0x1e 212 213 #define PCIR_PRIBUS_1 0x18 214 #define PCIR_SECBUS_1 0x19 215 #define PCIR_SUBBUS_1 0x1a 216 #define PCIR_SECLAT_1 0x1b 217 218 #define PCIR_IOBASEL_1 0x1c 219 #define PCIR_IOLIMITL_1 0x1d 220 #define PCIR_IOBASEH_1 0x30 221 #define PCIR_IOLIMITH_1 0x32 222 #define PCIM_BRIO_16 0x0 223 #define PCIM_BRIO_32 0x1 224 #define PCIM_BRIO_MASK 0xf 225 226 #define PCIR_MEMBASE_1 0x20 227 #define PCIR_MEMLIMIT_1 0x22 228 229 #define PCIR_PMBASEL_1 0x24 230 #define PCIR_PMLIMITL_1 0x26 231 #define PCIR_PMBASEH_1 0x28 232 #define PCIR_PMLIMITH_1 0x2c 233 #define PCIM_BRPM_32 0x0 234 #define PCIM_BRPM_64 0x1 235 #define PCIM_BRPM_MASK 0xf 236 237 #define PCIR_BIOS_1 0x38 238 #define PCIR_BRIDGECTL_1 0x3e 239 240 /* config registers for header type 2 (CardBus) devices */ 241 242 #define PCIR_MAX_BAR_2 0 243 #define PCIR_CAP_PTR_2 0x14 244 #define PCIR_SECSTAT_2 0x16 245 246 #define PCIR_PRIBUS_2 0x18 247 #define PCIR_SECBUS_2 0x19 248 #define PCIR_SUBBUS_2 0x1a 249 #define PCIR_SECLAT_2 0x1b 250 251 #define PCIR_MEMBASE0_2 0x1c 252 #define PCIR_MEMLIMIT0_2 0x20 253 #define PCIR_MEMBASE1_2 0x24 254 #define PCIR_MEMLIMIT1_2 0x28 255 #define PCIR_IOBASE0_2 0x2c 256 #define PCIR_IOLIMIT0_2 0x30 257 #define PCIR_IOBASE1_2 0x34 258 #define PCIR_IOLIMIT1_2 0x38 259 260 #define PCIR_BRIDGECTL_2 0x3e 261 262 #define PCIR_SUBVEND_2 0x40 263 #define PCIR_SUBDEV_2 0x42 264 265 #define PCIR_PCCARDIF_2 0x44 266 267 /* PCI device class, subclass and programming interface definitions */ 268 269 #define PCIC_OLD 0x00 270 #define PCIS_OLD_NONVGA 0x00 271 #define PCIS_OLD_VGA 0x01 272 273 #define PCIC_STORAGE 0x01 274 #define PCIS_STORAGE_SCSI 0x00 275 #define PCIS_STORAGE_IDE 0x01 276 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 277 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 278 #define PCIP_STORAGE_IDE_MODESEC 0x04 279 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 280 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 281 #define PCIS_STORAGE_FLOPPY 0x02 282 #define PCIS_STORAGE_IPI 0x03 283 #define PCIS_STORAGE_RAID 0x04 284 #define PCIS_STORAGE_ATA_ADMA 0x05 285 #define PCIS_STORAGE_SATA 0x06 286 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 287 #define PCIS_STORAGE_SAS 0x07 288 #define PCIS_STORAGE_NVM 0x08 289 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 290 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 291 #define PCIS_STORAGE_OTHER 0x80 292 293 #define PCIC_NETWORK 0x02 294 #define PCIS_NETWORK_ETHERNET 0x00 295 #define PCIS_NETWORK_TOKENRING 0x01 296 #define PCIS_NETWORK_FDDI 0x02 297 #define PCIS_NETWORK_ATM 0x03 298 #define PCIS_NETWORK_ISDN 0x04 299 #define PCIS_NETWORK_WORLDFIP 0x05 300 #define PCIS_NETWORK_PICMG 0x06 301 #define PCIS_NETWORK_OTHER 0x80 302 303 #define PCIC_DISPLAY 0x03 304 #define PCIS_DISPLAY_VGA 0x00 305 #define PCIS_DISPLAY_XGA 0x01 306 #define PCIS_DISPLAY_3D 0x02 307 #define PCIS_DISPLAY_OTHER 0x80 308 309 #define PCIC_MULTIMEDIA 0x04 310 #define PCIS_MULTIMEDIA_VIDEO 0x00 311 #define PCIS_MULTIMEDIA_AUDIO 0x01 312 #define PCIS_MULTIMEDIA_TELE 0x02 313 #define PCIS_MULTIMEDIA_HDA 0x03 314 #define PCIS_MULTIMEDIA_OTHER 0x80 315 316 #define PCIC_MEMORY 0x05 317 #define PCIS_MEMORY_RAM 0x00 318 #define PCIS_MEMORY_FLASH 0x01 319 #define PCIS_MEMORY_OTHER 0x80 320 321 #define PCIC_BRIDGE 0x06 322 #define PCIS_BRIDGE_HOST 0x00 323 #define PCIS_BRIDGE_ISA 0x01 324 #define PCIS_BRIDGE_EISA 0x02 325 #define PCIS_BRIDGE_MCA 0x03 326 #define PCIS_BRIDGE_PCI 0x04 327 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 328 #define PCIS_BRIDGE_PCMCIA 0x05 329 #define PCIS_BRIDGE_NUBUS 0x06 330 #define PCIS_BRIDGE_CARDBUS 0x07 331 #define PCIS_BRIDGE_RACEWAY 0x08 332 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 333 #define PCIS_BRIDGE_INFINIBAND 0x0a 334 #define PCIS_BRIDGE_OTHER 0x80 335 336 #define PCIC_SIMPLECOMM 0x07 337 #define PCIS_SIMPLECOMM_UART 0x00 338 #define PCIP_SIMPLECOMM_UART_8250 0x00 339 #define PCIP_SIMPLECOMM_UART_16450A 0x01 340 #define PCIP_SIMPLECOMM_UART_16550A 0x02 341 #define PCIP_SIMPLECOMM_UART_16650A 0x03 342 #define PCIP_SIMPLECOMM_UART_16750A 0x04 343 #define PCIP_SIMPLECOMM_UART_16850A 0x05 344 #define PCIP_SIMPLECOMM_UART_16950A 0x06 345 #define PCIS_SIMPLECOMM_PAR 0x01 346 #define PCIS_SIMPLECOMM_MULSER 0x02 347 #define PCIS_SIMPLECOMM_MODEM 0x03 348 #define PCIS_SIMPLECOMM_GPIB 0x04 349 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 350 #define PCIS_SIMPLECOMM_OTHER 0x80 351 352 #define PCIC_BASEPERIPH 0x08 353 #define PCIS_BASEPERIPH_PIC 0x00 354 #define PCIP_BASEPERIPH_PIC_8259A 0x00 355 #define PCIP_BASEPERIPH_PIC_ISA 0x01 356 #define PCIP_BASEPERIPH_PIC_EISA 0x02 357 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 358 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 359 #define PCIS_BASEPERIPH_DMA 0x01 360 #define PCIS_BASEPERIPH_TIMER 0x02 361 #define PCIS_BASEPERIPH_RTC 0x03 362 #define PCIS_BASEPERIPH_PCIHOT 0x04 363 #define PCIS_BASEPERIPH_SDHC 0x05 364 #define PCIS_BASEPERIPH_OTHER 0x80 365 366 #define PCIC_INPUTDEV 0x09 367 #define PCIS_INPUTDEV_KEYBOARD 0x00 368 #define PCIS_INPUTDEV_DIGITIZER 0x01 369 #define PCIS_INPUTDEV_MOUSE 0x02 370 #define PCIS_INPUTDEV_SCANNER 0x03 371 #define PCIS_INPUTDEV_GAMEPORT 0x04 372 #define PCIS_INPUTDEV_OTHER 0x80 373 374 #define PCIC_DOCKING 0x0a 375 #define PCIS_DOCKING_GENERIC 0x00 376 #define PCIS_DOCKING_OTHER 0x80 377 378 #define PCIC_PROCESSOR 0x0b 379 #define PCIS_PROCESSOR_386 0x00 380 #define PCIS_PROCESSOR_486 0x01 381 #define PCIS_PROCESSOR_PENTIUM 0x02 382 #define PCIS_PROCESSOR_ALPHA 0x10 383 #define PCIS_PROCESSOR_POWERPC 0x20 384 #define PCIS_PROCESSOR_MIPS 0x30 385 #define PCIS_PROCESSOR_COPROC 0x40 386 387 #define PCIC_SERIALBUS 0x0c 388 #define PCIS_SERIALBUS_FW 0x00 389 #define PCIS_SERIALBUS_ACCESS 0x01 390 #define PCIS_SERIALBUS_SSA 0x02 391 #define PCIS_SERIALBUS_USB 0x03 392 #define PCIP_SERIALBUS_USB_UHCI 0x00 393 #define PCIP_SERIALBUS_USB_OHCI 0x10 394 #define PCIP_SERIALBUS_USB_EHCI 0x20 395 #define PCIP_SERIALBUS_USB_XHCI 0x30 396 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 397 #define PCIS_SERIALBUS_FC 0x04 398 #define PCIS_SERIALBUS_SMBUS 0x05 399 #define PCIS_SERIALBUS_INFINIBAND 0x06 400 #define PCIS_SERIALBUS_IPMI 0x07 401 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 402 #define PCIP_SERIALBUS_IPMI_KCS 0x01 403 #define PCIP_SERIALBUS_IPMI_BT 0x02 404 #define PCIS_SERIALBUS_SERCOS 0x08 405 #define PCIS_SERIALBUS_CANBUS 0x09 406 407 #define PCIC_WIRELESS 0x0d 408 #define PCIS_WIRELESS_IRDA 0x00 409 #define PCIS_WIRELESS_IR 0x01 410 #define PCIS_WIRELESS_RF 0x10 411 #define PCIS_WIRELESS_BLUETOOTH 0x11 412 #define PCIS_WIRELESS_BROADBAND 0x12 413 #define PCIS_WIRELESS_80211A 0x20 414 #define PCIS_WIRELESS_80211B 0x21 415 #define PCIS_WIRELESS_OTHER 0x80 416 417 #define PCIC_INTELLIIO 0x0e 418 #define PCIS_INTELLIIO_I2O 0x00 419 420 #define PCIC_SATCOM 0x0f 421 #define PCIS_SATCOM_TV 0x01 422 #define PCIS_SATCOM_AUDIO 0x02 423 #define PCIS_SATCOM_VOICE 0x03 424 #define PCIS_SATCOM_DATA 0x04 425 426 #define PCIC_CRYPTO 0x10 427 #define PCIS_CRYPTO_NETCOMP 0x00 428 #define PCIS_CRYPTO_ENTERTAIN 0x10 429 #define PCIS_CRYPTO_OTHER 0x80 430 431 #define PCIC_DASP 0x11 432 #define PCIS_DASP_DPIO 0x00 433 #define PCIS_DASP_PERFCNTRS 0x01 434 #define PCIS_DASP_COMM_SYNC 0x10 435 #define PCIS_DASP_MGMT_CARD 0x20 436 #define PCIS_DASP_OTHER 0x80 437 438 #define PCIC_OTHER 0xff 439 440 /* Bridge Control Values. */ 441 #define PCIB_BCR_PERR_ENABLE 0x0001 442 #define PCIB_BCR_SERR_ENABLE 0x0002 443 #define PCIB_BCR_ISA_ENABLE 0x0004 444 #define PCIB_BCR_VGA_ENABLE 0x0008 445 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 446 #define PCIB_BCR_SECBUS_RESET 0x0040 447 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 448 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 449 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 450 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 451 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 452 453 /* PCI power manangement */ 454 #define PCIR_POWER_CAP 0x2 455 #define PCIM_PCAP_SPEC 0x0007 456 #define PCIM_PCAP_PMEREQCLK 0x0008 457 #define PCIM_PCAP_DEVSPECINIT 0x0020 458 #define PCIM_PCAP_AUXPWR_0 0x0000 459 #define PCIM_PCAP_AUXPWR_55 0x0040 460 #define PCIM_PCAP_AUXPWR_100 0x0080 461 #define PCIM_PCAP_AUXPWR_160 0x00c0 462 #define PCIM_PCAP_AUXPWR_220 0x0100 463 #define PCIM_PCAP_AUXPWR_270 0x0140 464 #define PCIM_PCAP_AUXPWR_320 0x0180 465 #define PCIM_PCAP_AUXPWR_375 0x01c0 466 #define PCIM_PCAP_AUXPWRMASK 0x01c0 467 #define PCIM_PCAP_D1SUPP 0x0200 468 #define PCIM_PCAP_D2SUPP 0x0400 469 #define PCIM_PCAP_D0PME 0x0800 470 #define PCIM_PCAP_D1PME 0x1000 471 #define PCIM_PCAP_D2PME 0x2000 472 #define PCIM_PCAP_D3PME_HOT 0x4000 473 #define PCIM_PCAP_D3PME_COLD 0x8000 474 475 #define PCIR_POWER_STATUS 0x4 476 #define PCIM_PSTAT_D0 0x0000 477 #define PCIM_PSTAT_D1 0x0001 478 #define PCIM_PSTAT_D2 0x0002 479 #define PCIM_PSTAT_D3 0x0003 480 #define PCIM_PSTAT_DMASK 0x0003 481 #define PCIM_PSTAT_NOSOFTRESET 0x0008 482 #define PCIM_PSTAT_PMEENABLE 0x0100 483 #define PCIM_PSTAT_D0POWER 0x0000 484 #define PCIM_PSTAT_D1POWER 0x0200 485 #define PCIM_PSTAT_D2POWER 0x0400 486 #define PCIM_PSTAT_D3POWER 0x0600 487 #define PCIM_PSTAT_D0HEAT 0x0800 488 #define PCIM_PSTAT_D1HEAT 0x0a00 489 #define PCIM_PSTAT_D2HEAT 0x0c00 490 #define PCIM_PSTAT_D3HEAT 0x0e00 491 #define PCIM_PSTAT_DATASELMASK 0x1e00 492 #define PCIM_PSTAT_DATAUNKN 0x0000 493 #define PCIM_PSTAT_DATADIV10 0x2000 494 #define PCIM_PSTAT_DATADIV100 0x4000 495 #define PCIM_PSTAT_DATADIV1000 0x6000 496 #define PCIM_PSTAT_DATADIVMASK 0x6000 497 #define PCIM_PSTAT_PME 0x8000 498 499 #define PCIR_POWER_BSE 0x6 500 #define PCIM_PMCSR_BSE_D3B3 0x00 501 #define PCIM_PMCSR_BSE_D3B2 0x40 502 #define PCIM_PMCSR_BSE_BPCCE 0x80 503 504 #define PCIR_POWER_DATA 0x7 505 506 /* VPD capability registers */ 507 #define PCIR_VPD_ADDR 0x2 508 #define PCIR_VPD_DATA 0x4 509 510 /* PCI Message Signalled Interrupts (MSI) */ 511 #define PCIR_MSI_CTRL 0x2 512 #define PCIM_MSICTRL_VECTOR 0x0100 513 #define PCIM_MSICTRL_64BIT 0x0080 514 #define PCIM_MSICTRL_MME_MASK 0x0070 515 #define PCIM_MSICTRL_MME_1 0x0000 516 #define PCIM_MSICTRL_MME_2 0x0010 517 #define PCIM_MSICTRL_MME_4 0x0020 518 #define PCIM_MSICTRL_MME_8 0x0030 519 #define PCIM_MSICTRL_MME_16 0x0040 520 #define PCIM_MSICTRL_MME_32 0x0050 521 #define PCIM_MSICTRL_MMC_MASK 0x000E 522 #define PCIM_MSICTRL_MMC_1 0x0000 523 #define PCIM_MSICTRL_MMC_2 0x0002 524 #define PCIM_MSICTRL_MMC_4 0x0004 525 #define PCIM_MSICTRL_MMC_8 0x0006 526 #define PCIM_MSICTRL_MMC_16 0x0008 527 #define PCIM_MSICTRL_MMC_32 0x000A 528 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 529 #define PCIR_MSI_ADDR 0x4 530 #define PCIR_MSI_ADDR_HIGH 0x8 531 #define PCIR_MSI_DATA 0x8 532 #define PCIR_MSI_DATA_64BIT 0xc 533 #define PCIR_MSI_MASK 0x10 534 #define PCIR_MSI_PENDING 0x14 535 536 /* PCI-X definitions */ 537 538 /* For header type 0 devices */ 539 #define PCIXR_COMMAND 0x2 540 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 541 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 542 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 543 #define PCIXM_COMMAND_MAX_READ_512 0x0000 544 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 545 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 546 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 547 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 548 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 549 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 550 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 551 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 552 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 553 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 554 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 555 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 556 #define PCIXM_COMMAND_VERSION 0x3000 557 #define PCIXR_STATUS 0x4 558 #define PCIXM_STATUS_DEVFN 0x000000FF 559 #define PCIXM_STATUS_BUS 0x0000FF00 560 #define PCIXM_STATUS_64BIT 0x00010000 561 #define PCIXM_STATUS_133CAP 0x00020000 562 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 563 #define PCIXM_STATUS_UNEXP_SC 0x00080000 564 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 565 #define PCIXM_STATUS_MAX_READ 0x00600000 566 #define PCIXM_STATUS_MAX_READ_512 0x00000000 567 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 568 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 569 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 570 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 571 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 572 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 573 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 574 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 575 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 576 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 577 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 578 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 579 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 580 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 581 #define PCIXM_STATUS_266CAP 0x40000000 582 #define PCIXM_STATUS_533CAP 0x80000000 583 584 /* For header type 1 devices (PCI-X bridges) */ 585 #define PCIXR_SEC_STATUS 0x2 586 #define PCIXM_SEC_STATUS_64BIT 0x0001 587 #define PCIXM_SEC_STATUS_133CAP 0x0002 588 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 589 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 590 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 591 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 592 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 593 #define PCIXM_SEC_STATUS_VERSION 0x3000 594 #define PCIXM_SEC_STATUS_266CAP 0x4000 595 #define PCIXM_SEC_STATUS_533CAP 0x8000 596 #define PCIXR_BRIDGE_STATUS 0x4 597 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 598 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 599 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 600 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 601 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 602 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 603 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 604 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 605 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 606 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 607 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 608 609 /* HT (HyperTransport) Capability definitions */ 610 #define PCIR_HT_COMMAND 0x2 611 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 612 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 613 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 614 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 615 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 616 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 617 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 618 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 619 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 620 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 621 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 622 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 623 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 624 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 625 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 626 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 627 #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 628 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 629 630 /* HT MSI Mapping Capability definitions. */ 631 #define PCIM_HTCMD_MSI_ENABLE 0x0001 632 #define PCIM_HTCMD_MSI_FIXED 0x0002 633 #define PCIR_HTMSI_ADDRESS_LO 0x4 634 #define PCIR_HTMSI_ADDRESS_HI 0x8 635 636 /* PCI Vendor capability definitions */ 637 #define PCIR_VENDOR_LENGTH 0x2 638 #define PCIR_VENDOR_DATA 0x3 639 640 /* PCI EHCI Debug Port definitions */ 641 #define PCIR_DEBUG_PORT 0x2 642 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 643 #define PCIM_DEBUG_PORT_BAR 0xe000 644 645 /* PCI-PCI Bridge Subvendor definitions */ 646 #define PCIR_SUBVENDCAP_ID 0x4 647 648 /* PCI Express definitions */ 649 #define PCIER_FLAGS 0x2 650 #define PCIEM_FLAGS_VERSION 0x000F 651 #define PCIEM_FLAGS_TYPE 0x00F0 652 #define PCIEM_TYPE_ENDPOINT 0x0000 653 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 654 #define PCIEM_TYPE_ROOT_PORT 0x0040 655 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 656 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 657 #define PCIEM_TYPE_PCI_BRIDGE 0x0070 658 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 659 #define PCIEM_TYPE_ROOT_INT_EP 0x0090 660 #define PCIEM_TYPE_ROOT_EC 0x00a0 661 #define PCIEM_FLAGS_SLOT 0x0100 662 #define PCIEM_FLAGS_IRQ 0x3e00 663 #define PCIER_DEVICE_CAP 0x4 664 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 665 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 666 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 667 #define PCIEM_CAP_L0S_LATENCY 0x000001c0 668 #define PCIEM_CAP_L1_LATENCY 0x00000e00 669 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 670 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 671 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 672 #define PCIEM_CAP_FLR 0x10000000 673 #define PCIER_DEVICE_CTL 0x8 674 #define PCIEM_CTL_COR_ENABLE 0x0001 675 #define PCIEM_CTL_NFER_ENABLE 0x0002 676 #define PCIEM_CTL_FER_ENABLE 0x0004 677 #define PCIEM_CTL_URR_ENABLE 0x0008 678 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 679 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 680 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 681 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 682 #define PCIEM_CTL_AUX_POWER_PM 0x0400 683 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 684 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 685 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 686 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 687 #define PCIER_DEVICE_STA 0xa 688 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 689 #define PCIEM_STA_NON_FATAL_ERROR 0x0002 690 #define PCIEM_STA_FATAL_ERROR 0x0004 691 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 692 #define PCIEM_STA_AUX_POWER 0x0010 693 #define PCIEM_STA_TRANSACTION_PND 0x0020 694 #define PCIER_LINK_CAP 0xc 695 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 696 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 697 #define PCIEM_LINK_CAP_ASPM 0x00000c00 698 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 699 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 700 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 701 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 702 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 703 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 704 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 705 #define PCIEM_LINK_CAP_PORT 0xff000000 706 #define PCIER_LINK_CTL 0x10 707 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 708 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 709 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 710 #define PCIEM_LINK_CTL_ASPMC 0x0003 711 #define PCIEM_LINK_CTL_RCB 0x0008 712 #define PCIEM_LINK_CTL_LINK_DIS 0x0010 713 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 714 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 715 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 716 #define PCIEM_LINK_CTL_ECPM 0x0100 717 #define PCIEM_LINK_CTL_HAWD 0x0200 718 #define PCIEM_LINK_CTL_LBMIE 0x0400 719 #define PCIEM_LINK_CTL_LABIE 0x0800 720 #define PCIER_LINK_STA 0x12 721 #define PCIEM_LINK_STA_SPEED 0x000f 722 #define PCIEM_LINK_STA_WIDTH 0x03f0 723 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 724 #define PCIEM_LINK_STA_TRAINING 0x0800 725 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 726 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 727 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 728 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 729 #define PCIER_SLOT_CAP 0x14 730 #define PCIEM_SLOT_CAP_APB 0x00000001 731 #define PCIEM_SLOT_CAP_PCP 0x00000002 732 #define PCIEM_SLOT_CAP_MRLSP 0x00000004 733 #define PCIEM_SLOT_CAP_AIP 0x00000008 734 #define PCIEM_SLOT_CAP_PIP 0x00000010 735 #define PCIEM_SLOT_CAP_HPS 0x00000020 736 #define PCIEM_SLOT_CAP_HPC 0x00000040 737 #define PCIEM_SLOT_CAP_SPLV 0x00007f80 738 #define PCIEM_SLOT_CAP_SPLS 0x00018000 739 #define PCIEM_SLOT_CAP_EIP 0x00020000 740 #define PCIEM_SLOT_CAP_NCCS 0x00040000 741 #define PCIEM_SLOT_CAP_PSN 0xfff80000 742 #define PCIER_SLOT_CTL 0x18 743 #define PCIEM_SLOT_CTL_ABPE 0x0001 744 #define PCIEM_SLOT_CTL_PFDE 0x0002 745 #define PCIEM_SLOT_CTL_MRLSCE 0x0004 746 #define PCIEM_SLOT_CTL_PDCE 0x0008 747 #define PCIEM_SLOT_CTL_CCIE 0x0010 748 #define PCIEM_SLOT_CTL_HPIE 0x0020 749 #define PCIEM_SLOT_CTL_AIC 0x00c0 750 #define PCIEM_SLOT_CTL_PIC 0x0300 751 #define PCIEM_SLOT_CTL_PCC 0x0400 752 #define PCIEM_SLOT_CTL_EIC 0x0800 753 #define PCIEM_SLOT_CTL_DLLSCE 0x1000 754 #define PCIER_SLOT_STA 0x1a 755 #define PCIEM_SLOT_STA_ABP 0x0001 756 #define PCIEM_SLOT_STA_PFD 0x0002 757 #define PCIEM_SLOT_STA_MRLSC 0x0004 758 #define PCIEM_SLOT_STA_PDC 0x0008 759 #define PCIEM_SLOT_STA_CC 0x0010 760 #define PCIEM_SLOT_STA_MRLSS 0x0020 761 #define PCIEM_SLOT_STA_PDS 0x0040 762 #define PCIEM_SLOT_STA_EIS 0x0080 763 #define PCIEM_SLOT_STA_DLLSC 0x0100 764 #define PCIER_ROOT_CTL 0x1c 765 #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 766 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 767 #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 768 #define PCIEM_ROOT_CTL_PME 0x0008 769 #define PCIEM_ROOT_CTL_CRS_VIS 0x0010 770 #define PCIER_ROOT_CAP 0x1e 771 #define PCIEM_ROOT_CAP_CRS_VIS 0x0001 772 #define PCIER_ROOT_STA 0x20 773 #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 774 #define PCIEM_ROOT_STA_PME_STATUS 0x00010000 775 #define PCIEM_ROOT_STA_PME_PEND 0x00020000 776 #define PCIER_DEVICE_CAP2 0x24 777 #define PCIER_DEVICE_CTL2 0x28 778 #define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 779 #define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 780 #define PCIEM_CTL2_ARI 0x0020 781 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 782 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 783 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 784 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 785 #define PCIEM_CTL2_LTR_ENABLE 0x0400 786 #define PCIEM_CTL2_OBFF 0x6000 787 #define PCIEM_OBFF_DISABLE 0x0000 788 #define PCIEM_OBFF_MSGA_ENABLE 0x2000 789 #define PCIEM_OBFF_MSGB_ENABLE 0x4000 790 #define PCIEM_OBFF_WAKE_ENABLE 0x6000 791 #define PCIEM_CTL2_END2END_TLP 0x8000 792 #define PCIER_DEVICE_STA2 0x2a 793 #define PCIER_LINK_CAP2 0x2c 794 #define PCIER_LINK_CTL2 0x30 795 #define PCIER_LINK_STA2 0x32 796 #define PCIER_SLOT_CAP2 0x34 797 #define PCIER_SLOT_CTL2 0x38 798 #define PCIER_SLOT_STA2 0x3a 799 800 /* MSI-X definitions */ 801 #define PCIR_MSIX_CTRL 0x2 802 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 803 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 804 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 805 #define PCIR_MSIX_TABLE 0x4 806 #define PCIR_MSIX_PBA 0x8 807 #define PCIM_MSIX_BIR_MASK 0x7 808 #define PCIM_MSIX_BIR_BAR_10 0 809 #define PCIM_MSIX_BIR_BAR_14 1 810 #define PCIM_MSIX_BIR_BAR_18 2 811 #define PCIM_MSIX_BIR_BAR_1C 3 812 #define PCIM_MSIX_BIR_BAR_20 4 813 #define PCIM_MSIX_BIR_BAR_24 5 814 #define PCIM_MSIX_VCTRL_MASK 0x1 815 816 /* PCI Advanced Features definitions */ 817 #define PCIR_PCIAF_CAP 0x3 818 #define PCIM_PCIAFCAP_TP 0x01 819 #define PCIM_PCIAFCAP_FLR 0x02 820 #define PCIR_PCIAF_CTRL 0x4 821 #define PCIR_PCIAFCTRL_FLR 0x01 822 #define PCIR_PCIAF_STATUS 0x5 823 #define PCIR_PCIAFSTATUS_TP 0x01 824 825 /* Advanced Error Reporting */ 826 #define PCIR_AER_UC_STATUS 0x04 827 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 828 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 829 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 830 #define PCIM_AER_UC_POISONED_TLP 0x00001000 831 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 832 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 833 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 834 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 835 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 836 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 837 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 838 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 839 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 840 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 841 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 842 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 843 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 844 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 845 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 846 #define PCIR_AER_COR_STATUS 0x10 847 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 848 #define PCIM_AER_COR_BAD_TLP 0x00000040 849 #define PCIM_AER_COR_BAD_DLLP 0x00000080 850 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 851 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 852 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 853 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 854 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 855 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 856 #define PCIR_AER_CAP_CONTROL 0x18 857 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 858 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 859 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 860 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 861 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 862 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 863 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 864 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 865 #define PCIR_AER_HEADER_LOG 0x1c 866 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 867 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 868 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 869 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 870 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 871 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 872 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 873 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 874 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 875 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 876 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 877 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 878 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 879 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 880 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 881 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 882 883 /* Virtual Channel definitions */ 884 #define PCIR_VC_CAP1 0x04 885 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 886 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 887 #define PCIR_VC_CAP2 0x08 888 #define PCIR_VC_CONTROL 0x0C 889 #define PCIR_VC_STATUS 0x0E 890 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 891 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 892 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 893 894 /* Serial Number definitions */ 895 #define PCIR_SERIAL_LOW 0x04 896 #define PCIR_SERIAL_HIGH 0x08 897