1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 */ 40 41 /* some PCI bus constants */ 42 43 #define PCI_BUSMAX 255 44 #define PCI_SLOTMAX 31 45 #define PCI_FUNCMAX 7 46 #define PCI_REGMAX 255 47 #define PCI_MAXHDRTYPE 2 48 49 /* PCI config header registers for all devices */ 50 51 #define PCIR_DEVVENDOR 0x00 52 #define PCIR_VENDOR 0x00 53 #define PCIR_DEVICE 0x02 54 #define PCIR_COMMAND 0x04 55 #define PCIM_CMD_PORTEN 0x0001 56 #define PCIM_CMD_MEMEN 0x0002 57 #define PCIM_CMD_BUSMASTEREN 0x0004 58 #define PCIM_CMD_SPECIALEN 0x0008 59 #define PCIM_CMD_MWRICEN 0x0010 60 #define PCIM_CMD_PERRESPEN 0x0040 61 #define PCIM_CMD_SERRESPEN 0x0100 62 #define PCIM_CMD_BACKTOBACK 0x0200 63 #define PCIM_CMD_INTxDIS 0x0400 64 #define PCIR_STATUS 0x06 65 #define PCIM_STATUS_CAPPRESENT 0x0010 66 #define PCIM_STATUS_66CAPABLE 0x0020 67 #define PCIM_STATUS_BACKTOBACK 0x0080 68 #define PCIM_STATUS_PERRREPORT 0x0100 69 #define PCIM_STATUS_SEL_FAST 0x0000 70 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 71 #define PCIM_STATUS_SEL_SLOW 0x0400 72 #define PCIM_STATUS_SEL_MASK 0x0600 73 #define PCIM_STATUS_STABORT 0x0800 74 #define PCIM_STATUS_RTABORT 0x1000 75 #define PCIM_STATUS_RMABORT 0x2000 76 #define PCIM_STATUS_SERR 0x4000 77 #define PCIM_STATUS_PERR 0x8000 78 #define PCIR_REVID 0x08 79 #define PCIR_PROGIF 0x09 80 #define PCIR_SUBCLASS 0x0a 81 #define PCIR_CLASS 0x0b 82 #define PCIR_CACHELNSZ 0x0c 83 #define PCIR_LATTIMER 0x0d 84 #define PCIR_HDRTYPE 0x0e 85 #define PCIM_HDRTYPE 0x7f 86 #define PCIM_HDRTYPE_NORMAL 0x00 87 #define PCIM_HDRTYPE_BRIDGE 0x01 88 #define PCIM_HDRTYPE_CARDBUS 0x02 89 #define PCIM_MFDEV 0x80 90 #define PCIR_BIST 0x0f 91 92 /* Capability Register Offsets */ 93 94 #define PCICAP_ID 0x0 95 #define PCICAP_NEXTPTR 0x1 96 97 /* Capability Identification Numbers */ 98 99 #define PCIY_PMG 0x01 /* PCI Power Management */ 100 #define PCIY_AGP 0x02 /* AGP */ 101 #define PCIY_VPD 0x03 /* Vital Product Data */ 102 #define PCIY_SLOTID 0x04 /* Slot Identification */ 103 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 104 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 105 #define PCIY_PCIX 0x07 /* PCI-X */ 106 #define PCIY_HT 0x08 /* HyperTransport */ 107 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 108 #define PCIY_DEBUG 0x0a /* Debug port */ 109 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 110 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 111 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 112 #define PCIY_AGP8X 0x0e /* AGP 8x */ 113 #define PCIY_SECDEV 0x0f /* Secure Device */ 114 #define PCIY_EXPRESS 0x10 /* PCI Express */ 115 #define PCIY_MSIX 0x11 /* MSI-X */ 116 #define PCIY_SATA 0x12 /* SATA */ 117 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 118 119 /* config registers for header type 0 devices */ 120 121 #define PCIR_BARS 0x10 122 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 123 #define PCIR_MAX_BAR_0 5 124 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 125 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 126 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 127 #define PCIM_BAR_SPACE 0x00000001 128 #define PCIM_BAR_MEM_SPACE 0 129 #define PCIM_BAR_IO_SPACE 1 130 #define PCIM_BAR_MEM_TYPE 0x00000006 131 #define PCIM_BAR_MEM_32 0 132 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 133 #define PCIM_BAR_MEM_64 4 134 #define PCIM_BAR_MEM_PREFETCH 0x00000008 135 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 136 #define PCIM_BAR_IO_RESERVED 0x00000002 137 #define PCIM_BAR_IO_BASE 0xfffffffc 138 #define PCIR_CIS 0x28 139 #define PCIM_CIS_ASI_MASK 0x00000007 140 #define PCIM_CIS_ASI_CONFIG 0 141 #define PCIM_CIS_ASI_BAR0 1 142 #define PCIM_CIS_ASI_BAR1 2 143 #define PCIM_CIS_ASI_BAR2 3 144 #define PCIM_CIS_ASI_BAR3 4 145 #define PCIM_CIS_ASI_BAR4 5 146 #define PCIM_CIS_ASI_BAR5 6 147 #define PCIM_CIS_ASI_ROM 7 148 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 149 #define PCIM_CIS_ROM_MASK 0xf0000000 150 #define PCIM_CIS_CONFIG_MASK 0xff 151 #define PCIR_SUBVEND_0 0x2c 152 #define PCIR_SUBDEV_0 0x2e 153 #define PCIR_BIOS 0x30 154 #define PCIM_BIOS_ENABLE 0x01 155 #define PCIM_BIOS_ADDR_MASK 0xfffff800 156 #define PCIR_CAP_PTR 0x34 157 #define PCIR_INTLINE 0x3c 158 #define PCIR_INTPIN 0x3d 159 #define PCIR_MINGNT 0x3e 160 #define PCIR_MAXLAT 0x3f 161 162 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 163 164 #define PCIR_MAX_BAR_1 1 165 #define PCIR_SECSTAT_1 0x1e 166 167 #define PCIR_PRIBUS_1 0x18 168 #define PCIR_SECBUS_1 0x19 169 #define PCIR_SUBBUS_1 0x1a 170 #define PCIR_SECLAT_1 0x1b 171 172 #define PCIR_IOBASEL_1 0x1c 173 #define PCIR_IOLIMITL_1 0x1d 174 #define PCIR_IOBASEH_1 0x30 175 #define PCIR_IOLIMITH_1 0x32 176 #define PCIM_BRIO_16 0x0 177 #define PCIM_BRIO_32 0x1 178 #define PCIM_BRIO_MASK 0xf 179 180 #define PCIR_MEMBASE_1 0x20 181 #define PCIR_MEMLIMIT_1 0x22 182 183 #define PCIR_PMBASEL_1 0x24 184 #define PCIR_PMLIMITL_1 0x26 185 #define PCIR_PMBASEH_1 0x28 186 #define PCIR_PMLIMITH_1 0x2c 187 #define PCIM_BRPM_32 0x0 188 #define PCIM_BRPM_64 0x1 189 #define PCIM_BRPM_MASK 0xf 190 191 #define PCIR_BRIDGECTL_1 0x3e 192 193 /* config registers for header type 2 (CardBus) devices */ 194 195 #define PCIR_MAX_BAR_2 0 196 #define PCIR_CAP_PTR_2 0x14 197 #define PCIR_SECSTAT_2 0x16 198 199 #define PCIR_PRIBUS_2 0x18 200 #define PCIR_SECBUS_2 0x19 201 #define PCIR_SUBBUS_2 0x1a 202 #define PCIR_SECLAT_2 0x1b 203 204 #define PCIR_MEMBASE0_2 0x1c 205 #define PCIR_MEMLIMIT0_2 0x20 206 #define PCIR_MEMBASE1_2 0x24 207 #define PCIR_MEMLIMIT1_2 0x28 208 #define PCIR_IOBASE0_2 0x2c 209 #define PCIR_IOLIMIT0_2 0x30 210 #define PCIR_IOBASE1_2 0x34 211 #define PCIR_IOLIMIT1_2 0x38 212 213 #define PCIR_BRIDGECTL_2 0x3e 214 215 #define PCIR_SUBVEND_2 0x40 216 #define PCIR_SUBDEV_2 0x42 217 218 #define PCIR_PCCARDIF_2 0x44 219 220 /* PCI device class, subclass and programming interface definitions */ 221 222 #define PCIC_OLD 0x00 223 #define PCIS_OLD_NONVGA 0x00 224 #define PCIS_OLD_VGA 0x01 225 226 #define PCIC_STORAGE 0x01 227 #define PCIS_STORAGE_SCSI 0x00 228 #define PCIS_STORAGE_IDE 0x01 229 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 230 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 231 #define PCIP_STORAGE_IDE_MODESEC 0x04 232 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 233 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 234 #define PCIS_STORAGE_FLOPPY 0x02 235 #define PCIS_STORAGE_IPI 0x03 236 #define PCIS_STORAGE_RAID 0x04 237 #define PCIS_STORAGE_ATA_ADMA 0x05 238 #define PCIS_STORAGE_SATA 0x06 239 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 240 #define PCIS_STORAGE_SAS 0x07 241 #define PCIS_STORAGE_OTHER 0x80 242 243 #define PCIC_NETWORK 0x02 244 #define PCIS_NETWORK_ETHERNET 0x00 245 #define PCIS_NETWORK_TOKENRING 0x01 246 #define PCIS_NETWORK_FDDI 0x02 247 #define PCIS_NETWORK_ATM 0x03 248 #define PCIS_NETWORK_ISDN 0x04 249 #define PCIS_NETWORK_WORLDFIP 0x05 250 #define PCIS_NETWORK_PICMG 0x06 251 #define PCIS_NETWORK_OTHER 0x80 252 253 #define PCIC_DISPLAY 0x03 254 #define PCIS_DISPLAY_VGA 0x00 255 #define PCIS_DISPLAY_XGA 0x01 256 #define PCIS_DISPLAY_3D 0x02 257 #define PCIS_DISPLAY_OTHER 0x80 258 259 #define PCIC_MULTIMEDIA 0x04 260 #define PCIS_MULTIMEDIA_VIDEO 0x00 261 #define PCIS_MULTIMEDIA_AUDIO 0x01 262 #define PCIS_MULTIMEDIA_TELE 0x02 263 #define PCIS_MULTIMEDIA_HDA 0x03 264 #define PCIS_MULTIMEDIA_OTHER 0x80 265 266 #define PCIC_MEMORY 0x05 267 #define PCIS_MEMORY_RAM 0x00 268 #define PCIS_MEMORY_FLASH 0x01 269 #define PCIS_MEMORY_OTHER 0x80 270 271 #define PCIC_BRIDGE 0x06 272 #define PCIS_BRIDGE_HOST 0x00 273 #define PCIS_BRIDGE_ISA 0x01 274 #define PCIS_BRIDGE_EISA 0x02 275 #define PCIS_BRIDGE_MCA 0x03 276 #define PCIS_BRIDGE_PCI 0x04 277 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 278 #define PCIS_BRIDGE_PCMCIA 0x05 279 #define PCIS_BRIDGE_NUBUS 0x06 280 #define PCIS_BRIDGE_CARDBUS 0x07 281 #define PCIS_BRIDGE_RACEWAY 0x08 282 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 283 #define PCIS_BRIDGE_INFINIBAND 0x0a 284 #define PCIS_BRIDGE_OTHER 0x80 285 286 #define PCIC_SIMPLECOMM 0x07 287 #define PCIS_SIMPLECOMM_UART 0x00 288 #define PCIP_SIMPLECOMM_UART_8250 0x00 289 #define PCIP_SIMPLECOMM_UART_16450A 0x01 290 #define PCIP_SIMPLECOMM_UART_16550A 0x02 291 #define PCIP_SIMPLECOMM_UART_16650A 0x03 292 #define PCIP_SIMPLECOMM_UART_16750A 0x04 293 #define PCIP_SIMPLECOMM_UART_16850A 0x05 294 #define PCIP_SIMPLECOMM_UART_16950A 0x06 295 #define PCIS_SIMPLECOMM_PAR 0x01 296 #define PCIS_SIMPLECOMM_MULSER 0x02 297 #define PCIS_SIMPLECOMM_MODEM 0x03 298 #define PCIS_SIMPLECOMM_GPIB 0x04 299 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 300 #define PCIS_SIMPLECOMM_OTHER 0x80 301 302 #define PCIC_BASEPERIPH 0x08 303 #define PCIS_BASEPERIPH_PIC 0x00 304 #define PCIP_BASEPERIPH_PIC_8259A 0x00 305 #define PCIP_BASEPERIPH_PIC_ISA 0x01 306 #define PCIP_BASEPERIPH_PIC_EISA 0x02 307 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 308 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 309 #define PCIS_BASEPERIPH_DMA 0x01 310 #define PCIS_BASEPERIPH_TIMER 0x02 311 #define PCIS_BASEPERIPH_RTC 0x03 312 #define PCIS_BASEPERIPH_PCIHOT 0x04 313 #define PCIS_BASEPERIPH_SDHC 0x05 314 #define PCIS_BASEPERIPH_OTHER 0x80 315 316 #define PCIC_INPUTDEV 0x09 317 #define PCIS_INPUTDEV_KEYBOARD 0x00 318 #define PCIS_INPUTDEV_DIGITIZER 0x01 319 #define PCIS_INPUTDEV_MOUSE 0x02 320 #define PCIS_INPUTDEV_SCANNER 0x03 321 #define PCIS_INPUTDEV_GAMEPORT 0x04 322 #define PCIS_INPUTDEV_OTHER 0x80 323 324 #define PCIC_DOCKING 0x0a 325 #define PCIS_DOCKING_GENERIC 0x00 326 #define PCIS_DOCKING_OTHER 0x80 327 328 #define PCIC_PROCESSOR 0x0b 329 #define PCIS_PROCESSOR_386 0x00 330 #define PCIS_PROCESSOR_486 0x01 331 #define PCIS_PROCESSOR_PENTIUM 0x02 332 #define PCIS_PROCESSOR_ALPHA 0x10 333 #define PCIS_PROCESSOR_POWERPC 0x20 334 #define PCIS_PROCESSOR_MIPS 0x30 335 #define PCIS_PROCESSOR_COPROC 0x40 336 337 #define PCIC_SERIALBUS 0x0c 338 #define PCIS_SERIALBUS_FW 0x00 339 #define PCIS_SERIALBUS_ACCESS 0x01 340 #define PCIS_SERIALBUS_SSA 0x02 341 #define PCIS_SERIALBUS_USB 0x03 342 #define PCIP_SERIALBUS_USB_UHCI 0x00 343 #define PCIP_SERIALBUS_USB_OHCI 0x10 344 #define PCIP_SERIALBUS_USB_EHCI 0x20 345 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 346 #define PCIS_SERIALBUS_FC 0x04 347 #define PCIS_SERIALBUS_SMBUS 0x05 348 #define PCIS_SERIALBUS_INFINIBAND 0x06 349 #define PCIS_SERIALBUS_IPMI 0x07 350 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 351 #define PCIP_SERIALBUS_IPMI_KCS 0x01 352 #define PCIP_SERIALBUS_IPMI_BT 0x02 353 #define PCIS_SERIALBUS_SERCOS 0x08 354 #define PCIS_SERIALBUS_CANBUS 0x09 355 356 #define PCIC_WIRELESS 0x0d 357 #define PCIS_WIRELESS_IRDA 0x00 358 #define PCIS_WIRELESS_IR 0x01 359 #define PCIS_WIRELESS_RF 0x10 360 #define PCIS_WIRELESS_BLUETOOTH 0x11 361 #define PCIS_WIRELESS_BROADBAND 0x12 362 #define PCIS_WIRELESS_80211A 0x20 363 #define PCIS_WIRELESS_80211B 0x21 364 #define PCIS_WIRELESS_OTHER 0x80 365 366 #define PCIC_INTELLIIO 0x0e 367 #define PCIS_INTELLIIO_I2O 0x00 368 369 #define PCIC_SATCOM 0x0f 370 #define PCIS_SATCOM_TV 0x01 371 #define PCIS_SATCOM_AUDIO 0x02 372 #define PCIS_SATCOM_VOICE 0x03 373 #define PCIS_SATCOM_DATA 0x04 374 375 #define PCIC_CRYPTO 0x10 376 #define PCIS_CRYPTO_NETCOMP 0x00 377 #define PCIS_CRYPTO_ENTERTAIN 0x10 378 #define PCIS_CRYPTO_OTHER 0x80 379 380 #define PCIC_DASP 0x11 381 #define PCIS_DASP_DPIO 0x00 382 #define PCIS_DASP_PERFCNTRS 0x01 383 #define PCIS_DASP_COMM_SYNC 0x10 384 #define PCIS_DASP_MGMT_CARD 0x20 385 #define PCIS_DASP_OTHER 0x80 386 387 #define PCIC_OTHER 0xff 388 389 /* Bridge Control Values. */ 390 #define PCIB_BCR_PERR_ENABLE 0x0001 391 #define PCIB_BCR_SERR_ENABLE 0x0002 392 #define PCIB_BCR_ISA_ENABLE 0x0004 393 #define PCIB_BCR_VGA_ENABLE 0x0008 394 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 395 #define PCIB_BCR_SECBUS_RESET 0x0040 396 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 397 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 398 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 399 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 400 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 401 402 /* PCI power manangement */ 403 #define PCIR_POWER_CAP 0x2 404 #define PCIM_PCAP_SPEC 0x0007 405 #define PCIM_PCAP_PMEREQCLK 0x0008 406 #define PCIM_PCAP_PMEREQPWR 0x0010 407 #define PCIM_PCAP_DEVSPECINIT 0x0020 408 #define PCIM_PCAP_DYNCLOCK 0x0040 409 #define PCIM_PCAP_SECCLOCK 0x00c0 410 #define PCIM_PCAP_CLOCKMASK 0x00c0 411 #define PCIM_PCAP_REQFULLCLOCK 0x0100 412 #define PCIM_PCAP_D1SUPP 0x0200 413 #define PCIM_PCAP_D2SUPP 0x0400 414 #define PCIM_PCAP_D0PME 0x0800 415 #define PCIM_PCAP_D1PME 0x1000 416 #define PCIM_PCAP_D2PME 0x2000 417 #define PCIM_PCAP_D3PME_HOT 0x4000 418 #define PCIM_PCAP_D3PME_COLD 0x8000 419 420 #define PCIR_POWER_STATUS 0x4 421 #define PCIM_PSTAT_D0 0x0000 422 #define PCIM_PSTAT_D1 0x0001 423 #define PCIM_PSTAT_D2 0x0002 424 #define PCIM_PSTAT_D3 0x0003 425 #define PCIM_PSTAT_DMASK 0x0003 426 #define PCIM_PSTAT_REPENABLE 0x0010 427 #define PCIM_PSTAT_PMEENABLE 0x0100 428 #define PCIM_PSTAT_D0POWER 0x0000 429 #define PCIM_PSTAT_D1POWER 0x0200 430 #define PCIM_PSTAT_D2POWER 0x0400 431 #define PCIM_PSTAT_D3POWER 0x0600 432 #define PCIM_PSTAT_D0HEAT 0x0800 433 #define PCIM_PSTAT_D1HEAT 0x1000 434 #define PCIM_PSTAT_D2HEAT 0x1200 435 #define PCIM_PSTAT_D3HEAT 0x1400 436 #define PCIM_PSTAT_DATAUNKN 0x0000 437 #define PCIM_PSTAT_DATADIV10 0x2000 438 #define PCIM_PSTAT_DATADIV100 0x4000 439 #define PCIM_PSTAT_DATADIV1000 0x6000 440 #define PCIM_PSTAT_DATADIVMASK 0x6000 441 #define PCIM_PSTAT_PME 0x8000 442 443 #define PCIR_POWER_PMCSR 0x6 444 #define PCIM_PMCSR_DCLOCK 0x10 445 #define PCIM_PMCSR_B2SUPP 0x20 446 #define PCIM_BMCSR_B3SUPP 0x40 447 #define PCIM_BMCSR_BPCE 0x80 448 449 #define PCIR_POWER_DATA 0x7 450 451 /* VPD capability registers */ 452 #define PCIR_VPD_ADDR 0x2 453 #define PCIR_VPD_DATA 0x4 454 455 /* PCI Message Signalled Interrupts (MSI) */ 456 #define PCIR_MSI_CTRL 0x2 457 #define PCIM_MSICTRL_VECTOR 0x0100 458 #define PCIM_MSICTRL_64BIT 0x0080 459 #define PCIM_MSICTRL_MME_MASK 0x0070 460 #define PCIM_MSICTRL_MME_1 0x0000 461 #define PCIM_MSICTRL_MME_2 0x0010 462 #define PCIM_MSICTRL_MME_4 0x0020 463 #define PCIM_MSICTRL_MME_8 0x0030 464 #define PCIM_MSICTRL_MME_16 0x0040 465 #define PCIM_MSICTRL_MME_32 0x0050 466 #define PCIM_MSICTRL_MMC_MASK 0x000E 467 #define PCIM_MSICTRL_MMC_1 0x0000 468 #define PCIM_MSICTRL_MMC_2 0x0002 469 #define PCIM_MSICTRL_MMC_4 0x0004 470 #define PCIM_MSICTRL_MMC_8 0x0006 471 #define PCIM_MSICTRL_MMC_16 0x0008 472 #define PCIM_MSICTRL_MMC_32 0x000A 473 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 474 #define PCIR_MSI_ADDR 0x4 475 #define PCIR_MSI_ADDR_HIGH 0x8 476 #define PCIR_MSI_DATA 0x8 477 #define PCIR_MSI_DATA_64BIT 0xc 478 #define PCIR_MSI_MASK 0x10 479 #define PCIR_MSI_PENDING 0x14 480 481 /* PCI-X definitions */ 482 483 /* For header type 0 devices */ 484 #define PCIXR_COMMAND 0x2 485 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 486 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 487 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 488 #define PCIXM_COMMAND_MAX_READ_512 0x0000 489 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 490 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 491 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 492 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 493 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 494 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 495 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 496 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 497 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 498 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 499 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 500 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 501 #define PCIXM_COMMAND_VERSION 0x3000 502 #define PCIXR_STATUS 0x4 503 #define PCIXM_STATUS_DEVFN 0x000000FF 504 #define PCIXM_STATUS_BUS 0x0000FF00 505 #define PCIXM_STATUS_64BIT 0x00010000 506 #define PCIXM_STATUS_133CAP 0x00020000 507 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 508 #define PCIXM_STATUS_UNEXP_SC 0x00080000 509 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 510 #define PCIXM_STATUS_MAX_READ 0x00600000 511 #define PCIXM_STATUS_MAX_READ_512 0x00000000 512 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 513 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 514 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 515 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 516 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 517 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 518 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 519 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 520 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 521 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 522 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 523 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 524 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 525 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 526 #define PCIXM_STATUS_266CAP 0x40000000 527 #define PCIXM_STATUS_533CAP 0x80000000 528 529 /* For header type 1 devices (PCI-X bridges) */ 530 #define PCIXR_SEC_STATUS 0x2 531 #define PCIXM_SEC_STATUS_64BIT 0x0001 532 #define PCIXM_SEC_STATUS_133CAP 0x0002 533 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 534 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 535 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 536 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 537 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 538 #define PCIXM_SEC_STATUS_VERSION 0x3000 539 #define PCIXM_SEC_STATUS_266CAP 0x4000 540 #define PCIXM_SEC_STATUS_533CAP 0x8000 541 #define PCIXR_BRIDGE_STATUS 0x4 542 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 543 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 544 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 545 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 546 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 547 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 548 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 549 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 550 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 551 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 552 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 553 554 /* HT (HyperTransport) Capability definitions */ 555 #define PCIR_HT_COMMAND 0x2 556 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 557 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 558 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 559 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 560 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 561 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 562 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 563 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 564 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 565 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 566 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 567 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 568 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 569 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 570 571 /* HT MSI Mapping Capability definitions. */ 572 #define PCIM_HTCMD_MSI_ENABLE 0x0001 573 #define PCIM_HTCMD_MSI_FIXED 0x0002 574 #define PCIR_HTMSI_ADDRESS_LO 0x4 575 #define PCIR_HTMSI_ADDRESS_HI 0x8 576 577 /* PCI Vendor capability definitions */ 578 #define PCIR_VENDOR_LENGTH 0x2 579 #define PCIR_VENDOR_DATA 0x3 580 581 /* PCI EHCI Debug Port definitions */ 582 #define PCIR_DEBUG_PORT 0x2 583 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 584 #define PCIM_DEBUG_PORT_BAR 0xe000 585 586 /* PCI-PCI Bridge Subvendor definitions */ 587 #define PCIR_SUBVENDCAP_ID 0x4 588 589 /* PCI Express definitions */ 590 #define PCIR_EXPRESS_FLAGS 0x2 591 #define PCIM_EXP_FLAGS_VERSION 0x000F 592 #define PCIM_EXP_FLAGS_TYPE 0x00F0 593 #define PCIM_EXP_TYPE_ENDPOINT 0x0000 594 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 595 #define PCIM_EXP_TYPE_ROOT_PORT 0x0040 596 #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 597 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 598 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 599 #define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 600 #define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 601 #define PCIM_EXP_TYPE_ROOT_EC 0x00a0 602 #define PCIM_EXP_FLAGS_SLOT 0x0100 603 #define PCIM_EXP_FLAGS_IRQ 0x3e00 604 #define PCIR_EXPRESS_DEVICE_CAP 0x4 605 #define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 606 #define PCIR_EXPRESS_DEVICE_CTL 0x8 607 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 608 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 609 #define PCIR_EXPRESS_DEVICE_STA 0xa 610 #define PCIR_EXPRESS_LINK_CAP 0xc 611 #define PCIM_LINK_CAP_MAX_SPEED 0x0000000f 612 #define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 613 #define PCIM_LINK_CAP_ASPM 0x00000c00 614 #define PCIM_LINK_CAP_L0S_EXIT 0x00007000 615 #define PCIM_LINK_CAP_L1_EXIT 0x00038000 616 #define PCIM_LINK_CAP_PORT 0xff000000 617 #define PCIR_EXPRESS_LINK_CTL 0x10 618 #define PCIR_EXPRESS_LINK_STA 0x12 619 #define PCIM_LINK_STA_SPEED 0x000f 620 #define PCIM_LINK_STA_WIDTH 0x03f0 621 #define PCIM_LINK_STA_TRAINING_ERROR 0x0400 622 #define PCIM_LINK_STA_TRAINING 0x0800 623 #define PCIM_LINK_STA_SLOT_CLOCK 0x1000 624 #define PCIR_EXPRESS_SLOT_CAP 0x14 625 #define PCIR_EXPRESS_SLOT_CTL 0x18 626 #define PCIR_EXPRESS_SLOT_STA 0x1a 627 #define PCIR_EXPRESS_ROOT_CTL 0x1c 628 #define PCIR_EXPRESS_ROOT_STA 0x20 629 630 /* MSI-X definitions */ 631 #define PCIR_MSIX_CTRL 0x2 632 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 633 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 634 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 635 #define PCIR_MSIX_TABLE 0x4 636 #define PCIR_MSIX_PBA 0x8 637 #define PCIM_MSIX_BIR_MASK 0x7 638 #define PCIM_MSIX_BIR_BAR_10 0 639 #define PCIM_MSIX_BIR_BAR_14 1 640 #define PCIM_MSIX_BIR_BAR_18 2 641 #define PCIM_MSIX_BIR_BAR_1C 3 642 #define PCIM_MSIX_BIR_BAR_20 4 643 #define PCIM_MSIX_BIR_BAR_24 5 644 #define PCIM_MSIX_VCTRL_MASK 0x1 645 646 /* PCI Advanced Features definitions */ 647 #define PCIR_PCIAF_CAP 0x3 648 #define PCIM_PCIAFCAP_TP 0x01 649 #define PCIM_PCIAFCAP_FLR 0x02 650 #define PCIR_PCIAF_CTRL 0x4 651 #define PCIR_PCIAFCTRL_FLR 0x01 652 #define PCIR_PCIAF_STATUS 0x5 653 #define PCIR_PCIAFSTATUS_TP 0x01 654