xref: /freebsd/sys/dev/pci/pcireg.h (revision 6990ffd8a95caaba6858ad44ff1b3157d1efba8f)
1 /*
2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  *
28  */
29 
30 /*
31  * PCIM_xxx: mask to locate subfield in register
32  * PCIR_xxx: config register offset
33  * PCIC_xxx: device class
34  * PCIS_xxx: device subclass
35  * PCIP_xxx: device programming interface
36  * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
37  * PCID_xxx: device ID
38  */
39 
40 /* some PCI bus constants */
41 
42 #define PCI_BUSMAX	255
43 #define PCI_SLOTMAX	31
44 #define PCI_FUNCMAX	7
45 #define PCI_REGMAX	255
46 
47 /* PCI config header registers for all devices */
48 
49 #define PCIR_DEVVENDOR	0x00
50 #define PCIR_VENDOR	0x00
51 #define PCIR_DEVICE	0x02
52 #define PCIR_COMMAND	0x04
53 #define PCIM_CMD_PORTEN		0x0001
54 #define PCIM_CMD_MEMEN		0x0002
55 #define PCIM_CMD_BUSMASTEREN	0x0004
56 #define PCIM_CMD_SPECIALEN	0x0008
57 #define PCIM_CMD_MWRICEN	0x0010
58 #define PCIM_CMD_PERRESPEN	0x0040
59 #define PCIM_CMD_SERREN		0x0100
60 #define PCIM_CMD_BACKTOBACK	0x0200
61 #define PCIR_STATUS	0x06
62 #define PCIM_STATUS_CAPPRESENT	0x0010
63 #define PCIM_STATUS_66CAPABLE	0x0020
64 #define PCIM_STATUS_BACKTOBACK	0x0080
65 #define PCIM_STATUS_PERRREPORT	0x0100
66 #define PCIM_STATUS_SEL_FAST	0x0000
67 #define PCIM_STATUS_SEL_MEDIMUM	0x0200
68 #define PCIM_STATUS_SEL_SLOW	0x0400
69 #define PCIM_STATUS_SEL_MASK	0x0600
70 #define PCIM_STATUS_STABORT	0x0800
71 #define PCIM_STATUS_RTABORT	0x1000
72 #define PCIM_STATUS_RMABORT	0x2000
73 #define PCIM_STATUS_SERR	0x4000
74 #define PCIM_STATUS_PERR	0x8000
75 #define PCIR_REVID	0x08
76 #define PCIR_PROGIF	0x09
77 #define PCIR_SUBCLASS	0x0a
78 #define PCIR_CLASS	0x0b
79 #define PCIR_CACHELNSZ	0x0c
80 #define PCIR_LATTIMER	0x0d
81 #define PCIR_HEADERTYPE	0x0e
82 #define PCIM_MFDEV		0x80
83 #define PCIR_BIST	0x0f
84 
85 /* config registers for header type 0 devices */
86 
87 #define PCIR_MAPS	0x10
88 #define PCIR_CARDBUSCIS	0x28
89 #define PCIR_SUBVEND_0	0x2c
90 #define PCIR_SUBDEV_0	0x2e
91 #define PCIR_BIOS	0x30
92 #define PCIM_BIOS_ENABLE	0x01
93 #define	PCIR_CAP_PTR	0x34
94 #define PCIR_INTLINE	0x3c
95 #define PCIR_INTPIN	0x3d
96 #define PCIR_MINGNT	0x3e
97 #define PCIR_MAXLAT	0x3f
98 
99 /* config registers for header type 1 devices */
100 
101 #define PCIR_SECSTAT_1	0x1e
102 
103 #define PCIR_PRIBUS_1	0x18
104 #define PCIR_SECBUS_1	0x19
105 #define PCIR_SUBBUS_1	0x1a
106 #define PCIR_SECLAT_1	0x1b
107 
108 #define PCIR_IOBASEL_1	0x1c
109 #define PCIR_IOLIMITL_1	0x1d
110 #define PCIR_IOBASEH_1	0x30
111 #define PCIR_IOLIMITH_1	0x32
112 #define PCIM_BRIO_16		0x0
113 #define PCIM_BRIO_32		0x1
114 #define PCIM_BRIO_MASK		0xf
115 
116 #define PCIR_MEMBASE_1	0x20
117 #define PCIR_MEMLIMIT_1	0x22
118 
119 #define PCIR_PMBASEL_1	0x24
120 #define PCIR_PMLIMITL_1	0x26
121 #define PCIR_PMBASEH_1	0x28
122 #define PCIR_PMLIMITH_1	0x2c
123 
124 #define PCIR_BRIDGECTL_1 0x3e
125 
126 #define PCIR_SUBVEND_1	0x34
127 #define PCIR_SUBDEV_1	0x36
128 
129 /* config registers for header type 2 devices */
130 
131 #define PCIR_SECSTAT_2	0x16
132 
133 #define PCIR_PRIBUS_2	0x18
134 #define PCIR_SECBUS_2	0x19
135 #define PCIR_SUBBUS_2	0x1a
136 #define PCIR_SECLAT_2	0x1b
137 
138 #define PCIR_MEMBASE0_2	0x1c
139 #define PCIR_MEMLIMIT0_2 0x20
140 #define PCIR_MEMBASE1_2	0x24
141 #define PCIR_MEMLIMIT1_2 0x28
142 #define PCIR_IOBASE0_2	0x2c
143 #define PCIR_IOLIMIT0_2	0x30
144 #define PCIR_IOBASE1_2	0x34
145 #define PCIR_IOLIMIT1_2	0x38
146 
147 #define PCIR_BRIDGECTL_2 0x3e
148 
149 #define PCIR_SUBVEND_2	0x40
150 #define PCIR_SUBDEV_2	0x42
151 
152 #define PCIR_PCCARDIF_2	0x44
153 
154 /* PCI device class, subclass and programming interface definitions */
155 
156 #define PCIC_OLD	0x00
157 #define PCIS_OLD_NONVGA		0x00
158 #define PCIS_OLD_VGA		0x01
159 
160 #define PCIC_STORAGE	0x01
161 #define PCIS_STORAGE_SCSI	0x00
162 #define PCIS_STORAGE_IDE	0x01
163 #define PCIP_STORAGE_IDE_MODEPRIM	0x01
164 #define PCIP_STORAGE_IDE_PROGINDPRIM	0x02
165 #define PCIP_STORAGE_IDE_MODESEC	0x04
166 #define PCIP_STORAGE_IDE_PROGINDSEC	0x08
167 #define PCIP_STORAGE_IDE_MASTERDEV	0x80
168 #define PCIS_STORAGE_FLOPPY	0x02
169 #define PCIS_STORAGE_IPI	0x03
170 #define PCIS_STORAGE_RAID	0x04
171 #define PCIS_STORAGE_OTHER	0x80
172 
173 #define PCIC_NETWORK	0x02
174 #define PCIS_NETWORK_ETHERNET	0x00
175 #define PCIS_NETWORK_TOKENRING	0x01
176 #define PCIS_NETWORK_FDDI	0x02
177 #define PCIS_NETWORK_ATM	0x03
178 #define PCIS_NETWORK_OTHER	0x80
179 
180 #define PCIC_DISPLAY	0x03
181 #define PCIS_DISPLAY_VGA	0x00
182 #define PCIS_DISPLAY_XGA	0x01
183 #define PCIS_DISPLAY_OTHER	0x80
184 
185 #define PCIC_MULTIMEDIA	0x04
186 #define PCIS_MULTIMEDIA_VIDEO	0x00
187 #define PCIS_MULTIMEDIA_AUDIO	0x01
188 #define PCIS_MULTIMEDIA_OTHER	0x80
189 
190 #define PCIC_MEMORY	0x05
191 #define PCIS_MEMORY_RAM		0x00
192 #define PCIS_MEMORY_FLASH	0x01
193 #define PCIS_MEMORY_OTHER	0x80
194 
195 #define PCIC_BRIDGE	0x06
196 #define PCIS_BRIDGE_HOST	0x00
197 #define PCIS_BRIDGE_ISA		0x01
198 #define PCIS_BRIDGE_EISA	0x02
199 #define PCIS_BRIDGE_MCA		0x03
200 #define PCIS_BRIDGE_PCI		0x04
201 #define PCIS_BRIDGE_PCMCIA	0x05
202 #define PCIS_BRIDGE_NUBUS	0x06
203 #define PCIS_BRIDGE_CARDBUS	0x07
204 #define PCIS_BRIDGE_OTHER	0x80
205 
206 #define PCIC_SIMPLECOMM	0x07
207 #define PCIS_SIMPLECOMM_UART	0x00
208 #define PCIP_SIMPLECOMM_UART_16550A	0x02
209 #define PCIS_SIMPLECOMM_PAR	0x01
210 #define PCIS_SIMPLECOMM_OTHER	0x80
211 
212 #define PCIC_BASEPERIPH	0x08
213 #define PCIS_BASEPERIPH_PIC	0x00
214 #define PCIS_BASEPERIPH_DMA	0x01
215 #define PCIS_BASEPERIPH_TIMER	0x02
216 #define PCIS_BASEPERIPH_RTC	0x03
217 #define PCIS_BASEPERIPH_OTHER	0x80
218 
219 #define PCIC_INPUTDEV	0x09
220 #define PCIS_INPUTDEV_KEYBOARD	0x00
221 #define PCIS_INPUTDEV_DIGITIZER	0x01
222 #define PCIS_INPUTDEV_MOUSE	0x02
223 #define PCIS_INPUTDEV_OTHER	0x80
224 
225 #define PCIC_DOCKING	0x0a
226 #define PCIS_DOCKING_GENERIC	0x00
227 #define PCIS_DOCKING_OTHER	0x80
228 
229 #define PCIC_PROCESSOR	0x0b
230 #define PCIS_PROCESSOR_386	0x00
231 #define PCIS_PROCESSOR_486	0x01
232 #define PCIS_PROCESSOR_PENTIUM	0x02
233 #define PCIS_PROCESSOR_ALPHA	0x10
234 #define PCIS_PROCESSOR_POWERPC	0x20
235 #define PCIS_PROCESSOR_COPROC	0x40
236 
237 #define PCIC_SERIALBUS	0x0c
238 #define PCIS_SERIALBUS_FW	0x00
239 #define PCIS_SERIALBUS_ACCESS	0x01
240 #define PCIS_SERIALBUS_SSA	0x02
241 #define PCIS_SERIALBUS_USB	0x03
242 #define PCIS_SERIALBUS_FC	0x04
243 #define PCIS_SERIALBUS_SMBUS	0x05
244 
245 #define PCIC_OTHER	0xff
246 
247 /* PCI power manangement */
248 
249 #define PCIR_POWER_CAP		0x2
250 #define PCIM_PCAP_SPEC			0x0007
251 #define PCIM_PCAP_PMEREQCLK		0x0008
252 #define PCIM_PCAP_PMEREQPWR		0x0010
253 #define PCIM_PCAP_DEVSPECINIT		0x0020
254 #define PCIM_PCAP_DYNCLOCK		0x0040
255 #define PCIM_PCAP_SECCLOCK		0x00c0
256 #define PCIM_PCAP_CLOCKMASK		0x00c0
257 #define PCIM_PCAP_REQFULLCLOCK		0x0100
258 #define PCIM_PCAP_D1SUPP		0x0200
259 #define PCIM_PCAP_D2SUPP		0x0400
260 #define PCIM_PCAP_D0PME			0x1000
261 #define PCIM_PCAP_D1PME			0x2000
262 #define PCIM_PCAP_D2PME			0x4000
263 
264 #define PCIR_POWER_STATUS	0x4
265 #define PCIM_PSTAT_D0			0x0000
266 #define PCIM_PSTAT_D1			0x0001
267 #define PCIM_PSTAT_D2			0x0002
268 #define PCIM_PSTAT_D3			0x0003
269 #define PCIM_PSTAT_DMASK		0x0003
270 #define PCIM_PSTAT_REPENABLE		0x0010
271 #define PCIM_PSTAT_PMEENABLE		0x0100
272 #define PCIM_PSTAT_D0POWER		0x0000
273 #define PCIM_PSTAT_D1POWER		0x0200
274 #define PCIM_PSTAT_D2POWER		0x0400
275 #define PCIM_PSTAT_D3POWER		0x0600
276 #define PCIM_PSTAT_D0HEAT		0x0800
277 #define PCIM_PSTAT_D1HEAT		0x1000
278 #define PCIM_PSTAT_D2HEAT		0x1200
279 #define PCIM_PSTAT_D3HEAT		0x1400
280 #define PCIM_PSTAT_DATAUNKN		0x0000
281 #define PCIM_PSTAT_DATADIV10		0x2000
282 #define PCIM_PSTAT_DATADIV100		0x4000
283 #define PCIM_PSTAT_DATADIV1000		0x6000
284 #define PCIM_PSTAT_DATADIVMASK		0x6000
285 #define PCIM_PSTAT_PME			0x8000
286 
287 #define PCIR_POWER_PMCSR	0x6
288 #define PCIM_PMCSR_DCLOCK		0x10
289 #define PCIM_PMCSR_B2SUPP		0x20
290 #define PCIM_BMCSR_B3SUPP		0x40
291 #define PCIM_BMCSR_BPCE			0x80
292 
293 #define PCIR_POWER_DATA		0x7
294 
295 #if 0
296 /* some PCI vendor definitions (only used to identify ancient devices !!! */
297 
298 #define PCIV_INTEL	0x8086
299 
300 #define PCID_INTEL_SATURN	0x0483
301 #define PCID_INTEL_ORION	0x84c4
302 #endif
303