1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42 /* some PCI bus constants */ 43 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44 #define PCI_BUSMAX 255 /* highest supported bus number */ 45 #define PCI_SLOTMAX 31 /* highest supported slot number */ 46 #define PCI_FUNCMAX 7 /* highest supported function number */ 47 #define PCI_REGMAX 255 /* highest supported config register addr. */ 48 #define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49 #define PCI_MAXHDRTYPE 2 50 51 #define PCIE_ARI_SLOTMAX 0 52 #define PCIE_ARI_FUNCMAX 255 53 54 #define PCI_RID_DOMAIN_SHIFT 16 55 #define PCI_RID_BUS_SHIFT 8 56 #define PCI_RID_SLOT_SHIFT 3 57 #define PCI_RID_FUNC_SHIFT 0 58 59 #define PCI_RID(bus, slot, func) \ 60 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 61 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 62 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 63 64 #define PCI_ARI_RID(bus, func) \ 65 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 66 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 67 68 #define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 69 #define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 70 #define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 71 72 #define PCIE_ARI_RID2SLOT(rid) (0) 73 #define PCIE_ARI_RID2FUNC(rid) \ 74 (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX) 75 76 #define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 77 #define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 78 79 /* PCI config header registers for all devices */ 80 81 #define PCIR_DEVVENDOR 0x00 82 #define PCIR_VENDOR 0x00 83 #define PCIR_DEVICE 0x02 84 #define PCIR_COMMAND 0x04 85 #define PCIM_CMD_PORTEN 0x0001 86 #define PCIM_CMD_MEMEN 0x0002 87 #define PCIM_CMD_BUSMASTEREN 0x0004 88 #define PCIM_CMD_SPECIALEN 0x0008 89 #define PCIM_CMD_MWRICEN 0x0010 90 #define PCIM_CMD_PERRESPEN 0x0040 91 #define PCIM_CMD_SERRESPEN 0x0100 92 #define PCIM_CMD_BACKTOBACK 0x0200 93 #define PCIM_CMD_INTxDIS 0x0400 94 #define PCIR_STATUS 0x06 95 #define PCIM_STATUS_INTxSTATE 0x0008 96 #define PCIM_STATUS_CAPPRESENT 0x0010 97 #define PCIM_STATUS_66CAPABLE 0x0020 98 #define PCIM_STATUS_BACKTOBACK 0x0080 99 #define PCIM_STATUS_MDPERR 0x0100 100 #define PCIM_STATUS_SEL_FAST 0x0000 101 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 102 #define PCIM_STATUS_SEL_SLOW 0x0400 103 #define PCIM_STATUS_SEL_MASK 0x0600 104 #define PCIM_STATUS_STABORT 0x0800 105 #define PCIM_STATUS_RTABORT 0x1000 106 #define PCIM_STATUS_RMABORT 0x2000 107 #define PCIM_STATUS_SERR 0x4000 108 #define PCIM_STATUS_PERR 0x8000 109 #define PCIR_REVID 0x08 110 #define PCIR_PROGIF 0x09 111 #define PCIR_SUBCLASS 0x0a 112 #define PCIR_CLASS 0x0b 113 #define PCIR_CACHELNSZ 0x0c 114 #define PCIR_LATTIMER 0x0d 115 #define PCIR_HDRTYPE 0x0e 116 #define PCIM_HDRTYPE 0x7f 117 #define PCIM_HDRTYPE_NORMAL 0x00 118 #define PCIM_HDRTYPE_BRIDGE 0x01 119 #define PCIM_HDRTYPE_CARDBUS 0x02 120 #define PCIM_MFDEV 0x80 121 #define PCIR_BIST 0x0f 122 123 /* Capability Register Offsets */ 124 125 #define PCICAP_ID 0x0 126 #define PCICAP_NEXTPTR 0x1 127 128 /* Capability Identification Numbers */ 129 130 #define PCIY_PMG 0x01 /* PCI Power Management */ 131 #define PCIY_AGP 0x02 /* AGP */ 132 #define PCIY_VPD 0x03 /* Vital Product Data */ 133 #define PCIY_SLOTID 0x04 /* Slot Identification */ 134 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 135 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 136 #define PCIY_PCIX 0x07 /* PCI-X */ 137 #define PCIY_HT 0x08 /* HyperTransport */ 138 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 139 #define PCIY_DEBUG 0x0a /* Debug port */ 140 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 141 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 142 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 143 #define PCIY_AGP8X 0x0e /* AGP 8x */ 144 #define PCIY_SECDEV 0x0f /* Secure Device */ 145 #define PCIY_EXPRESS 0x10 /* PCI Express */ 146 #define PCIY_MSIX 0x11 /* MSI-X */ 147 #define PCIY_SATA 0x12 /* SATA */ 148 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 149 150 /* Extended Capability Register Fields */ 151 152 #define PCIR_EXTCAP 0x100 153 #define PCIM_EXTCAP_ID 0x0000ffff 154 #define PCIM_EXTCAP_VER 0x000f0000 155 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 156 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 157 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 158 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 159 160 /* Extended Capability Identification Numbers */ 161 162 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 163 #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 164 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 165 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 166 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 167 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 168 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 169 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 170 #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 171 #define PCIZ_RCRB 0x000a /* RCRB Header */ 172 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 173 #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 174 #define PCIZ_ACS 0x000d /* Access Control Services */ 175 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 176 #define PCIZ_ATS 0x000f /* Address Translation Services */ 177 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 178 #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 179 #define PCIZ_MULTICAST 0x0012 /* Multicast */ 180 #define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 181 #define PCIZ_AMD 0x0014 /* Reserved for AMD */ 182 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 183 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 184 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 185 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 186 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 187 #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 188 #define PCIZ_PASID 0x001b /* Process Address Space ID */ 189 #define PCIZ_LN_REQ 0x001c /* LN Requester */ 190 #define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 191 #define PCIZ_L1PM 0x001e /* L1 PM Substates */ 192 193 /* config registers for header type 0 devices */ 194 195 #define PCIR_BARS 0x10 196 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 197 #define PCIR_MAX_BAR_0 5 198 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 199 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 200 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 201 #define PCIM_BAR_SPACE 0x00000001 202 #define PCIM_BAR_MEM_SPACE 0 203 #define PCIM_BAR_IO_SPACE 1 204 #define PCIM_BAR_MEM_TYPE 0x00000006 205 #define PCIM_BAR_MEM_32 0 206 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 207 #define PCIM_BAR_MEM_64 4 208 #define PCIM_BAR_MEM_PREFETCH 0x00000008 209 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 210 #define PCIM_BAR_IO_RESERVED 0x00000002 211 #define PCIM_BAR_IO_BASE 0xfffffffc 212 #define PCIR_CIS 0x28 213 #define PCIM_CIS_ASI_MASK 0x00000007 214 #define PCIM_CIS_ASI_CONFIG 0 215 #define PCIM_CIS_ASI_BAR0 1 216 #define PCIM_CIS_ASI_BAR1 2 217 #define PCIM_CIS_ASI_BAR2 3 218 #define PCIM_CIS_ASI_BAR3 4 219 #define PCIM_CIS_ASI_BAR4 5 220 #define PCIM_CIS_ASI_BAR5 6 221 #define PCIM_CIS_ASI_ROM 7 222 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 223 #define PCIM_CIS_ROM_MASK 0xf0000000 224 #define PCIM_CIS_CONFIG_MASK 0xff 225 #define PCIR_SUBVEND_0 0x2c 226 #define PCIR_SUBDEV_0 0x2e 227 #define PCIR_BIOS 0x30 228 #define PCIM_BIOS_ENABLE 0x01 229 #define PCIM_BIOS_ADDR_MASK 0xfffff800 230 #define PCIR_CAP_PTR 0x34 231 #define PCIR_INTLINE 0x3c 232 #define PCIR_INTPIN 0x3d 233 #define PCIR_MINGNT 0x3e 234 #define PCIR_MAXLAT 0x3f 235 236 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 237 238 #define PCIR_MAX_BAR_1 1 239 #define PCIR_SECSTAT_1 0x1e 240 241 #define PCIR_PRIBUS_1 0x18 242 #define PCIR_SECBUS_1 0x19 243 #define PCIR_SUBBUS_1 0x1a 244 #define PCIR_SECLAT_1 0x1b 245 246 #define PCIR_IOBASEL_1 0x1c 247 #define PCIR_IOLIMITL_1 0x1d 248 #define PCIR_IOBASEH_1 0x30 249 #define PCIR_IOLIMITH_1 0x32 250 #define PCIM_BRIO_16 0x0 251 #define PCIM_BRIO_32 0x1 252 #define PCIM_BRIO_MASK 0xf 253 254 #define PCIR_MEMBASE_1 0x20 255 #define PCIR_MEMLIMIT_1 0x22 256 257 #define PCIR_PMBASEL_1 0x24 258 #define PCIR_PMLIMITL_1 0x26 259 #define PCIR_PMBASEH_1 0x28 260 #define PCIR_PMLIMITH_1 0x2c 261 #define PCIM_BRPM_32 0x0 262 #define PCIM_BRPM_64 0x1 263 #define PCIM_BRPM_MASK 0xf 264 265 #define PCIR_BIOS_1 0x38 266 #define PCIR_BRIDGECTL_1 0x3e 267 268 #define PCI_PPBMEMBASE(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 269 #define PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff) 270 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 271 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 272 273 /* config registers for header type 2 (CardBus) devices */ 274 275 #define PCIR_MAX_BAR_2 0 276 #define PCIR_CAP_PTR_2 0x14 277 #define PCIR_SECSTAT_2 0x16 278 279 #define PCIR_PRIBUS_2 0x18 280 #define PCIR_SECBUS_2 0x19 281 #define PCIR_SUBBUS_2 0x1a 282 #define PCIR_SECLAT_2 0x1b 283 284 #define PCIR_MEMBASE0_2 0x1c 285 #define PCIR_MEMLIMIT0_2 0x20 286 #define PCIR_MEMBASE1_2 0x24 287 #define PCIR_MEMLIMIT1_2 0x28 288 #define PCIR_IOBASE0_2 0x2c 289 #define PCIR_IOLIMIT0_2 0x30 290 #define PCIR_IOBASE1_2 0x34 291 #define PCIR_IOLIMIT1_2 0x38 292 #define PCIM_CBBIO_16 0x0 293 #define PCIM_CBBIO_32 0x1 294 #define PCIM_CBBIO_MASK 0x3 295 296 #define PCIR_BRIDGECTL_2 0x3e 297 298 #define PCIR_SUBVEND_2 0x40 299 #define PCIR_SUBDEV_2 0x42 300 301 #define PCIR_PCCARDIF_2 0x44 302 303 #define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) 304 #define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) 305 #define PCI_CBBIOBASE(l) ((l) & ~0x3) 306 #define PCI_CBBIOLIMIT(l) ((l) | 0x3) 307 308 /* PCI device class, subclass and programming interface definitions */ 309 310 #define PCIC_OLD 0x00 311 #define PCIS_OLD_NONVGA 0x00 312 #define PCIS_OLD_VGA 0x01 313 314 #define PCIC_STORAGE 0x01 315 #define PCIS_STORAGE_SCSI 0x00 316 #define PCIS_STORAGE_IDE 0x01 317 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 318 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 319 #define PCIP_STORAGE_IDE_MODESEC 0x04 320 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 321 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 322 #define PCIS_STORAGE_FLOPPY 0x02 323 #define PCIS_STORAGE_IPI 0x03 324 #define PCIS_STORAGE_RAID 0x04 325 #define PCIS_STORAGE_ATA_ADMA 0x05 326 #define PCIS_STORAGE_SATA 0x06 327 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 328 #define PCIS_STORAGE_SAS 0x07 329 #define PCIS_STORAGE_NVM 0x08 330 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 331 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 332 #define PCIS_STORAGE_OTHER 0x80 333 334 #define PCIC_NETWORK 0x02 335 #define PCIS_NETWORK_ETHERNET 0x00 336 #define PCIS_NETWORK_TOKENRING 0x01 337 #define PCIS_NETWORK_FDDI 0x02 338 #define PCIS_NETWORK_ATM 0x03 339 #define PCIS_NETWORK_ISDN 0x04 340 #define PCIS_NETWORK_WORLDFIP 0x05 341 #define PCIS_NETWORK_PICMG 0x06 342 #define PCIS_NETWORK_OTHER 0x80 343 344 #define PCIC_DISPLAY 0x03 345 #define PCIS_DISPLAY_VGA 0x00 346 #define PCIS_DISPLAY_XGA 0x01 347 #define PCIS_DISPLAY_3D 0x02 348 #define PCIS_DISPLAY_OTHER 0x80 349 350 #define PCIC_MULTIMEDIA 0x04 351 #define PCIS_MULTIMEDIA_VIDEO 0x00 352 #define PCIS_MULTIMEDIA_AUDIO 0x01 353 #define PCIS_MULTIMEDIA_TELE 0x02 354 #define PCIS_MULTIMEDIA_HDA 0x03 355 #define PCIS_MULTIMEDIA_OTHER 0x80 356 357 #define PCIC_MEMORY 0x05 358 #define PCIS_MEMORY_RAM 0x00 359 #define PCIS_MEMORY_FLASH 0x01 360 #define PCIS_MEMORY_OTHER 0x80 361 362 #define PCIC_BRIDGE 0x06 363 #define PCIS_BRIDGE_HOST 0x00 364 #define PCIS_BRIDGE_ISA 0x01 365 #define PCIS_BRIDGE_EISA 0x02 366 #define PCIS_BRIDGE_MCA 0x03 367 #define PCIS_BRIDGE_PCI 0x04 368 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 369 #define PCIS_BRIDGE_PCMCIA 0x05 370 #define PCIS_BRIDGE_NUBUS 0x06 371 #define PCIS_BRIDGE_CARDBUS 0x07 372 #define PCIS_BRIDGE_RACEWAY 0x08 373 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 374 #define PCIS_BRIDGE_INFINIBAND 0x0a 375 #define PCIS_BRIDGE_OTHER 0x80 376 377 #define PCIC_SIMPLECOMM 0x07 378 #define PCIS_SIMPLECOMM_UART 0x00 379 #define PCIP_SIMPLECOMM_UART_8250 0x00 380 #define PCIP_SIMPLECOMM_UART_16450A 0x01 381 #define PCIP_SIMPLECOMM_UART_16550A 0x02 382 #define PCIP_SIMPLECOMM_UART_16650A 0x03 383 #define PCIP_SIMPLECOMM_UART_16750A 0x04 384 #define PCIP_SIMPLECOMM_UART_16850A 0x05 385 #define PCIP_SIMPLECOMM_UART_16950A 0x06 386 #define PCIS_SIMPLECOMM_PAR 0x01 387 #define PCIS_SIMPLECOMM_MULSER 0x02 388 #define PCIS_SIMPLECOMM_MODEM 0x03 389 #define PCIS_SIMPLECOMM_GPIB 0x04 390 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 391 #define PCIS_SIMPLECOMM_OTHER 0x80 392 393 #define PCIC_BASEPERIPH 0x08 394 #define PCIS_BASEPERIPH_PIC 0x00 395 #define PCIP_BASEPERIPH_PIC_8259A 0x00 396 #define PCIP_BASEPERIPH_PIC_ISA 0x01 397 #define PCIP_BASEPERIPH_PIC_EISA 0x02 398 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 399 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 400 #define PCIS_BASEPERIPH_DMA 0x01 401 #define PCIS_BASEPERIPH_TIMER 0x02 402 #define PCIS_BASEPERIPH_RTC 0x03 403 #define PCIS_BASEPERIPH_PCIHOT 0x04 404 #define PCIS_BASEPERIPH_SDHC 0x05 405 #define PCIS_BASEPERIPH_IOMMU 0x06 406 #define PCIS_BASEPERIPH_OTHER 0x80 407 408 #define PCIC_INPUTDEV 0x09 409 #define PCIS_INPUTDEV_KEYBOARD 0x00 410 #define PCIS_INPUTDEV_DIGITIZER 0x01 411 #define PCIS_INPUTDEV_MOUSE 0x02 412 #define PCIS_INPUTDEV_SCANNER 0x03 413 #define PCIS_INPUTDEV_GAMEPORT 0x04 414 #define PCIS_INPUTDEV_OTHER 0x80 415 416 #define PCIC_DOCKING 0x0a 417 #define PCIS_DOCKING_GENERIC 0x00 418 #define PCIS_DOCKING_OTHER 0x80 419 420 #define PCIC_PROCESSOR 0x0b 421 #define PCIS_PROCESSOR_386 0x00 422 #define PCIS_PROCESSOR_486 0x01 423 #define PCIS_PROCESSOR_PENTIUM 0x02 424 #define PCIS_PROCESSOR_ALPHA 0x10 425 #define PCIS_PROCESSOR_POWERPC 0x20 426 #define PCIS_PROCESSOR_MIPS 0x30 427 #define PCIS_PROCESSOR_COPROC 0x40 428 429 #define PCIC_SERIALBUS 0x0c 430 #define PCIS_SERIALBUS_FW 0x00 431 #define PCIS_SERIALBUS_ACCESS 0x01 432 #define PCIS_SERIALBUS_SSA 0x02 433 #define PCIS_SERIALBUS_USB 0x03 434 #define PCIP_SERIALBUS_USB_UHCI 0x00 435 #define PCIP_SERIALBUS_USB_OHCI 0x10 436 #define PCIP_SERIALBUS_USB_EHCI 0x20 437 #define PCIP_SERIALBUS_USB_XHCI 0x30 438 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 439 #define PCIS_SERIALBUS_FC 0x04 440 #define PCIS_SERIALBUS_SMBUS 0x05 441 #define PCIS_SERIALBUS_INFINIBAND 0x06 442 #define PCIS_SERIALBUS_IPMI 0x07 443 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 444 #define PCIP_SERIALBUS_IPMI_KCS 0x01 445 #define PCIP_SERIALBUS_IPMI_BT 0x02 446 #define PCIS_SERIALBUS_SERCOS 0x08 447 #define PCIS_SERIALBUS_CANBUS 0x09 448 449 #define PCIC_WIRELESS 0x0d 450 #define PCIS_WIRELESS_IRDA 0x00 451 #define PCIS_WIRELESS_IR 0x01 452 #define PCIS_WIRELESS_RF 0x10 453 #define PCIS_WIRELESS_BLUETOOTH 0x11 454 #define PCIS_WIRELESS_BROADBAND 0x12 455 #define PCIS_WIRELESS_80211A 0x20 456 #define PCIS_WIRELESS_80211B 0x21 457 #define PCIS_WIRELESS_OTHER 0x80 458 459 #define PCIC_INTELLIIO 0x0e 460 #define PCIS_INTELLIIO_I2O 0x00 461 462 #define PCIC_SATCOM 0x0f 463 #define PCIS_SATCOM_TV 0x01 464 #define PCIS_SATCOM_AUDIO 0x02 465 #define PCIS_SATCOM_VOICE 0x03 466 #define PCIS_SATCOM_DATA 0x04 467 468 #define PCIC_CRYPTO 0x10 469 #define PCIS_CRYPTO_NETCOMP 0x00 470 #define PCIS_CRYPTO_ENTERTAIN 0x10 471 #define PCIS_CRYPTO_OTHER 0x80 472 473 #define PCIC_DASP 0x11 474 #define PCIS_DASP_DPIO 0x00 475 #define PCIS_DASP_PERFCNTRS 0x01 476 #define PCIS_DASP_COMM_SYNC 0x10 477 #define PCIS_DASP_MGMT_CARD 0x20 478 #define PCIS_DASP_OTHER 0x80 479 480 #define PCIC_OTHER 0xff 481 482 /* Bridge Control Values. */ 483 #define PCIB_BCR_PERR_ENABLE 0x0001 484 #define PCIB_BCR_SERR_ENABLE 0x0002 485 #define PCIB_BCR_ISA_ENABLE 0x0004 486 #define PCIB_BCR_VGA_ENABLE 0x0008 487 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 488 #define PCIB_BCR_SECBUS_RESET 0x0040 489 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 490 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 491 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 492 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 493 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 494 495 #define CBB_BCR_PERR_ENABLE 0x0001 496 #define CBB_BCR_SERR_ENABLE 0x0002 497 #define CBB_BCR_ISA_ENABLE 0x0004 498 #define CBB_BCR_VGA_ENABLE 0x0008 499 #define CBB_BCR_MASTER_ABORT_MODE 0x0020 500 #define CBB_BCR_CARDBUS_RESET 0x0040 501 #define CBB_BCR_IREQ_INT_ENABLE 0x0080 502 #define CBB_BCR_PREFETCH_0_ENABLE 0x0100 503 #define CBB_BCR_PREFETCH_1_ENABLE 0x0200 504 #define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 505 506 /* PCI power manangement */ 507 #define PCIR_POWER_CAP 0x2 508 #define PCIM_PCAP_SPEC 0x0007 509 #define PCIM_PCAP_PMEREQCLK 0x0008 510 #define PCIM_PCAP_DEVSPECINIT 0x0020 511 #define PCIM_PCAP_AUXPWR_0 0x0000 512 #define PCIM_PCAP_AUXPWR_55 0x0040 513 #define PCIM_PCAP_AUXPWR_100 0x0080 514 #define PCIM_PCAP_AUXPWR_160 0x00c0 515 #define PCIM_PCAP_AUXPWR_220 0x0100 516 #define PCIM_PCAP_AUXPWR_270 0x0140 517 #define PCIM_PCAP_AUXPWR_320 0x0180 518 #define PCIM_PCAP_AUXPWR_375 0x01c0 519 #define PCIM_PCAP_AUXPWRMASK 0x01c0 520 #define PCIM_PCAP_D1SUPP 0x0200 521 #define PCIM_PCAP_D2SUPP 0x0400 522 #define PCIM_PCAP_D0PME 0x0800 523 #define PCIM_PCAP_D1PME 0x1000 524 #define PCIM_PCAP_D2PME 0x2000 525 #define PCIM_PCAP_D3PME_HOT 0x4000 526 #define PCIM_PCAP_D3PME_COLD 0x8000 527 528 #define PCIR_POWER_STATUS 0x4 529 #define PCIM_PSTAT_D0 0x0000 530 #define PCIM_PSTAT_D1 0x0001 531 #define PCIM_PSTAT_D2 0x0002 532 #define PCIM_PSTAT_D3 0x0003 533 #define PCIM_PSTAT_DMASK 0x0003 534 #define PCIM_PSTAT_NOSOFTRESET 0x0008 535 #define PCIM_PSTAT_PMEENABLE 0x0100 536 #define PCIM_PSTAT_D0POWER 0x0000 537 #define PCIM_PSTAT_D1POWER 0x0200 538 #define PCIM_PSTAT_D2POWER 0x0400 539 #define PCIM_PSTAT_D3POWER 0x0600 540 #define PCIM_PSTAT_D0HEAT 0x0800 541 #define PCIM_PSTAT_D1HEAT 0x0a00 542 #define PCIM_PSTAT_D2HEAT 0x0c00 543 #define PCIM_PSTAT_D3HEAT 0x0e00 544 #define PCIM_PSTAT_DATASELMASK 0x1e00 545 #define PCIM_PSTAT_DATAUNKN 0x0000 546 #define PCIM_PSTAT_DATADIV10 0x2000 547 #define PCIM_PSTAT_DATADIV100 0x4000 548 #define PCIM_PSTAT_DATADIV1000 0x6000 549 #define PCIM_PSTAT_DATADIVMASK 0x6000 550 #define PCIM_PSTAT_PME 0x8000 551 552 #define PCIR_POWER_BSE 0x6 553 #define PCIM_PMCSR_BSE_D3B3 0x00 554 #define PCIM_PMCSR_BSE_D3B2 0x40 555 #define PCIM_PMCSR_BSE_BPCCE 0x80 556 557 #define PCIR_POWER_DATA 0x7 558 559 /* VPD capability registers */ 560 #define PCIR_VPD_ADDR 0x2 561 #define PCIR_VPD_DATA 0x4 562 563 /* PCI Message Signalled Interrupts (MSI) */ 564 #define PCIR_MSI_CTRL 0x2 565 #define PCIM_MSICTRL_VECTOR 0x0100 566 #define PCIM_MSICTRL_64BIT 0x0080 567 #define PCIM_MSICTRL_MME_MASK 0x0070 568 #define PCIM_MSICTRL_MME_1 0x0000 569 #define PCIM_MSICTRL_MME_2 0x0010 570 #define PCIM_MSICTRL_MME_4 0x0020 571 #define PCIM_MSICTRL_MME_8 0x0030 572 #define PCIM_MSICTRL_MME_16 0x0040 573 #define PCIM_MSICTRL_MME_32 0x0050 574 #define PCIM_MSICTRL_MMC_MASK 0x000E 575 #define PCIM_MSICTRL_MMC_1 0x0000 576 #define PCIM_MSICTRL_MMC_2 0x0002 577 #define PCIM_MSICTRL_MMC_4 0x0004 578 #define PCIM_MSICTRL_MMC_8 0x0006 579 #define PCIM_MSICTRL_MMC_16 0x0008 580 #define PCIM_MSICTRL_MMC_32 0x000A 581 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 582 #define PCIR_MSI_ADDR 0x4 583 #define PCIR_MSI_ADDR_HIGH 0x8 584 #define PCIR_MSI_DATA 0x8 585 #define PCIR_MSI_DATA_64BIT 0xc 586 #define PCIR_MSI_MASK 0x10 587 #define PCIR_MSI_PENDING 0x14 588 589 /* PCI-X definitions */ 590 591 /* For header type 0 devices */ 592 #define PCIXR_COMMAND 0x2 593 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 594 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 595 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 596 #define PCIXM_COMMAND_MAX_READ_512 0x0000 597 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 598 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 599 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 600 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 601 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 602 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 603 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 604 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 605 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 606 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 607 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 608 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 609 #define PCIXM_COMMAND_VERSION 0x3000 610 #define PCIXR_STATUS 0x4 611 #define PCIXM_STATUS_DEVFN 0x000000FF 612 #define PCIXM_STATUS_BUS 0x0000FF00 613 #define PCIXM_STATUS_64BIT 0x00010000 614 #define PCIXM_STATUS_133CAP 0x00020000 615 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 616 #define PCIXM_STATUS_UNEXP_SC 0x00080000 617 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 618 #define PCIXM_STATUS_MAX_READ 0x00600000 619 #define PCIXM_STATUS_MAX_READ_512 0x00000000 620 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 621 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 622 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 623 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 624 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 625 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 626 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 627 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 628 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 629 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 630 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 631 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 632 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 633 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 634 #define PCIXM_STATUS_266CAP 0x40000000 635 #define PCIXM_STATUS_533CAP 0x80000000 636 637 /* For header type 1 devices (PCI-X bridges) */ 638 #define PCIXR_SEC_STATUS 0x2 639 #define PCIXM_SEC_STATUS_64BIT 0x0001 640 #define PCIXM_SEC_STATUS_133CAP 0x0002 641 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 642 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 643 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 644 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 645 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 646 #define PCIXM_SEC_STATUS_VERSION 0x3000 647 #define PCIXM_SEC_STATUS_266CAP 0x4000 648 #define PCIXM_SEC_STATUS_533CAP 0x8000 649 #define PCIXR_BRIDGE_STATUS 0x4 650 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 651 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 652 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 653 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 654 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 655 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 656 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 657 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 658 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 659 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 660 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 661 662 /* HT (HyperTransport) Capability definitions */ 663 #define PCIR_HT_COMMAND 0x2 664 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 665 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 666 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 667 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 668 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 669 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 670 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 671 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 672 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 673 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 674 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 675 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 676 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 677 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 678 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 679 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 680 #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 681 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 682 683 /* HT MSI Mapping Capability definitions. */ 684 #define PCIM_HTCMD_MSI_ENABLE 0x0001 685 #define PCIM_HTCMD_MSI_FIXED 0x0002 686 #define PCIR_HTMSI_ADDRESS_LO 0x4 687 #define PCIR_HTMSI_ADDRESS_HI 0x8 688 689 /* PCI Vendor capability definitions */ 690 #define PCIR_VENDOR_LENGTH 0x2 691 #define PCIR_VENDOR_DATA 0x3 692 693 /* PCI Device capability definitions */ 694 #define PCIR_DEVICE_LENGTH 0x2 695 696 /* PCI EHCI Debug Port definitions */ 697 #define PCIR_DEBUG_PORT 0x2 698 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 699 #define PCIM_DEBUG_PORT_BAR 0xe000 700 701 /* PCI-PCI Bridge Subvendor definitions */ 702 #define PCIR_SUBVENDCAP_ID 0x4 703 704 /* PCI Express definitions */ 705 #define PCIER_FLAGS 0x2 706 #define PCIEM_FLAGS_VERSION 0x000F 707 #define PCIEM_FLAGS_TYPE 0x00F0 708 #define PCIEM_TYPE_ENDPOINT 0x0000 709 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 710 #define PCIEM_TYPE_ROOT_PORT 0x0040 711 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 712 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 713 #define PCIEM_TYPE_PCI_BRIDGE 0x0070 714 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 715 #define PCIEM_TYPE_ROOT_INT_EP 0x0090 716 #define PCIEM_TYPE_ROOT_EC 0x00a0 717 #define PCIEM_FLAGS_SLOT 0x0100 718 #define PCIEM_FLAGS_IRQ 0x3e00 719 #define PCIER_DEVICE_CAP 0x4 720 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 721 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 722 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 723 #define PCIEM_CAP_L0S_LATENCY 0x000001c0 724 #define PCIEM_CAP_L1_LATENCY 0x00000e00 725 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 726 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 727 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 728 #define PCIEM_CAP_FLR 0x10000000 729 #define PCIER_DEVICE_CTL 0x8 730 #define PCIEM_CTL_COR_ENABLE 0x0001 731 #define PCIEM_CTL_NFER_ENABLE 0x0002 732 #define PCIEM_CTL_FER_ENABLE 0x0004 733 #define PCIEM_CTL_URR_ENABLE 0x0008 734 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 735 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 736 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 737 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 738 #define PCIEM_CTL_AUX_POWER_PM 0x0400 739 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 740 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 741 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 742 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 743 #define PCIER_DEVICE_STA 0xa 744 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 745 #define PCIEM_STA_NON_FATAL_ERROR 0x0002 746 #define PCIEM_STA_FATAL_ERROR 0x0004 747 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 748 #define PCIEM_STA_AUX_POWER 0x0010 749 #define PCIEM_STA_TRANSACTION_PND 0x0020 750 #define PCIER_LINK_CAP 0xc 751 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 752 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 753 #define PCIEM_LINK_CAP_ASPM 0x00000c00 754 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 755 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 756 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 757 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 758 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 759 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 760 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 761 #define PCIEM_LINK_CAP_PORT 0xff000000 762 #define PCIER_LINK_CTL 0x10 763 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 764 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 765 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 766 #define PCIEM_LINK_CTL_ASPMC 0x0003 767 #define PCIEM_LINK_CTL_RCB 0x0008 768 #define PCIEM_LINK_CTL_LINK_DIS 0x0010 769 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 770 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 771 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 772 #define PCIEM_LINK_CTL_ECPM 0x0100 773 #define PCIEM_LINK_CTL_HAWD 0x0200 774 #define PCIEM_LINK_CTL_LBMIE 0x0400 775 #define PCIEM_LINK_CTL_LABIE 0x0800 776 #define PCIER_LINK_STA 0x12 777 #define PCIEM_LINK_STA_SPEED 0x000f 778 #define PCIEM_LINK_STA_WIDTH 0x03f0 779 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 780 #define PCIEM_LINK_STA_TRAINING 0x0800 781 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 782 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 783 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 784 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 785 #define PCIER_SLOT_CAP 0x14 786 #define PCIEM_SLOT_CAP_APB 0x00000001 787 #define PCIEM_SLOT_CAP_PCP 0x00000002 788 #define PCIEM_SLOT_CAP_MRLSP 0x00000004 789 #define PCIEM_SLOT_CAP_AIP 0x00000008 790 #define PCIEM_SLOT_CAP_PIP 0x00000010 791 #define PCIEM_SLOT_CAP_HPS 0x00000020 792 #define PCIEM_SLOT_CAP_HPC 0x00000040 793 #define PCIEM_SLOT_CAP_SPLV 0x00007f80 794 #define PCIEM_SLOT_CAP_SPLS 0x00018000 795 #define PCIEM_SLOT_CAP_EIP 0x00020000 796 #define PCIEM_SLOT_CAP_NCCS 0x00040000 797 #define PCIEM_SLOT_CAP_PSN 0xfff80000 798 #define PCIER_SLOT_CTL 0x18 799 #define PCIEM_SLOT_CTL_ABPE 0x0001 800 #define PCIEM_SLOT_CTL_PFDE 0x0002 801 #define PCIEM_SLOT_CTL_MRLSCE 0x0004 802 #define PCIEM_SLOT_CTL_PDCE 0x0008 803 #define PCIEM_SLOT_CTL_CCIE 0x0010 804 #define PCIEM_SLOT_CTL_HPIE 0x0020 805 #define PCIEM_SLOT_CTL_AIC 0x00c0 806 #define PCIEM_SLOT_CTL_PIC 0x0300 807 #define PCIEM_SLOT_CTL_PCC 0x0400 808 #define PCIEM_SLOT_CTL_EIC 0x0800 809 #define PCIEM_SLOT_CTL_DLLSCE 0x1000 810 #define PCIER_SLOT_STA 0x1a 811 #define PCIEM_SLOT_STA_ABP 0x0001 812 #define PCIEM_SLOT_STA_PFD 0x0002 813 #define PCIEM_SLOT_STA_MRLSC 0x0004 814 #define PCIEM_SLOT_STA_PDC 0x0008 815 #define PCIEM_SLOT_STA_CC 0x0010 816 #define PCIEM_SLOT_STA_MRLSS 0x0020 817 #define PCIEM_SLOT_STA_PDS 0x0040 818 #define PCIEM_SLOT_STA_EIS 0x0080 819 #define PCIEM_SLOT_STA_DLLSC 0x0100 820 #define PCIER_ROOT_CTL 0x1c 821 #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 822 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 823 #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 824 #define PCIEM_ROOT_CTL_PME 0x0008 825 #define PCIEM_ROOT_CTL_CRS_VIS 0x0010 826 #define PCIER_ROOT_CAP 0x1e 827 #define PCIEM_ROOT_CAP_CRS_VIS 0x0001 828 #define PCIER_ROOT_STA 0x20 829 #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 830 #define PCIEM_ROOT_STA_PME_STATUS 0x00010000 831 #define PCIEM_ROOT_STA_PME_PEND 0x00020000 832 #define PCIER_DEVICE_CAP2 0x24 833 #define PCIEM_CAP2_ARI 0x20 834 #define PCIER_DEVICE_CTL2 0x28 835 #define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 836 #define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 837 #define PCIEM_CTL2_ARI 0x0020 838 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 839 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 840 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 841 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 842 #define PCIEM_CTL2_LTR_ENABLE 0x0400 843 #define PCIEM_CTL2_OBFF 0x6000 844 #define PCIEM_OBFF_DISABLE 0x0000 845 #define PCIEM_OBFF_MSGA_ENABLE 0x2000 846 #define PCIEM_OBFF_MSGB_ENABLE 0x4000 847 #define PCIEM_OBFF_WAKE_ENABLE 0x6000 848 #define PCIEM_CTL2_END2END_TLP 0x8000 849 #define PCIER_DEVICE_STA2 0x2a 850 #define PCIER_LINK_CAP2 0x2c 851 #define PCIER_LINK_CTL2 0x30 852 #define PCIER_LINK_STA2 0x32 853 #define PCIER_SLOT_CAP2 0x34 854 #define PCIER_SLOT_CTL2 0x38 855 #define PCIER_SLOT_STA2 0x3a 856 857 /* MSI-X definitions */ 858 #define PCIR_MSIX_CTRL 0x2 859 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 860 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 861 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 862 #define PCIR_MSIX_TABLE 0x4 863 #define PCIR_MSIX_PBA 0x8 864 #define PCIM_MSIX_BIR_MASK 0x7 865 #define PCIM_MSIX_BIR_BAR_10 0 866 #define PCIM_MSIX_BIR_BAR_14 1 867 #define PCIM_MSIX_BIR_BAR_18 2 868 #define PCIM_MSIX_BIR_BAR_1C 3 869 #define PCIM_MSIX_BIR_BAR_20 4 870 #define PCIM_MSIX_BIR_BAR_24 5 871 #define PCIM_MSIX_VCTRL_MASK 0x1 872 873 /* PCI Advanced Features definitions */ 874 #define PCIR_PCIAF_CAP 0x3 875 #define PCIM_PCIAFCAP_TP 0x01 876 #define PCIM_PCIAFCAP_FLR 0x02 877 #define PCIR_PCIAF_CTRL 0x4 878 #define PCIR_PCIAFCTRL_FLR 0x01 879 #define PCIR_PCIAF_STATUS 0x5 880 #define PCIR_PCIAFSTATUS_TP 0x01 881 882 /* Advanced Error Reporting */ 883 #define PCIR_AER_UC_STATUS 0x04 884 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 885 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 886 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 887 #define PCIM_AER_UC_POISONED_TLP 0x00001000 888 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 889 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 890 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 891 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 892 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 893 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 894 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 895 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 896 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 897 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 898 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 899 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 900 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 901 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 902 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 903 #define PCIR_AER_COR_STATUS 0x10 904 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 905 #define PCIM_AER_COR_BAD_TLP 0x00000040 906 #define PCIM_AER_COR_BAD_DLLP 0x00000080 907 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 908 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 909 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 910 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 911 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 912 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 913 #define PCIR_AER_CAP_CONTROL 0x18 914 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 915 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 916 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 917 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 918 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 919 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 920 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 921 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 922 #define PCIR_AER_HEADER_LOG 0x1c 923 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 924 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 925 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 926 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 927 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 928 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 929 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 930 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 931 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 932 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 933 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 934 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 935 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 936 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 937 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 938 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 939 940 /* Virtual Channel definitions */ 941 #define PCIR_VC_CAP1 0x04 942 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 943 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 944 #define PCIR_VC_CAP2 0x08 945 #define PCIR_VC_CONTROL 0x0C 946 #define PCIR_VC_STATUS 0x0E 947 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 948 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 949 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 950 951 /* Serial Number definitions */ 952 #define PCIR_SERIAL_LOW 0x04 953 #define PCIR_SERIAL_HIGH 0x08 954 955 /* SR-IOV definitions */ 956 #define PCIR_SRIOV_CTL 0x08 957 #define PCIM_SRIOV_VF_EN 0x01 958 #define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */ 959 #define PCIM_SRIOV_ARI_EN 0x10 960 #define PCIR_SRIOV_TOTAL_VFS 0x0E 961 #define PCIR_SRIOV_NUM_VFS 0x10 962 #define PCIR_SRIOV_VF_OFF 0x14 963 #define PCIR_SRIOV_VF_STRIDE 0x16 964 #define PCIR_SRIOV_VF_DID 0x1A 965 #define PCIR_SRIOV_PAGE_CAP 0x1C 966 #define PCIR_SRIOV_PAGE_SIZE 0x20 967 968 #define PCI_SRIOV_BASE_PAGE_SHIFT 12 969 970 #define PCIR_SRIOV_BARS 0x24 971 #define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) 972 973