1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef __PCIB_PRIVATE_H__ 34 #define __PCIB_PRIVATE_H__ 35 36 #include <sys/taskqueue.h> 37 38 /* 39 * Data structure and routines that Host to PCI bridge drivers can use 40 * to restrict allocations for child devices to ranges decoded by the 41 * bridge. 42 */ 43 struct pcib_host_resources { 44 device_t hr_pcib; 45 struct resource_list hr_rl; 46 }; 47 48 int pcib_host_res_init(device_t pcib, 49 struct pcib_host_resources *hr); 50 int pcib_host_res_free(device_t pcib, 51 struct pcib_host_resources *hr); 52 int pcib_host_res_decodes(struct pcib_host_resources *hr, int type, 53 rman_res_t start, rman_res_t end, u_int flags); 54 struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr, 55 device_t dev, int type, int *rid, rman_res_t start, 56 rman_res_t end, rman_res_t count, u_int flags); 57 int pcib_host_res_adjust(struct pcib_host_resources *hr, 58 device_t dev, struct resource *r, rman_res_t start, 59 rman_res_t end); 60 61 /* 62 * Export portions of generic PCI:PCI bridge support so that it can be 63 * used by subclasses. 64 */ 65 DECLARE_CLASS(pcib_driver); 66 67 #define WIN_IO 0x1 68 #define WIN_MEM 0x2 69 #define WIN_PMEM 0x4 70 71 struct pcib_window { 72 pci_addr_t base; /* base address */ 73 pci_addr_t limit; /* topmost address */ 74 struct rman rman; 75 struct resource **res; 76 int count; /* size of 'res' array */ 77 int reg; /* resource id from parent */ 78 int valid; 79 int mask; /* WIN_* bitmask of this window */ 80 int step; /* log_2 of window granularity */ 81 const char *name; 82 }; 83 84 struct pcib_secbus { 85 u_int sec; 86 u_int sub; 87 device_t dev; 88 struct rman rman; 89 struct resource *res; 90 const char *name; 91 int sub_reg; 92 }; 93 94 /* 95 * Bridge-specific data. 96 */ 97 struct pcib_softc 98 { 99 device_t dev; 100 device_t child; 101 uint32_t flags; /* flags */ 102 #define PCIB_SUBTRACTIVE 0x1 103 #define PCIB_DISABLE_MSI 0x2 104 #define PCIB_DISABLE_MSIX 0x4 105 #define PCIB_ENABLE_ARI 0x8 106 #define PCIB_HOTPLUG 0x10 107 #define PCIB_HOTPLUG_CMD_PENDING 0x20 108 #define PCIB_DETACH_PENDING 0x40 109 #define PCIB_DETACHING 0x80 110 u_int domain; /* domain number */ 111 u_int pribus; /* primary bus number */ 112 struct pcib_secbus bus; /* secondary bus numbers */ 113 struct pcib_window io; /* I/O port window */ 114 struct pcib_window mem; /* memory window */ 115 struct pcib_window pmem; /* prefetchable memory window */ 116 uint16_t bridgectl; /* bridge control register */ 117 uint16_t pcie_link_sta; 118 uint16_t pcie_slot_sta; 119 uint32_t pcie_slot_cap; 120 struct resource *pcie_mem; 121 struct resource *pcie_irq; 122 void *pcie_ihand; 123 struct task pcie_hp_task; 124 struct timeout_task pcie_ab_task; 125 struct timeout_task pcie_cc_task; 126 struct timeout_task pcie_dll_task; 127 struct mtx *pcie_hp_lock; 128 }; 129 130 #define PCIB_HP_LOCK(sc) mtx_lock((sc)->pcie_hp_lock) 131 #define PCIB_HP_UNLOCK(sc) mtx_unlock((sc)->pcie_hp_lock) 132 #define PCIB_HP_LOCK_ASSERT(sc) mtx_assert((sc)->pcie_hp_lock, MA_OWNED) 133 134 #define PCIB_SUPPORTED_ARI_VER 1 135 136 typedef uint32_t pci_read_config_fn(int d, int b, int s, int f, int reg, 137 int width); 138 139 int host_pcib_get_busno(pci_read_config_fn read_config, int bus, 140 int slot, int func, uint8_t *busnum); 141 struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid, 142 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); 143 int pci_domain_adjust_bus(int domain, device_t dev, 144 struct resource *r, rman_res_t start, rman_res_t end); 145 int pci_domain_release_bus(int domain, device_t dev, 146 struct resource *r); 147 int pci_domain_activate_bus(int domain, device_t dev, 148 struct resource *r); 149 int pci_domain_deactivate_bus(int domain, device_t dev, 150 struct resource *r); 151 struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, 152 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, 153 u_int flags); 154 void pcib_free_secbus(device_t dev, struct pcib_secbus *bus); 155 void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, 156 int min_count); 157 int pcib_attach(device_t dev); 158 int pcib_attach_child(device_t dev); 159 void pcib_attach_common(device_t dev); 160 void pcib_bridge_init(device_t dev); 161 const char *pcib_child_name(device_t child); 162 int pcib_detach(device_t dev); 163 int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 164 int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 165 int pcib_maxslots(device_t dev); 166 int pcib_maxfuncs(device_t dev); 167 int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 168 int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs); 169 int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs); 170 int pcib_alloc_msix(device_t pcib, device_t dev, int *irq); 171 int pcib_release_msix(device_t pcib, device_t dev, int irq); 172 int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data); 173 int pcib_get_id(device_t pcib, device_t dev, enum pci_id_type type, 174 uintptr_t *id); 175 void pcib_decode_rid(device_t pcib, uint16_t rid, int *bus, 176 int *slot, int *func); 177 int pcib_request_feature(device_t dev, enum pci_feature feature); 178 int pcib_request_feature_allow(device_t pcib, device_t dev, enum pci_feature feature); 179 180 #endif 181