1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef __PCIB_PRIVATE_H__ 34 #define __PCIB_PRIVATE_H__ 35 36 #include <sys/taskqueue.h> 37 38 #ifdef NEW_PCIB 39 /* 40 * Data structure and routines that Host to PCI bridge drivers can use 41 * to restrict allocations for child devices to ranges decoded by the 42 * bridge. 43 */ 44 struct pcib_host_resources { 45 device_t hr_pcib; 46 struct resource_list hr_rl; 47 }; 48 49 int pcib_host_res_init(device_t pcib, 50 struct pcib_host_resources *hr); 51 int pcib_host_res_free(device_t pcib, 52 struct pcib_host_resources *hr); 53 int pcib_host_res_decodes(struct pcib_host_resources *hr, int type, 54 rman_res_t start, rman_res_t end, u_int flags); 55 struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr, 56 device_t dev, int type, int *rid, rman_res_t start, 57 rman_res_t end, rman_res_t count, u_int flags); 58 int pcib_host_res_adjust(struct pcib_host_resources *hr, 59 device_t dev, int type, struct resource *r, rman_res_t start, 60 rman_res_t end); 61 #endif 62 63 /* 64 * Export portions of generic PCI:PCI bridge support so that it can be 65 * used by subclasses. 66 */ 67 DECLARE_CLASS(pcib_driver); 68 69 #ifdef NEW_PCIB 70 #define WIN_IO 0x1 71 #define WIN_MEM 0x2 72 #define WIN_PMEM 0x4 73 74 struct pcib_window { 75 pci_addr_t base; /* base address */ 76 pci_addr_t limit; /* topmost address */ 77 struct rman rman; 78 struct resource **res; 79 int count; /* size of 'res' array */ 80 int reg; /* resource id from parent */ 81 int valid; 82 int mask; /* WIN_* bitmask of this window */ 83 int step; /* log_2 of window granularity */ 84 const char *name; 85 }; 86 #endif 87 88 struct pcib_secbus { 89 u_int sec; 90 u_int sub; 91 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 92 device_t dev; 93 struct rman rman; 94 struct resource *res; 95 const char *name; 96 int sub_reg; 97 #endif 98 }; 99 100 /* 101 * Bridge-specific data. 102 */ 103 struct pcib_softc 104 { 105 device_t dev; 106 device_t child; 107 uint32_t flags; /* flags */ 108 #define PCIB_SUBTRACTIVE 0x1 109 #define PCIB_DISABLE_MSI 0x2 110 #define PCIB_DISABLE_MSIX 0x4 111 #define PCIB_ENABLE_ARI 0x8 112 #define PCIB_HOTPLUG 0x10 113 #define PCIB_HOTPLUG_CMD_PENDING 0x20 114 #define PCIB_DETACH_PENDING 0x40 115 #define PCIB_DETACHING 0x80 116 u_int domain; /* domain number */ 117 u_int pribus; /* primary bus number */ 118 struct pcib_secbus bus; /* secondary bus numbers */ 119 #ifdef NEW_PCIB 120 struct pcib_window io; /* I/O port window */ 121 struct pcib_window mem; /* memory window */ 122 struct pcib_window pmem; /* prefetchable memory window */ 123 #else 124 pci_addr_t pmembase; /* base address of prefetchable memory */ 125 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 126 pci_addr_t membase; /* base address of memory window */ 127 pci_addr_t memlimit; /* topmost address of memory window */ 128 uint32_t iobase; /* base address of port window */ 129 uint32_t iolimit; /* topmost address of port window */ 130 #endif 131 uint16_t bridgectl; /* bridge control register */ 132 uint16_t pcie_link_sta; 133 uint16_t pcie_slot_sta; 134 uint32_t pcie_slot_cap; 135 struct resource *pcie_mem; 136 struct resource *pcie_irq; 137 void *pcie_ihand; 138 struct task pcie_hp_task; 139 struct timeout_task pcie_ab_task; 140 struct timeout_task pcie_cc_task; 141 struct timeout_task pcie_dll_task; 142 struct mtx *pcie_hp_lock; 143 }; 144 145 #define PCIB_HP_LOCK(sc) mtx_lock((sc)->pcie_hp_lock) 146 #define PCIB_HP_UNLOCK(sc) mtx_unlock((sc)->pcie_hp_lock) 147 #define PCIB_HP_LOCK_ASSERT(sc) mtx_assert((sc)->pcie_hp_lock, MA_OWNED) 148 149 #define PCIB_SUPPORTED_ARI_VER 1 150 151 typedef uint32_t pci_read_config_fn(int d, int b, int s, int f, int reg, 152 int width); 153 154 int host_pcib_get_busno(pci_read_config_fn read_config, int bus, 155 int slot, int func, uint8_t *busnum); 156 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 157 struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid, 158 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); 159 int pci_domain_adjust_bus(int domain, device_t dev, 160 struct resource *r, rman_res_t start, rman_res_t end); 161 int pci_domain_release_bus(int domain, device_t dev, int rid, 162 struct resource *r); 163 struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, 164 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, 165 u_int flags); 166 void pcib_free_secbus(device_t dev, struct pcib_secbus *bus); 167 void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, 168 int min_count); 169 #endif 170 int pcib_attach(device_t dev); 171 int pcib_attach_child(device_t dev); 172 void pcib_attach_common(device_t dev); 173 void pcib_bridge_init(device_t dev); 174 #ifdef NEW_PCIB 175 const char *pcib_child_name(device_t child); 176 #endif 177 int pcib_child_present(device_t dev, device_t child); 178 int pcib_detach(device_t dev); 179 int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 180 int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 181 struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 182 rman_res_t start, rman_res_t end, 183 rman_res_t count, u_int flags); 184 #ifdef NEW_PCIB 185 int pcib_adjust_resource(device_t bus, device_t child, int type, 186 struct resource *r, rman_res_t start, rman_res_t end); 187 int pcib_release_resource(device_t dev, device_t child, int type, int rid, 188 struct resource *r); 189 #endif 190 int pcib_maxslots(device_t dev); 191 int pcib_maxfuncs(device_t dev); 192 int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 193 int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs); 194 int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs); 195 int pcib_alloc_msix(device_t pcib, device_t dev, int *irq); 196 int pcib_release_msix(device_t pcib, device_t dev, int irq); 197 int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data); 198 int pcib_get_id(device_t pcib, device_t dev, enum pci_id_type type, 199 uintptr_t *id); 200 void pcib_decode_rid(device_t pcib, uint16_t rid, int *bus, 201 int *slot, int *func); 202 int pcib_request_feature(device_t dev, enum pci_feature feature); 203 int pcib_request_feature_allow(device_t pcib, device_t dev, enum pci_feature feature); 204 205 #endif 206