1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/pciio.h> 48 #include <sys/rman.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_private.h> 56 #include <dev/pci/pcib_private.h> 57 58 #include "pcib_if.h" 59 60 static int pcib_probe(device_t dev); 61 static int pcib_resume(device_t dev); 62 63 static bus_child_present_t pcib_child_present; 64 static bus_alloc_resource_t pcib_alloc_resource; 65 static bus_adjust_resource_t pcib_adjust_resource; 66 static bus_release_resource_t pcib_release_resource; 67 static bus_activate_resource_t pcib_activate_resource; 68 static bus_deactivate_resource_t pcib_deactivate_resource; 69 static bus_map_resource_t pcib_map_resource; 70 static bus_unmap_resource_t pcib_unmap_resource; 71 static int pcib_reset_child(device_t dev, device_t child, int flags); 72 73 static int pcib_power_for_sleep(device_t pcib, device_t dev, 74 int *pstate); 75 static int pcib_ari_get_id(device_t pcib, device_t dev, 76 enum pci_id_type type, uintptr_t *id); 77 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 78 u_int f, u_int reg, int width); 79 static void pcib_write_config(device_t dev, u_int b, u_int s, 80 u_int f, u_int reg, uint32_t val, int width); 81 static int pcib_ari_maxslots(device_t dev); 82 static int pcib_ari_maxfuncs(device_t dev); 83 static int pcib_try_enable_ari(device_t pcib, device_t dev); 84 static int pcib_ari_enabled(device_t pcib); 85 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 86 int *bus, int *slot, int *func); 87 #ifdef PCI_HP 88 static void pcib_pcie_ab_timeout(void *arg, int pending); 89 static void pcib_pcie_cc_timeout(void *arg, int pending); 90 static void pcib_pcie_dll_timeout(void *arg, int pending); 91 #endif 92 static int pcib_request_feature_default(device_t pcib, device_t dev, 93 enum pci_feature feature); 94 95 static device_method_t pcib_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pcib_probe), 98 DEVMETHOD(device_attach, pcib_attach), 99 DEVMETHOD(device_detach, pcib_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, bus_generic_suspend), 102 DEVMETHOD(device_resume, pcib_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_child_present, pcib_child_present), 106 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 107 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 108 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 109 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 110 DEVMETHOD(bus_release_resource, pcib_release_resource), 111 DEVMETHOD(bus_activate_resource, pcib_activate_resource), 112 DEVMETHOD(bus_deactivate_resource, pcib_deactivate_resource), 113 DEVMETHOD(bus_map_resource, pcib_map_resource), 114 DEVMETHOD(bus_unmap_resource, pcib_unmap_resource), 115 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 116 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 117 DEVMETHOD(bus_reset_child, pcib_reset_child), 118 119 /* pcib interface */ 120 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 121 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 122 DEVMETHOD(pcib_read_config, pcib_read_config), 123 DEVMETHOD(pcib_write_config, pcib_write_config), 124 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 125 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 126 DEVMETHOD(pcib_release_msi, pcib_release_msi), 127 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 128 DEVMETHOD(pcib_release_msix, pcib_release_msix), 129 DEVMETHOD(pcib_map_msi, pcib_map_msi), 130 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 131 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 132 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 133 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 134 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 135 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 136 137 DEVMETHOD_END 138 }; 139 140 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 141 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, NULL, NULL, BUS_PASS_BUS); 142 143 SYSCTL_DECL(_hw_pci); 144 145 static int pci_clear_pcib; 146 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 147 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 148 149 /* 150 * Get the corresponding window if this resource from a child device was 151 * sub-allocated from one of our window resource managers. 152 */ 153 static struct pcib_window * 154 pcib_get_resource_window(struct pcib_softc *sc, struct resource *r) 155 { 156 switch (rman_get_type(r)) { 157 case SYS_RES_IOPORT: 158 if (rman_is_region_manager(r, &sc->io.rman)) 159 return (&sc->io); 160 break; 161 case SYS_RES_MEMORY: 162 /* Prefetchable resources may live in either memory rman. */ 163 if (rman_get_flags(r) & RF_PREFETCHABLE && 164 rman_is_region_manager(r, &sc->pmem.rman)) 165 return (&sc->pmem); 166 if (rman_is_region_manager(r, &sc->mem.rman)) 167 return (&sc->mem); 168 break; 169 } 170 return (NULL); 171 } 172 173 /* 174 * Is a resource from a child device sub-allocated from one of our 175 * resource managers? 176 */ 177 static int 178 pcib_is_resource_managed(struct pcib_softc *sc, struct resource *r) 179 { 180 181 if (rman_get_type(r) == PCI_RES_BUS) 182 return (rman_is_region_manager(r, &sc->bus.rman)); 183 return (pcib_get_resource_window(sc, r) != NULL); 184 } 185 186 static int 187 pcib_is_window_open(struct pcib_window *pw) 188 { 189 190 return (pw->valid && pw->base < pw->limit); 191 } 192 193 /* 194 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 195 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 196 * when allocating the resource windows and rely on the PCI bus driver 197 * to do this for us. 198 */ 199 static void 200 pcib_activate_window(struct pcib_softc *sc, int type) 201 { 202 203 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 204 } 205 206 static void 207 pcib_write_windows(struct pcib_softc *sc, int mask) 208 { 209 device_t dev; 210 uint32_t val; 211 212 dev = sc->dev; 213 if (sc->io.valid && mask & WIN_IO) { 214 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 215 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 216 pci_write_config(dev, PCIR_IOBASEH_1, 217 sc->io.base >> 16, 2); 218 pci_write_config(dev, PCIR_IOLIMITH_1, 219 sc->io.limit >> 16, 2); 220 } 221 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 222 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 223 } 224 225 if (mask & WIN_MEM) { 226 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 227 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 228 } 229 230 if (sc->pmem.valid && mask & WIN_PMEM) { 231 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 232 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 233 pci_write_config(dev, PCIR_PMBASEH_1, 234 sc->pmem.base >> 32, 4); 235 pci_write_config(dev, PCIR_PMLIMITH_1, 236 sc->pmem.limit >> 32, 4); 237 } 238 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 239 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 240 } 241 } 242 243 /* 244 * This is used to reject I/O port allocations that conflict with an 245 * ISA alias range. 246 */ 247 static int 248 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 249 rman_res_t count) 250 { 251 rman_res_t next_alias; 252 253 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 254 return (0); 255 256 /* Only check fixed ranges for overlap. */ 257 if (start + count - 1 != end) 258 return (0); 259 260 /* ISA aliases are only in the lower 64KB of I/O space. */ 261 if (start >= 65536) 262 return (0); 263 264 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 265 if (start < 0x100) 266 goto alias; 267 268 /* 269 * If the start address is an alias, the range is an alias. 270 * Otherwise, compute the start of the next alias range and 271 * check if it is before the end of the candidate range. 272 */ 273 if ((start & 0x300) != 0) 274 goto alias; 275 next_alias = (start & ~0x3fful) | 0x100; 276 if (next_alias <= end) 277 goto alias; 278 return (0); 279 280 alias: 281 if (bootverbose) 282 device_printf(sc->dev, 283 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 284 end); 285 return (1); 286 } 287 288 static void 289 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 290 int count) 291 { 292 struct resource **newarray; 293 int error, i; 294 295 newarray = malloc(sizeof(struct resource *) * (w->count + count), 296 M_DEVBUF, M_WAITOK); 297 if (w->res != NULL) 298 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 299 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 300 free(w->res, M_DEVBUF); 301 w->res = newarray; 302 w->count += count; 303 304 for (i = 0; i < count; i++) { 305 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 306 rman_get_end(res[i])); 307 if (error) 308 panic("Failed to add resource to rman"); 309 } 310 } 311 312 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 313 314 static void 315 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 316 void *arg) 317 { 318 rman_res_t next_end; 319 320 /* 321 * If start is within an ISA alias range, move up to the start 322 * of the next non-alias range. As a special case, addresses 323 * in the range 0x000 - 0x0ff should also be skipped since 324 * those are used for various system I/O devices in ISA 325 * systems. 326 */ 327 if (start <= 65535) { 328 if (start < 0x100 || (start & 0x300) != 0) { 329 start &= ~0x3ff; 330 start += 0x400; 331 } 332 } 333 334 /* ISA aliases are only in the lower 64KB of I/O space. */ 335 while (start <= MIN(end, 65535)) { 336 next_end = MIN(start | 0xff, end); 337 cb(start, next_end, arg); 338 start += 0x400; 339 } 340 341 if (start <= end) 342 cb(start, end, arg); 343 } 344 345 static void 346 count_ranges(rman_res_t start, rman_res_t end, void *arg) 347 { 348 int *countp; 349 350 countp = arg; 351 (*countp)++; 352 } 353 354 struct alloc_state { 355 struct resource **res; 356 struct pcib_softc *sc; 357 int count, error; 358 }; 359 360 static void 361 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 362 { 363 struct alloc_state *as; 364 struct pcib_window *w; 365 int rid; 366 367 as = arg; 368 if (as->error != 0) 369 return; 370 371 w = &as->sc->io; 372 rid = w->reg; 373 if (bootverbose) 374 device_printf(as->sc->dev, 375 "allocating non-ISA range %#jx-%#jx\n", start, end); 376 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 377 &rid, start, end, end - start + 1, RF_ACTIVE | RF_UNMAPPED); 378 if (as->res[as->count] == NULL) 379 as->error = ENXIO; 380 else 381 as->count++; 382 } 383 384 static int 385 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 386 { 387 struct alloc_state as; 388 int i, new_count; 389 390 /* First, see how many ranges we need. */ 391 new_count = 0; 392 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 393 394 /* Second, allocate the ranges. */ 395 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 396 M_WAITOK); 397 as.sc = sc; 398 as.count = 0; 399 as.error = 0; 400 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 401 if (as.error != 0) { 402 for (i = 0; i < as.count; i++) 403 bus_release_resource(sc->dev, SYS_RES_IOPORT, 404 sc->io.reg, as.res[i]); 405 free(as.res, M_DEVBUF); 406 return (as.error); 407 } 408 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 409 410 /* Third, add the ranges to the window. */ 411 pcib_add_window_resources(&sc->io, as.res, as.count); 412 free(as.res, M_DEVBUF); 413 return (0); 414 } 415 416 static void 417 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 418 int flags, pci_addr_t max_address) 419 { 420 struct resource *res; 421 char buf[64]; 422 int error, rid; 423 424 if (max_address != (rman_res_t)max_address) 425 max_address = ~0; 426 w->rman.rm_start = 0; 427 w->rman.rm_end = max_address; 428 w->rman.rm_type = RMAN_ARRAY; 429 snprintf(buf, sizeof(buf), "%s %s window", 430 device_get_nameunit(sc->dev), w->name); 431 w->rman.rm_descr = strdup(buf, M_DEVBUF); 432 error = rman_init(&w->rman); 433 if (error) 434 panic("Failed to initialize %s %s rman", 435 device_get_nameunit(sc->dev), w->name); 436 437 if (!pcib_is_window_open(w)) 438 return; 439 440 if (w->base > max_address || w->limit > max_address) { 441 device_printf(sc->dev, 442 "initial %s window has too many bits, ignoring\n", w->name); 443 return; 444 } 445 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 446 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 447 else { 448 rid = w->reg; 449 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 450 w->limit - w->base + 1, flags | RF_ACTIVE | RF_UNMAPPED); 451 if (res != NULL) 452 pcib_add_window_resources(w, &res, 1); 453 } 454 if (w->res == NULL) { 455 device_printf(sc->dev, 456 "failed to allocate initial %s window: %#jx-%#jx\n", 457 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 458 w->base = max_address; 459 w->limit = 0; 460 pcib_write_windows(sc, w->mask); 461 return; 462 } 463 pcib_activate_window(sc, type); 464 } 465 466 /* 467 * Initialize I/O windows. 468 */ 469 static void 470 pcib_probe_windows(struct pcib_softc *sc) 471 { 472 pci_addr_t max; 473 device_t dev; 474 uint32_t val; 475 476 dev = sc->dev; 477 478 if (pci_clear_pcib) { 479 pcib_bridge_init(dev); 480 } 481 482 /* Determine if the I/O port window is implemented. */ 483 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 484 if (val == 0) { 485 /* 486 * If 'val' is zero, then only 16-bits of I/O space 487 * are supported. 488 */ 489 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 490 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 491 sc->io.valid = 1; 492 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 493 } 494 } else 495 sc->io.valid = 1; 496 497 /* Read the existing I/O port window. */ 498 if (sc->io.valid) { 499 sc->io.reg = PCIR_IOBASEL_1; 500 sc->io.step = 12; 501 sc->io.mask = WIN_IO; 502 sc->io.name = "I/O port"; 503 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 504 sc->io.base = PCI_PPBIOBASE( 505 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 506 sc->io.limit = PCI_PPBIOLIMIT( 507 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 508 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 509 max = 0xffffffff; 510 } else { 511 sc->io.base = PCI_PPBIOBASE(0, val); 512 sc->io.limit = PCI_PPBIOLIMIT(0, 513 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 514 max = 0xffff; 515 } 516 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 517 } 518 519 /* Read the existing memory window. */ 520 sc->mem.valid = 1; 521 sc->mem.reg = PCIR_MEMBASE_1; 522 sc->mem.step = 20; 523 sc->mem.mask = WIN_MEM; 524 sc->mem.name = "memory"; 525 sc->mem.base = PCI_PPBMEMBASE(0, 526 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 527 sc->mem.limit = PCI_PPBMEMLIMIT(0, 528 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 529 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 530 531 /* Determine if the prefetchable memory window is implemented. */ 532 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 533 if (val == 0) { 534 /* 535 * If 'val' is zero, then only 32-bits of memory space 536 * are supported. 537 */ 538 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 539 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 540 sc->pmem.valid = 1; 541 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 542 } 543 } else 544 sc->pmem.valid = 1; 545 546 /* Read the existing prefetchable memory window. */ 547 if (sc->pmem.valid) { 548 sc->pmem.reg = PCIR_PMBASEL_1; 549 sc->pmem.step = 20; 550 sc->pmem.mask = WIN_PMEM; 551 sc->pmem.name = "prefetch"; 552 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 553 sc->pmem.base = PCI_PPBMEMBASE( 554 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 555 sc->pmem.limit = PCI_PPBMEMLIMIT( 556 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 557 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 558 max = 0xffffffffffffffff; 559 } else { 560 sc->pmem.base = PCI_PPBMEMBASE(0, val); 561 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 562 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 563 max = 0xffffffff; 564 } 565 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 566 RF_PREFETCHABLE, max); 567 } 568 } 569 570 static void 571 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 572 { 573 device_t dev; 574 int error, i; 575 576 if (!w->valid) 577 return; 578 579 dev = sc->dev; 580 error = rman_fini(&w->rman); 581 if (error) { 582 device_printf(dev, "failed to release %s rman\n", w->name); 583 return; 584 } 585 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 586 587 for (i = 0; i < w->count; i++) { 588 error = bus_free_resource(dev, type, w->res[i]); 589 if (error) 590 device_printf(dev, 591 "failed to release %s resource: %d\n", w->name, 592 error); 593 } 594 free(w->res, M_DEVBUF); 595 } 596 597 static void 598 pcib_free_windows(struct pcib_softc *sc) 599 { 600 601 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 602 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 603 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 604 } 605 606 /* 607 * Allocate a suitable secondary bus for this bridge if needed and 608 * initialize the resource manager for the secondary bus range. Note 609 * that the minimum count is a desired value and this may allocate a 610 * smaller range. 611 */ 612 void 613 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 614 { 615 char buf[64]; 616 int error, rid, sec_reg; 617 618 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 619 case PCIM_HDRTYPE_BRIDGE: 620 sec_reg = PCIR_SECBUS_1; 621 bus->sub_reg = PCIR_SUBBUS_1; 622 break; 623 case PCIM_HDRTYPE_CARDBUS: 624 sec_reg = PCIR_SECBUS_2; 625 bus->sub_reg = PCIR_SUBBUS_2; 626 break; 627 default: 628 panic("not a PCI bridge"); 629 } 630 bus->sec = pci_read_config(dev, sec_reg, 1); 631 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 632 bus->dev = dev; 633 bus->rman.rm_start = 0; 634 bus->rman.rm_end = PCI_BUSMAX; 635 bus->rman.rm_type = RMAN_ARRAY; 636 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 637 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 638 error = rman_init(&bus->rman); 639 if (error) 640 panic("Failed to initialize %s bus number rman", 641 device_get_nameunit(dev)); 642 643 /* 644 * Allocate a bus range. This will return an existing bus range 645 * if one exists, or a new bus range if one does not. 646 */ 647 rid = 0; 648 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 649 min_count, RF_ACTIVE); 650 if (bus->res == NULL) { 651 /* 652 * Fall back to just allocating a range of a single bus 653 * number. 654 */ 655 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 656 1, RF_ACTIVE); 657 } else if (rman_get_size(bus->res) < min_count) 658 /* 659 * Attempt to grow the existing range to satisfy the 660 * minimum desired count. 661 */ 662 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 663 rman_get_start(bus->res), rman_get_start(bus->res) + 664 min_count - 1); 665 666 /* 667 * Add the initial resource to the rman. 668 */ 669 if (bus->res != NULL) { 670 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 671 rman_get_end(bus->res)); 672 if (error) 673 panic("Failed to add resource to rman"); 674 bus->sec = rman_get_start(bus->res); 675 bus->sub = rman_get_end(bus->res); 676 } 677 } 678 679 void 680 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 681 { 682 int error; 683 684 error = rman_fini(&bus->rman); 685 if (error) { 686 device_printf(dev, "failed to release bus number rman\n"); 687 return; 688 } 689 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 690 691 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 692 if (error) 693 device_printf(dev, 694 "failed to release bus numbers resource: %d\n", error); 695 } 696 697 static struct resource * 698 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 699 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 700 { 701 struct resource *res; 702 703 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 704 child); 705 if (res == NULL) 706 return (NULL); 707 708 if (bootverbose) 709 device_printf(bus->dev, 710 "allocated bus range (%ju-%ju) for rid %d of %s\n", 711 rman_get_start(res), rman_get_end(res), *rid, 712 pcib_child_name(child)); 713 rman_set_rid(res, *rid); 714 rman_set_type(res, PCI_RES_BUS); 715 return (res); 716 } 717 718 /* 719 * Attempt to grow the secondary bus range. This is much simpler than 720 * for I/O windows as the range can only be grown by increasing 721 * subbus. 722 */ 723 static int 724 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 725 { 726 rman_res_t old_end; 727 int error; 728 729 old_end = rman_get_end(bus->res); 730 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 731 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 732 rman_get_start(bus->res), new_end); 733 if (error) 734 return (error); 735 if (bootverbose) 736 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 737 rman_get_start(bus->res), rman_get_end(bus->res)); 738 error = rman_manage_region(&bus->rman, old_end + 1, 739 rman_get_end(bus->res)); 740 if (error) 741 panic("Failed to add resource to rman"); 742 bus->sub = rman_get_end(bus->res); 743 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 744 return (0); 745 } 746 747 struct resource * 748 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 749 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 750 { 751 struct resource *res; 752 rman_res_t start_free, end_free, new_end; 753 754 /* 755 * First, see if the request can be satisified by the existing 756 * bus range. 757 */ 758 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 759 if (res != NULL) 760 return (res); 761 762 /* 763 * Figure out a range to grow the bus range. First, find the 764 * first bus number after the last allocated bus in the rman and 765 * enforce that as a minimum starting point for the range. 766 */ 767 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 768 end_free != bus->sub) 769 start_free = bus->sub + 1; 770 if (start_free < start) 771 start_free = start; 772 new_end = start_free + count - 1; 773 774 /* 775 * See if this new range would satisfy the request if it 776 * succeeds. 777 */ 778 if (new_end > end) 779 return (NULL); 780 781 /* Finally, attempt to grow the existing resource. */ 782 if (bootverbose) { 783 device_printf(bus->dev, 784 "attempting to grow bus range for %ju buses\n", count); 785 printf("\tback candidate range: %ju-%ju\n", start_free, 786 new_end); 787 } 788 if (pcib_grow_subbus(bus, new_end) == 0) 789 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 790 flags)); 791 return (NULL); 792 } 793 794 #ifdef PCI_HP 795 /* 796 * PCI-express HotPlug support. 797 */ 798 static int pci_enable_pcie_hp = 1; 799 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 800 &pci_enable_pcie_hp, 0, 801 "Enable support for native PCI-express HotPlug."); 802 803 static sbintime_t pcie_hp_detach_timeout = 5 * SBT_1S; 804 SYSCTL_SBINTIME_MSEC(_hw_pci, OID_AUTO, pcie_hp_detach_timeout, CTLFLAG_RWTUN, 805 &pcie_hp_detach_timeout, 806 "Attention Button delay for PCI-express Eject."); 807 808 static void 809 pcib_probe_hotplug(struct pcib_softc *sc) 810 { 811 device_t dev; 812 uint32_t link_cap; 813 uint16_t link_sta, slot_sta; 814 815 if (!pci_enable_pcie_hp) 816 return; 817 818 dev = sc->dev; 819 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 820 return; 821 822 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 823 return; 824 825 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 826 827 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 828 return; 829 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 830 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 831 return; 832 833 /* 834 * Some devices report that they have an MRL when they actually 835 * do not. Since they always report that the MRL is open, child 836 * devices would be ignored. Try to detect these devices and 837 * ignore their claim of HotPlug support. 838 * 839 * If there is an open MRL but the Data Link Layer is active, 840 * the MRL is not real. 841 */ 842 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 843 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 844 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 845 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 846 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 847 return; 848 } 849 } 850 851 /* 852 * Now that we're sure we want to do hot plug, ask the 853 * firmware, if any, if that's OK. 854 */ 855 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 856 if (bootverbose) 857 device_printf(dev, "Unable to activate hot plug feature.\n"); 858 return; 859 } 860 861 sc->flags |= PCIB_HOTPLUG; 862 } 863 864 /* 865 * Send a HotPlug command to the slot control register. If this slot 866 * uses command completion interrupts and a previous command is still 867 * in progress, then the command is dropped. Once the previous 868 * command completes or times out, pcib_pcie_hotplug_update() will be 869 * invoked to post a new command based on the slot's state at that 870 * time. 871 */ 872 static void 873 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 874 { 875 device_t dev; 876 uint16_t ctl, new; 877 878 dev = sc->dev; 879 880 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 881 return; 882 883 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 884 new = (ctl & ~mask) | val; 885 if (new == ctl) 886 return; 887 if (bootverbose) 888 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 889 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 890 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 891 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 892 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 893 if (!cold) 894 taskqueue_enqueue_timeout(taskqueue_bus, 895 &sc->pcie_cc_task, hz); 896 } 897 } 898 899 static void 900 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 901 { 902 device_t dev; 903 904 dev = sc->dev; 905 906 if (bootverbose) 907 device_printf(dev, "Command Completed\n"); 908 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 909 return; 910 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, NULL); 911 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 912 wakeup(sc); 913 } 914 915 /* 916 * Returns true if a card is fully inserted from the user's 917 * perspective. It may not yet be ready for access, but the driver 918 * can now start enabling access if necessary. 919 */ 920 static bool 921 pcib_hotplug_inserted(struct pcib_softc *sc) 922 { 923 924 /* Pretend the card isn't present if a detach is forced. */ 925 if (sc->flags & PCIB_DETACHING) 926 return (false); 927 928 /* Card must be present in the slot. */ 929 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 930 return (false); 931 932 /* A power fault implicitly turns off power to the slot. */ 933 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP && 934 sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 935 return (false); 936 937 /* If the MRL is disengaged, the slot is powered off. */ 938 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 939 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 940 return (false); 941 942 return (true); 943 } 944 945 /* 946 * Returns -1 if the card is fully inserted, powered, and ready for 947 * access. Otherwise, returns 0. 948 */ 949 static int 950 pcib_hotplug_present(struct pcib_softc *sc) 951 { 952 953 /* Card must be inserted. */ 954 if (!pcib_hotplug_inserted(sc)) 955 return (0); 956 957 /* Require the Data Link Layer to be active. */ 958 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 959 return (0); 960 961 return (-1); 962 } 963 964 static int pci_enable_pcie_ei = 0; 965 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_ei, CTLFLAG_RWTUN, 966 &pci_enable_pcie_ei, 0, 967 "Enable support for PCI-express Electromechanical Interlock."); 968 969 static void 970 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 971 bool schedule_task) 972 { 973 bool card_inserted, ei_engaged; 974 975 /* Clear DETACHING if Presence Detect has cleared. */ 976 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 977 PCIEM_SLOT_STA_PDC) 978 sc->flags &= ~PCIB_DETACHING; 979 980 card_inserted = pcib_hotplug_inserted(sc); 981 982 /* Turn the power indicator on if a card is inserted. */ 983 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 984 mask |= PCIEM_SLOT_CTL_PIC; 985 if (card_inserted) 986 val |= PCIEM_SLOT_CTL_PI_ON; 987 else if (sc->flags & PCIB_DETACH_PENDING) 988 val |= PCIEM_SLOT_CTL_PI_BLINK; 989 else 990 val |= PCIEM_SLOT_CTL_PI_OFF; 991 } 992 993 /* Turn the power on via the Power Controller if a card is inserted. */ 994 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 995 mask |= PCIEM_SLOT_CTL_PCC; 996 if (card_inserted) 997 val |= PCIEM_SLOT_CTL_PC_ON; 998 else 999 val |= PCIEM_SLOT_CTL_PC_OFF; 1000 } 1001 1002 /* 1003 * If a card is inserted, enable the Electromechanical 1004 * Interlock. If a card is not inserted (or we are in the 1005 * process of detaching), disable the Electromechanical 1006 * Interlock. 1007 */ 1008 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) && 1009 pci_enable_pcie_ei) { 1010 mask |= PCIEM_SLOT_CTL_EIC; 1011 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1012 if (card_inserted != ei_engaged) 1013 val |= PCIEM_SLOT_CTL_EIC; 1014 } 1015 1016 /* 1017 * Start a timer to see if the Data Link Layer times out. 1018 * Note that we only start the timer if Presence Detect or MRL Sensor 1019 * changed on this interrupt. Stop any scheduled timer if 1020 * the Data Link Layer is active. 1021 */ 1022 if (card_inserted && 1023 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1024 sc->pcie_slot_sta & 1025 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1026 if (cold) 1027 device_printf(sc->dev, 1028 "Data Link Layer inactive\n"); 1029 else 1030 taskqueue_enqueue_timeout(taskqueue_bus, 1031 &sc->pcie_dll_task, hz); 1032 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1033 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_dll_task, 1034 NULL); 1035 1036 pcib_pcie_hotplug_command(sc, val, mask); 1037 1038 /* 1039 * During attach the child "pci" device is added synchronously; 1040 * otherwise, the task is scheduled to manage the child 1041 * device. 1042 */ 1043 if (schedule_task && 1044 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1045 taskqueue_enqueue(taskqueue_bus, &sc->pcie_hp_task); 1046 } 1047 1048 static void 1049 pcib_pcie_intr_hotplug(void *arg) 1050 { 1051 struct pcib_softc *sc; 1052 device_t dev; 1053 uint16_t old_slot_sta; 1054 1055 sc = arg; 1056 dev = sc->dev; 1057 PCIB_HP_LOCK(sc); 1058 old_slot_sta = sc->pcie_slot_sta; 1059 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1060 1061 /* Clear the events just reported. */ 1062 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1063 1064 if (bootverbose) 1065 device_printf(dev, "HotPlug interrupt: %#x\n", 1066 sc->pcie_slot_sta); 1067 1068 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1069 if (sc->flags & PCIB_DETACH_PENDING) { 1070 device_printf(dev, 1071 "Attention Button Pressed: Detach Cancelled\n"); 1072 sc->flags &= ~PCIB_DETACH_PENDING; 1073 taskqueue_cancel_timeout(taskqueue_bus, 1074 &sc->pcie_ab_task, NULL); 1075 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) { 1076 /* Only initiate detach sequence if device present. */ 1077 if (pcie_hp_detach_timeout != 0) { 1078 device_printf(dev, 1079 "Attention Button Pressed: Detaching in %ld ms\n", 1080 (long)(pcie_hp_detach_timeout / SBT_1MS)); 1081 sc->flags |= PCIB_DETACH_PENDING; 1082 taskqueue_enqueue_timeout_sbt(taskqueue_bus, 1083 &sc->pcie_ab_task, pcie_hp_detach_timeout, 1084 SBT_1S, 0); 1085 } else { 1086 sc->flags |= PCIB_DETACHING; 1087 } 1088 } 1089 } 1090 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1091 device_printf(dev, "Power Fault Detected\n"); 1092 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1093 device_printf(dev, "MRL Sensor Changed to %s\n", 1094 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1095 "closed"); 1096 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1097 device_printf(dev, "Presence Detect Changed to %s\n", 1098 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1099 "empty"); 1100 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1101 pcib_pcie_hotplug_command_completed(sc); 1102 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1103 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1104 if (bootverbose) 1105 device_printf(dev, 1106 "Data Link Layer State Changed to %s\n", 1107 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1108 "active" : "inactive"); 1109 } 1110 1111 pcib_pcie_hotplug_update(sc, 0, 0, true); 1112 PCIB_HP_UNLOCK(sc); 1113 } 1114 1115 static void 1116 pcib_pcie_hotplug_task(void *context, int pending) 1117 { 1118 struct pcib_softc *sc; 1119 device_t dev; 1120 1121 sc = context; 1122 PCIB_HP_LOCK(sc); 1123 dev = sc->dev; 1124 if (pcib_hotplug_present(sc) != 0) { 1125 if (sc->child == NULL) { 1126 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1127 bus_attach_children(dev); 1128 } 1129 } else { 1130 if (sc->child != NULL) { 1131 if (device_delete_child(dev, sc->child) == 0) 1132 sc->child = NULL; 1133 } 1134 } 1135 PCIB_HP_UNLOCK(sc); 1136 } 1137 1138 static void 1139 pcib_pcie_ab_timeout(void *arg, int pending) 1140 { 1141 struct pcib_softc *sc = arg; 1142 1143 PCIB_HP_LOCK(sc); 1144 if (sc->flags & PCIB_DETACH_PENDING) { 1145 sc->flags |= PCIB_DETACHING; 1146 sc->flags &= ~PCIB_DETACH_PENDING; 1147 pcib_pcie_hotplug_update(sc, 0, 0, true); 1148 } 1149 PCIB_HP_UNLOCK(sc); 1150 } 1151 1152 static void 1153 pcib_pcie_cc_timeout(void *arg, int pending) 1154 { 1155 struct pcib_softc *sc = arg; 1156 device_t dev = sc->dev; 1157 uint16_t sta; 1158 1159 PCIB_HP_LOCK(sc); 1160 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1161 if (!(sta & PCIEM_SLOT_STA_CC)) { 1162 device_printf(dev, "HotPlug Command Timed Out\n"); 1163 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1164 } else { 1165 device_printf(dev, 1166 "Missed HotPlug interrupt waiting for Command Completion\n"); 1167 pcib_pcie_intr_hotplug(sc); 1168 } 1169 PCIB_HP_UNLOCK(sc); 1170 } 1171 1172 static void 1173 pcib_pcie_dll_timeout(void *arg, int pending) 1174 { 1175 struct pcib_softc *sc = arg; 1176 device_t dev = sc->dev; 1177 uint16_t sta; 1178 1179 PCIB_HP_LOCK(sc); 1180 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1181 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1182 device_printf(dev, 1183 "Timed out waiting for Data Link Layer Active\n"); 1184 sc->flags |= PCIB_DETACHING; 1185 pcib_pcie_hotplug_update(sc, 0, 0, true); 1186 } else if (sta != sc->pcie_link_sta) { 1187 device_printf(dev, 1188 "Missed HotPlug interrupt waiting for DLL Active\n"); 1189 pcib_pcie_intr_hotplug(sc); 1190 } 1191 PCIB_HP_UNLOCK(sc); 1192 } 1193 1194 static int 1195 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1196 { 1197 device_t dev; 1198 int count, error, mem_rid, rid; 1199 1200 rid = -1; 1201 dev = sc->dev; 1202 1203 /* 1204 * For simplicity, only use MSI-X if there is a single message. 1205 * To support a device with multiple messages we would have to 1206 * use remap intr if the MSI number is not 0. 1207 */ 1208 count = pci_msix_count(dev); 1209 if (count == 1) { 1210 mem_rid = pci_msix_table_bar(dev); 1211 sc->pcie_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1212 &mem_rid, RF_ACTIVE); 1213 if (sc->pcie_mem == NULL) { 1214 device_printf(dev, 1215 "Failed to allocate BAR for MSI-X table\n"); 1216 } else { 1217 error = pci_alloc_msix(dev, &count); 1218 if (error == 0) 1219 rid = 1; 1220 } 1221 } 1222 1223 if (rid < 0 && pci_msi_count(dev) > 0) { 1224 count = 1; 1225 error = pci_alloc_msi(dev, &count); 1226 if (error == 0) 1227 rid = 1; 1228 } 1229 1230 if (rid < 0) 1231 rid = 0; 1232 1233 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1234 RF_ACTIVE | RF_SHAREABLE); 1235 if (sc->pcie_irq == NULL) { 1236 device_printf(dev, 1237 "Failed to allocate interrupt for PCI-e events\n"); 1238 if (rid > 0) 1239 pci_release_msi(dev); 1240 return (ENXIO); 1241 } 1242 1243 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE, 1244 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1245 if (error) { 1246 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1247 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1248 if (rid > 0) 1249 pci_release_msi(dev); 1250 return (error); 1251 } 1252 return (0); 1253 } 1254 1255 static int 1256 pcib_release_pcie_irq(struct pcib_softc *sc) 1257 { 1258 device_t dev; 1259 int error; 1260 1261 dev = sc->dev; 1262 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1263 if (error) 1264 return (error); 1265 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1266 if (error) 1267 return (error); 1268 error = pci_release_msi(dev); 1269 if (error) 1270 return (error); 1271 if (sc->pcie_mem != NULL) 1272 error = bus_free_resource(dev, SYS_RES_MEMORY, sc->pcie_mem); 1273 return (error); 1274 } 1275 1276 static void 1277 pcib_setup_hotplug(struct pcib_softc *sc) 1278 { 1279 device_t dev; 1280 uint16_t mask, val; 1281 1282 dev = sc->dev; 1283 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1284 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_ab_task, 0, 1285 pcib_pcie_ab_timeout, sc); 1286 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_cc_task, 0, 1287 pcib_pcie_cc_timeout, sc); 1288 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_dll_task, 0, 1289 pcib_pcie_dll_timeout, sc); 1290 sc->pcie_hp_lock = bus_topo_mtx(); 1291 1292 /* Allocate IRQ. */ 1293 if (pcib_alloc_pcie_irq(sc) != 0) 1294 return; 1295 1296 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1297 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1298 1299 /* Clear any events previously pending. */ 1300 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1301 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1302 1303 /* Enable HotPlug events. */ 1304 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1305 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1306 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1307 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1308 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1309 val |= PCIEM_SLOT_CTL_ABPE; 1310 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1311 val |= PCIEM_SLOT_CTL_PFDE; 1312 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1313 val |= PCIEM_SLOT_CTL_MRLSCE; 1314 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1315 val |= PCIEM_SLOT_CTL_CCIE; 1316 1317 /* Turn the attention indicator off. */ 1318 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1319 mask |= PCIEM_SLOT_CTL_AIC; 1320 val |= PCIEM_SLOT_CTL_AI_OFF; 1321 } 1322 1323 pcib_pcie_hotplug_update(sc, val, mask, false); 1324 } 1325 1326 static int 1327 pcib_detach_hotplug(struct pcib_softc *sc) 1328 { 1329 uint16_t mask, val; 1330 int error; 1331 1332 /* Disable the card in the slot and force it to detach. */ 1333 if (sc->flags & PCIB_DETACH_PENDING) { 1334 sc->flags &= ~PCIB_DETACH_PENDING; 1335 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_ab_task, 1336 NULL); 1337 } 1338 sc->flags |= PCIB_DETACHING; 1339 1340 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1341 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, 1342 NULL); 1343 tsleep(sc, 0, "hpcmd", hz); 1344 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1345 } 1346 1347 /* Disable HotPlug events. */ 1348 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1349 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1350 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1351 val = 0; 1352 1353 /* Turn the attention indicator off. */ 1354 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1355 mask |= PCIEM_SLOT_CTL_AIC; 1356 val |= PCIEM_SLOT_CTL_AI_OFF; 1357 } 1358 1359 pcib_pcie_hotplug_update(sc, val, mask, false); 1360 1361 error = pcib_release_pcie_irq(sc); 1362 if (error) 1363 return (error); 1364 taskqueue_drain(taskqueue_bus, &sc->pcie_hp_task); 1365 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_ab_task); 1366 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_cc_task); 1367 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_dll_task); 1368 return (0); 1369 } 1370 #endif 1371 1372 /* 1373 * Restore previous bridge configuration. 1374 */ 1375 static void 1376 pcib_cfg_restore(struct pcib_softc *sc) 1377 { 1378 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1379 } 1380 1381 /* 1382 * Generic device interface 1383 */ 1384 static int 1385 pcib_probe(device_t dev) 1386 { 1387 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1388 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1389 device_set_desc(dev, "PCI-PCI bridge"); 1390 return(-10000); 1391 } 1392 return(ENXIO); 1393 } 1394 1395 void 1396 pcib_attach_common(device_t dev) 1397 { 1398 struct pcib_softc *sc; 1399 struct sysctl_ctx_list *sctx; 1400 struct sysctl_oid *soid; 1401 int comma; 1402 1403 sc = device_get_softc(dev); 1404 sc->dev = dev; 1405 1406 /* 1407 * Get current bridge configuration. 1408 */ 1409 sc->domain = pci_get_domain(dev); 1410 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1411 1412 /* 1413 * The primary bus register should always be the bus of the 1414 * parent. 1415 */ 1416 sc->pribus = pci_get_bus(dev); 1417 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1418 1419 /* 1420 * Setup sysctl reporting nodes 1421 */ 1422 sctx = device_get_sysctl_ctx(dev); 1423 soid = device_get_sysctl_tree(dev); 1424 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1425 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1426 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1427 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1428 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1429 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1430 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1431 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1432 1433 /* 1434 * Quirk handling. 1435 */ 1436 switch (pci_get_devid(dev)) { 1437 /* 1438 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1439 * and it is a subtractive bridge. However, the ProgIf is wrong 1440 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1441 * happen. There are also Toshiba and Cavium ThunderX bridges 1442 * that behave this way. 1443 */ 1444 case 0xa002177d: /* Cavium ThunderX */ 1445 case 0x124b8086: /* Intel 82380FB Mobile */ 1446 case 0x060513d7: /* Toshiba ???? */ 1447 sc->flags |= PCIB_SUBTRACTIVE; 1448 break; 1449 } 1450 1451 if (pci_msi_device_blacklisted(dev)) 1452 sc->flags |= PCIB_DISABLE_MSI; 1453 1454 if (pci_msix_device_blacklisted(dev)) 1455 sc->flags |= PCIB_DISABLE_MSIX; 1456 1457 /* 1458 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1459 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1460 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1461 * This means they act as if they were subtractively decoding 1462 * bridges and pass all transactions. Mark them and real ProgIf 1 1463 * parts as subtractive. 1464 */ 1465 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1466 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1467 sc->flags |= PCIB_SUBTRACTIVE; 1468 1469 #ifdef PCI_HP 1470 pcib_probe_hotplug(sc); 1471 #endif 1472 pcib_setup_secbus(dev, &sc->bus, 1); 1473 pcib_probe_windows(sc); 1474 #ifdef PCI_HP 1475 if (sc->flags & PCIB_HOTPLUG) 1476 pcib_setup_hotplug(sc); 1477 #endif 1478 if (bootverbose) { 1479 device_printf(dev, " domain %d\n", sc->domain); 1480 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1481 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1482 if (pcib_is_window_open(&sc->io)) 1483 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1484 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1485 if (pcib_is_window_open(&sc->mem)) 1486 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1487 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1488 if (pcib_is_window_open(&sc->pmem)) 1489 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1490 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1491 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1492 sc->flags & PCIB_SUBTRACTIVE) { 1493 device_printf(dev, " special decode "); 1494 comma = 0; 1495 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1496 printf("ISA"); 1497 comma = 1; 1498 } 1499 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1500 printf("%sVGA", comma ? ", " : ""); 1501 comma = 1; 1502 } 1503 if (sc->flags & PCIB_SUBTRACTIVE) 1504 printf("%ssubtractive", comma ? ", " : ""); 1505 printf("\n"); 1506 } 1507 } 1508 1509 /* 1510 * Always enable busmastering on bridges so that transactions 1511 * initiated on the secondary bus are passed through to the 1512 * primary bus. 1513 */ 1514 pci_enable_busmaster(dev); 1515 } 1516 1517 #ifdef PCI_HP 1518 static int 1519 pcib_present(struct pcib_softc *sc) 1520 { 1521 1522 if (sc->flags & PCIB_HOTPLUG) 1523 return (pcib_hotplug_present(sc) != 0); 1524 return (1); 1525 } 1526 #endif 1527 1528 int 1529 pcib_attach_child(device_t dev) 1530 { 1531 struct pcib_softc *sc; 1532 1533 sc = device_get_softc(dev); 1534 if (sc->bus.sec == 0) { 1535 /* no secondary bus; we should have fixed this */ 1536 return(0); 1537 } 1538 1539 #ifdef PCI_HP 1540 if (!pcib_present(sc)) { 1541 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1542 return (0); 1543 } 1544 #endif 1545 1546 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1547 bus_attach_children(dev); 1548 return (0); 1549 } 1550 1551 int 1552 pcib_attach(device_t dev) 1553 { 1554 1555 pcib_attach_common(dev); 1556 return (pcib_attach_child(dev)); 1557 } 1558 1559 int 1560 pcib_detach(device_t dev) 1561 { 1562 struct pcib_softc *sc; 1563 int error; 1564 1565 sc = device_get_softc(dev); 1566 error = bus_detach_children(dev); 1567 if (error) 1568 return (error); 1569 #ifdef PCI_HP 1570 if (sc->flags & PCIB_HOTPLUG) { 1571 error = pcib_detach_hotplug(sc); 1572 if (error) 1573 return (error); 1574 } 1575 #endif 1576 error = device_delete_children(dev); 1577 if (error) 1578 return (error); 1579 pcib_free_windows(sc); 1580 pcib_free_secbus(dev, &sc->bus); 1581 return (0); 1582 } 1583 1584 int 1585 pcib_resume(device_t dev) 1586 { 1587 1588 pcib_cfg_restore(device_get_softc(dev)); 1589 1590 /* 1591 * Restore the Command register only after restoring the windows. 1592 * The bridge should not be claiming random windows. 1593 */ 1594 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2); 1595 return (bus_generic_resume(dev)); 1596 } 1597 1598 void 1599 pcib_bridge_init(device_t dev) 1600 { 1601 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1602 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1603 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1604 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1605 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1606 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1607 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1608 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1609 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1610 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1611 } 1612 1613 int 1614 pcib_child_present(device_t dev, device_t child) 1615 { 1616 #ifdef PCI_HP 1617 struct pcib_softc *sc = device_get_softc(dev); 1618 int retval; 1619 1620 retval = bus_child_present(dev); 1621 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1622 retval = pcib_hotplug_present(sc); 1623 return (retval); 1624 #else 1625 return (bus_child_present(dev)); 1626 #endif 1627 } 1628 1629 int 1630 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1631 { 1632 struct pcib_softc *sc = device_get_softc(dev); 1633 1634 switch (which) { 1635 case PCIB_IVAR_DOMAIN: 1636 *result = sc->domain; 1637 return(0); 1638 case PCIB_IVAR_BUS: 1639 *result = sc->bus.sec; 1640 return(0); 1641 } 1642 return(ENOENT); 1643 } 1644 1645 int 1646 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1647 { 1648 1649 switch (which) { 1650 case PCIB_IVAR_DOMAIN: 1651 return(EINVAL); 1652 case PCIB_IVAR_BUS: 1653 return(EINVAL); 1654 } 1655 return(ENOENT); 1656 } 1657 1658 /* 1659 * Attempt to allocate a resource from the existing resources assigned 1660 * to a window. 1661 */ 1662 static struct resource * 1663 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1664 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1665 rman_res_t count, u_int flags) 1666 { 1667 struct resource *res; 1668 1669 if (!pcib_is_window_open(w)) 1670 return (NULL); 1671 1672 res = rman_reserve_resource(&w->rman, start, end, count, 1673 flags & ~RF_ACTIVE, child); 1674 if (res == NULL) 1675 return (NULL); 1676 1677 if (bootverbose) 1678 device_printf(sc->dev, 1679 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1680 w->name, rman_get_start(res), rman_get_end(res), *rid, 1681 pcib_child_name(child)); 1682 rman_set_rid(res, *rid); 1683 rman_set_type(res, type); 1684 1685 if (flags & RF_ACTIVE) { 1686 if (bus_activate_resource(child, type, *rid, res) != 0) { 1687 rman_release_resource(res); 1688 return (NULL); 1689 } 1690 } 1691 1692 return (res); 1693 } 1694 1695 /* Allocate a fresh resource range for an unconfigured window. */ 1696 static int 1697 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1698 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1699 { 1700 struct resource *res; 1701 rman_res_t base, limit, wmask; 1702 int rid; 1703 1704 /* 1705 * If this is an I/O window on a bridge with ISA enable set 1706 * and the start address is below 64k, then try to allocate an 1707 * initial window of 0x1000 bytes long starting at address 1708 * 0xf000 and walking down. Note that if the original request 1709 * was larger than the non-aliased range size of 0x100 our 1710 * caller would have raised the start address up to 64k 1711 * already. 1712 */ 1713 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1714 start < 65536) { 1715 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1716 limit = base + 0xfff; 1717 1718 /* 1719 * Skip ranges that wouldn't work for the 1720 * original request. Note that the actual 1721 * window that overlaps are the non-alias 1722 * ranges within [base, limit], so this isn't 1723 * quite a simple comparison. 1724 */ 1725 if (start + count > limit - 0x400) 1726 continue; 1727 if (base == 0) { 1728 /* 1729 * The first open region for the window at 1730 * 0 is 0x400-0x4ff. 1731 */ 1732 if (end - count + 1 < 0x400) 1733 continue; 1734 } else { 1735 if (end - count + 1 < base) 1736 continue; 1737 } 1738 1739 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1740 w->base = base; 1741 w->limit = limit; 1742 return (0); 1743 } 1744 } 1745 return (ENOSPC); 1746 } 1747 1748 wmask = ((rman_res_t)1 << w->step) - 1; 1749 if (RF_ALIGNMENT(flags) < w->step) { 1750 flags &= ~RF_ALIGNMENT_MASK; 1751 flags |= RF_ALIGNMENT_LOG2(w->step); 1752 } 1753 start &= ~wmask; 1754 end |= wmask; 1755 count = roundup2(count, (rman_res_t)1 << w->step); 1756 rid = w->reg; 1757 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1758 flags | RF_ACTIVE | RF_UNMAPPED); 1759 if (res == NULL) 1760 return (ENOSPC); 1761 pcib_add_window_resources(w, &res, 1); 1762 pcib_activate_window(sc, type); 1763 w->base = rman_get_start(res); 1764 w->limit = rman_get_end(res); 1765 return (0); 1766 } 1767 1768 /* Try to expand an existing window to the requested base and limit. */ 1769 static int 1770 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1771 rman_res_t base, rman_res_t limit) 1772 { 1773 struct resource *res; 1774 int error, i, force_64k_base; 1775 1776 KASSERT(base <= w->base && limit >= w->limit, 1777 ("attempting to shrink window")); 1778 1779 /* 1780 * XXX: pcib_grow_window() doesn't try to do this anyway and 1781 * the error handling for all the edge cases would be tedious. 1782 */ 1783 KASSERT(limit == w->limit || base == w->base, 1784 ("attempting to grow both ends of a window")); 1785 1786 /* 1787 * Yet more special handling for requests to expand an I/O 1788 * window behind an ISA-enabled bridge. Since I/O windows 1789 * have to grow in 0x1000 increments and the end of the 0xffff 1790 * range is an alias, growing a window below 64k will always 1791 * result in allocating new resources and never adjusting an 1792 * existing resource. 1793 */ 1794 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1795 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1796 KASSERT(limit == w->limit || limit <= 65535, 1797 ("attempting to grow both ends across 64k ISA alias")); 1798 1799 if (base != w->base) 1800 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1801 else 1802 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1803 limit); 1804 if (error == 0) { 1805 w->base = base; 1806 w->limit = limit; 1807 } 1808 return (error); 1809 } 1810 1811 /* 1812 * Find the existing resource to adjust. Usually there is only one, 1813 * but for an ISA-enabled bridge we might be growing the I/O window 1814 * above 64k and need to find the existing resource that maps all 1815 * of the area above 64k. 1816 */ 1817 for (i = 0; i < w->count; i++) { 1818 if (rman_get_end(w->res[i]) == w->limit) 1819 break; 1820 } 1821 KASSERT(i != w->count, ("did not find existing resource")); 1822 res = w->res[i]; 1823 1824 /* 1825 * Usually the resource we found should match the window's 1826 * existing range. The one exception is the ISA-enabled case 1827 * mentioned above in which case the resource should start at 1828 * 64k. 1829 */ 1830 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1831 w->base <= 65535) { 1832 KASSERT(rman_get_start(res) == 65536, 1833 ("existing resource mismatch")); 1834 force_64k_base = 1; 1835 } else { 1836 KASSERT(w->base == rman_get_start(res), 1837 ("existing resource mismatch")); 1838 force_64k_base = 0; 1839 } 1840 1841 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1842 rman_get_start(res) : base, limit); 1843 if (error) 1844 return (error); 1845 1846 /* Add the newly allocated region to the resource manager. */ 1847 if (w->base != base) { 1848 error = rman_manage_region(&w->rman, base, w->base - 1); 1849 w->base = base; 1850 } else { 1851 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1852 w->limit = limit; 1853 } 1854 if (error) { 1855 if (bootverbose) 1856 device_printf(sc->dev, 1857 "failed to expand %s resource manager\n", w->name); 1858 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1859 rman_get_start(res) : w->base, w->limit); 1860 } 1861 return (error); 1862 } 1863 1864 /* 1865 * Attempt to grow a window to make room for a given resource request. 1866 */ 1867 static int 1868 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1869 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1870 { 1871 rman_res_t align, start_free, end_free, front, back, wmask; 1872 int error; 1873 1874 /* 1875 * Clamp the desired resource range to the maximum address 1876 * this window supports. Reject impossible requests. 1877 * 1878 * For I/O port requests behind a bridge with the ISA enable 1879 * bit set, force large allocations to start above 64k. 1880 */ 1881 if (!w->valid) 1882 return (EINVAL); 1883 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1884 start < 65536) 1885 start = 65536; 1886 if (end > w->rman.rm_end) 1887 end = w->rman.rm_end; 1888 if (start + count - 1 > end || start + count < start) 1889 return (EINVAL); 1890 wmask = ((rman_res_t)1 << w->step) - 1; 1891 1892 /* 1893 * If there is no resource at all, just try to allocate enough 1894 * aligned space for this resource. 1895 */ 1896 if (w->res == NULL) { 1897 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1898 flags); 1899 if (error) { 1900 if (bootverbose) 1901 device_printf(sc->dev, 1902 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 1903 w->name, start, end, count); 1904 return (error); 1905 } 1906 if (bootverbose) 1907 device_printf(sc->dev, 1908 "allocated initial %s window of %#jx-%#jx\n", 1909 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1910 goto updatewin; 1911 } 1912 1913 /* 1914 * See if growing the window would help. Compute the minimum 1915 * amount of address space needed on both the front and back 1916 * ends of the existing window to satisfy the allocation. 1917 * 1918 * For each end, build a candidate region adjusting for the 1919 * required alignment, etc. If there is a free region at the 1920 * edge of the window, grow from the inner edge of the free 1921 * region. Otherwise grow from the window boundary. 1922 * 1923 * Growing an I/O window below 64k for a bridge with the ISA 1924 * enable bit doesn't require any special magic as the step 1925 * size of an I/O window (1k) always includes multiple 1926 * non-alias ranges when it is grown in either direction. 1927 * 1928 * XXX: Special case: if w->res is completely empty and the 1929 * request size is larger than w->res, we should find the 1930 * optimal aligned buffer containing w->res and allocate that. 1931 */ 1932 if (bootverbose) 1933 device_printf(sc->dev, 1934 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 1935 w->name, start, end, count); 1936 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 1937 if (start < w->base) { 1938 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1939 0 || start_free != w->base) 1940 end_free = w->base; 1941 if (end_free > end) 1942 end_free = end + 1; 1943 1944 /* Move end_free down until it is properly aligned. */ 1945 end_free &= ~(align - 1); 1946 end_free--; 1947 front = end_free - (count - 1); 1948 1949 /* 1950 * The resource would now be allocated at (front, 1951 * end_free). Ensure that fits in the (start, end) 1952 * bounds. end_free is checked above. If 'front' is 1953 * ok, ensure it is properly aligned for this window. 1954 * Also check for underflow. 1955 */ 1956 if (front >= start && front <= end_free) { 1957 if (bootverbose) 1958 printf("\tfront candidate range: %#jx-%#jx\n", 1959 front, end_free); 1960 front &= ~wmask; 1961 front = w->base - front; 1962 } else 1963 front = 0; 1964 } else 1965 front = 0; 1966 if (end > w->limit) { 1967 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1968 0 || end_free != w->limit) 1969 start_free = w->limit + 1; 1970 if (start_free < start) 1971 start_free = start; 1972 1973 /* Move start_free up until it is properly aligned. */ 1974 start_free = roundup2(start_free, align); 1975 back = start_free + count - 1; 1976 1977 /* 1978 * The resource would now be allocated at (start_free, 1979 * back). Ensure that fits in the (start, end) 1980 * bounds. start_free is checked above. If 'back' is 1981 * ok, ensure it is properly aligned for this window. 1982 * Also check for overflow. 1983 */ 1984 if (back <= end && start_free <= back) { 1985 if (bootverbose) 1986 printf("\tback candidate range: %#jx-%#jx\n", 1987 start_free, back); 1988 back |= wmask; 1989 back -= w->limit; 1990 } else 1991 back = 0; 1992 } else 1993 back = 0; 1994 1995 /* 1996 * Try to allocate the smallest needed region first. 1997 * If that fails, fall back to the other region. 1998 */ 1999 error = ENOSPC; 2000 while (front != 0 || back != 0) { 2001 if (front != 0 && (front <= back || back == 0)) { 2002 error = pcib_expand_window(sc, w, type, w->base - front, 2003 w->limit); 2004 if (error == 0) 2005 break; 2006 front = 0; 2007 } else { 2008 error = pcib_expand_window(sc, w, type, w->base, 2009 w->limit + back); 2010 if (error == 0) 2011 break; 2012 back = 0; 2013 } 2014 } 2015 2016 if (error) 2017 return (error); 2018 if (bootverbose) 2019 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2020 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2021 2022 updatewin: 2023 /* Write the new window. */ 2024 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2025 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2026 pcib_write_windows(sc, w->mask); 2027 return (0); 2028 } 2029 2030 /* 2031 * We have to trap resource allocation requests and ensure that the bridge 2032 * is set up to, or capable of handling them. 2033 */ 2034 static struct resource * 2035 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2036 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2037 { 2038 struct pcib_softc *sc; 2039 struct resource *r; 2040 2041 sc = device_get_softc(dev); 2042 2043 /* 2044 * VGA resources are decoded iff the VGA enable bit is set in 2045 * the bridge control register. VGA resources do not fall into 2046 * the resource windows and are passed up to the parent. 2047 */ 2048 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2049 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2050 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2051 return (bus_generic_alloc_resource(dev, child, type, 2052 rid, start, end, count, flags)); 2053 else 2054 return (NULL); 2055 } 2056 2057 switch (type) { 2058 case PCI_RES_BUS: 2059 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2060 count, flags)); 2061 case SYS_RES_IOPORT: 2062 if (pcib_is_isa_range(sc, start, end, count)) 2063 return (NULL); 2064 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2065 end, count, flags); 2066 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2067 break; 2068 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2069 flags) == 0) 2070 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2071 rid, start, end, count, flags); 2072 break; 2073 case SYS_RES_MEMORY: 2074 /* 2075 * For prefetchable resources, prefer the prefetchable 2076 * memory window, but fall back to the regular memory 2077 * window if that fails. Try both windows before 2078 * attempting to grow a window in case the firmware 2079 * has used a range in the regular memory window to 2080 * map a prefetchable BAR. 2081 */ 2082 if (flags & RF_PREFETCHABLE) { 2083 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2084 rid, start, end, count, flags); 2085 if (r != NULL) 2086 break; 2087 } 2088 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2089 start, end, count, flags); 2090 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2091 break; 2092 if (flags & RF_PREFETCHABLE) { 2093 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2094 count, flags) == 0) { 2095 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2096 type, rid, start, end, count, flags); 2097 if (r != NULL) 2098 break; 2099 } 2100 } 2101 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2102 flags & ~RF_PREFETCHABLE) == 0) 2103 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2104 rid, start, end, count, flags); 2105 break; 2106 default: 2107 return (bus_generic_alloc_resource(dev, child, type, rid, 2108 start, end, count, flags)); 2109 } 2110 2111 /* 2112 * If attempts to suballocate from the window fail but this is a 2113 * subtractive bridge, pass the request up the tree. 2114 */ 2115 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2116 return (bus_generic_alloc_resource(dev, child, type, rid, 2117 start, end, count, flags)); 2118 return (r); 2119 } 2120 2121 static int 2122 pcib_adjust_resource(device_t bus, device_t child, struct resource *r, 2123 rman_res_t start, rman_res_t end) 2124 { 2125 struct pcib_softc *sc; 2126 struct pcib_window *w; 2127 rman_res_t wmask; 2128 int error, type; 2129 2130 sc = device_get_softc(bus); 2131 type = rman_get_type(r); 2132 2133 /* 2134 * If the resource wasn't sub-allocated from one of our region 2135 * managers then just pass the request up. 2136 */ 2137 if (!pcib_is_resource_managed(sc, r)) 2138 return (bus_generic_adjust_resource(bus, child, r, start, end)); 2139 2140 if (type == PCI_RES_BUS) { 2141 /* 2142 * If our bus range isn't big enough to grow the sub-allocation 2143 * then we need to grow our bus range. Any request that would 2144 * require us to decrease the start of our own bus range is 2145 * invalid, we can only extend the end; ignore such requests 2146 * and let rman_adjust_resource fail below. 2147 */ 2148 if (start >= sc->bus.sec && end > sc->bus.sub) { 2149 error = pcib_grow_subbus(&sc->bus, end); 2150 if (error != 0) 2151 return (error); 2152 } 2153 } else { 2154 /* 2155 * Resource is managed and not a secondary bus number, must 2156 * be from one of our windows. 2157 */ 2158 w = pcib_get_resource_window(sc, r); 2159 KASSERT(w != NULL, 2160 ("%s: no window for resource (%#jx-%#jx) type %d", 2161 __func__, rman_get_start(r), rman_get_end(r), type)); 2162 2163 /* 2164 * If our window isn't big enough to grow the sub-allocation 2165 * then we need to expand the window. 2166 */ 2167 if (start < w->base || end > w->limit) { 2168 wmask = ((rman_res_t)1 << w->step) - 1; 2169 error = pcib_expand_window(sc, w, type, 2170 MIN(start & ~wmask, w->base), 2171 MAX(end | wmask, w->limit)); 2172 if (error != 0) 2173 return (error); 2174 if (bootverbose) 2175 device_printf(sc->dev, 2176 "grew %s window to %#jx-%#jx\n", 2177 w->name, (uintmax_t)w->base, 2178 (uintmax_t)w->limit); 2179 pcib_write_windows(sc, w->mask); 2180 } 2181 } 2182 2183 return (rman_adjust_resource(r, start, end)); 2184 } 2185 2186 static int 2187 pcib_release_resource(device_t dev, device_t child, struct resource *r) 2188 { 2189 struct pcib_softc *sc; 2190 int error; 2191 2192 sc = device_get_softc(dev); 2193 if (pcib_is_resource_managed(sc, r)) { 2194 if (rman_get_flags(r) & RF_ACTIVE) { 2195 error = bus_deactivate_resource(child, r); 2196 if (error) 2197 return (error); 2198 } 2199 return (rman_release_resource(r)); 2200 } 2201 return (bus_generic_release_resource(dev, child, r)); 2202 } 2203 2204 static int 2205 pcib_activate_resource(device_t dev, device_t child, struct resource *r) 2206 { 2207 struct pcib_softc *sc = device_get_softc(dev); 2208 struct resource_map map; 2209 int error, type; 2210 2211 if (!pcib_is_resource_managed(sc, r)) 2212 return (bus_generic_activate_resource(dev, child, r)); 2213 2214 error = rman_activate_resource(r); 2215 if (error != 0) 2216 return (error); 2217 2218 type = rman_get_type(r); 2219 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2220 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2221 error = BUS_MAP_RESOURCE(dev, child, r, NULL, &map); 2222 if (error != 0) { 2223 rman_deactivate_resource(r); 2224 return (error); 2225 } 2226 2227 rman_set_mapping(r, &map); 2228 } 2229 return (0); 2230 } 2231 2232 static int 2233 pcib_deactivate_resource(device_t dev, device_t child, struct resource *r) 2234 { 2235 struct pcib_softc *sc = device_get_softc(dev); 2236 struct resource_map map; 2237 int error, type; 2238 2239 if (!pcib_is_resource_managed(sc, r)) 2240 return (bus_generic_deactivate_resource(dev, child, r)); 2241 2242 error = rman_deactivate_resource(r); 2243 if (error != 0) 2244 return (error); 2245 2246 type = rman_get_type(r); 2247 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2248 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2249 rman_get_mapping(r, &map); 2250 BUS_UNMAP_RESOURCE(dev, child, r, &map); 2251 } 2252 return (0); 2253 } 2254 2255 static struct resource * 2256 pcib_find_parent_resource(struct pcib_window *w, struct resource *r) 2257 { 2258 for (int i = 0; i < w->count; i++) { 2259 if (rman_get_start(w->res[i]) <= rman_get_start(r) && 2260 rman_get_end(w->res[i]) >= rman_get_end(r)) 2261 return (w->res[i]); 2262 } 2263 return (NULL); 2264 } 2265 2266 static int 2267 pcib_map_resource(device_t dev, device_t child, struct resource *r, 2268 struct resource_map_request *argsp, struct resource_map *map) 2269 { 2270 struct pcib_softc *sc = device_get_softc(dev); 2271 struct resource_map_request args; 2272 struct pcib_window *w; 2273 struct resource *pres; 2274 rman_res_t length, start; 2275 int error; 2276 2277 w = pcib_get_resource_window(sc, r); 2278 if (w == NULL) 2279 return (bus_generic_map_resource(dev, child, r, argsp, map)); 2280 2281 /* Resources must be active to be mapped. */ 2282 if (!(rman_get_flags(r) & RF_ACTIVE)) 2283 return (ENXIO); 2284 2285 resource_init_map_request(&args); 2286 error = resource_validate_map_request(r, argsp, &args, &start, &length); 2287 if (error) 2288 return (error); 2289 2290 pres = pcib_find_parent_resource(w, r); 2291 if (pres == NULL) 2292 return (ENOENT); 2293 2294 args.offset = start - rman_get_start(pres); 2295 args.length = length; 2296 return (bus_map_resource(dev, pres, &args, map)); 2297 } 2298 2299 static int 2300 pcib_unmap_resource(device_t dev, device_t child, struct resource *r, 2301 struct resource_map *map) 2302 { 2303 struct pcib_softc *sc = device_get_softc(dev); 2304 struct pcib_window *w; 2305 struct resource *pres; 2306 2307 w = pcib_get_resource_window(sc, r); 2308 if (w == NULL) 2309 return (bus_generic_unmap_resource(dev, child, r, map)); 2310 2311 pres = pcib_find_parent_resource(w, r); 2312 if (pres == NULL) 2313 return (ENOENT); 2314 return (bus_unmap_resource(dev, pres, map)); 2315 } 2316 2317 /* 2318 * If ARI is enabled on this downstream port, translate the function number 2319 * to the non-ARI slot/function. The downstream port will convert it back in 2320 * hardware. If ARI is not enabled slot and func are not modified. 2321 */ 2322 static __inline void 2323 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2324 { 2325 struct pcib_softc *sc; 2326 int ari_func; 2327 2328 sc = device_get_softc(pcib); 2329 ari_func = *func; 2330 2331 if (sc->flags & PCIB_ENABLE_ARI) { 2332 KASSERT(*slot == 0, 2333 ("Non-zero slot number with ARI enabled!")); 2334 *slot = PCIE_ARI_SLOT(ari_func); 2335 *func = PCIE_ARI_FUNC(ari_func); 2336 } 2337 } 2338 2339 static void 2340 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2341 { 2342 uint32_t ctl2; 2343 2344 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2345 ctl2 |= PCIEM_CTL2_ARI; 2346 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2347 2348 sc->flags |= PCIB_ENABLE_ARI; 2349 } 2350 2351 /* 2352 * PCIB interface. 2353 */ 2354 int 2355 pcib_maxslots(device_t dev) 2356 { 2357 #if !defined(__amd64__) && !defined(__i386__) 2358 uint32_t pcie_pos; 2359 uint16_t val; 2360 2361 /* 2362 * If this is a PCIe rootport or downstream switch port, there's only 2363 * one slot permitted. 2364 */ 2365 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) { 2366 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2); 2367 val &= PCIEM_FLAGS_TYPE; 2368 if (val == PCIEM_TYPE_ROOT_PORT || 2369 val == PCIEM_TYPE_DOWNSTREAM_PORT) 2370 return (0); 2371 } 2372 #endif 2373 return (PCI_SLOTMAX); 2374 } 2375 2376 static int 2377 pcib_ari_maxslots(device_t dev) 2378 { 2379 struct pcib_softc *sc; 2380 2381 sc = device_get_softc(dev); 2382 2383 if (sc->flags & PCIB_ENABLE_ARI) 2384 return (PCIE_ARI_SLOTMAX); 2385 else 2386 return (pcib_maxslots(dev)); 2387 } 2388 2389 static int 2390 pcib_ari_maxfuncs(device_t dev) 2391 { 2392 struct pcib_softc *sc; 2393 2394 sc = device_get_softc(dev); 2395 2396 if (sc->flags & PCIB_ENABLE_ARI) 2397 return (PCIE_ARI_FUNCMAX); 2398 else 2399 return (PCI_FUNCMAX); 2400 } 2401 2402 static void 2403 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2404 int *func) 2405 { 2406 struct pcib_softc *sc; 2407 2408 sc = device_get_softc(pcib); 2409 2410 *bus = PCI_RID2BUS(rid); 2411 if (sc->flags & PCIB_ENABLE_ARI) { 2412 *slot = PCIE_ARI_RID2SLOT(rid); 2413 *func = PCIE_ARI_RID2FUNC(rid); 2414 } else { 2415 *slot = PCI_RID2SLOT(rid); 2416 *func = PCI_RID2FUNC(rid); 2417 } 2418 } 2419 2420 /* 2421 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2422 */ 2423 static uint32_t 2424 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2425 { 2426 #ifdef PCI_HP 2427 struct pcib_softc *sc; 2428 2429 sc = device_get_softc(dev); 2430 if (!pcib_present(sc)) { 2431 switch (width) { 2432 case 2: 2433 return (0xffff); 2434 case 1: 2435 return (0xff); 2436 default: 2437 return (0xffffffff); 2438 } 2439 } 2440 #endif 2441 pcib_xlate_ari(dev, b, &s, &f); 2442 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2443 f, reg, width)); 2444 } 2445 2446 static void 2447 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2448 { 2449 #ifdef PCI_HP 2450 struct pcib_softc *sc; 2451 2452 sc = device_get_softc(dev); 2453 if (!pcib_present(sc)) 2454 return; 2455 #endif 2456 pcib_xlate_ari(dev, b, &s, &f); 2457 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2458 reg, val, width); 2459 } 2460 2461 /* 2462 * Route an interrupt across a PCI bridge. 2463 */ 2464 int 2465 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2466 { 2467 device_t bus; 2468 int parent_intpin; 2469 int intnum; 2470 2471 /* 2472 * 2473 * The PCI standard defines a swizzle of the child-side device/intpin to 2474 * the parent-side intpin as follows. 2475 * 2476 * device = device on child bus 2477 * child_intpin = intpin on child bus slot (0-3) 2478 * parent_intpin = intpin on parent bus slot (0-3) 2479 * 2480 * parent_intpin = (device + child_intpin) % 4 2481 */ 2482 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2483 2484 /* 2485 * Our parent is a PCI bus. Its parent must export the pcib interface 2486 * which includes the ability to route interrupts. 2487 */ 2488 bus = device_get_parent(pcib); 2489 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2490 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2491 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2492 pci_get_slot(dev), 'A' + pin - 1, intnum); 2493 } 2494 return(intnum); 2495 } 2496 2497 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2498 int 2499 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2500 { 2501 struct pcib_softc *sc = device_get_softc(pcib); 2502 device_t bus; 2503 2504 if (sc->flags & PCIB_DISABLE_MSI) 2505 return (ENXIO); 2506 bus = device_get_parent(pcib); 2507 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2508 irqs)); 2509 } 2510 2511 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2512 int 2513 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2514 { 2515 device_t bus; 2516 2517 bus = device_get_parent(pcib); 2518 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2519 } 2520 2521 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2522 int 2523 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2524 { 2525 struct pcib_softc *sc = device_get_softc(pcib); 2526 device_t bus; 2527 2528 if (sc->flags & PCIB_DISABLE_MSIX) 2529 return (ENXIO); 2530 bus = device_get_parent(pcib); 2531 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2532 } 2533 2534 /* Pass request to release an MSI-X message up to the parent bridge. */ 2535 int 2536 pcib_release_msix(device_t pcib, device_t dev, int irq) 2537 { 2538 device_t bus; 2539 2540 bus = device_get_parent(pcib); 2541 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2542 } 2543 2544 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2545 int 2546 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2547 uint32_t *data) 2548 { 2549 device_t bus; 2550 int error; 2551 2552 bus = device_get_parent(pcib); 2553 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2554 if (error) 2555 return (error); 2556 2557 pci_ht_map_msi(pcib, *addr); 2558 return (0); 2559 } 2560 2561 /* Pass request for device power state up to parent bridge. */ 2562 int 2563 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2564 { 2565 device_t bus; 2566 2567 bus = device_get_parent(pcib); 2568 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2569 } 2570 2571 static int 2572 pcib_ari_enabled(device_t pcib) 2573 { 2574 struct pcib_softc *sc; 2575 2576 sc = device_get_softc(pcib); 2577 2578 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2579 } 2580 2581 static int 2582 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2583 uintptr_t *id) 2584 { 2585 struct pcib_softc *sc; 2586 device_t bus_dev; 2587 uint8_t bus, slot, func; 2588 2589 if (type != PCI_ID_RID) { 2590 bus_dev = device_get_parent(pcib); 2591 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2592 } 2593 2594 sc = device_get_softc(pcib); 2595 2596 if (sc->flags & PCIB_ENABLE_ARI) { 2597 bus = pci_get_bus(dev); 2598 func = pci_get_function(dev); 2599 2600 *id = (PCI_ARI_RID(bus, func)); 2601 } else { 2602 bus = pci_get_bus(dev); 2603 slot = pci_get_slot(dev); 2604 func = pci_get_function(dev); 2605 2606 *id = (PCI_RID(bus, slot, func)); 2607 } 2608 2609 return (0); 2610 } 2611 2612 /* 2613 * Check that the downstream port (pcib) and the endpoint device (dev) both 2614 * support ARI. If so, enable it and return 0, otherwise return an error. 2615 */ 2616 static int 2617 pcib_try_enable_ari(device_t pcib, device_t dev) 2618 { 2619 struct pcib_softc *sc; 2620 int error; 2621 uint32_t cap2; 2622 int ari_cap_off; 2623 uint32_t ari_ver; 2624 uint32_t pcie_pos; 2625 2626 sc = device_get_softc(pcib); 2627 2628 /* 2629 * ARI is controlled in a register in the PCIe capability structure. 2630 * If the downstream port does not have the PCIe capability structure 2631 * then it does not support ARI. 2632 */ 2633 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2634 if (error != 0) 2635 return (ENODEV); 2636 2637 /* Check that the PCIe port advertises ARI support. */ 2638 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2639 if (!(cap2 & PCIEM_CAP2_ARI)) 2640 return (ENODEV); 2641 2642 /* 2643 * Check that the endpoint device advertises ARI support via the ARI 2644 * extended capability structure. 2645 */ 2646 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2647 if (error != 0) 2648 return (ENODEV); 2649 2650 /* 2651 * Finally, check that the endpoint device supports the same version 2652 * of ARI that we do. 2653 */ 2654 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2655 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2656 if (bootverbose) 2657 device_printf(pcib, 2658 "Unsupported version of ARI (%d) detected\n", 2659 PCI_EXTCAP_VER(ari_ver)); 2660 2661 return (ENXIO); 2662 } 2663 2664 pcib_enable_ari(sc, pcie_pos); 2665 2666 return (0); 2667 } 2668 2669 int 2670 pcib_request_feature_allow(device_t pcib, device_t dev, 2671 enum pci_feature feature) 2672 { 2673 /* 2674 * No host firmware we have to negotiate with, so we allow 2675 * every valid feature requested. 2676 */ 2677 switch (feature) { 2678 case PCI_FEATURE_AER: 2679 case PCI_FEATURE_HP: 2680 break; 2681 default: 2682 return (EINVAL); 2683 } 2684 2685 return (0); 2686 } 2687 2688 int 2689 pcib_request_feature(device_t dev, enum pci_feature feature) 2690 { 2691 2692 /* 2693 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2694 * the firmware overrides the method of PCI-PCI bridges. 2695 */ 2696 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2697 } 2698 2699 /* 2700 * Pass the request to use this PCI feature up the tree. Either there's a 2701 * firmware like ACPI that's using this feature that will approve (or deny) the 2702 * request to take it over, or the platform has no such firmware, in which case 2703 * the request will be approved. If the request is approved, the OS is expected 2704 * to make use of the feature or render it harmless. 2705 */ 2706 static int 2707 pcib_request_feature_default(device_t pcib, device_t dev, 2708 enum pci_feature feature) 2709 { 2710 device_t bus; 2711 2712 /* 2713 * Our parent is necessarily a pci bus. Its parent will either be 2714 * another pci bridge (which passes it up) or a host bridge that can 2715 * approve or reject the request. 2716 */ 2717 bus = device_get_parent(pcib); 2718 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2719 } 2720 2721 static int 2722 pcib_reset_child(device_t dev, device_t child, int flags) 2723 { 2724 struct pci_devinfo *pdinfo; 2725 int error; 2726 2727 error = 0; 2728 if (dev == NULL || device_get_parent(child) != dev) 2729 goto out; 2730 error = ENXIO; 2731 if (device_get_devclass(child) != devclass_find("pci")) 2732 goto out; 2733 pdinfo = device_get_ivars(dev); 2734 if (pdinfo->cfg.pcie.pcie_location != 0 && 2735 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT || 2736 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) { 2737 error = bus_helper_reset_prepare(child, flags); 2738 if (error == 0) { 2739 error = pcie_link_reset(dev, 2740 pdinfo->cfg.pcie.pcie_location); 2741 /* XXXKIB call _post even if error != 0 ? */ 2742 bus_helper_reset_post(child, flags); 2743 } 2744 } 2745 out: 2746 return (error); 2747 } 2748