1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "pcib_if.h" 54 55 static int pcib_probe(device_t dev); 56 57 static device_method_t pcib_methods[] = { 58 /* Device interface */ 59 DEVMETHOD(device_probe, pcib_probe), 60 DEVMETHOD(device_attach, pcib_attach), 61 DEVMETHOD(device_detach, bus_generic_detach), 62 DEVMETHOD(device_shutdown, bus_generic_shutdown), 63 DEVMETHOD(device_suspend, bus_generic_suspend), 64 DEVMETHOD(device_resume, bus_generic_resume), 65 66 /* Bus interface */ 67 DEVMETHOD(bus_print_child, bus_generic_print_child), 68 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 69 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 71 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 76 77 /* pcib interface */ 78 DEVMETHOD(pcib_maxslots, pcib_maxslots), 79 DEVMETHOD(pcib_read_config, pcib_read_config), 80 DEVMETHOD(pcib_write_config, pcib_write_config), 81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 82 83 { 0, 0 } 84 }; 85 86 static devclass_t pcib_devclass; 87 88 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 89 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 90 91 /* 92 * Generic device interface 93 */ 94 static int 95 pcib_probe(device_t dev) 96 { 97 if ((pci_get_class(dev) == PCIC_BRIDGE) && 98 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 99 device_set_desc(dev, "PCI-PCI bridge"); 100 return(-10000); 101 } 102 return(ENXIO); 103 } 104 105 void 106 pcib_attach_common(device_t dev) 107 { 108 struct pcib_softc *sc; 109 uint8_t iolow; 110 111 sc = device_get_softc(dev); 112 sc->dev = dev; 113 114 /* 115 * Get current bridge configuration. 116 */ 117 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 118 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 119 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 120 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 121 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 122 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 123 124 /* 125 * Determine current I/O decode. 126 */ 127 if (sc->command & PCIM_CMD_PORTEN) { 128 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 129 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 130 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 131 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 132 } else { 133 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 134 } 135 136 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 137 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 138 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 139 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 140 } else { 141 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 142 } 143 } 144 145 /* 146 * Determine current memory decode. 147 */ 148 if (sc->command & PCIM_CMD_MEMEN) { 149 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 150 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 151 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 152 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 153 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 154 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 155 } 156 157 /* 158 * Quirk handling. 159 */ 160 switch (pci_get_devid(dev)) { 161 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 162 { 163 uint8_t supbus; 164 165 supbus = pci_read_config(dev, 0x41, 1); 166 if (supbus != 0xff) { 167 sc->secbus = supbus + 1; 168 sc->subbus = supbus + 1; 169 } 170 break; 171 } 172 173 /* 174 * The i82380FB mobile docking controller is a PCI-PCI bridge, 175 * and it is a subtractive bridge. However, the ProgIf is wrong 176 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 177 * happen. There's also a Toshiba bridge that behaves this 178 * way. 179 */ 180 case 0x124b8086: /* Intel 82380FB Mobile */ 181 case 0x060513d7: /* Toshiba ???? */ 182 sc->flags |= PCIB_SUBTRACTIVE; 183 break; 184 185 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 186 case 0x00dd10de: 187 { 188 char *cp; 189 190 if ((cp = getenv("smbios.planar.maker")) == NULL) 191 break; 192 if (strncmp(cp, "Compal", 6) != 0) { 193 freeenv(cp); 194 break; 195 } 196 freeenv(cp); 197 if ((cp = getenv("smbios.planar.product")) == NULL) 198 break; 199 if (strncmp(cp, "08A0", 4) != 0) { 200 freeenv(cp); 201 break; 202 } 203 freeenv(cp); 204 if (sc->subbus < 0xa) { 205 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 206 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 207 } 208 break; 209 } 210 } 211 212 /* 213 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 214 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 215 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 216 * This means they act as if they were subtractively decoding 217 * bridges and pass all transactions. Mark them and real ProgIf 1 218 * parts as subtractive. 219 */ 220 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 221 pci_read_config(dev, PCIR_PROGIF, 1) == 1) 222 sc->flags |= PCIB_SUBTRACTIVE; 223 224 if (bootverbose) { 225 device_printf(dev, " secondary bus %d\n", sc->secbus); 226 device_printf(dev, " subordinate bus %d\n", sc->subbus); 227 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 228 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 229 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 230 if (sc->flags & PCIB_SUBTRACTIVE) 231 device_printf(dev, " Subtractively decoded bridge.\n"); 232 } 233 234 /* 235 * XXX If the secondary bus number is zero, we should assign a bus number 236 * since the BIOS hasn't, then initialise the bridge. 237 */ 238 239 /* 240 * XXX If the subordinate bus number is less than the secondary bus number, 241 * we should pick a better value. One sensible alternative would be to 242 * pick 255; the only tradeoff here is that configuration transactions 243 * would be more widely routed than absolutely necessary. 244 */ 245 } 246 247 int 248 pcib_attach(device_t dev) 249 { 250 struct pcib_softc *sc; 251 device_t child; 252 253 pcib_attach_common(dev); 254 sc = device_get_softc(dev); 255 if (sc->secbus != 0) { 256 child = device_add_child(dev, "pci", sc->secbus); 257 if (child != NULL) 258 return(bus_generic_attach(dev)); 259 } 260 261 /* no secondary bus; we should have fixed this */ 262 return(0); 263 } 264 265 int 266 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 267 { 268 struct pcib_softc *sc = device_get_softc(dev); 269 270 switch (which) { 271 case PCIB_IVAR_BUS: 272 *result = sc->secbus; 273 return(0); 274 } 275 return(ENOENT); 276 } 277 278 int 279 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 280 { 281 struct pcib_softc *sc = device_get_softc(dev); 282 283 switch (which) { 284 case PCIB_IVAR_BUS: 285 sc->secbus = value; 286 break; 287 } 288 return(ENOENT); 289 } 290 291 /* 292 * Is the prefetch window open (eg, can we allocate memory in it?) 293 */ 294 static int 295 pcib_is_prefetch_open(struct pcib_softc *sc) 296 { 297 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 298 } 299 300 /* 301 * Is the nonprefetch window open (eg, can we allocate memory in it?) 302 */ 303 static int 304 pcib_is_nonprefetch_open(struct pcib_softc *sc) 305 { 306 return (sc->membase > 0 && sc->membase < sc->memlimit); 307 } 308 309 /* 310 * Is the io window open (eg, can we allocate ports in it?) 311 */ 312 static int 313 pcib_is_io_open(struct pcib_softc *sc) 314 { 315 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 316 } 317 318 /* 319 * We have to trap resource allocation requests and ensure that the bridge 320 * is set up to, or capable of handling them. 321 */ 322 struct resource * 323 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 324 u_long start, u_long end, u_long count, u_int flags) 325 { 326 struct pcib_softc *sc = device_get_softc(dev); 327 int ok; 328 329 /* 330 * Fail the allocation for this range if it's not supported. 331 */ 332 switch (type) { 333 case SYS_RES_IOPORT: 334 ok = 0; 335 if (!pcib_is_io_open(sc)) 336 break; 337 ok = (start >= sc->iobase && end <= sc->iolimit); 338 339 /* 340 * Make sure we allow access to VGA I/O addresses when the 341 * bridge has the "VGA Enable" bit set. 342 */ 343 if (!ok && pci_is_vga_ioport_range(start, end)) 344 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 345 346 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 347 if (!ok) { 348 if (start < sc->iobase) 349 start = sc->iobase; 350 if (end > sc->iolimit) 351 end = sc->iolimit; 352 if (start < end) 353 ok = 1; 354 } 355 } else { 356 ok = 1; 357 #if 1 358 if (start < sc->iobase && end > sc->iolimit) { 359 start = sc->iobase; 360 end = sc->iolimit; 361 } 362 #endif 363 } 364 if (end < start) { 365 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 366 end, start); 367 start = 0; 368 end = 0; 369 ok = 0; 370 } 371 if (!ok) { 372 device_printf(dev, "%s requested unsupported I/O " 373 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 374 device_get_nameunit(child), start, end, 375 sc->iobase, sc->iolimit); 376 return (NULL); 377 } 378 if (bootverbose) 379 device_printf(dev, 380 "%s requested I/O range 0x%lx-0x%lx: in range\n", 381 device_get_nameunit(child), start, end); 382 break; 383 384 case SYS_RES_MEMORY: 385 ok = 0; 386 if (pcib_is_nonprefetch_open(sc)) 387 ok = ok || (start >= sc->membase && end <= sc->memlimit); 388 if (pcib_is_prefetch_open(sc)) 389 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 390 391 /* 392 * Make sure we allow access to VGA memory addresses when the 393 * bridge has the "VGA Enable" bit set. 394 */ 395 if (!ok && pci_is_vga_memory_range(start, end)) 396 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 397 398 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 399 if (!ok) { 400 ok = 1; 401 if (flags & RF_PREFETCHABLE) { 402 if (pcib_is_prefetch_open(sc)) { 403 if (start < sc->pmembase) 404 start = sc->pmembase; 405 if (end > sc->pmemlimit) 406 end = sc->pmemlimit; 407 } else { 408 ok = 0; 409 } 410 } else { /* non-prefetchable */ 411 if (pcib_is_nonprefetch_open(sc)) { 412 if (start < sc->membase) 413 start = sc->membase; 414 if (end > sc->memlimit) 415 end = sc->memlimit; 416 } else { 417 ok = 0; 418 } 419 } 420 } 421 } else if (!ok) { 422 ok = 1; /* subtractive bridge: always ok */ 423 #if 1 424 if (pcib_is_nonprefetch_open(sc)) { 425 if (start < sc->membase && end > sc->memlimit) { 426 start = sc->membase; 427 end = sc->memlimit; 428 } 429 } 430 if (pcib_is_prefetch_open(sc)) { 431 if (start < sc->pmembase && end > sc->pmemlimit) { 432 start = sc->pmembase; 433 end = sc->pmemlimit; 434 } 435 } 436 #endif 437 } 438 if (end < start) { 439 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 440 end, start); 441 start = 0; 442 end = 0; 443 ok = 0; 444 } 445 if (!ok && bootverbose) 446 device_printf(dev, 447 "%s requested unsupported memory range " 448 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 449 device_get_nameunit(child), start, end, 450 sc->membase, sc->memlimit, sc->pmembase, 451 sc->pmemlimit); 452 if (!ok) 453 return (NULL); 454 if (bootverbose) 455 device_printf(dev,"%s requested memory range " 456 "0x%lx-0x%lx: good\n", 457 device_get_nameunit(child), start, end); 458 break; 459 460 default: 461 break; 462 } 463 /* 464 * Bridge is OK decoding this resource, so pass it up. 465 */ 466 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 467 count, flags)); 468 } 469 470 /* 471 * PCIB interface. 472 */ 473 int 474 pcib_maxslots(device_t dev) 475 { 476 return(PCI_SLOTMAX); 477 } 478 479 /* 480 * Since we are a child of a PCI bus, its parent must support the pcib interface. 481 */ 482 uint32_t 483 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 484 { 485 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 486 } 487 488 void 489 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 490 { 491 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 492 } 493 494 /* 495 * Route an interrupt across a PCI bridge. 496 */ 497 int 498 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 499 { 500 device_t bus; 501 int parent_intpin; 502 int intnum; 503 504 /* 505 * 506 * The PCI standard defines a swizzle of the child-side device/intpin to 507 * the parent-side intpin as follows. 508 * 509 * device = device on child bus 510 * child_intpin = intpin on child bus slot (0-3) 511 * parent_intpin = intpin on parent bus slot (0-3) 512 * 513 * parent_intpin = (device + child_intpin) % 4 514 */ 515 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 516 517 /* 518 * Our parent is a PCI bus. Its parent must export the pcib interface 519 * which includes the ability to route interrupts. 520 */ 521 bus = device_get_parent(pcib); 522 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 523 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 524 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 525 pci_get_slot(dev), 'A' + pin - 1, intnum); 526 } 527 return(intnum); 528 } 529 530 /* 531 * Try to read the bus number of a host-PCI bridge using appropriate config 532 * registers. 533 */ 534 int 535 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 536 uint8_t *busnum) 537 { 538 uint32_t id; 539 540 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 541 if (id == 0xffffffff) 542 return (0); 543 544 switch (id) { 545 case 0x12258086: 546 /* Intel 824?? */ 547 /* XXX This is a guess */ 548 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 549 *busnum = bus; 550 break; 551 case 0x84c48086: 552 /* Intel 82454KX/GX (Orion) */ 553 *busnum = read_config(bus, slot, func, 0x4a, 1); 554 break; 555 case 0x84ca8086: 556 /* 557 * For the 450nx chipset, there is a whole bundle of 558 * things pretending to be host bridges. The MIOC will 559 * be seen first and isn't really a pci bridge (the 560 * actual busses are attached to the PXB's). We need to 561 * read the registers of the MIOC to figure out the 562 * bus numbers for the PXB channels. 563 * 564 * Since the MIOC doesn't have a pci bus attached, we 565 * pretend it wasn't there. 566 */ 567 return (0); 568 case 0x84cb8086: 569 switch (slot) { 570 case 0x12: 571 /* Intel 82454NX PXB#0, Bus#A */ 572 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 573 break; 574 case 0x13: 575 /* Intel 82454NX PXB#0, Bus#B */ 576 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 577 break; 578 case 0x14: 579 /* Intel 82454NX PXB#1, Bus#A */ 580 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 581 break; 582 case 0x15: 583 /* Intel 82454NX PXB#1, Bus#B */ 584 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 585 break; 586 } 587 break; 588 589 /* ServerWorks -- vendor 0x1166 */ 590 case 0x00051166: 591 case 0x00061166: 592 case 0x00081166: 593 case 0x00091166: 594 case 0x00101166: 595 case 0x00111166: 596 case 0x00171166: 597 case 0x01011166: 598 case 0x010f1014: 599 case 0x02011166: 600 case 0x03021014: 601 *busnum = read_config(bus, slot, func, 0x44, 1); 602 break; 603 604 /* Compaq/HP -- vendor 0x0e11 */ 605 case 0x60100e11: 606 *busnum = read_config(bus, slot, func, 0xc8, 1); 607 break; 608 default: 609 /* Don't know how to read bus number. */ 610 return 0; 611 } 612 613 return 1; 614 } 615