1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 #include <sys/taskqueue.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pci_private.h> 53 #include <dev/pci/pcib_private.h> 54 55 #include "pcib_if.h" 56 57 static int pcib_probe(device_t dev); 58 static int pcib_suspend(device_t dev); 59 static int pcib_resume(device_t dev); 60 static int pcib_power_for_sleep(device_t pcib, device_t dev, 61 int *pstate); 62 static int pcib_ari_get_id(device_t pcib, device_t dev, 63 enum pci_id_type type, uintptr_t *id); 64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 65 u_int f, u_int reg, int width); 66 static void pcib_write_config(device_t dev, u_int b, u_int s, 67 u_int f, u_int reg, uint32_t val, int width); 68 static int pcib_ari_maxslots(device_t dev); 69 static int pcib_ari_maxfuncs(device_t dev); 70 static int pcib_try_enable_ari(device_t pcib, device_t dev); 71 static int pcib_ari_enabled(device_t pcib); 72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 73 int *bus, int *slot, int *func); 74 #ifdef PCI_HP 75 static void pcib_pcie_ab_timeout(void *arg); 76 static void pcib_pcie_cc_timeout(void *arg); 77 static void pcib_pcie_dll_timeout(void *arg); 78 #endif 79 80 static device_method_t pcib_methods[] = { 81 /* Device interface */ 82 DEVMETHOD(device_probe, pcib_probe), 83 DEVMETHOD(device_attach, pcib_attach), 84 DEVMETHOD(device_detach, pcib_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 DEVMETHOD(device_suspend, pcib_suspend), 87 DEVMETHOD(device_resume, pcib_resume), 88 89 /* Bus interface */ 90 DEVMETHOD(bus_child_present, pcib_child_present), 91 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 92 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 94 #ifdef NEW_PCIB 95 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 96 DEVMETHOD(bus_release_resource, pcib_release_resource), 97 #else 98 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 99 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 100 #endif 101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 /* pcib interface */ 107 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 108 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 109 DEVMETHOD(pcib_read_config, pcib_read_config), 110 DEVMETHOD(pcib_write_config, pcib_write_config), 111 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 112 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 113 DEVMETHOD(pcib_release_msi, pcib_release_msi), 114 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 115 DEVMETHOD(pcib_release_msix, pcib_release_msix), 116 DEVMETHOD(pcib_map_msi, pcib_map_msi), 117 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 118 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 119 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 120 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 121 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 122 123 DEVMETHOD_END 124 }; 125 126 static devclass_t pcib_devclass; 127 128 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 129 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 130 131 #if defined(NEW_PCIB) || defined(PCI_HP) 132 SYSCTL_DECL(_hw_pci); 133 #endif 134 135 #ifdef NEW_PCIB 136 static int pci_clear_pcib; 137 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 138 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 139 140 /* 141 * Is a resource from a child device sub-allocated from one of our 142 * resource managers? 143 */ 144 static int 145 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 146 { 147 148 switch (type) { 149 #ifdef PCI_RES_BUS 150 case PCI_RES_BUS: 151 return (rman_is_region_manager(r, &sc->bus.rman)); 152 #endif 153 case SYS_RES_IOPORT: 154 return (rman_is_region_manager(r, &sc->io.rman)); 155 case SYS_RES_MEMORY: 156 /* Prefetchable resources may live in either memory rman. */ 157 if (rman_get_flags(r) & RF_PREFETCHABLE && 158 rman_is_region_manager(r, &sc->pmem.rman)) 159 return (1); 160 return (rman_is_region_manager(r, &sc->mem.rman)); 161 } 162 return (0); 163 } 164 165 static int 166 pcib_is_window_open(struct pcib_window *pw) 167 { 168 169 return (pw->valid && pw->base < pw->limit); 170 } 171 172 /* 173 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 174 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 175 * when allocating the resource windows and rely on the PCI bus driver 176 * to do this for us. 177 */ 178 static void 179 pcib_activate_window(struct pcib_softc *sc, int type) 180 { 181 182 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 183 } 184 185 static void 186 pcib_write_windows(struct pcib_softc *sc, int mask) 187 { 188 device_t dev; 189 uint32_t val; 190 191 dev = sc->dev; 192 if (sc->io.valid && mask & WIN_IO) { 193 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 194 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 195 pci_write_config(dev, PCIR_IOBASEH_1, 196 sc->io.base >> 16, 2); 197 pci_write_config(dev, PCIR_IOLIMITH_1, 198 sc->io.limit >> 16, 2); 199 } 200 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 201 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 202 } 203 204 if (mask & WIN_MEM) { 205 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 206 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 207 } 208 209 if (sc->pmem.valid && mask & WIN_PMEM) { 210 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 211 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 212 pci_write_config(dev, PCIR_PMBASEH_1, 213 sc->pmem.base >> 32, 4); 214 pci_write_config(dev, PCIR_PMLIMITH_1, 215 sc->pmem.limit >> 32, 4); 216 } 217 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 218 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 219 } 220 } 221 222 /* 223 * This is used to reject I/O port allocations that conflict with an 224 * ISA alias range. 225 */ 226 static int 227 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 228 rman_res_t count) 229 { 230 rman_res_t next_alias; 231 232 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 233 return (0); 234 235 /* Only check fixed ranges for overlap. */ 236 if (start + count - 1 != end) 237 return (0); 238 239 /* ISA aliases are only in the lower 64KB of I/O space. */ 240 if (start >= 65536) 241 return (0); 242 243 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 244 if (start < 0x100) 245 goto alias; 246 247 /* 248 * If the start address is an alias, the range is an alias. 249 * Otherwise, compute the start of the next alias range and 250 * check if it is before the end of the candidate range. 251 */ 252 if ((start & 0x300) != 0) 253 goto alias; 254 next_alias = (start & ~0x3fful) | 0x100; 255 if (next_alias <= end) 256 goto alias; 257 return (0); 258 259 alias: 260 if (bootverbose) 261 device_printf(sc->dev, 262 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 263 end); 264 return (1); 265 } 266 267 static void 268 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 269 int count) 270 { 271 struct resource **newarray; 272 int error, i; 273 274 newarray = malloc(sizeof(struct resource *) * (w->count + count), 275 M_DEVBUF, M_WAITOK); 276 if (w->res != NULL) 277 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 278 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 279 free(w->res, M_DEVBUF); 280 w->res = newarray; 281 w->count += count; 282 283 for (i = 0; i < count; i++) { 284 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 285 rman_get_end(res[i])); 286 if (error) 287 panic("Failed to add resource to rman"); 288 } 289 } 290 291 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 292 293 static void 294 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 295 void *arg) 296 { 297 rman_res_t next_end; 298 299 /* 300 * If start is within an ISA alias range, move up to the start 301 * of the next non-alias range. As a special case, addresses 302 * in the range 0x000 - 0x0ff should also be skipped since 303 * those are used for various system I/O devices in ISA 304 * systems. 305 */ 306 if (start <= 65535) { 307 if (start < 0x100 || (start & 0x300) != 0) { 308 start &= ~0x3ff; 309 start += 0x400; 310 } 311 } 312 313 /* ISA aliases are only in the lower 64KB of I/O space. */ 314 while (start <= MIN(end, 65535)) { 315 next_end = MIN(start | 0xff, end); 316 cb(start, next_end, arg); 317 start += 0x400; 318 } 319 320 if (start <= end) 321 cb(start, end, arg); 322 } 323 324 static void 325 count_ranges(rman_res_t start, rman_res_t end, void *arg) 326 { 327 int *countp; 328 329 countp = arg; 330 (*countp)++; 331 } 332 333 struct alloc_state { 334 struct resource **res; 335 struct pcib_softc *sc; 336 int count, error; 337 }; 338 339 static void 340 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 341 { 342 struct alloc_state *as; 343 struct pcib_window *w; 344 int rid; 345 346 as = arg; 347 if (as->error != 0) 348 return; 349 350 w = &as->sc->io; 351 rid = w->reg; 352 if (bootverbose) 353 device_printf(as->sc->dev, 354 "allocating non-ISA range %#jx-%#jx\n", start, end); 355 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 356 &rid, start, end, end - start + 1, 0); 357 if (as->res[as->count] == NULL) 358 as->error = ENXIO; 359 else 360 as->count++; 361 } 362 363 static int 364 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 365 { 366 struct alloc_state as; 367 int i, new_count; 368 369 /* First, see how many ranges we need. */ 370 new_count = 0; 371 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 372 373 /* Second, allocate the ranges. */ 374 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 375 M_WAITOK); 376 as.sc = sc; 377 as.count = 0; 378 as.error = 0; 379 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 380 if (as.error != 0) { 381 for (i = 0; i < as.count; i++) 382 bus_release_resource(sc->dev, SYS_RES_IOPORT, 383 sc->io.reg, as.res[i]); 384 free(as.res, M_DEVBUF); 385 return (as.error); 386 } 387 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 388 389 /* Third, add the ranges to the window. */ 390 pcib_add_window_resources(&sc->io, as.res, as.count); 391 free(as.res, M_DEVBUF); 392 return (0); 393 } 394 395 static void 396 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 397 int flags, pci_addr_t max_address) 398 { 399 struct resource *res; 400 char buf[64]; 401 int error, rid; 402 403 if (max_address != (rman_res_t)max_address) 404 max_address = ~0; 405 w->rman.rm_start = 0; 406 w->rman.rm_end = max_address; 407 w->rman.rm_type = RMAN_ARRAY; 408 snprintf(buf, sizeof(buf), "%s %s window", 409 device_get_nameunit(sc->dev), w->name); 410 w->rman.rm_descr = strdup(buf, M_DEVBUF); 411 error = rman_init(&w->rman); 412 if (error) 413 panic("Failed to initialize %s %s rman", 414 device_get_nameunit(sc->dev), w->name); 415 416 if (!pcib_is_window_open(w)) 417 return; 418 419 if (w->base > max_address || w->limit > max_address) { 420 device_printf(sc->dev, 421 "initial %s window has too many bits, ignoring\n", w->name); 422 return; 423 } 424 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 425 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 426 else { 427 rid = w->reg; 428 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 429 w->limit - w->base + 1, flags); 430 if (res != NULL) 431 pcib_add_window_resources(w, &res, 1); 432 } 433 if (w->res == NULL) { 434 device_printf(sc->dev, 435 "failed to allocate initial %s window: %#jx-%#jx\n", 436 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 437 w->base = max_address; 438 w->limit = 0; 439 pcib_write_windows(sc, w->mask); 440 return; 441 } 442 pcib_activate_window(sc, type); 443 } 444 445 /* 446 * Initialize I/O windows. 447 */ 448 static void 449 pcib_probe_windows(struct pcib_softc *sc) 450 { 451 pci_addr_t max; 452 device_t dev; 453 uint32_t val; 454 455 dev = sc->dev; 456 457 if (pci_clear_pcib) { 458 pcib_bridge_init(dev); 459 } 460 461 /* Determine if the I/O port window is implemented. */ 462 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 463 if (val == 0) { 464 /* 465 * If 'val' is zero, then only 16-bits of I/O space 466 * are supported. 467 */ 468 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 469 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 470 sc->io.valid = 1; 471 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 472 } 473 } else 474 sc->io.valid = 1; 475 476 /* Read the existing I/O port window. */ 477 if (sc->io.valid) { 478 sc->io.reg = PCIR_IOBASEL_1; 479 sc->io.step = 12; 480 sc->io.mask = WIN_IO; 481 sc->io.name = "I/O port"; 482 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 483 sc->io.base = PCI_PPBIOBASE( 484 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 485 sc->io.limit = PCI_PPBIOLIMIT( 486 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 487 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 488 max = 0xffffffff; 489 } else { 490 sc->io.base = PCI_PPBIOBASE(0, val); 491 sc->io.limit = PCI_PPBIOLIMIT(0, 492 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 493 max = 0xffff; 494 } 495 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 496 } 497 498 /* Read the existing memory window. */ 499 sc->mem.valid = 1; 500 sc->mem.reg = PCIR_MEMBASE_1; 501 sc->mem.step = 20; 502 sc->mem.mask = WIN_MEM; 503 sc->mem.name = "memory"; 504 sc->mem.base = PCI_PPBMEMBASE(0, 505 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 506 sc->mem.limit = PCI_PPBMEMLIMIT(0, 507 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 508 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 509 510 /* Determine if the prefetchable memory window is implemented. */ 511 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 512 if (val == 0) { 513 /* 514 * If 'val' is zero, then only 32-bits of memory space 515 * are supported. 516 */ 517 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 518 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 519 sc->pmem.valid = 1; 520 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 521 } 522 } else 523 sc->pmem.valid = 1; 524 525 /* Read the existing prefetchable memory window. */ 526 if (sc->pmem.valid) { 527 sc->pmem.reg = PCIR_PMBASEL_1; 528 sc->pmem.step = 20; 529 sc->pmem.mask = WIN_PMEM; 530 sc->pmem.name = "prefetch"; 531 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 532 sc->pmem.base = PCI_PPBMEMBASE( 533 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 534 sc->pmem.limit = PCI_PPBMEMLIMIT( 535 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 536 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 537 max = 0xffffffffffffffff; 538 } else { 539 sc->pmem.base = PCI_PPBMEMBASE(0, val); 540 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 541 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 542 max = 0xffffffff; 543 } 544 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 545 RF_PREFETCHABLE, max); 546 } 547 } 548 549 static void 550 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 551 { 552 device_t dev; 553 int error, i; 554 555 if (!w->valid) 556 return; 557 558 dev = sc->dev; 559 error = rman_fini(&w->rman); 560 if (error) { 561 device_printf(dev, "failed to release %s rman\n", w->name); 562 return; 563 } 564 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 565 566 for (i = 0; i < w->count; i++) { 567 error = bus_free_resource(dev, type, w->res[i]); 568 if (error) 569 device_printf(dev, 570 "failed to release %s resource: %d\n", w->name, 571 error); 572 } 573 free(w->res, M_DEVBUF); 574 } 575 576 static void 577 pcib_free_windows(struct pcib_softc *sc) 578 { 579 580 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 581 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 582 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 583 } 584 585 #ifdef PCI_RES_BUS 586 /* 587 * Allocate a suitable secondary bus for this bridge if needed and 588 * initialize the resource manager for the secondary bus range. Note 589 * that the minimum count is a desired value and this may allocate a 590 * smaller range. 591 */ 592 void 593 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 594 { 595 char buf[64]; 596 int error, rid, sec_reg; 597 598 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 599 case PCIM_HDRTYPE_BRIDGE: 600 sec_reg = PCIR_SECBUS_1; 601 bus->sub_reg = PCIR_SUBBUS_1; 602 break; 603 case PCIM_HDRTYPE_CARDBUS: 604 sec_reg = PCIR_SECBUS_2; 605 bus->sub_reg = PCIR_SUBBUS_2; 606 break; 607 default: 608 panic("not a PCI bridge"); 609 } 610 bus->sec = pci_read_config(dev, sec_reg, 1); 611 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 612 bus->dev = dev; 613 bus->rman.rm_start = 0; 614 bus->rman.rm_end = PCI_BUSMAX; 615 bus->rman.rm_type = RMAN_ARRAY; 616 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 617 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 618 error = rman_init(&bus->rman); 619 if (error) 620 panic("Failed to initialize %s bus number rman", 621 device_get_nameunit(dev)); 622 623 /* 624 * Allocate a bus range. This will return an existing bus range 625 * if one exists, or a new bus range if one does not. 626 */ 627 rid = 0; 628 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 629 min_count, 0); 630 if (bus->res == NULL) { 631 /* 632 * Fall back to just allocating a range of a single bus 633 * number. 634 */ 635 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 636 1, 0); 637 } else if (rman_get_size(bus->res) < min_count) 638 /* 639 * Attempt to grow the existing range to satisfy the 640 * minimum desired count. 641 */ 642 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 643 rman_get_start(bus->res), rman_get_start(bus->res) + 644 min_count - 1); 645 646 /* 647 * Add the initial resource to the rman. 648 */ 649 if (bus->res != NULL) { 650 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 651 rman_get_end(bus->res)); 652 if (error) 653 panic("Failed to add resource to rman"); 654 bus->sec = rman_get_start(bus->res); 655 bus->sub = rman_get_end(bus->res); 656 } 657 } 658 659 void 660 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 661 { 662 int error; 663 664 error = rman_fini(&bus->rman); 665 if (error) { 666 device_printf(dev, "failed to release bus number rman\n"); 667 return; 668 } 669 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 670 671 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 672 if (error) 673 device_printf(dev, 674 "failed to release bus numbers resource: %d\n", error); 675 } 676 677 static struct resource * 678 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 679 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 680 { 681 struct resource *res; 682 683 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 684 child); 685 if (res == NULL) 686 return (NULL); 687 688 if (bootverbose) 689 device_printf(bus->dev, 690 "allocated bus range (%ju-%ju) for rid %d of %s\n", 691 rman_get_start(res), rman_get_end(res), *rid, 692 pcib_child_name(child)); 693 rman_set_rid(res, *rid); 694 return (res); 695 } 696 697 /* 698 * Attempt to grow the secondary bus range. This is much simpler than 699 * for I/O windows as the range can only be grown by increasing 700 * subbus. 701 */ 702 static int 703 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 704 { 705 rman_res_t old_end; 706 int error; 707 708 old_end = rman_get_end(bus->res); 709 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 710 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 711 rman_get_start(bus->res), new_end); 712 if (error) 713 return (error); 714 if (bootverbose) 715 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 716 rman_get_start(bus->res), rman_get_end(bus->res)); 717 error = rman_manage_region(&bus->rman, old_end + 1, 718 rman_get_end(bus->res)); 719 if (error) 720 panic("Failed to add resource to rman"); 721 bus->sub = rman_get_end(bus->res); 722 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 723 return (0); 724 } 725 726 struct resource * 727 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 728 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 729 { 730 struct resource *res; 731 rman_res_t start_free, end_free, new_end; 732 733 /* 734 * First, see if the request can be satisified by the existing 735 * bus range. 736 */ 737 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 738 if (res != NULL) 739 return (res); 740 741 /* 742 * Figure out a range to grow the bus range. First, find the 743 * first bus number after the last allocated bus in the rman and 744 * enforce that as a minimum starting point for the range. 745 */ 746 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 747 end_free != bus->sub) 748 start_free = bus->sub + 1; 749 if (start_free < start) 750 start_free = start; 751 new_end = start_free + count - 1; 752 753 /* 754 * See if this new range would satisfy the request if it 755 * succeeds. 756 */ 757 if (new_end > end) 758 return (NULL); 759 760 /* Finally, attempt to grow the existing resource. */ 761 if (bootverbose) { 762 device_printf(bus->dev, 763 "attempting to grow bus range for %ju buses\n", count); 764 printf("\tback candidate range: %ju-%ju\n", start_free, 765 new_end); 766 } 767 if (pcib_grow_subbus(bus, new_end) == 0) 768 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 769 flags)); 770 return (NULL); 771 } 772 #endif 773 774 #else 775 776 /* 777 * Is the prefetch window open (eg, can we allocate memory in it?) 778 */ 779 static int 780 pcib_is_prefetch_open(struct pcib_softc *sc) 781 { 782 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 783 } 784 785 /* 786 * Is the nonprefetch window open (eg, can we allocate memory in it?) 787 */ 788 static int 789 pcib_is_nonprefetch_open(struct pcib_softc *sc) 790 { 791 return (sc->membase > 0 && sc->membase < sc->memlimit); 792 } 793 794 /* 795 * Is the io window open (eg, can we allocate ports in it?) 796 */ 797 static int 798 pcib_is_io_open(struct pcib_softc *sc) 799 { 800 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 801 } 802 803 /* 804 * Get current I/O decode. 805 */ 806 static void 807 pcib_get_io_decode(struct pcib_softc *sc) 808 { 809 device_t dev; 810 uint32_t iolow; 811 812 dev = sc->dev; 813 814 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 815 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 816 sc->iobase = PCI_PPBIOBASE( 817 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 818 else 819 sc->iobase = PCI_PPBIOBASE(0, iolow); 820 821 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 822 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 823 sc->iolimit = PCI_PPBIOLIMIT( 824 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 825 else 826 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 827 } 828 829 /* 830 * Get current memory decode. 831 */ 832 static void 833 pcib_get_mem_decode(struct pcib_softc *sc) 834 { 835 device_t dev; 836 pci_addr_t pmemlow; 837 838 dev = sc->dev; 839 840 sc->membase = PCI_PPBMEMBASE(0, 841 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 842 sc->memlimit = PCI_PPBMEMLIMIT(0, 843 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 844 845 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 846 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 847 sc->pmembase = PCI_PPBMEMBASE( 848 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 849 else 850 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 851 852 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 853 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 854 sc->pmemlimit = PCI_PPBMEMLIMIT( 855 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 856 else 857 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 858 } 859 860 /* 861 * Restore previous I/O decode. 862 */ 863 static void 864 pcib_set_io_decode(struct pcib_softc *sc) 865 { 866 device_t dev; 867 uint32_t iohi; 868 869 dev = sc->dev; 870 871 iohi = sc->iobase >> 16; 872 if (iohi > 0) 873 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 874 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 875 876 iohi = sc->iolimit >> 16; 877 if (iohi > 0) 878 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 879 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 880 } 881 882 /* 883 * Restore previous memory decode. 884 */ 885 static void 886 pcib_set_mem_decode(struct pcib_softc *sc) 887 { 888 device_t dev; 889 pci_addr_t pmemhi; 890 891 dev = sc->dev; 892 893 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 894 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 895 896 pmemhi = sc->pmembase >> 32; 897 if (pmemhi > 0) 898 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 899 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 900 901 pmemhi = sc->pmemlimit >> 32; 902 if (pmemhi > 0) 903 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 904 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 905 } 906 #endif 907 908 #ifdef PCI_HP 909 /* 910 * PCI-express HotPlug support. 911 */ 912 static int pci_enable_pcie_hp = 1; 913 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 914 &pci_enable_pcie_hp, 0, 915 "Enable support for native PCI-express HotPlug."); 916 917 static void 918 pcib_probe_hotplug(struct pcib_softc *sc) 919 { 920 device_t dev; 921 uint16_t link_sta, slot_sta; 922 923 if (!pci_enable_pcie_hp) 924 return; 925 926 dev = sc->dev; 927 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 928 return; 929 930 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 931 return; 932 933 sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 934 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 935 936 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 937 return; 938 939 /* 940 * Some devices report that they have an MRL when they actually 941 * do not. Since they always report that the MRL is open, child 942 * devices would be ignored. Try to detect these devices and 943 * ignore their claim of HotPlug support. 944 * 945 * If there is an open MRL but the Data Link Layer is active, 946 * the MRL is not real. 947 */ 948 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0 && 949 (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) != 0) { 950 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 951 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 952 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 953 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 954 return; 955 } 956 } 957 958 sc->flags |= PCIB_HOTPLUG; 959 } 960 961 /* 962 * Send a HotPlug command to the slot control register. If this slot 963 * uses command completion interrupts and a previous command is still 964 * in progress, then the command is dropped. Once the previous 965 * command completes or times out, pcib_pcie_hotplug_update() will be 966 * invoked to post a new command based on the slot's state at that 967 * time. 968 */ 969 static void 970 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 971 { 972 device_t dev; 973 uint16_t ctl, new; 974 975 dev = sc->dev; 976 977 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 978 return; 979 980 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 981 new = (ctl & ~mask) | val; 982 if (new == ctl) 983 return; 984 if (bootverbose) 985 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 986 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 987 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 988 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 989 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 990 if (!cold) 991 callout_reset(&sc->pcie_cc_timer, hz, 992 pcib_pcie_cc_timeout, sc); 993 } 994 } 995 996 static void 997 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 998 { 999 device_t dev; 1000 1001 dev = sc->dev; 1002 1003 if (bootverbose) 1004 device_printf(dev, "Command Completed\n"); 1005 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 1006 return; 1007 callout_stop(&sc->pcie_cc_timer); 1008 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1009 wakeup(sc); 1010 } 1011 1012 /* 1013 * Returns true if a card is fully inserted from the user's 1014 * perspective. It may not yet be ready for access, but the driver 1015 * can now start enabling access if necessary. 1016 */ 1017 static bool 1018 pcib_hotplug_inserted(struct pcib_softc *sc) 1019 { 1020 1021 /* Pretend the card isn't present if a detach is forced. */ 1022 if (sc->flags & PCIB_DETACHING) 1023 return (false); 1024 1025 /* Card must be present in the slot. */ 1026 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1027 return (false); 1028 1029 /* A power fault implicitly turns off power to the slot. */ 1030 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1031 return (false); 1032 1033 /* If the MRL is disengaged, the slot is powered off. */ 1034 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1035 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1036 return (false); 1037 1038 return (true); 1039 } 1040 1041 /* 1042 * Returns -1 if the card is fully inserted, powered, and ready for 1043 * access. Otherwise, returns 0. 1044 */ 1045 static int 1046 pcib_hotplug_present(struct pcib_softc *sc) 1047 { 1048 1049 /* Card must be inserted. */ 1050 if (!pcib_hotplug_inserted(sc)) 1051 return (0); 1052 1053 /* 1054 * Require the Electromechanical Interlock to be engaged if 1055 * present. 1056 */ 1057 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP && 1058 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0) 1059 return (0); 1060 1061 /* Require the Data Link Layer to be active. */ 1062 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1063 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1064 return (0); 1065 } 1066 1067 return (-1); 1068 } 1069 1070 static void 1071 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1072 bool schedule_task) 1073 { 1074 bool card_inserted, ei_engaged; 1075 1076 /* Clear DETACHING if Presence Detect has cleared. */ 1077 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1078 PCIEM_SLOT_STA_PDC) 1079 sc->flags &= ~PCIB_DETACHING; 1080 1081 card_inserted = pcib_hotplug_inserted(sc); 1082 1083 /* Turn the power indicator on if a card is inserted. */ 1084 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1085 mask |= PCIEM_SLOT_CTL_PIC; 1086 if (card_inserted) 1087 val |= PCIEM_SLOT_CTL_PI_ON; 1088 else if (sc->flags & PCIB_DETACH_PENDING) 1089 val |= PCIEM_SLOT_CTL_PI_BLINK; 1090 else 1091 val |= PCIEM_SLOT_CTL_PI_OFF; 1092 } 1093 1094 /* Turn the power on via the Power Controller if a card is inserted. */ 1095 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1096 mask |= PCIEM_SLOT_CTL_PCC; 1097 if (card_inserted) 1098 val |= PCIEM_SLOT_CTL_PC_ON; 1099 else 1100 val |= PCIEM_SLOT_CTL_PC_OFF; 1101 } 1102 1103 /* 1104 * If a card is inserted, enable the Electromechanical 1105 * Interlock. If a card is not inserted (or we are in the 1106 * process of detaching), disable the Electromechanical 1107 * Interlock. 1108 */ 1109 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { 1110 mask |= PCIEM_SLOT_CTL_EIC; 1111 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1112 if (card_inserted != ei_engaged) 1113 val |= PCIEM_SLOT_CTL_EIC; 1114 } 1115 1116 /* 1117 * Start a timer to see if the Data Link Layer times out. 1118 * Note that we only start the timer if Presence Detect or MRL Sensor 1119 * changed on this interrupt. Stop any scheduled timer if 1120 * the Data Link Layer is active. 1121 */ 1122 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1123 if (card_inserted && 1124 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1125 sc->pcie_slot_sta & 1126 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1127 if (cold) 1128 device_printf(sc->dev, 1129 "Data Link Layer inactive\n"); 1130 else 1131 callout_reset(&sc->pcie_dll_timer, hz, 1132 pcib_pcie_dll_timeout, sc); 1133 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1134 callout_stop(&sc->pcie_dll_timer); 1135 } 1136 1137 pcib_pcie_hotplug_command(sc, val, mask); 1138 1139 /* 1140 * During attach the child "pci" device is added synchronously; 1141 * otherwise, the task is scheduled to manage the child 1142 * device. 1143 */ 1144 if (schedule_task && 1145 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1146 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task); 1147 } 1148 1149 static void 1150 pcib_pcie_intr(void *arg) 1151 { 1152 struct pcib_softc *sc; 1153 device_t dev; 1154 1155 sc = arg; 1156 dev = sc->dev; 1157 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1158 1159 /* Clear the events just reported. */ 1160 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1161 1162 if (bootverbose) 1163 device_printf(dev, "HotPlug interrupt: %#x\n", 1164 sc->pcie_slot_sta); 1165 1166 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1167 if (sc->flags & PCIB_DETACH_PENDING) { 1168 device_printf(dev, 1169 "Attention Button Pressed: Detach Cancelled\n"); 1170 sc->flags &= ~PCIB_DETACH_PENDING; 1171 callout_stop(&sc->pcie_ab_timer); 1172 } else { 1173 device_printf(dev, 1174 "Attention Button Pressed: Detaching in 5 seconds\n"); 1175 sc->flags |= PCIB_DETACH_PENDING; 1176 callout_reset(&sc->pcie_ab_timer, 5 * hz, 1177 pcib_pcie_ab_timeout, sc); 1178 } 1179 } 1180 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1181 device_printf(dev, "Power Fault Detected\n"); 1182 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1183 device_printf(dev, "MRL Sensor Changed to %s\n", 1184 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1185 "closed"); 1186 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1187 device_printf(dev, "Presence Detect Changed to %s\n", 1188 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1189 "empty"); 1190 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1191 pcib_pcie_hotplug_command_completed(sc); 1192 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1193 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1194 if (bootverbose) 1195 device_printf(dev, 1196 "Data Link Layer State Changed to %s\n", 1197 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1198 "active" : "inactive"); 1199 } 1200 1201 pcib_pcie_hotplug_update(sc, 0, 0, true); 1202 } 1203 1204 static void 1205 pcib_pcie_hotplug_task(void *context, int pending) 1206 { 1207 struct pcib_softc *sc; 1208 device_t dev; 1209 1210 sc = context; 1211 mtx_lock(&Giant); 1212 dev = sc->dev; 1213 if (pcib_hotplug_present(sc) != 0) { 1214 if (sc->child == NULL) { 1215 sc->child = device_add_child(dev, "pci", -1); 1216 bus_generic_attach(dev); 1217 } 1218 } else { 1219 if (sc->child != NULL) { 1220 if (device_delete_child(dev, sc->child) == 0) 1221 sc->child = NULL; 1222 } 1223 } 1224 mtx_unlock(&Giant); 1225 } 1226 1227 static void 1228 pcib_pcie_ab_timeout(void *arg) 1229 { 1230 struct pcib_softc *sc; 1231 device_t dev; 1232 1233 sc = arg; 1234 dev = sc->dev; 1235 mtx_assert(&Giant, MA_OWNED); 1236 if (sc->flags & PCIB_DETACH_PENDING) { 1237 sc->flags |= PCIB_DETACHING; 1238 sc->flags &= ~PCIB_DETACH_PENDING; 1239 pcib_pcie_hotplug_update(sc, 0, 0, true); 1240 } 1241 } 1242 1243 static void 1244 pcib_pcie_cc_timeout(void *arg) 1245 { 1246 struct pcib_softc *sc; 1247 device_t dev; 1248 uint16_t sta; 1249 1250 sc = arg; 1251 dev = sc->dev; 1252 mtx_assert(&Giant, MA_OWNED); 1253 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1254 if (!(sta & PCIEM_SLOT_STA_CC)) { 1255 device_printf(dev, 1256 "HotPlug Command Timed Out - forcing detach\n"); 1257 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING); 1258 sc->flags |= PCIB_DETACHING; 1259 pcib_pcie_hotplug_update(sc, 0, 0, true); 1260 } else { 1261 device_printf(dev, 1262 "Missed HotPlug interrupt waiting for Command Completion\n"); 1263 pcib_pcie_intr(sc); 1264 } 1265 } 1266 1267 static void 1268 pcib_pcie_dll_timeout(void *arg) 1269 { 1270 struct pcib_softc *sc; 1271 device_t dev; 1272 uint16_t sta; 1273 1274 sc = arg; 1275 dev = sc->dev; 1276 mtx_assert(&Giant, MA_OWNED); 1277 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1278 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1279 device_printf(dev, 1280 "Timed out waiting for Data Link Layer Active\n"); 1281 sc->flags |= PCIB_DETACHING; 1282 pcib_pcie_hotplug_update(sc, 0, 0, true); 1283 } else if (sta != sc->pcie_link_sta) { 1284 device_printf(dev, 1285 "Missed HotPlug interrupt waiting for DLL Active\n"); 1286 pcib_pcie_intr(sc); 1287 } 1288 } 1289 1290 static int 1291 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1292 { 1293 device_t dev; 1294 int count, error, rid; 1295 1296 rid = -1; 1297 dev = sc->dev; 1298 1299 /* 1300 * For simplicity, only use MSI-X if there is a single message. 1301 * To support a device with multiple messages we would have to 1302 * use remap intr if the MSI number is not 0. 1303 */ 1304 count = pci_msix_count(dev); 1305 if (count == 1) { 1306 error = pci_alloc_msix(dev, &count); 1307 if (error == 0) 1308 rid = 1; 1309 } 1310 1311 if (rid < 0 && pci_msi_count(dev) > 0) { 1312 count = 1; 1313 error = pci_alloc_msi(dev, &count); 1314 if (error == 0) 1315 rid = 1; 1316 } 1317 1318 if (rid < 0) 1319 rid = 0; 1320 1321 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1322 RF_ACTIVE); 1323 if (sc->pcie_irq == NULL) { 1324 device_printf(dev, 1325 "Failed to allocate interrupt for PCI-e events\n"); 1326 if (rid > 0) 1327 pci_release_msi(dev); 1328 return (ENXIO); 1329 } 1330 1331 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC, 1332 NULL, pcib_pcie_intr, sc, &sc->pcie_ihand); 1333 if (error) { 1334 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1335 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1336 if (rid > 0) 1337 pci_release_msi(dev); 1338 return (error); 1339 } 1340 return (0); 1341 } 1342 1343 static int 1344 pcib_release_pcie_irq(struct pcib_softc *sc) 1345 { 1346 device_t dev; 1347 int error; 1348 1349 dev = sc->dev; 1350 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1351 if (error) 1352 return (error); 1353 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1354 if (error) 1355 return (error); 1356 return (pci_release_msi(dev)); 1357 } 1358 1359 static void 1360 pcib_setup_hotplug(struct pcib_softc *sc) 1361 { 1362 device_t dev; 1363 uint16_t mask, val; 1364 1365 dev = sc->dev; 1366 callout_init(&sc->pcie_ab_timer, 0); 1367 callout_init(&sc->pcie_cc_timer, 0); 1368 callout_init(&sc->pcie_dll_timer, 0); 1369 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1370 1371 /* Allocate IRQ. */ 1372 if (pcib_alloc_pcie_irq(sc) != 0) 1373 return; 1374 1375 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1376 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1377 1378 /* Clear any events previously pending. */ 1379 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1380 1381 /* Enable HotPlug events. */ 1382 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1383 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1384 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1385 val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE; 1386 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1387 val |= PCIEM_SLOT_CTL_ABPE; 1388 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1389 val |= PCIEM_SLOT_CTL_PFDE; 1390 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1391 val |= PCIEM_SLOT_CTL_MRLSCE; 1392 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1393 val |= PCIEM_SLOT_CTL_CCIE; 1394 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) 1395 val |= PCIEM_SLOT_CTL_DLLSCE; 1396 1397 /* Turn the attention indicator off. */ 1398 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1399 mask |= PCIEM_SLOT_CTL_AIC; 1400 val |= PCIEM_SLOT_CTL_AI_OFF; 1401 } 1402 1403 pcib_pcie_hotplug_update(sc, val, mask, false); 1404 } 1405 1406 static int 1407 pcib_detach_hotplug(struct pcib_softc *sc) 1408 { 1409 uint16_t mask, val; 1410 int error; 1411 1412 /* Disable the card in the slot and force it to detach. */ 1413 if (sc->flags & PCIB_DETACH_PENDING) { 1414 sc->flags &= ~PCIB_DETACH_PENDING; 1415 callout_stop(&sc->pcie_ab_timer); 1416 } 1417 sc->flags |= PCIB_DETACHING; 1418 1419 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1420 callout_stop(&sc->pcie_cc_timer); 1421 tsleep(sc, 0, "hpcmd", hz); 1422 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1423 } 1424 1425 /* Disable HotPlug events. */ 1426 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1427 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1428 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1429 val = 0; 1430 1431 /* Turn the attention indicator off. */ 1432 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1433 mask |= PCIEM_SLOT_CTL_AIC; 1434 val |= PCIEM_SLOT_CTL_AI_OFF; 1435 } 1436 1437 pcib_pcie_hotplug_update(sc, val, mask, false); 1438 1439 error = pcib_release_pcie_irq(sc); 1440 if (error) 1441 return (error); 1442 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task); 1443 callout_drain(&sc->pcie_ab_timer); 1444 callout_drain(&sc->pcie_cc_timer); 1445 callout_drain(&sc->pcie_dll_timer); 1446 return (0); 1447 } 1448 #endif 1449 1450 /* 1451 * Get current bridge configuration. 1452 */ 1453 static void 1454 pcib_cfg_save(struct pcib_softc *sc) 1455 { 1456 #ifndef NEW_PCIB 1457 device_t dev; 1458 uint16_t command; 1459 1460 dev = sc->dev; 1461 1462 command = pci_read_config(dev, PCIR_COMMAND, 2); 1463 if (command & PCIM_CMD_PORTEN) 1464 pcib_get_io_decode(sc); 1465 if (command & PCIM_CMD_MEMEN) 1466 pcib_get_mem_decode(sc); 1467 #endif 1468 } 1469 1470 /* 1471 * Restore previous bridge configuration. 1472 */ 1473 static void 1474 pcib_cfg_restore(struct pcib_softc *sc) 1475 { 1476 device_t dev; 1477 #ifndef NEW_PCIB 1478 uint16_t command; 1479 #endif 1480 dev = sc->dev; 1481 1482 #ifdef NEW_PCIB 1483 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1484 #else 1485 command = pci_read_config(dev, PCIR_COMMAND, 2); 1486 if (command & PCIM_CMD_PORTEN) 1487 pcib_set_io_decode(sc); 1488 if (command & PCIM_CMD_MEMEN) 1489 pcib_set_mem_decode(sc); 1490 #endif 1491 } 1492 1493 /* 1494 * Generic device interface 1495 */ 1496 static int 1497 pcib_probe(device_t dev) 1498 { 1499 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1500 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1501 device_set_desc(dev, "PCI-PCI bridge"); 1502 return(-10000); 1503 } 1504 return(ENXIO); 1505 } 1506 1507 void 1508 pcib_attach_common(device_t dev) 1509 { 1510 struct pcib_softc *sc; 1511 struct sysctl_ctx_list *sctx; 1512 struct sysctl_oid *soid; 1513 int comma; 1514 1515 sc = device_get_softc(dev); 1516 sc->dev = dev; 1517 1518 /* 1519 * Get current bridge configuration. 1520 */ 1521 sc->domain = pci_get_domain(dev); 1522 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1523 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1524 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1525 #endif 1526 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1527 pcib_cfg_save(sc); 1528 1529 /* 1530 * The primary bus register should always be the bus of the 1531 * parent. 1532 */ 1533 sc->pribus = pci_get_bus(dev); 1534 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1535 1536 /* 1537 * Setup sysctl reporting nodes 1538 */ 1539 sctx = device_get_sysctl_ctx(dev); 1540 soid = device_get_sysctl_tree(dev); 1541 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1542 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1543 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1544 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1545 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1546 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1547 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1548 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1549 1550 /* 1551 * Quirk handling. 1552 */ 1553 switch (pci_get_devid(dev)) { 1554 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1555 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1556 { 1557 uint8_t supbus; 1558 1559 supbus = pci_read_config(dev, 0x41, 1); 1560 if (supbus != 0xff) { 1561 sc->bus.sec = supbus + 1; 1562 sc->bus.sub = supbus + 1; 1563 } 1564 break; 1565 } 1566 #endif 1567 1568 /* 1569 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1570 * and it is a subtractive bridge. However, the ProgIf is wrong 1571 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1572 * happen. There are also Toshiba and Cavium ThunderX bridges 1573 * that behave this way. 1574 */ 1575 case 0xa002177d: /* Cavium ThunderX */ 1576 case 0x124b8086: /* Intel 82380FB Mobile */ 1577 case 0x060513d7: /* Toshiba ???? */ 1578 sc->flags |= PCIB_SUBTRACTIVE; 1579 break; 1580 1581 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1582 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1583 case 0x00dd10de: 1584 { 1585 char *cp; 1586 1587 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1588 break; 1589 if (strncmp(cp, "Compal", 6) != 0) { 1590 freeenv(cp); 1591 break; 1592 } 1593 freeenv(cp); 1594 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1595 break; 1596 if (strncmp(cp, "08A0", 4) != 0) { 1597 freeenv(cp); 1598 break; 1599 } 1600 freeenv(cp); 1601 if (sc->bus.sub < 0xa) { 1602 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1603 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1604 } 1605 break; 1606 } 1607 #endif 1608 } 1609 1610 if (pci_msi_device_blacklisted(dev)) 1611 sc->flags |= PCIB_DISABLE_MSI; 1612 1613 if (pci_msix_device_blacklisted(dev)) 1614 sc->flags |= PCIB_DISABLE_MSIX; 1615 1616 /* 1617 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1618 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1619 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1620 * This means they act as if they were subtractively decoding 1621 * bridges and pass all transactions. Mark them and real ProgIf 1 1622 * parts as subtractive. 1623 */ 1624 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1625 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1626 sc->flags |= PCIB_SUBTRACTIVE; 1627 1628 #ifdef PCI_HP 1629 pcib_probe_hotplug(sc); 1630 #endif 1631 #ifdef NEW_PCIB 1632 #ifdef PCI_RES_BUS 1633 pcib_setup_secbus(dev, &sc->bus, 1); 1634 #endif 1635 pcib_probe_windows(sc); 1636 #endif 1637 #ifdef PCI_HP 1638 if (sc->flags & PCIB_HOTPLUG) 1639 pcib_setup_hotplug(sc); 1640 #endif 1641 if (bootverbose) { 1642 device_printf(dev, " domain %d\n", sc->domain); 1643 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1644 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1645 #ifdef NEW_PCIB 1646 if (pcib_is_window_open(&sc->io)) 1647 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1648 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1649 if (pcib_is_window_open(&sc->mem)) 1650 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1651 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1652 if (pcib_is_window_open(&sc->pmem)) 1653 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1654 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1655 #else 1656 if (pcib_is_io_open(sc)) 1657 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1658 sc->iobase, sc->iolimit); 1659 if (pcib_is_nonprefetch_open(sc)) 1660 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1661 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1662 if (pcib_is_prefetch_open(sc)) 1663 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1664 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1665 #endif 1666 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1667 sc->flags & PCIB_SUBTRACTIVE) { 1668 device_printf(dev, " special decode "); 1669 comma = 0; 1670 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1671 printf("ISA"); 1672 comma = 1; 1673 } 1674 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1675 printf("%sVGA", comma ? ", " : ""); 1676 comma = 1; 1677 } 1678 if (sc->flags & PCIB_SUBTRACTIVE) 1679 printf("%ssubtractive", comma ? ", " : ""); 1680 printf("\n"); 1681 } 1682 } 1683 1684 /* 1685 * Always enable busmastering on bridges so that transactions 1686 * initiated on the secondary bus are passed through to the 1687 * primary bus. 1688 */ 1689 pci_enable_busmaster(dev); 1690 } 1691 1692 #ifdef PCI_HP 1693 static int 1694 pcib_present(struct pcib_softc *sc) 1695 { 1696 1697 if (sc->flags & PCIB_HOTPLUG) 1698 return (pcib_hotplug_present(sc) != 0); 1699 return (1); 1700 } 1701 #endif 1702 1703 int 1704 pcib_attach_child(device_t dev) 1705 { 1706 struct pcib_softc *sc; 1707 1708 sc = device_get_softc(dev); 1709 if (sc->bus.sec == 0) { 1710 /* no secondary bus; we should have fixed this */ 1711 return(0); 1712 } 1713 1714 #ifdef PCI_HP 1715 if (!pcib_present(sc)) { 1716 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1717 return (0); 1718 } 1719 #endif 1720 1721 sc->child = device_add_child(dev, "pci", -1); 1722 return (bus_generic_attach(dev)); 1723 } 1724 1725 int 1726 pcib_attach(device_t dev) 1727 { 1728 1729 pcib_attach_common(dev); 1730 return (pcib_attach_child(dev)); 1731 } 1732 1733 int 1734 pcib_detach(device_t dev) 1735 { 1736 #if defined(PCI_HP) || defined(NEW_PCIB) 1737 struct pcib_softc *sc; 1738 #endif 1739 int error; 1740 1741 #if defined(PCI_HP) || defined(NEW_PCIB) 1742 sc = device_get_softc(dev); 1743 #endif 1744 error = bus_generic_detach(dev); 1745 if (error) 1746 return (error); 1747 #ifdef PCI_HP 1748 if (sc->flags & PCIB_HOTPLUG) { 1749 error = pcib_detach_hotplug(sc); 1750 if (error) 1751 return (error); 1752 } 1753 #endif 1754 error = device_delete_children(dev); 1755 if (error) 1756 return (error); 1757 #ifdef NEW_PCIB 1758 pcib_free_windows(sc); 1759 #ifdef PCI_RES_BUS 1760 pcib_free_secbus(dev, &sc->bus); 1761 #endif 1762 #endif 1763 return (0); 1764 } 1765 1766 int 1767 pcib_suspend(device_t dev) 1768 { 1769 1770 pcib_cfg_save(device_get_softc(dev)); 1771 return (bus_generic_suspend(dev)); 1772 } 1773 1774 int 1775 pcib_resume(device_t dev) 1776 { 1777 1778 pcib_cfg_restore(device_get_softc(dev)); 1779 return (bus_generic_resume(dev)); 1780 } 1781 1782 void 1783 pcib_bridge_init(device_t dev) 1784 { 1785 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1786 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1787 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1788 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1789 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1790 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1791 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1792 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1793 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1794 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1795 } 1796 1797 int 1798 pcib_child_present(device_t dev, device_t child) 1799 { 1800 #ifdef PCI_HP 1801 struct pcib_softc *sc = device_get_softc(dev); 1802 int retval; 1803 1804 retval = bus_child_present(dev); 1805 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1806 retval = pcib_hotplug_present(sc); 1807 return (retval); 1808 #else 1809 return (bus_child_present(dev)); 1810 #endif 1811 } 1812 1813 int 1814 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1815 { 1816 struct pcib_softc *sc = device_get_softc(dev); 1817 1818 switch (which) { 1819 case PCIB_IVAR_DOMAIN: 1820 *result = sc->domain; 1821 return(0); 1822 case PCIB_IVAR_BUS: 1823 *result = sc->bus.sec; 1824 return(0); 1825 } 1826 return(ENOENT); 1827 } 1828 1829 int 1830 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1831 { 1832 1833 switch (which) { 1834 case PCIB_IVAR_DOMAIN: 1835 return(EINVAL); 1836 case PCIB_IVAR_BUS: 1837 return(EINVAL); 1838 } 1839 return(ENOENT); 1840 } 1841 1842 #ifdef NEW_PCIB 1843 /* 1844 * Attempt to allocate a resource from the existing resources assigned 1845 * to a window. 1846 */ 1847 static struct resource * 1848 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1849 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1850 rman_res_t count, u_int flags) 1851 { 1852 struct resource *res; 1853 1854 if (!pcib_is_window_open(w)) 1855 return (NULL); 1856 1857 res = rman_reserve_resource(&w->rman, start, end, count, 1858 flags & ~RF_ACTIVE, child); 1859 if (res == NULL) 1860 return (NULL); 1861 1862 if (bootverbose) 1863 device_printf(sc->dev, 1864 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1865 w->name, rman_get_start(res), rman_get_end(res), *rid, 1866 pcib_child_name(child)); 1867 rman_set_rid(res, *rid); 1868 1869 /* 1870 * If the resource should be active, pass that request up the 1871 * tree. This assumes the parent drivers can handle 1872 * activating sub-allocated resources. 1873 */ 1874 if (flags & RF_ACTIVE) { 1875 if (bus_activate_resource(child, type, *rid, res) != 0) { 1876 rman_release_resource(res); 1877 return (NULL); 1878 } 1879 } 1880 1881 return (res); 1882 } 1883 1884 /* Allocate a fresh resource range for an unconfigured window. */ 1885 static int 1886 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1887 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1888 { 1889 struct resource *res; 1890 rman_res_t base, limit, wmask; 1891 int rid; 1892 1893 /* 1894 * If this is an I/O window on a bridge with ISA enable set 1895 * and the start address is below 64k, then try to allocate an 1896 * initial window of 0x1000 bytes long starting at address 1897 * 0xf000 and walking down. Note that if the original request 1898 * was larger than the non-aliased range size of 0x100 our 1899 * caller would have raised the start address up to 64k 1900 * already. 1901 */ 1902 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1903 start < 65536) { 1904 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1905 limit = base + 0xfff; 1906 1907 /* 1908 * Skip ranges that wouldn't work for the 1909 * original request. Note that the actual 1910 * window that overlaps are the non-alias 1911 * ranges within [base, limit], so this isn't 1912 * quite a simple comparison. 1913 */ 1914 if (start + count > limit - 0x400) 1915 continue; 1916 if (base == 0) { 1917 /* 1918 * The first open region for the window at 1919 * 0 is 0x400-0x4ff. 1920 */ 1921 if (end - count + 1 < 0x400) 1922 continue; 1923 } else { 1924 if (end - count + 1 < base) 1925 continue; 1926 } 1927 1928 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1929 w->base = base; 1930 w->limit = limit; 1931 return (0); 1932 } 1933 } 1934 return (ENOSPC); 1935 } 1936 1937 wmask = ((rman_res_t)1 << w->step) - 1; 1938 if (RF_ALIGNMENT(flags) < w->step) { 1939 flags &= ~RF_ALIGNMENT_MASK; 1940 flags |= RF_ALIGNMENT_LOG2(w->step); 1941 } 1942 start &= ~wmask; 1943 end |= wmask; 1944 count = roundup2(count, (rman_res_t)1 << w->step); 1945 rid = w->reg; 1946 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1947 flags & ~RF_ACTIVE); 1948 if (res == NULL) 1949 return (ENOSPC); 1950 pcib_add_window_resources(w, &res, 1); 1951 pcib_activate_window(sc, type); 1952 w->base = rman_get_start(res); 1953 w->limit = rman_get_end(res); 1954 return (0); 1955 } 1956 1957 /* Try to expand an existing window to the requested base and limit. */ 1958 static int 1959 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1960 rman_res_t base, rman_res_t limit) 1961 { 1962 struct resource *res; 1963 int error, i, force_64k_base; 1964 1965 KASSERT(base <= w->base && limit >= w->limit, 1966 ("attempting to shrink window")); 1967 1968 /* 1969 * XXX: pcib_grow_window() doesn't try to do this anyway and 1970 * the error handling for all the edge cases would be tedious. 1971 */ 1972 KASSERT(limit == w->limit || base == w->base, 1973 ("attempting to grow both ends of a window")); 1974 1975 /* 1976 * Yet more special handling for requests to expand an I/O 1977 * window behind an ISA-enabled bridge. Since I/O windows 1978 * have to grow in 0x1000 increments and the end of the 0xffff 1979 * range is an alias, growing a window below 64k will always 1980 * result in allocating new resources and never adjusting an 1981 * existing resource. 1982 */ 1983 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1984 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1985 KASSERT(limit == w->limit || limit <= 65535, 1986 ("attempting to grow both ends across 64k ISA alias")); 1987 1988 if (base != w->base) 1989 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1990 else 1991 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1992 limit); 1993 if (error == 0) { 1994 w->base = base; 1995 w->limit = limit; 1996 } 1997 return (error); 1998 } 1999 2000 /* 2001 * Find the existing resource to adjust. Usually there is only one, 2002 * but for an ISA-enabled bridge we might be growing the I/O window 2003 * above 64k and need to find the existing resource that maps all 2004 * of the area above 64k. 2005 */ 2006 for (i = 0; i < w->count; i++) { 2007 if (rman_get_end(w->res[i]) == w->limit) 2008 break; 2009 } 2010 KASSERT(i != w->count, ("did not find existing resource")); 2011 res = w->res[i]; 2012 2013 /* 2014 * Usually the resource we found should match the window's 2015 * existing range. The one exception is the ISA-enabled case 2016 * mentioned above in which case the resource should start at 2017 * 64k. 2018 */ 2019 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2020 w->base <= 65535) { 2021 KASSERT(rman_get_start(res) == 65536, 2022 ("existing resource mismatch")); 2023 force_64k_base = 1; 2024 } else { 2025 KASSERT(w->base == rman_get_start(res), 2026 ("existing resource mismatch")); 2027 force_64k_base = 0; 2028 } 2029 2030 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2031 rman_get_start(res) : base, limit); 2032 if (error) 2033 return (error); 2034 2035 /* Add the newly allocated region to the resource manager. */ 2036 if (w->base != base) { 2037 error = rman_manage_region(&w->rman, base, w->base - 1); 2038 w->base = base; 2039 } else { 2040 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2041 w->limit = limit; 2042 } 2043 if (error) { 2044 if (bootverbose) 2045 device_printf(sc->dev, 2046 "failed to expand %s resource manager\n", w->name); 2047 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2048 rman_get_start(res) : w->base, w->limit); 2049 } 2050 return (error); 2051 } 2052 2053 /* 2054 * Attempt to grow a window to make room for a given resource request. 2055 */ 2056 static int 2057 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2058 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2059 { 2060 rman_res_t align, start_free, end_free, front, back, wmask; 2061 int error; 2062 2063 /* 2064 * Clamp the desired resource range to the maximum address 2065 * this window supports. Reject impossible requests. 2066 * 2067 * For I/O port requests behind a bridge with the ISA enable 2068 * bit set, force large allocations to start above 64k. 2069 */ 2070 if (!w->valid) 2071 return (EINVAL); 2072 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2073 start < 65536) 2074 start = 65536; 2075 if (end > w->rman.rm_end) 2076 end = w->rman.rm_end; 2077 if (start + count - 1 > end || start + count < start) 2078 return (EINVAL); 2079 wmask = ((rman_res_t)1 << w->step) - 1; 2080 2081 /* 2082 * If there is no resource at all, just try to allocate enough 2083 * aligned space for this resource. 2084 */ 2085 if (w->res == NULL) { 2086 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2087 flags); 2088 if (error) { 2089 if (bootverbose) 2090 device_printf(sc->dev, 2091 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2092 w->name, start, end, count); 2093 return (error); 2094 } 2095 if (bootverbose) 2096 device_printf(sc->dev, 2097 "allocated initial %s window of %#jx-%#jx\n", 2098 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2099 goto updatewin; 2100 } 2101 2102 /* 2103 * See if growing the window would help. Compute the minimum 2104 * amount of address space needed on both the front and back 2105 * ends of the existing window to satisfy the allocation. 2106 * 2107 * For each end, build a candidate region adjusting for the 2108 * required alignment, etc. If there is a free region at the 2109 * edge of the window, grow from the inner edge of the free 2110 * region. Otherwise grow from the window boundary. 2111 * 2112 * Growing an I/O window below 64k for a bridge with the ISA 2113 * enable bit doesn't require any special magic as the step 2114 * size of an I/O window (1k) always includes multiple 2115 * non-alias ranges when it is grown in either direction. 2116 * 2117 * XXX: Special case: if w->res is completely empty and the 2118 * request size is larger than w->res, we should find the 2119 * optimal aligned buffer containing w->res and allocate that. 2120 */ 2121 if (bootverbose) 2122 device_printf(sc->dev, 2123 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2124 w->name, start, end, count); 2125 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2126 if (start < w->base) { 2127 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2128 0 || start_free != w->base) 2129 end_free = w->base; 2130 if (end_free > end) 2131 end_free = end + 1; 2132 2133 /* Move end_free down until it is properly aligned. */ 2134 end_free &= ~(align - 1); 2135 end_free--; 2136 front = end_free - (count - 1); 2137 2138 /* 2139 * The resource would now be allocated at (front, 2140 * end_free). Ensure that fits in the (start, end) 2141 * bounds. end_free is checked above. If 'front' is 2142 * ok, ensure it is properly aligned for this window. 2143 * Also check for underflow. 2144 */ 2145 if (front >= start && front <= end_free) { 2146 if (bootverbose) 2147 printf("\tfront candidate range: %#jx-%#jx\n", 2148 front, end_free); 2149 front &= ~wmask; 2150 front = w->base - front; 2151 } else 2152 front = 0; 2153 } else 2154 front = 0; 2155 if (end > w->limit) { 2156 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2157 0 || end_free != w->limit) 2158 start_free = w->limit + 1; 2159 if (start_free < start) 2160 start_free = start; 2161 2162 /* Move start_free up until it is properly aligned. */ 2163 start_free = roundup2(start_free, align); 2164 back = start_free + count - 1; 2165 2166 /* 2167 * The resource would now be allocated at (start_free, 2168 * back). Ensure that fits in the (start, end) 2169 * bounds. start_free is checked above. If 'back' is 2170 * ok, ensure it is properly aligned for this window. 2171 * Also check for overflow. 2172 */ 2173 if (back <= end && start_free <= back) { 2174 if (bootverbose) 2175 printf("\tback candidate range: %#jx-%#jx\n", 2176 start_free, back); 2177 back |= wmask; 2178 back -= w->limit; 2179 } else 2180 back = 0; 2181 } else 2182 back = 0; 2183 2184 /* 2185 * Try to allocate the smallest needed region first. 2186 * If that fails, fall back to the other region. 2187 */ 2188 error = ENOSPC; 2189 while (front != 0 || back != 0) { 2190 if (front != 0 && (front <= back || back == 0)) { 2191 error = pcib_expand_window(sc, w, type, w->base - front, 2192 w->limit); 2193 if (error == 0) 2194 break; 2195 front = 0; 2196 } else { 2197 error = pcib_expand_window(sc, w, type, w->base, 2198 w->limit + back); 2199 if (error == 0) 2200 break; 2201 back = 0; 2202 } 2203 } 2204 2205 if (error) 2206 return (error); 2207 if (bootverbose) 2208 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2209 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2210 2211 updatewin: 2212 /* Write the new window. */ 2213 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2214 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2215 pcib_write_windows(sc, w->mask); 2216 return (0); 2217 } 2218 2219 /* 2220 * We have to trap resource allocation requests and ensure that the bridge 2221 * is set up to, or capable of handling them. 2222 */ 2223 struct resource * 2224 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2225 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2226 { 2227 struct pcib_softc *sc; 2228 struct resource *r; 2229 2230 sc = device_get_softc(dev); 2231 2232 /* 2233 * VGA resources are decoded iff the VGA enable bit is set in 2234 * the bridge control register. VGA resources do not fall into 2235 * the resource windows and are passed up to the parent. 2236 */ 2237 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2238 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2239 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2240 return (bus_generic_alloc_resource(dev, child, type, 2241 rid, start, end, count, flags)); 2242 else 2243 return (NULL); 2244 } 2245 2246 switch (type) { 2247 #ifdef PCI_RES_BUS 2248 case PCI_RES_BUS: 2249 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2250 count, flags)); 2251 #endif 2252 case SYS_RES_IOPORT: 2253 if (pcib_is_isa_range(sc, start, end, count)) 2254 return (NULL); 2255 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2256 end, count, flags); 2257 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2258 break; 2259 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2260 flags) == 0) 2261 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2262 rid, start, end, count, flags); 2263 break; 2264 case SYS_RES_MEMORY: 2265 /* 2266 * For prefetchable resources, prefer the prefetchable 2267 * memory window, but fall back to the regular memory 2268 * window if that fails. Try both windows before 2269 * attempting to grow a window in case the firmware 2270 * has used a range in the regular memory window to 2271 * map a prefetchable BAR. 2272 */ 2273 if (flags & RF_PREFETCHABLE) { 2274 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2275 rid, start, end, count, flags); 2276 if (r != NULL) 2277 break; 2278 } 2279 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2280 start, end, count, flags); 2281 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2282 break; 2283 if (flags & RF_PREFETCHABLE) { 2284 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2285 count, flags) == 0) { 2286 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2287 type, rid, start, end, count, flags); 2288 if (r != NULL) 2289 break; 2290 } 2291 } 2292 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2293 flags & ~RF_PREFETCHABLE) == 0) 2294 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2295 rid, start, end, count, flags); 2296 break; 2297 default: 2298 return (bus_generic_alloc_resource(dev, child, type, rid, 2299 start, end, count, flags)); 2300 } 2301 2302 /* 2303 * If attempts to suballocate from the window fail but this is a 2304 * subtractive bridge, pass the request up the tree. 2305 */ 2306 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2307 return (bus_generic_alloc_resource(dev, child, type, rid, 2308 start, end, count, flags)); 2309 return (r); 2310 } 2311 2312 int 2313 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2314 rman_res_t start, rman_res_t end) 2315 { 2316 struct pcib_softc *sc; 2317 2318 sc = device_get_softc(bus); 2319 if (pcib_is_resource_managed(sc, type, r)) 2320 return (rman_adjust_resource(r, start, end)); 2321 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 2322 } 2323 2324 int 2325 pcib_release_resource(device_t dev, device_t child, int type, int rid, 2326 struct resource *r) 2327 { 2328 struct pcib_softc *sc; 2329 int error; 2330 2331 sc = device_get_softc(dev); 2332 if (pcib_is_resource_managed(sc, type, r)) { 2333 if (rman_get_flags(r) & RF_ACTIVE) { 2334 error = bus_deactivate_resource(child, type, rid, r); 2335 if (error) 2336 return (error); 2337 } 2338 return (rman_release_resource(r)); 2339 } 2340 return (bus_generic_release_resource(dev, child, type, rid, r)); 2341 } 2342 #else 2343 /* 2344 * We have to trap resource allocation requests and ensure that the bridge 2345 * is set up to, or capable of handling them. 2346 */ 2347 struct resource * 2348 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2349 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2350 { 2351 struct pcib_softc *sc = device_get_softc(dev); 2352 const char *name, *suffix; 2353 int ok; 2354 2355 /* 2356 * Fail the allocation for this range if it's not supported. 2357 */ 2358 name = device_get_nameunit(child); 2359 if (name == NULL) { 2360 name = ""; 2361 suffix = ""; 2362 } else 2363 suffix = " "; 2364 switch (type) { 2365 case SYS_RES_IOPORT: 2366 ok = 0; 2367 if (!pcib_is_io_open(sc)) 2368 break; 2369 ok = (start >= sc->iobase && end <= sc->iolimit); 2370 2371 /* 2372 * Make sure we allow access to VGA I/O addresses when the 2373 * bridge has the "VGA Enable" bit set. 2374 */ 2375 if (!ok && pci_is_vga_ioport_range(start, end)) 2376 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2377 2378 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2379 if (!ok) { 2380 if (start < sc->iobase) 2381 start = sc->iobase; 2382 if (end > sc->iolimit) 2383 end = sc->iolimit; 2384 if (start < end) 2385 ok = 1; 2386 } 2387 } else { 2388 ok = 1; 2389 #if 0 2390 /* 2391 * If we overlap with the subtractive range, then 2392 * pick the upper range to use. 2393 */ 2394 if (start < sc->iolimit && end > sc->iobase) 2395 start = sc->iolimit + 1; 2396 #endif 2397 } 2398 if (end < start) { 2399 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2400 end, start); 2401 start = 0; 2402 end = 0; 2403 ok = 0; 2404 } 2405 if (!ok) { 2406 device_printf(dev, "%s%srequested unsupported I/O " 2407 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2408 name, suffix, start, end, sc->iobase, sc->iolimit); 2409 return (NULL); 2410 } 2411 if (bootverbose) 2412 device_printf(dev, 2413 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2414 name, suffix, start, end); 2415 break; 2416 2417 case SYS_RES_MEMORY: 2418 ok = 0; 2419 if (pcib_is_nonprefetch_open(sc)) 2420 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2421 if (pcib_is_prefetch_open(sc)) 2422 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2423 2424 /* 2425 * Make sure we allow access to VGA memory addresses when the 2426 * bridge has the "VGA Enable" bit set. 2427 */ 2428 if (!ok && pci_is_vga_memory_range(start, end)) 2429 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2430 2431 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2432 if (!ok) { 2433 ok = 1; 2434 if (flags & RF_PREFETCHABLE) { 2435 if (pcib_is_prefetch_open(sc)) { 2436 if (start < sc->pmembase) 2437 start = sc->pmembase; 2438 if (end > sc->pmemlimit) 2439 end = sc->pmemlimit; 2440 } else { 2441 ok = 0; 2442 } 2443 } else { /* non-prefetchable */ 2444 if (pcib_is_nonprefetch_open(sc)) { 2445 if (start < sc->membase) 2446 start = sc->membase; 2447 if (end > sc->memlimit) 2448 end = sc->memlimit; 2449 } else { 2450 ok = 0; 2451 } 2452 } 2453 } 2454 } else if (!ok) { 2455 ok = 1; /* subtractive bridge: always ok */ 2456 #if 0 2457 if (pcib_is_nonprefetch_open(sc)) { 2458 if (start < sc->memlimit && end > sc->membase) 2459 start = sc->memlimit + 1; 2460 } 2461 if (pcib_is_prefetch_open(sc)) { 2462 if (start < sc->pmemlimit && end > sc->pmembase) 2463 start = sc->pmemlimit + 1; 2464 } 2465 #endif 2466 } 2467 if (end < start) { 2468 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2469 end, start); 2470 start = 0; 2471 end = 0; 2472 ok = 0; 2473 } 2474 if (!ok && bootverbose) 2475 device_printf(dev, 2476 "%s%srequested unsupported memory range %#jx-%#jx " 2477 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2478 name, suffix, start, end, 2479 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2480 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2481 if (!ok) 2482 return (NULL); 2483 if (bootverbose) 2484 device_printf(dev,"%s%srequested memory range " 2485 "0x%jx-0x%jx: good\n", 2486 name, suffix, start, end); 2487 break; 2488 2489 default: 2490 break; 2491 } 2492 /* 2493 * Bridge is OK decoding this resource, so pass it up. 2494 */ 2495 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2496 count, flags)); 2497 } 2498 #endif 2499 2500 /* 2501 * If ARI is enabled on this downstream port, translate the function number 2502 * to the non-ARI slot/function. The downstream port will convert it back in 2503 * hardware. If ARI is not enabled slot and func are not modified. 2504 */ 2505 static __inline void 2506 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2507 { 2508 struct pcib_softc *sc; 2509 int ari_func; 2510 2511 sc = device_get_softc(pcib); 2512 ari_func = *func; 2513 2514 if (sc->flags & PCIB_ENABLE_ARI) { 2515 KASSERT(*slot == 0, 2516 ("Non-zero slot number with ARI enabled!")); 2517 *slot = PCIE_ARI_SLOT(ari_func); 2518 *func = PCIE_ARI_FUNC(ari_func); 2519 } 2520 } 2521 2522 2523 static void 2524 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2525 { 2526 uint32_t ctl2; 2527 2528 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2529 ctl2 |= PCIEM_CTL2_ARI; 2530 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2531 2532 sc->flags |= PCIB_ENABLE_ARI; 2533 } 2534 2535 /* 2536 * PCIB interface. 2537 */ 2538 int 2539 pcib_maxslots(device_t dev) 2540 { 2541 return (PCI_SLOTMAX); 2542 } 2543 2544 static int 2545 pcib_ari_maxslots(device_t dev) 2546 { 2547 struct pcib_softc *sc; 2548 2549 sc = device_get_softc(dev); 2550 2551 if (sc->flags & PCIB_ENABLE_ARI) 2552 return (PCIE_ARI_SLOTMAX); 2553 else 2554 return (PCI_SLOTMAX); 2555 } 2556 2557 static int 2558 pcib_ari_maxfuncs(device_t dev) 2559 { 2560 struct pcib_softc *sc; 2561 2562 sc = device_get_softc(dev); 2563 2564 if (sc->flags & PCIB_ENABLE_ARI) 2565 return (PCIE_ARI_FUNCMAX); 2566 else 2567 return (PCI_FUNCMAX); 2568 } 2569 2570 static void 2571 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2572 int *func) 2573 { 2574 struct pcib_softc *sc; 2575 2576 sc = device_get_softc(pcib); 2577 2578 *bus = PCI_RID2BUS(rid); 2579 if (sc->flags & PCIB_ENABLE_ARI) { 2580 *slot = PCIE_ARI_RID2SLOT(rid); 2581 *func = PCIE_ARI_RID2FUNC(rid); 2582 } else { 2583 *slot = PCI_RID2SLOT(rid); 2584 *func = PCI_RID2FUNC(rid); 2585 } 2586 } 2587 2588 /* 2589 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2590 */ 2591 static uint32_t 2592 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2593 { 2594 #ifdef PCI_HP 2595 struct pcib_softc *sc; 2596 2597 sc = device_get_softc(dev); 2598 if (!pcib_present(sc)) { 2599 switch (width) { 2600 case 2: 2601 return (0xffff); 2602 case 1: 2603 return (0xff); 2604 default: 2605 return (0xffffffff); 2606 } 2607 } 2608 #endif 2609 pcib_xlate_ari(dev, b, &s, &f); 2610 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2611 f, reg, width)); 2612 } 2613 2614 static void 2615 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2616 { 2617 #ifdef PCI_HP 2618 struct pcib_softc *sc; 2619 2620 sc = device_get_softc(dev); 2621 if (!pcib_present(sc)) 2622 return; 2623 #endif 2624 pcib_xlate_ari(dev, b, &s, &f); 2625 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2626 reg, val, width); 2627 } 2628 2629 /* 2630 * Route an interrupt across a PCI bridge. 2631 */ 2632 int 2633 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2634 { 2635 device_t bus; 2636 int parent_intpin; 2637 int intnum; 2638 2639 /* 2640 * 2641 * The PCI standard defines a swizzle of the child-side device/intpin to 2642 * the parent-side intpin as follows. 2643 * 2644 * device = device on child bus 2645 * child_intpin = intpin on child bus slot (0-3) 2646 * parent_intpin = intpin on parent bus slot (0-3) 2647 * 2648 * parent_intpin = (device + child_intpin) % 4 2649 */ 2650 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2651 2652 /* 2653 * Our parent is a PCI bus. Its parent must export the pcib interface 2654 * which includes the ability to route interrupts. 2655 */ 2656 bus = device_get_parent(pcib); 2657 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2658 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2659 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2660 pci_get_slot(dev), 'A' + pin - 1, intnum); 2661 } 2662 return(intnum); 2663 } 2664 2665 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2666 int 2667 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2668 { 2669 struct pcib_softc *sc = device_get_softc(pcib); 2670 device_t bus; 2671 2672 if (sc->flags & PCIB_DISABLE_MSI) 2673 return (ENXIO); 2674 bus = device_get_parent(pcib); 2675 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2676 irqs)); 2677 } 2678 2679 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2680 int 2681 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2682 { 2683 device_t bus; 2684 2685 bus = device_get_parent(pcib); 2686 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2687 } 2688 2689 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2690 int 2691 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2692 { 2693 struct pcib_softc *sc = device_get_softc(pcib); 2694 device_t bus; 2695 2696 if (sc->flags & PCIB_DISABLE_MSIX) 2697 return (ENXIO); 2698 bus = device_get_parent(pcib); 2699 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2700 } 2701 2702 /* Pass request to release an MSI-X message up to the parent bridge. */ 2703 int 2704 pcib_release_msix(device_t pcib, device_t dev, int irq) 2705 { 2706 device_t bus; 2707 2708 bus = device_get_parent(pcib); 2709 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2710 } 2711 2712 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2713 int 2714 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2715 uint32_t *data) 2716 { 2717 device_t bus; 2718 int error; 2719 2720 bus = device_get_parent(pcib); 2721 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2722 if (error) 2723 return (error); 2724 2725 pci_ht_map_msi(pcib, *addr); 2726 return (0); 2727 } 2728 2729 /* Pass request for device power state up to parent bridge. */ 2730 int 2731 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2732 { 2733 device_t bus; 2734 2735 bus = device_get_parent(pcib); 2736 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2737 } 2738 2739 static int 2740 pcib_ari_enabled(device_t pcib) 2741 { 2742 struct pcib_softc *sc; 2743 2744 sc = device_get_softc(pcib); 2745 2746 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2747 } 2748 2749 static int 2750 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2751 uintptr_t *id) 2752 { 2753 struct pcib_softc *sc; 2754 device_t bus_dev; 2755 uint8_t bus, slot, func; 2756 2757 if (type != PCI_ID_RID) { 2758 bus_dev = device_get_parent(pcib); 2759 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2760 } 2761 2762 sc = device_get_softc(pcib); 2763 2764 if (sc->flags & PCIB_ENABLE_ARI) { 2765 bus = pci_get_bus(dev); 2766 func = pci_get_function(dev); 2767 2768 *id = (PCI_ARI_RID(bus, func)); 2769 } else { 2770 bus = pci_get_bus(dev); 2771 slot = pci_get_slot(dev); 2772 func = pci_get_function(dev); 2773 2774 *id = (PCI_RID(bus, slot, func)); 2775 } 2776 2777 return (0); 2778 } 2779 2780 /* 2781 * Check that the downstream port (pcib) and the endpoint device (dev) both 2782 * support ARI. If so, enable it and return 0, otherwise return an error. 2783 */ 2784 static int 2785 pcib_try_enable_ari(device_t pcib, device_t dev) 2786 { 2787 struct pcib_softc *sc; 2788 int error; 2789 uint32_t cap2; 2790 int ari_cap_off; 2791 uint32_t ari_ver; 2792 uint32_t pcie_pos; 2793 2794 sc = device_get_softc(pcib); 2795 2796 /* 2797 * ARI is controlled in a register in the PCIe capability structure. 2798 * If the downstream port does not have the PCIe capability structure 2799 * then it does not support ARI. 2800 */ 2801 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2802 if (error != 0) 2803 return (ENODEV); 2804 2805 /* Check that the PCIe port advertises ARI support. */ 2806 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2807 if (!(cap2 & PCIEM_CAP2_ARI)) 2808 return (ENODEV); 2809 2810 /* 2811 * Check that the endpoint device advertises ARI support via the ARI 2812 * extended capability structure. 2813 */ 2814 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2815 if (error != 0) 2816 return (ENODEV); 2817 2818 /* 2819 * Finally, check that the endpoint device supports the same version 2820 * of ARI that we do. 2821 */ 2822 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2823 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2824 if (bootverbose) 2825 device_printf(pcib, 2826 "Unsupported version of ARI (%d) detected\n", 2827 PCI_EXTCAP_VER(ari_ver)); 2828 2829 return (ENXIO); 2830 } 2831 2832 pcib_enable_ari(sc, pcie_pos); 2833 2834 return (0); 2835 } 2836