1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 #include <sys/taskqueue.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pci_private.h> 53 #include <dev/pci/pcib_private.h> 54 55 #include "pcib_if.h" 56 57 static int pcib_probe(device_t dev); 58 static int pcib_suspend(device_t dev); 59 static int pcib_resume(device_t dev); 60 static int pcib_power_for_sleep(device_t pcib, device_t dev, 61 int *pstate); 62 static int pcib_ari_get_id(device_t pcib, device_t dev, 63 enum pci_id_type type, uintptr_t *id); 64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 65 u_int f, u_int reg, int width); 66 static void pcib_write_config(device_t dev, u_int b, u_int s, 67 u_int f, u_int reg, uint32_t val, int width); 68 static int pcib_ari_maxslots(device_t dev); 69 static int pcib_ari_maxfuncs(device_t dev); 70 static int pcib_try_enable_ari(device_t pcib, device_t dev); 71 static int pcib_ari_enabled(device_t pcib); 72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 73 int *bus, int *slot, int *func); 74 #ifdef PCI_HP 75 static void pcib_pcie_ab_timeout(void *arg); 76 static void pcib_pcie_cc_timeout(void *arg); 77 static void pcib_pcie_dll_timeout(void *arg); 78 #endif 79 static int pcib_request_feature_default(device_t pcib, device_t dev, 80 enum pci_feature feature); 81 82 static device_method_t pcib_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, pcib_probe), 85 DEVMETHOD(device_attach, pcib_attach), 86 DEVMETHOD(device_detach, pcib_detach), 87 DEVMETHOD(device_shutdown, bus_generic_shutdown), 88 DEVMETHOD(device_suspend, pcib_suspend), 89 DEVMETHOD(device_resume, pcib_resume), 90 91 /* Bus interface */ 92 DEVMETHOD(bus_child_present, pcib_child_present), 93 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 94 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 95 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 96 #ifdef NEW_PCIB 97 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 98 DEVMETHOD(bus_release_resource, pcib_release_resource), 99 #else 100 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 101 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 102 #endif 103 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 104 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 105 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 106 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 107 108 /* pcib interface */ 109 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 110 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 111 DEVMETHOD(pcib_read_config, pcib_read_config), 112 DEVMETHOD(pcib_write_config, pcib_write_config), 113 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 114 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 115 DEVMETHOD(pcib_release_msi, pcib_release_msi), 116 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 117 DEVMETHOD(pcib_release_msix, pcib_release_msix), 118 DEVMETHOD(pcib_map_msi, pcib_map_msi), 119 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 120 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 121 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 122 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 123 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 124 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 125 126 DEVMETHOD_END 127 }; 128 129 static devclass_t pcib_devclass; 130 131 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 132 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 133 134 #if defined(NEW_PCIB) || defined(PCI_HP) 135 SYSCTL_DECL(_hw_pci); 136 #endif 137 138 #ifdef NEW_PCIB 139 static int pci_clear_pcib; 140 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 141 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 142 143 /* 144 * Is a resource from a child device sub-allocated from one of our 145 * resource managers? 146 */ 147 static int 148 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 149 { 150 151 switch (type) { 152 #ifdef PCI_RES_BUS 153 case PCI_RES_BUS: 154 return (rman_is_region_manager(r, &sc->bus.rman)); 155 #endif 156 case SYS_RES_IOPORT: 157 return (rman_is_region_manager(r, &sc->io.rman)); 158 case SYS_RES_MEMORY: 159 /* Prefetchable resources may live in either memory rman. */ 160 if (rman_get_flags(r) & RF_PREFETCHABLE && 161 rman_is_region_manager(r, &sc->pmem.rman)) 162 return (1); 163 return (rman_is_region_manager(r, &sc->mem.rman)); 164 } 165 return (0); 166 } 167 168 static int 169 pcib_is_window_open(struct pcib_window *pw) 170 { 171 172 return (pw->valid && pw->base < pw->limit); 173 } 174 175 /* 176 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 177 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 178 * when allocating the resource windows and rely on the PCI bus driver 179 * to do this for us. 180 */ 181 static void 182 pcib_activate_window(struct pcib_softc *sc, int type) 183 { 184 185 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 186 } 187 188 static void 189 pcib_write_windows(struct pcib_softc *sc, int mask) 190 { 191 device_t dev; 192 uint32_t val; 193 194 dev = sc->dev; 195 if (sc->io.valid && mask & WIN_IO) { 196 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 197 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 198 pci_write_config(dev, PCIR_IOBASEH_1, 199 sc->io.base >> 16, 2); 200 pci_write_config(dev, PCIR_IOLIMITH_1, 201 sc->io.limit >> 16, 2); 202 } 203 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 204 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 205 } 206 207 if (mask & WIN_MEM) { 208 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 209 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 210 } 211 212 if (sc->pmem.valid && mask & WIN_PMEM) { 213 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 214 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 215 pci_write_config(dev, PCIR_PMBASEH_1, 216 sc->pmem.base >> 32, 4); 217 pci_write_config(dev, PCIR_PMLIMITH_1, 218 sc->pmem.limit >> 32, 4); 219 } 220 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 221 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 222 } 223 } 224 225 /* 226 * This is used to reject I/O port allocations that conflict with an 227 * ISA alias range. 228 */ 229 static int 230 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 231 rman_res_t count) 232 { 233 rman_res_t next_alias; 234 235 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 236 return (0); 237 238 /* Only check fixed ranges for overlap. */ 239 if (start + count - 1 != end) 240 return (0); 241 242 /* ISA aliases are only in the lower 64KB of I/O space. */ 243 if (start >= 65536) 244 return (0); 245 246 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 247 if (start < 0x100) 248 goto alias; 249 250 /* 251 * If the start address is an alias, the range is an alias. 252 * Otherwise, compute the start of the next alias range and 253 * check if it is before the end of the candidate range. 254 */ 255 if ((start & 0x300) != 0) 256 goto alias; 257 next_alias = (start & ~0x3fful) | 0x100; 258 if (next_alias <= end) 259 goto alias; 260 return (0); 261 262 alias: 263 if (bootverbose) 264 device_printf(sc->dev, 265 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 266 end); 267 return (1); 268 } 269 270 static void 271 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 272 int count) 273 { 274 struct resource **newarray; 275 int error, i; 276 277 newarray = malloc(sizeof(struct resource *) * (w->count + count), 278 M_DEVBUF, M_WAITOK); 279 if (w->res != NULL) 280 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 281 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 282 free(w->res, M_DEVBUF); 283 w->res = newarray; 284 w->count += count; 285 286 for (i = 0; i < count; i++) { 287 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 288 rman_get_end(res[i])); 289 if (error) 290 panic("Failed to add resource to rman"); 291 } 292 } 293 294 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 295 296 static void 297 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 298 void *arg) 299 { 300 rman_res_t next_end; 301 302 /* 303 * If start is within an ISA alias range, move up to the start 304 * of the next non-alias range. As a special case, addresses 305 * in the range 0x000 - 0x0ff should also be skipped since 306 * those are used for various system I/O devices in ISA 307 * systems. 308 */ 309 if (start <= 65535) { 310 if (start < 0x100 || (start & 0x300) != 0) { 311 start &= ~0x3ff; 312 start += 0x400; 313 } 314 } 315 316 /* ISA aliases are only in the lower 64KB of I/O space. */ 317 while (start <= MIN(end, 65535)) { 318 next_end = MIN(start | 0xff, end); 319 cb(start, next_end, arg); 320 start += 0x400; 321 } 322 323 if (start <= end) 324 cb(start, end, arg); 325 } 326 327 static void 328 count_ranges(rman_res_t start, rman_res_t end, void *arg) 329 { 330 int *countp; 331 332 countp = arg; 333 (*countp)++; 334 } 335 336 struct alloc_state { 337 struct resource **res; 338 struct pcib_softc *sc; 339 int count, error; 340 }; 341 342 static void 343 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 344 { 345 struct alloc_state *as; 346 struct pcib_window *w; 347 int rid; 348 349 as = arg; 350 if (as->error != 0) 351 return; 352 353 w = &as->sc->io; 354 rid = w->reg; 355 if (bootverbose) 356 device_printf(as->sc->dev, 357 "allocating non-ISA range %#jx-%#jx\n", start, end); 358 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 359 &rid, start, end, end - start + 1, 0); 360 if (as->res[as->count] == NULL) 361 as->error = ENXIO; 362 else 363 as->count++; 364 } 365 366 static int 367 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 368 { 369 struct alloc_state as; 370 int i, new_count; 371 372 /* First, see how many ranges we need. */ 373 new_count = 0; 374 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 375 376 /* Second, allocate the ranges. */ 377 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 378 M_WAITOK); 379 as.sc = sc; 380 as.count = 0; 381 as.error = 0; 382 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 383 if (as.error != 0) { 384 for (i = 0; i < as.count; i++) 385 bus_release_resource(sc->dev, SYS_RES_IOPORT, 386 sc->io.reg, as.res[i]); 387 free(as.res, M_DEVBUF); 388 return (as.error); 389 } 390 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 391 392 /* Third, add the ranges to the window. */ 393 pcib_add_window_resources(&sc->io, as.res, as.count); 394 free(as.res, M_DEVBUF); 395 return (0); 396 } 397 398 static void 399 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 400 int flags, pci_addr_t max_address) 401 { 402 struct resource *res; 403 char buf[64]; 404 int error, rid; 405 406 if (max_address != (rman_res_t)max_address) 407 max_address = ~0; 408 w->rman.rm_start = 0; 409 w->rman.rm_end = max_address; 410 w->rman.rm_type = RMAN_ARRAY; 411 snprintf(buf, sizeof(buf), "%s %s window", 412 device_get_nameunit(sc->dev), w->name); 413 w->rman.rm_descr = strdup(buf, M_DEVBUF); 414 error = rman_init(&w->rman); 415 if (error) 416 panic("Failed to initialize %s %s rman", 417 device_get_nameunit(sc->dev), w->name); 418 419 if (!pcib_is_window_open(w)) 420 return; 421 422 if (w->base > max_address || w->limit > max_address) { 423 device_printf(sc->dev, 424 "initial %s window has too many bits, ignoring\n", w->name); 425 return; 426 } 427 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 428 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 429 else { 430 rid = w->reg; 431 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 432 w->limit - w->base + 1, flags); 433 if (res != NULL) 434 pcib_add_window_resources(w, &res, 1); 435 } 436 if (w->res == NULL) { 437 device_printf(sc->dev, 438 "failed to allocate initial %s window: %#jx-%#jx\n", 439 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 440 w->base = max_address; 441 w->limit = 0; 442 pcib_write_windows(sc, w->mask); 443 return; 444 } 445 pcib_activate_window(sc, type); 446 } 447 448 /* 449 * Initialize I/O windows. 450 */ 451 static void 452 pcib_probe_windows(struct pcib_softc *sc) 453 { 454 pci_addr_t max; 455 device_t dev; 456 uint32_t val; 457 458 dev = sc->dev; 459 460 if (pci_clear_pcib) { 461 pcib_bridge_init(dev); 462 } 463 464 /* Determine if the I/O port window is implemented. */ 465 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 466 if (val == 0) { 467 /* 468 * If 'val' is zero, then only 16-bits of I/O space 469 * are supported. 470 */ 471 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 472 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 473 sc->io.valid = 1; 474 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 475 } 476 } else 477 sc->io.valid = 1; 478 479 /* Read the existing I/O port window. */ 480 if (sc->io.valid) { 481 sc->io.reg = PCIR_IOBASEL_1; 482 sc->io.step = 12; 483 sc->io.mask = WIN_IO; 484 sc->io.name = "I/O port"; 485 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 486 sc->io.base = PCI_PPBIOBASE( 487 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 488 sc->io.limit = PCI_PPBIOLIMIT( 489 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 490 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 491 max = 0xffffffff; 492 } else { 493 sc->io.base = PCI_PPBIOBASE(0, val); 494 sc->io.limit = PCI_PPBIOLIMIT(0, 495 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 496 max = 0xffff; 497 } 498 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 499 } 500 501 /* Read the existing memory window. */ 502 sc->mem.valid = 1; 503 sc->mem.reg = PCIR_MEMBASE_1; 504 sc->mem.step = 20; 505 sc->mem.mask = WIN_MEM; 506 sc->mem.name = "memory"; 507 sc->mem.base = PCI_PPBMEMBASE(0, 508 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 509 sc->mem.limit = PCI_PPBMEMLIMIT(0, 510 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 511 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 512 513 /* Determine if the prefetchable memory window is implemented. */ 514 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 515 if (val == 0) { 516 /* 517 * If 'val' is zero, then only 32-bits of memory space 518 * are supported. 519 */ 520 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 521 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 522 sc->pmem.valid = 1; 523 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 524 } 525 } else 526 sc->pmem.valid = 1; 527 528 /* Read the existing prefetchable memory window. */ 529 if (sc->pmem.valid) { 530 sc->pmem.reg = PCIR_PMBASEL_1; 531 sc->pmem.step = 20; 532 sc->pmem.mask = WIN_PMEM; 533 sc->pmem.name = "prefetch"; 534 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 535 sc->pmem.base = PCI_PPBMEMBASE( 536 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 537 sc->pmem.limit = PCI_PPBMEMLIMIT( 538 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 539 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 540 max = 0xffffffffffffffff; 541 } else { 542 sc->pmem.base = PCI_PPBMEMBASE(0, val); 543 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 544 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 545 max = 0xffffffff; 546 } 547 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 548 RF_PREFETCHABLE, max); 549 } 550 } 551 552 static void 553 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 554 { 555 device_t dev; 556 int error, i; 557 558 if (!w->valid) 559 return; 560 561 dev = sc->dev; 562 error = rman_fini(&w->rman); 563 if (error) { 564 device_printf(dev, "failed to release %s rman\n", w->name); 565 return; 566 } 567 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 568 569 for (i = 0; i < w->count; i++) { 570 error = bus_free_resource(dev, type, w->res[i]); 571 if (error) 572 device_printf(dev, 573 "failed to release %s resource: %d\n", w->name, 574 error); 575 } 576 free(w->res, M_DEVBUF); 577 } 578 579 static void 580 pcib_free_windows(struct pcib_softc *sc) 581 { 582 583 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 584 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 585 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 586 } 587 588 #ifdef PCI_RES_BUS 589 /* 590 * Allocate a suitable secondary bus for this bridge if needed and 591 * initialize the resource manager for the secondary bus range. Note 592 * that the minimum count is a desired value and this may allocate a 593 * smaller range. 594 */ 595 void 596 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 597 { 598 char buf[64]; 599 int error, rid, sec_reg; 600 601 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 602 case PCIM_HDRTYPE_BRIDGE: 603 sec_reg = PCIR_SECBUS_1; 604 bus->sub_reg = PCIR_SUBBUS_1; 605 break; 606 case PCIM_HDRTYPE_CARDBUS: 607 sec_reg = PCIR_SECBUS_2; 608 bus->sub_reg = PCIR_SUBBUS_2; 609 break; 610 default: 611 panic("not a PCI bridge"); 612 } 613 bus->sec = pci_read_config(dev, sec_reg, 1); 614 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 615 bus->dev = dev; 616 bus->rman.rm_start = 0; 617 bus->rman.rm_end = PCI_BUSMAX; 618 bus->rman.rm_type = RMAN_ARRAY; 619 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 620 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 621 error = rman_init(&bus->rman); 622 if (error) 623 panic("Failed to initialize %s bus number rman", 624 device_get_nameunit(dev)); 625 626 /* 627 * Allocate a bus range. This will return an existing bus range 628 * if one exists, or a new bus range if one does not. 629 */ 630 rid = 0; 631 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 632 min_count, 0); 633 if (bus->res == NULL) { 634 /* 635 * Fall back to just allocating a range of a single bus 636 * number. 637 */ 638 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 639 1, 0); 640 } else if (rman_get_size(bus->res) < min_count) 641 /* 642 * Attempt to grow the existing range to satisfy the 643 * minimum desired count. 644 */ 645 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 646 rman_get_start(bus->res), rman_get_start(bus->res) + 647 min_count - 1); 648 649 /* 650 * Add the initial resource to the rman. 651 */ 652 if (bus->res != NULL) { 653 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 654 rman_get_end(bus->res)); 655 if (error) 656 panic("Failed to add resource to rman"); 657 bus->sec = rman_get_start(bus->res); 658 bus->sub = rman_get_end(bus->res); 659 } 660 } 661 662 void 663 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 664 { 665 int error; 666 667 error = rman_fini(&bus->rman); 668 if (error) { 669 device_printf(dev, "failed to release bus number rman\n"); 670 return; 671 } 672 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 673 674 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 675 if (error) 676 device_printf(dev, 677 "failed to release bus numbers resource: %d\n", error); 678 } 679 680 static struct resource * 681 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 682 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 683 { 684 struct resource *res; 685 686 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 687 child); 688 if (res == NULL) 689 return (NULL); 690 691 if (bootverbose) 692 device_printf(bus->dev, 693 "allocated bus range (%ju-%ju) for rid %d of %s\n", 694 rman_get_start(res), rman_get_end(res), *rid, 695 pcib_child_name(child)); 696 rman_set_rid(res, *rid); 697 return (res); 698 } 699 700 /* 701 * Attempt to grow the secondary bus range. This is much simpler than 702 * for I/O windows as the range can only be grown by increasing 703 * subbus. 704 */ 705 static int 706 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 707 { 708 rman_res_t old_end; 709 int error; 710 711 old_end = rman_get_end(bus->res); 712 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 713 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 714 rman_get_start(bus->res), new_end); 715 if (error) 716 return (error); 717 if (bootverbose) 718 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 719 rman_get_start(bus->res), rman_get_end(bus->res)); 720 error = rman_manage_region(&bus->rman, old_end + 1, 721 rman_get_end(bus->res)); 722 if (error) 723 panic("Failed to add resource to rman"); 724 bus->sub = rman_get_end(bus->res); 725 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 726 return (0); 727 } 728 729 struct resource * 730 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 731 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 732 { 733 struct resource *res; 734 rman_res_t start_free, end_free, new_end; 735 736 /* 737 * First, see if the request can be satisified by the existing 738 * bus range. 739 */ 740 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 741 if (res != NULL) 742 return (res); 743 744 /* 745 * Figure out a range to grow the bus range. First, find the 746 * first bus number after the last allocated bus in the rman and 747 * enforce that as a minimum starting point for the range. 748 */ 749 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 750 end_free != bus->sub) 751 start_free = bus->sub + 1; 752 if (start_free < start) 753 start_free = start; 754 new_end = start_free + count - 1; 755 756 /* 757 * See if this new range would satisfy the request if it 758 * succeeds. 759 */ 760 if (new_end > end) 761 return (NULL); 762 763 /* Finally, attempt to grow the existing resource. */ 764 if (bootverbose) { 765 device_printf(bus->dev, 766 "attempting to grow bus range for %ju buses\n", count); 767 printf("\tback candidate range: %ju-%ju\n", start_free, 768 new_end); 769 } 770 if (pcib_grow_subbus(bus, new_end) == 0) 771 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 772 flags)); 773 return (NULL); 774 } 775 #endif 776 777 #else 778 779 /* 780 * Is the prefetch window open (eg, can we allocate memory in it?) 781 */ 782 static int 783 pcib_is_prefetch_open(struct pcib_softc *sc) 784 { 785 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 786 } 787 788 /* 789 * Is the nonprefetch window open (eg, can we allocate memory in it?) 790 */ 791 static int 792 pcib_is_nonprefetch_open(struct pcib_softc *sc) 793 { 794 return (sc->membase > 0 && sc->membase < sc->memlimit); 795 } 796 797 /* 798 * Is the io window open (eg, can we allocate ports in it?) 799 */ 800 static int 801 pcib_is_io_open(struct pcib_softc *sc) 802 { 803 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 804 } 805 806 /* 807 * Get current I/O decode. 808 */ 809 static void 810 pcib_get_io_decode(struct pcib_softc *sc) 811 { 812 device_t dev; 813 uint32_t iolow; 814 815 dev = sc->dev; 816 817 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 818 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 819 sc->iobase = PCI_PPBIOBASE( 820 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 821 else 822 sc->iobase = PCI_PPBIOBASE(0, iolow); 823 824 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 825 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 826 sc->iolimit = PCI_PPBIOLIMIT( 827 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 828 else 829 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 830 } 831 832 /* 833 * Get current memory decode. 834 */ 835 static void 836 pcib_get_mem_decode(struct pcib_softc *sc) 837 { 838 device_t dev; 839 pci_addr_t pmemlow; 840 841 dev = sc->dev; 842 843 sc->membase = PCI_PPBMEMBASE(0, 844 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 845 sc->memlimit = PCI_PPBMEMLIMIT(0, 846 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 847 848 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 849 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 850 sc->pmembase = PCI_PPBMEMBASE( 851 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 852 else 853 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 854 855 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 856 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 857 sc->pmemlimit = PCI_PPBMEMLIMIT( 858 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 859 else 860 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 861 } 862 863 /* 864 * Restore previous I/O decode. 865 */ 866 static void 867 pcib_set_io_decode(struct pcib_softc *sc) 868 { 869 device_t dev; 870 uint32_t iohi; 871 872 dev = sc->dev; 873 874 iohi = sc->iobase >> 16; 875 if (iohi > 0) 876 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 877 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 878 879 iohi = sc->iolimit >> 16; 880 if (iohi > 0) 881 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 882 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 883 } 884 885 /* 886 * Restore previous memory decode. 887 */ 888 static void 889 pcib_set_mem_decode(struct pcib_softc *sc) 890 { 891 device_t dev; 892 pci_addr_t pmemhi; 893 894 dev = sc->dev; 895 896 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 897 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 898 899 pmemhi = sc->pmembase >> 32; 900 if (pmemhi > 0) 901 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 902 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 903 904 pmemhi = sc->pmemlimit >> 32; 905 if (pmemhi > 0) 906 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 907 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 908 } 909 #endif 910 911 #ifdef PCI_HP 912 /* 913 * PCI-express HotPlug support. 914 */ 915 static int pci_enable_pcie_hp = 1; 916 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 917 &pci_enable_pcie_hp, 0, 918 "Enable support for native PCI-express HotPlug."); 919 920 static void 921 pcib_probe_hotplug(struct pcib_softc *sc) 922 { 923 device_t dev; 924 uint32_t link_cap; 925 uint16_t link_sta, slot_sta; 926 927 if (!pci_enable_pcie_hp) 928 return; 929 930 dev = sc->dev; 931 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 932 return; 933 934 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 935 return; 936 937 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 938 939 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 940 return; 941 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 942 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 943 return; 944 945 /* 946 * Some devices report that they have an MRL when they actually 947 * do not. Since they always report that the MRL is open, child 948 * devices would be ignored. Try to detect these devices and 949 * ignore their claim of HotPlug support. 950 * 951 * If there is an open MRL but the Data Link Layer is active, 952 * the MRL is not real. 953 */ 954 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 955 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 956 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 957 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 958 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 959 return; 960 } 961 } 962 963 /* 964 * Now that we're sure we want to do hot plug, ask the 965 * firmware, if any, if that's OK. 966 */ 967 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 968 if (bootverbose) 969 device_printf(dev, "Unable to activate hot plug feature.\n"); 970 return; 971 } 972 973 sc->flags |= PCIB_HOTPLUG; 974 } 975 976 /* 977 * Send a HotPlug command to the slot control register. If this slot 978 * uses command completion interrupts and a previous command is still 979 * in progress, then the command is dropped. Once the previous 980 * command completes or times out, pcib_pcie_hotplug_update() will be 981 * invoked to post a new command based on the slot's state at that 982 * time. 983 */ 984 static void 985 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 986 { 987 device_t dev; 988 uint16_t ctl, new; 989 990 dev = sc->dev; 991 992 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 993 return; 994 995 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 996 new = (ctl & ~mask) | val; 997 if (new == ctl) 998 return; 999 if (bootverbose) 1000 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 1001 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 1002 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 1003 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 1004 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 1005 if (!cold) 1006 callout_reset(&sc->pcie_cc_timer, hz, 1007 pcib_pcie_cc_timeout, sc); 1008 } 1009 } 1010 1011 static void 1012 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 1013 { 1014 device_t dev; 1015 1016 dev = sc->dev; 1017 1018 if (bootverbose) 1019 device_printf(dev, "Command Completed\n"); 1020 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 1021 return; 1022 callout_stop(&sc->pcie_cc_timer); 1023 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1024 wakeup(sc); 1025 } 1026 1027 /* 1028 * Returns true if a card is fully inserted from the user's 1029 * perspective. It may not yet be ready for access, but the driver 1030 * can now start enabling access if necessary. 1031 */ 1032 static bool 1033 pcib_hotplug_inserted(struct pcib_softc *sc) 1034 { 1035 1036 /* Pretend the card isn't present if a detach is forced. */ 1037 if (sc->flags & PCIB_DETACHING) 1038 return (false); 1039 1040 /* Card must be present in the slot. */ 1041 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1042 return (false); 1043 1044 /* A power fault implicitly turns off power to the slot. */ 1045 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1046 return (false); 1047 1048 /* If the MRL is disengaged, the slot is powered off. */ 1049 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1050 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1051 return (false); 1052 1053 return (true); 1054 } 1055 1056 /* 1057 * Returns -1 if the card is fully inserted, powered, and ready for 1058 * access. Otherwise, returns 0. 1059 */ 1060 static int 1061 pcib_hotplug_present(struct pcib_softc *sc) 1062 { 1063 1064 /* Card must be inserted. */ 1065 if (!pcib_hotplug_inserted(sc)) 1066 return (0); 1067 1068 /* 1069 * Require the Electromechanical Interlock to be engaged if 1070 * present. 1071 */ 1072 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP && 1073 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0) 1074 return (0); 1075 1076 /* Require the Data Link Layer to be active. */ 1077 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1078 return (0); 1079 1080 return (-1); 1081 } 1082 1083 static void 1084 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1085 bool schedule_task) 1086 { 1087 bool card_inserted, ei_engaged; 1088 1089 /* Clear DETACHING if Presence Detect has cleared. */ 1090 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1091 PCIEM_SLOT_STA_PDC) 1092 sc->flags &= ~PCIB_DETACHING; 1093 1094 card_inserted = pcib_hotplug_inserted(sc); 1095 1096 /* Turn the power indicator on if a card is inserted. */ 1097 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1098 mask |= PCIEM_SLOT_CTL_PIC; 1099 if (card_inserted) 1100 val |= PCIEM_SLOT_CTL_PI_ON; 1101 else if (sc->flags & PCIB_DETACH_PENDING) 1102 val |= PCIEM_SLOT_CTL_PI_BLINK; 1103 else 1104 val |= PCIEM_SLOT_CTL_PI_OFF; 1105 } 1106 1107 /* Turn the power on via the Power Controller if a card is inserted. */ 1108 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1109 mask |= PCIEM_SLOT_CTL_PCC; 1110 if (card_inserted) 1111 val |= PCIEM_SLOT_CTL_PC_ON; 1112 else 1113 val |= PCIEM_SLOT_CTL_PC_OFF; 1114 } 1115 1116 /* 1117 * If a card is inserted, enable the Electromechanical 1118 * Interlock. If a card is not inserted (or we are in the 1119 * process of detaching), disable the Electromechanical 1120 * Interlock. 1121 */ 1122 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { 1123 mask |= PCIEM_SLOT_CTL_EIC; 1124 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1125 if (card_inserted != ei_engaged) 1126 val |= PCIEM_SLOT_CTL_EIC; 1127 } 1128 1129 /* 1130 * Start a timer to see if the Data Link Layer times out. 1131 * Note that we only start the timer if Presence Detect or MRL Sensor 1132 * changed on this interrupt. Stop any scheduled timer if 1133 * the Data Link Layer is active. 1134 */ 1135 if (card_inserted && 1136 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1137 sc->pcie_slot_sta & 1138 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1139 if (cold) 1140 device_printf(sc->dev, 1141 "Data Link Layer inactive\n"); 1142 else 1143 callout_reset(&sc->pcie_dll_timer, hz, 1144 pcib_pcie_dll_timeout, sc); 1145 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1146 callout_stop(&sc->pcie_dll_timer); 1147 1148 pcib_pcie_hotplug_command(sc, val, mask); 1149 1150 /* 1151 * During attach the child "pci" device is added synchronously; 1152 * otherwise, the task is scheduled to manage the child 1153 * device. 1154 */ 1155 if (schedule_task && 1156 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1157 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task); 1158 } 1159 1160 static void 1161 pcib_pcie_intr_hotplug(void *arg) 1162 { 1163 struct pcib_softc *sc; 1164 device_t dev; 1165 1166 sc = arg; 1167 dev = sc->dev; 1168 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1169 1170 /* Clear the events just reported. */ 1171 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1172 1173 if (bootverbose) 1174 device_printf(dev, "HotPlug interrupt: %#x\n", 1175 sc->pcie_slot_sta); 1176 1177 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1178 if (sc->flags & PCIB_DETACH_PENDING) { 1179 device_printf(dev, 1180 "Attention Button Pressed: Detach Cancelled\n"); 1181 sc->flags &= ~PCIB_DETACH_PENDING; 1182 callout_stop(&sc->pcie_ab_timer); 1183 } else { 1184 device_printf(dev, 1185 "Attention Button Pressed: Detaching in 5 seconds\n"); 1186 sc->flags |= PCIB_DETACH_PENDING; 1187 callout_reset(&sc->pcie_ab_timer, 5 * hz, 1188 pcib_pcie_ab_timeout, sc); 1189 } 1190 } 1191 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1192 device_printf(dev, "Power Fault Detected\n"); 1193 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1194 device_printf(dev, "MRL Sensor Changed to %s\n", 1195 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1196 "closed"); 1197 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1198 device_printf(dev, "Presence Detect Changed to %s\n", 1199 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1200 "empty"); 1201 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1202 pcib_pcie_hotplug_command_completed(sc); 1203 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1204 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1205 if (bootverbose) 1206 device_printf(dev, 1207 "Data Link Layer State Changed to %s\n", 1208 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1209 "active" : "inactive"); 1210 } 1211 1212 pcib_pcie_hotplug_update(sc, 0, 0, true); 1213 } 1214 1215 static void 1216 pcib_pcie_hotplug_task(void *context, int pending) 1217 { 1218 struct pcib_softc *sc; 1219 device_t dev; 1220 1221 sc = context; 1222 mtx_lock(&Giant); 1223 dev = sc->dev; 1224 if (pcib_hotplug_present(sc) != 0) { 1225 if (sc->child == NULL) { 1226 sc->child = device_add_child(dev, "pci", -1); 1227 bus_generic_attach(dev); 1228 } 1229 } else { 1230 if (sc->child != NULL) { 1231 if (device_delete_child(dev, sc->child) == 0) 1232 sc->child = NULL; 1233 } 1234 } 1235 mtx_unlock(&Giant); 1236 } 1237 1238 static void 1239 pcib_pcie_ab_timeout(void *arg) 1240 { 1241 struct pcib_softc *sc; 1242 device_t dev; 1243 1244 sc = arg; 1245 dev = sc->dev; 1246 mtx_assert(&Giant, MA_OWNED); 1247 if (sc->flags & PCIB_DETACH_PENDING) { 1248 sc->flags |= PCIB_DETACHING; 1249 sc->flags &= ~PCIB_DETACH_PENDING; 1250 pcib_pcie_hotplug_update(sc, 0, 0, true); 1251 } 1252 } 1253 1254 static void 1255 pcib_pcie_cc_timeout(void *arg) 1256 { 1257 struct pcib_softc *sc; 1258 device_t dev; 1259 uint16_t sta; 1260 1261 sc = arg; 1262 dev = sc->dev; 1263 mtx_assert(&Giant, MA_OWNED); 1264 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1265 if (!(sta & PCIEM_SLOT_STA_CC)) { 1266 device_printf(dev, 1267 "HotPlug Command Timed Out - forcing detach\n"); 1268 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING); 1269 sc->flags |= PCIB_DETACHING; 1270 pcib_pcie_hotplug_update(sc, 0, 0, true); 1271 } else { 1272 device_printf(dev, 1273 "Missed HotPlug interrupt waiting for Command Completion\n"); 1274 pcib_pcie_intr_hotplug(sc); 1275 } 1276 } 1277 1278 static void 1279 pcib_pcie_dll_timeout(void *arg) 1280 { 1281 struct pcib_softc *sc; 1282 device_t dev; 1283 uint16_t sta; 1284 1285 sc = arg; 1286 dev = sc->dev; 1287 mtx_assert(&Giant, MA_OWNED); 1288 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1289 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1290 device_printf(dev, 1291 "Timed out waiting for Data Link Layer Active\n"); 1292 sc->flags |= PCIB_DETACHING; 1293 pcib_pcie_hotplug_update(sc, 0, 0, true); 1294 } else if (sta != sc->pcie_link_sta) { 1295 device_printf(dev, 1296 "Missed HotPlug interrupt waiting for DLL Active\n"); 1297 pcib_pcie_intr_hotplug(sc); 1298 } 1299 } 1300 1301 static int 1302 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1303 { 1304 device_t dev; 1305 int count, error, rid; 1306 1307 rid = -1; 1308 dev = sc->dev; 1309 1310 /* 1311 * For simplicity, only use MSI-X if there is a single message. 1312 * To support a device with multiple messages we would have to 1313 * use remap intr if the MSI number is not 0. 1314 */ 1315 count = pci_msix_count(dev); 1316 if (count == 1) { 1317 error = pci_alloc_msix(dev, &count); 1318 if (error == 0) 1319 rid = 1; 1320 } 1321 1322 if (rid < 0 && pci_msi_count(dev) > 0) { 1323 count = 1; 1324 error = pci_alloc_msi(dev, &count); 1325 if (error == 0) 1326 rid = 1; 1327 } 1328 1329 if (rid < 0) 1330 rid = 0; 1331 1332 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1333 RF_ACTIVE); 1334 if (sc->pcie_irq == NULL) { 1335 device_printf(dev, 1336 "Failed to allocate interrupt for PCI-e events\n"); 1337 if (rid > 0) 1338 pci_release_msi(dev); 1339 return (ENXIO); 1340 } 1341 1342 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC, 1343 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1344 if (error) { 1345 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1346 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1347 if (rid > 0) 1348 pci_release_msi(dev); 1349 return (error); 1350 } 1351 return (0); 1352 } 1353 1354 static int 1355 pcib_release_pcie_irq(struct pcib_softc *sc) 1356 { 1357 device_t dev; 1358 int error; 1359 1360 dev = sc->dev; 1361 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1362 if (error) 1363 return (error); 1364 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1365 if (error) 1366 return (error); 1367 return (pci_release_msi(dev)); 1368 } 1369 1370 static void 1371 pcib_setup_hotplug(struct pcib_softc *sc) 1372 { 1373 device_t dev; 1374 uint16_t mask, val; 1375 1376 dev = sc->dev; 1377 callout_init(&sc->pcie_ab_timer, 0); 1378 callout_init(&sc->pcie_cc_timer, 0); 1379 callout_init(&sc->pcie_dll_timer, 0); 1380 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1381 1382 /* Allocate IRQ. */ 1383 if (pcib_alloc_pcie_irq(sc) != 0) 1384 return; 1385 1386 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1387 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1388 1389 /* Clear any events previously pending. */ 1390 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1391 1392 /* Enable HotPlug events. */ 1393 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1394 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1395 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1396 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1397 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1398 val |= PCIEM_SLOT_CTL_ABPE; 1399 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1400 val |= PCIEM_SLOT_CTL_PFDE; 1401 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1402 val |= PCIEM_SLOT_CTL_MRLSCE; 1403 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1404 val |= PCIEM_SLOT_CTL_CCIE; 1405 1406 /* Turn the attention indicator off. */ 1407 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1408 mask |= PCIEM_SLOT_CTL_AIC; 1409 val |= PCIEM_SLOT_CTL_AI_OFF; 1410 } 1411 1412 pcib_pcie_hotplug_update(sc, val, mask, false); 1413 } 1414 1415 static int 1416 pcib_detach_hotplug(struct pcib_softc *sc) 1417 { 1418 uint16_t mask, val; 1419 int error; 1420 1421 /* Disable the card in the slot and force it to detach. */ 1422 if (sc->flags & PCIB_DETACH_PENDING) { 1423 sc->flags &= ~PCIB_DETACH_PENDING; 1424 callout_stop(&sc->pcie_ab_timer); 1425 } 1426 sc->flags |= PCIB_DETACHING; 1427 1428 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1429 callout_stop(&sc->pcie_cc_timer); 1430 tsleep(sc, 0, "hpcmd", hz); 1431 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1432 } 1433 1434 /* Disable HotPlug events. */ 1435 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1436 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1437 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1438 val = 0; 1439 1440 /* Turn the attention indicator off. */ 1441 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1442 mask |= PCIEM_SLOT_CTL_AIC; 1443 val |= PCIEM_SLOT_CTL_AI_OFF; 1444 } 1445 1446 pcib_pcie_hotplug_update(sc, val, mask, false); 1447 1448 error = pcib_release_pcie_irq(sc); 1449 if (error) 1450 return (error); 1451 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task); 1452 callout_drain(&sc->pcie_ab_timer); 1453 callout_drain(&sc->pcie_cc_timer); 1454 callout_drain(&sc->pcie_dll_timer); 1455 return (0); 1456 } 1457 #endif 1458 1459 /* 1460 * Get current bridge configuration. 1461 */ 1462 static void 1463 pcib_cfg_save(struct pcib_softc *sc) 1464 { 1465 #ifndef NEW_PCIB 1466 device_t dev; 1467 uint16_t command; 1468 1469 dev = sc->dev; 1470 1471 command = pci_read_config(dev, PCIR_COMMAND, 2); 1472 if (command & PCIM_CMD_PORTEN) 1473 pcib_get_io_decode(sc); 1474 if (command & PCIM_CMD_MEMEN) 1475 pcib_get_mem_decode(sc); 1476 #endif 1477 } 1478 1479 /* 1480 * Restore previous bridge configuration. 1481 */ 1482 static void 1483 pcib_cfg_restore(struct pcib_softc *sc) 1484 { 1485 device_t dev; 1486 #ifndef NEW_PCIB 1487 uint16_t command; 1488 #endif 1489 dev = sc->dev; 1490 1491 #ifdef NEW_PCIB 1492 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1493 #else 1494 command = pci_read_config(dev, PCIR_COMMAND, 2); 1495 if (command & PCIM_CMD_PORTEN) 1496 pcib_set_io_decode(sc); 1497 if (command & PCIM_CMD_MEMEN) 1498 pcib_set_mem_decode(sc); 1499 #endif 1500 } 1501 1502 /* 1503 * Generic device interface 1504 */ 1505 static int 1506 pcib_probe(device_t dev) 1507 { 1508 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1509 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1510 device_set_desc(dev, "PCI-PCI bridge"); 1511 return(-10000); 1512 } 1513 return(ENXIO); 1514 } 1515 1516 void 1517 pcib_attach_common(device_t dev) 1518 { 1519 struct pcib_softc *sc; 1520 struct sysctl_ctx_list *sctx; 1521 struct sysctl_oid *soid; 1522 int comma; 1523 1524 sc = device_get_softc(dev); 1525 sc->dev = dev; 1526 1527 /* 1528 * Get current bridge configuration. 1529 */ 1530 sc->domain = pci_get_domain(dev); 1531 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1532 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1533 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1534 #endif 1535 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1536 pcib_cfg_save(sc); 1537 1538 /* 1539 * The primary bus register should always be the bus of the 1540 * parent. 1541 */ 1542 sc->pribus = pci_get_bus(dev); 1543 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1544 1545 /* 1546 * Setup sysctl reporting nodes 1547 */ 1548 sctx = device_get_sysctl_ctx(dev); 1549 soid = device_get_sysctl_tree(dev); 1550 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1551 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1552 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1553 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1554 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1555 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1556 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1557 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1558 1559 /* 1560 * Quirk handling. 1561 */ 1562 switch (pci_get_devid(dev)) { 1563 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1564 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1565 { 1566 uint8_t supbus; 1567 1568 supbus = pci_read_config(dev, 0x41, 1); 1569 if (supbus != 0xff) { 1570 sc->bus.sec = supbus + 1; 1571 sc->bus.sub = supbus + 1; 1572 } 1573 break; 1574 } 1575 #endif 1576 1577 /* 1578 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1579 * and it is a subtractive bridge. However, the ProgIf is wrong 1580 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1581 * happen. There are also Toshiba and Cavium ThunderX bridges 1582 * that behave this way. 1583 */ 1584 case 0xa002177d: /* Cavium ThunderX */ 1585 case 0x124b8086: /* Intel 82380FB Mobile */ 1586 case 0x060513d7: /* Toshiba ???? */ 1587 sc->flags |= PCIB_SUBTRACTIVE; 1588 break; 1589 1590 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1591 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1592 case 0x00dd10de: 1593 { 1594 char *cp; 1595 1596 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1597 break; 1598 if (strncmp(cp, "Compal", 6) != 0) { 1599 freeenv(cp); 1600 break; 1601 } 1602 freeenv(cp); 1603 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1604 break; 1605 if (strncmp(cp, "08A0", 4) != 0) { 1606 freeenv(cp); 1607 break; 1608 } 1609 freeenv(cp); 1610 if (sc->bus.sub < 0xa) { 1611 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1612 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1613 } 1614 break; 1615 } 1616 #endif 1617 } 1618 1619 if (pci_msi_device_blacklisted(dev)) 1620 sc->flags |= PCIB_DISABLE_MSI; 1621 1622 if (pci_msix_device_blacklisted(dev)) 1623 sc->flags |= PCIB_DISABLE_MSIX; 1624 1625 /* 1626 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1627 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1628 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1629 * This means they act as if they were subtractively decoding 1630 * bridges and pass all transactions. Mark them and real ProgIf 1 1631 * parts as subtractive. 1632 */ 1633 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1634 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1635 sc->flags |= PCIB_SUBTRACTIVE; 1636 1637 #ifdef PCI_HP 1638 pcib_probe_hotplug(sc); 1639 #endif 1640 #ifdef NEW_PCIB 1641 #ifdef PCI_RES_BUS 1642 pcib_setup_secbus(dev, &sc->bus, 1); 1643 #endif 1644 pcib_probe_windows(sc); 1645 #endif 1646 #ifdef PCI_HP 1647 if (sc->flags & PCIB_HOTPLUG) 1648 pcib_setup_hotplug(sc); 1649 #endif 1650 if (bootverbose) { 1651 device_printf(dev, " domain %d\n", sc->domain); 1652 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1653 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1654 #ifdef NEW_PCIB 1655 if (pcib_is_window_open(&sc->io)) 1656 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1657 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1658 if (pcib_is_window_open(&sc->mem)) 1659 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1660 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1661 if (pcib_is_window_open(&sc->pmem)) 1662 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1663 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1664 #else 1665 if (pcib_is_io_open(sc)) 1666 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1667 sc->iobase, sc->iolimit); 1668 if (pcib_is_nonprefetch_open(sc)) 1669 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1670 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1671 if (pcib_is_prefetch_open(sc)) 1672 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1673 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1674 #endif 1675 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1676 sc->flags & PCIB_SUBTRACTIVE) { 1677 device_printf(dev, " special decode "); 1678 comma = 0; 1679 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1680 printf("ISA"); 1681 comma = 1; 1682 } 1683 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1684 printf("%sVGA", comma ? ", " : ""); 1685 comma = 1; 1686 } 1687 if (sc->flags & PCIB_SUBTRACTIVE) 1688 printf("%ssubtractive", comma ? ", " : ""); 1689 printf("\n"); 1690 } 1691 } 1692 1693 /* 1694 * Always enable busmastering on bridges so that transactions 1695 * initiated on the secondary bus are passed through to the 1696 * primary bus. 1697 */ 1698 pci_enable_busmaster(dev); 1699 } 1700 1701 #ifdef PCI_HP 1702 static int 1703 pcib_present(struct pcib_softc *sc) 1704 { 1705 1706 if (sc->flags & PCIB_HOTPLUG) 1707 return (pcib_hotplug_present(sc) != 0); 1708 return (1); 1709 } 1710 #endif 1711 1712 int 1713 pcib_attach_child(device_t dev) 1714 { 1715 struct pcib_softc *sc; 1716 1717 sc = device_get_softc(dev); 1718 if (sc->bus.sec == 0) { 1719 /* no secondary bus; we should have fixed this */ 1720 return(0); 1721 } 1722 1723 #ifdef PCI_HP 1724 if (!pcib_present(sc)) { 1725 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1726 return (0); 1727 } 1728 #endif 1729 1730 sc->child = device_add_child(dev, "pci", -1); 1731 return (bus_generic_attach(dev)); 1732 } 1733 1734 int 1735 pcib_attach(device_t dev) 1736 { 1737 1738 pcib_attach_common(dev); 1739 return (pcib_attach_child(dev)); 1740 } 1741 1742 int 1743 pcib_detach(device_t dev) 1744 { 1745 #if defined(PCI_HP) || defined(NEW_PCIB) 1746 struct pcib_softc *sc; 1747 #endif 1748 int error; 1749 1750 #if defined(PCI_HP) || defined(NEW_PCIB) 1751 sc = device_get_softc(dev); 1752 #endif 1753 error = bus_generic_detach(dev); 1754 if (error) 1755 return (error); 1756 #ifdef PCI_HP 1757 if (sc->flags & PCIB_HOTPLUG) { 1758 error = pcib_detach_hotplug(sc); 1759 if (error) 1760 return (error); 1761 } 1762 #endif 1763 error = device_delete_children(dev); 1764 if (error) 1765 return (error); 1766 #ifdef NEW_PCIB 1767 pcib_free_windows(sc); 1768 #ifdef PCI_RES_BUS 1769 pcib_free_secbus(dev, &sc->bus); 1770 #endif 1771 #endif 1772 return (0); 1773 } 1774 1775 int 1776 pcib_suspend(device_t dev) 1777 { 1778 1779 pcib_cfg_save(device_get_softc(dev)); 1780 return (bus_generic_suspend(dev)); 1781 } 1782 1783 int 1784 pcib_resume(device_t dev) 1785 { 1786 1787 pcib_cfg_restore(device_get_softc(dev)); 1788 return (bus_generic_resume(dev)); 1789 } 1790 1791 void 1792 pcib_bridge_init(device_t dev) 1793 { 1794 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1795 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1796 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1797 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1798 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1799 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1800 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1801 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1802 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1803 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1804 } 1805 1806 int 1807 pcib_child_present(device_t dev, device_t child) 1808 { 1809 #ifdef PCI_HP 1810 struct pcib_softc *sc = device_get_softc(dev); 1811 int retval; 1812 1813 retval = bus_child_present(dev); 1814 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1815 retval = pcib_hotplug_present(sc); 1816 return (retval); 1817 #else 1818 return (bus_child_present(dev)); 1819 #endif 1820 } 1821 1822 int 1823 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1824 { 1825 struct pcib_softc *sc = device_get_softc(dev); 1826 1827 switch (which) { 1828 case PCIB_IVAR_DOMAIN: 1829 *result = sc->domain; 1830 return(0); 1831 case PCIB_IVAR_BUS: 1832 *result = sc->bus.sec; 1833 return(0); 1834 } 1835 return(ENOENT); 1836 } 1837 1838 int 1839 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1840 { 1841 1842 switch (which) { 1843 case PCIB_IVAR_DOMAIN: 1844 return(EINVAL); 1845 case PCIB_IVAR_BUS: 1846 return(EINVAL); 1847 } 1848 return(ENOENT); 1849 } 1850 1851 #ifdef NEW_PCIB 1852 /* 1853 * Attempt to allocate a resource from the existing resources assigned 1854 * to a window. 1855 */ 1856 static struct resource * 1857 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1858 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1859 rman_res_t count, u_int flags) 1860 { 1861 struct resource *res; 1862 1863 if (!pcib_is_window_open(w)) 1864 return (NULL); 1865 1866 res = rman_reserve_resource(&w->rman, start, end, count, 1867 flags & ~RF_ACTIVE, child); 1868 if (res == NULL) 1869 return (NULL); 1870 1871 if (bootverbose) 1872 device_printf(sc->dev, 1873 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1874 w->name, rman_get_start(res), rman_get_end(res), *rid, 1875 pcib_child_name(child)); 1876 rman_set_rid(res, *rid); 1877 1878 /* 1879 * If the resource should be active, pass that request up the 1880 * tree. This assumes the parent drivers can handle 1881 * activating sub-allocated resources. 1882 */ 1883 if (flags & RF_ACTIVE) { 1884 if (bus_activate_resource(child, type, *rid, res) != 0) { 1885 rman_release_resource(res); 1886 return (NULL); 1887 } 1888 } 1889 1890 return (res); 1891 } 1892 1893 /* Allocate a fresh resource range for an unconfigured window. */ 1894 static int 1895 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1896 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1897 { 1898 struct resource *res; 1899 rman_res_t base, limit, wmask; 1900 int rid; 1901 1902 /* 1903 * If this is an I/O window on a bridge with ISA enable set 1904 * and the start address is below 64k, then try to allocate an 1905 * initial window of 0x1000 bytes long starting at address 1906 * 0xf000 and walking down. Note that if the original request 1907 * was larger than the non-aliased range size of 0x100 our 1908 * caller would have raised the start address up to 64k 1909 * already. 1910 */ 1911 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1912 start < 65536) { 1913 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1914 limit = base + 0xfff; 1915 1916 /* 1917 * Skip ranges that wouldn't work for the 1918 * original request. Note that the actual 1919 * window that overlaps are the non-alias 1920 * ranges within [base, limit], so this isn't 1921 * quite a simple comparison. 1922 */ 1923 if (start + count > limit - 0x400) 1924 continue; 1925 if (base == 0) { 1926 /* 1927 * The first open region for the window at 1928 * 0 is 0x400-0x4ff. 1929 */ 1930 if (end - count + 1 < 0x400) 1931 continue; 1932 } else { 1933 if (end - count + 1 < base) 1934 continue; 1935 } 1936 1937 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1938 w->base = base; 1939 w->limit = limit; 1940 return (0); 1941 } 1942 } 1943 return (ENOSPC); 1944 } 1945 1946 wmask = ((rman_res_t)1 << w->step) - 1; 1947 if (RF_ALIGNMENT(flags) < w->step) { 1948 flags &= ~RF_ALIGNMENT_MASK; 1949 flags |= RF_ALIGNMENT_LOG2(w->step); 1950 } 1951 start &= ~wmask; 1952 end |= wmask; 1953 count = roundup2(count, (rman_res_t)1 << w->step); 1954 rid = w->reg; 1955 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1956 flags & ~RF_ACTIVE); 1957 if (res == NULL) 1958 return (ENOSPC); 1959 pcib_add_window_resources(w, &res, 1); 1960 pcib_activate_window(sc, type); 1961 w->base = rman_get_start(res); 1962 w->limit = rman_get_end(res); 1963 return (0); 1964 } 1965 1966 /* Try to expand an existing window to the requested base and limit. */ 1967 static int 1968 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1969 rman_res_t base, rman_res_t limit) 1970 { 1971 struct resource *res; 1972 int error, i, force_64k_base; 1973 1974 KASSERT(base <= w->base && limit >= w->limit, 1975 ("attempting to shrink window")); 1976 1977 /* 1978 * XXX: pcib_grow_window() doesn't try to do this anyway and 1979 * the error handling for all the edge cases would be tedious. 1980 */ 1981 KASSERT(limit == w->limit || base == w->base, 1982 ("attempting to grow both ends of a window")); 1983 1984 /* 1985 * Yet more special handling for requests to expand an I/O 1986 * window behind an ISA-enabled bridge. Since I/O windows 1987 * have to grow in 0x1000 increments and the end of the 0xffff 1988 * range is an alias, growing a window below 64k will always 1989 * result in allocating new resources and never adjusting an 1990 * existing resource. 1991 */ 1992 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1993 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1994 KASSERT(limit == w->limit || limit <= 65535, 1995 ("attempting to grow both ends across 64k ISA alias")); 1996 1997 if (base != w->base) 1998 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1999 else 2000 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 2001 limit); 2002 if (error == 0) { 2003 w->base = base; 2004 w->limit = limit; 2005 } 2006 return (error); 2007 } 2008 2009 /* 2010 * Find the existing resource to adjust. Usually there is only one, 2011 * but for an ISA-enabled bridge we might be growing the I/O window 2012 * above 64k and need to find the existing resource that maps all 2013 * of the area above 64k. 2014 */ 2015 for (i = 0; i < w->count; i++) { 2016 if (rman_get_end(w->res[i]) == w->limit) 2017 break; 2018 } 2019 KASSERT(i != w->count, ("did not find existing resource")); 2020 res = w->res[i]; 2021 2022 /* 2023 * Usually the resource we found should match the window's 2024 * existing range. The one exception is the ISA-enabled case 2025 * mentioned above in which case the resource should start at 2026 * 64k. 2027 */ 2028 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2029 w->base <= 65535) { 2030 KASSERT(rman_get_start(res) == 65536, 2031 ("existing resource mismatch")); 2032 force_64k_base = 1; 2033 } else { 2034 KASSERT(w->base == rman_get_start(res), 2035 ("existing resource mismatch")); 2036 force_64k_base = 0; 2037 } 2038 2039 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2040 rman_get_start(res) : base, limit); 2041 if (error) 2042 return (error); 2043 2044 /* Add the newly allocated region to the resource manager. */ 2045 if (w->base != base) { 2046 error = rman_manage_region(&w->rman, base, w->base - 1); 2047 w->base = base; 2048 } else { 2049 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2050 w->limit = limit; 2051 } 2052 if (error) { 2053 if (bootverbose) 2054 device_printf(sc->dev, 2055 "failed to expand %s resource manager\n", w->name); 2056 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2057 rman_get_start(res) : w->base, w->limit); 2058 } 2059 return (error); 2060 } 2061 2062 /* 2063 * Attempt to grow a window to make room for a given resource request. 2064 */ 2065 static int 2066 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2067 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2068 { 2069 rman_res_t align, start_free, end_free, front, back, wmask; 2070 int error; 2071 2072 /* 2073 * Clamp the desired resource range to the maximum address 2074 * this window supports. Reject impossible requests. 2075 * 2076 * For I/O port requests behind a bridge with the ISA enable 2077 * bit set, force large allocations to start above 64k. 2078 */ 2079 if (!w->valid) 2080 return (EINVAL); 2081 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2082 start < 65536) 2083 start = 65536; 2084 if (end > w->rman.rm_end) 2085 end = w->rman.rm_end; 2086 if (start + count - 1 > end || start + count < start) 2087 return (EINVAL); 2088 wmask = ((rman_res_t)1 << w->step) - 1; 2089 2090 /* 2091 * If there is no resource at all, just try to allocate enough 2092 * aligned space for this resource. 2093 */ 2094 if (w->res == NULL) { 2095 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2096 flags); 2097 if (error) { 2098 if (bootverbose) 2099 device_printf(sc->dev, 2100 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2101 w->name, start, end, count); 2102 return (error); 2103 } 2104 if (bootverbose) 2105 device_printf(sc->dev, 2106 "allocated initial %s window of %#jx-%#jx\n", 2107 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2108 goto updatewin; 2109 } 2110 2111 /* 2112 * See if growing the window would help. Compute the minimum 2113 * amount of address space needed on both the front and back 2114 * ends of the existing window to satisfy the allocation. 2115 * 2116 * For each end, build a candidate region adjusting for the 2117 * required alignment, etc. If there is a free region at the 2118 * edge of the window, grow from the inner edge of the free 2119 * region. Otherwise grow from the window boundary. 2120 * 2121 * Growing an I/O window below 64k for a bridge with the ISA 2122 * enable bit doesn't require any special magic as the step 2123 * size of an I/O window (1k) always includes multiple 2124 * non-alias ranges when it is grown in either direction. 2125 * 2126 * XXX: Special case: if w->res is completely empty and the 2127 * request size is larger than w->res, we should find the 2128 * optimal aligned buffer containing w->res and allocate that. 2129 */ 2130 if (bootverbose) 2131 device_printf(sc->dev, 2132 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2133 w->name, start, end, count); 2134 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2135 if (start < w->base) { 2136 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2137 0 || start_free != w->base) 2138 end_free = w->base; 2139 if (end_free > end) 2140 end_free = end + 1; 2141 2142 /* Move end_free down until it is properly aligned. */ 2143 end_free &= ~(align - 1); 2144 end_free--; 2145 front = end_free - (count - 1); 2146 2147 /* 2148 * The resource would now be allocated at (front, 2149 * end_free). Ensure that fits in the (start, end) 2150 * bounds. end_free is checked above. If 'front' is 2151 * ok, ensure it is properly aligned for this window. 2152 * Also check for underflow. 2153 */ 2154 if (front >= start && front <= end_free) { 2155 if (bootverbose) 2156 printf("\tfront candidate range: %#jx-%#jx\n", 2157 front, end_free); 2158 front &= ~wmask; 2159 front = w->base - front; 2160 } else 2161 front = 0; 2162 } else 2163 front = 0; 2164 if (end > w->limit) { 2165 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2166 0 || end_free != w->limit) 2167 start_free = w->limit + 1; 2168 if (start_free < start) 2169 start_free = start; 2170 2171 /* Move start_free up until it is properly aligned. */ 2172 start_free = roundup2(start_free, align); 2173 back = start_free + count - 1; 2174 2175 /* 2176 * The resource would now be allocated at (start_free, 2177 * back). Ensure that fits in the (start, end) 2178 * bounds. start_free is checked above. If 'back' is 2179 * ok, ensure it is properly aligned for this window. 2180 * Also check for overflow. 2181 */ 2182 if (back <= end && start_free <= back) { 2183 if (bootverbose) 2184 printf("\tback candidate range: %#jx-%#jx\n", 2185 start_free, back); 2186 back |= wmask; 2187 back -= w->limit; 2188 } else 2189 back = 0; 2190 } else 2191 back = 0; 2192 2193 /* 2194 * Try to allocate the smallest needed region first. 2195 * If that fails, fall back to the other region. 2196 */ 2197 error = ENOSPC; 2198 while (front != 0 || back != 0) { 2199 if (front != 0 && (front <= back || back == 0)) { 2200 error = pcib_expand_window(sc, w, type, w->base - front, 2201 w->limit); 2202 if (error == 0) 2203 break; 2204 front = 0; 2205 } else { 2206 error = pcib_expand_window(sc, w, type, w->base, 2207 w->limit + back); 2208 if (error == 0) 2209 break; 2210 back = 0; 2211 } 2212 } 2213 2214 if (error) 2215 return (error); 2216 if (bootverbose) 2217 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2218 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2219 2220 updatewin: 2221 /* Write the new window. */ 2222 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2223 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2224 pcib_write_windows(sc, w->mask); 2225 return (0); 2226 } 2227 2228 /* 2229 * We have to trap resource allocation requests and ensure that the bridge 2230 * is set up to, or capable of handling them. 2231 */ 2232 struct resource * 2233 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2234 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2235 { 2236 struct pcib_softc *sc; 2237 struct resource *r; 2238 2239 sc = device_get_softc(dev); 2240 2241 /* 2242 * VGA resources are decoded iff the VGA enable bit is set in 2243 * the bridge control register. VGA resources do not fall into 2244 * the resource windows and are passed up to the parent. 2245 */ 2246 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2247 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2248 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2249 return (bus_generic_alloc_resource(dev, child, type, 2250 rid, start, end, count, flags)); 2251 else 2252 return (NULL); 2253 } 2254 2255 switch (type) { 2256 #ifdef PCI_RES_BUS 2257 case PCI_RES_BUS: 2258 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2259 count, flags)); 2260 #endif 2261 case SYS_RES_IOPORT: 2262 if (pcib_is_isa_range(sc, start, end, count)) 2263 return (NULL); 2264 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2265 end, count, flags); 2266 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2267 break; 2268 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2269 flags) == 0) 2270 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2271 rid, start, end, count, flags); 2272 break; 2273 case SYS_RES_MEMORY: 2274 /* 2275 * For prefetchable resources, prefer the prefetchable 2276 * memory window, but fall back to the regular memory 2277 * window if that fails. Try both windows before 2278 * attempting to grow a window in case the firmware 2279 * has used a range in the regular memory window to 2280 * map a prefetchable BAR. 2281 */ 2282 if (flags & RF_PREFETCHABLE) { 2283 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2284 rid, start, end, count, flags); 2285 if (r != NULL) 2286 break; 2287 } 2288 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2289 start, end, count, flags); 2290 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2291 break; 2292 if (flags & RF_PREFETCHABLE) { 2293 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2294 count, flags) == 0) { 2295 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2296 type, rid, start, end, count, flags); 2297 if (r != NULL) 2298 break; 2299 } 2300 } 2301 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2302 flags & ~RF_PREFETCHABLE) == 0) 2303 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2304 rid, start, end, count, flags); 2305 break; 2306 default: 2307 return (bus_generic_alloc_resource(dev, child, type, rid, 2308 start, end, count, flags)); 2309 } 2310 2311 /* 2312 * If attempts to suballocate from the window fail but this is a 2313 * subtractive bridge, pass the request up the tree. 2314 */ 2315 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2316 return (bus_generic_alloc_resource(dev, child, type, rid, 2317 start, end, count, flags)); 2318 return (r); 2319 } 2320 2321 int 2322 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2323 rman_res_t start, rman_res_t end) 2324 { 2325 struct pcib_softc *sc; 2326 2327 sc = device_get_softc(bus); 2328 if (pcib_is_resource_managed(sc, type, r)) 2329 return (rman_adjust_resource(r, start, end)); 2330 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 2331 } 2332 2333 int 2334 pcib_release_resource(device_t dev, device_t child, int type, int rid, 2335 struct resource *r) 2336 { 2337 struct pcib_softc *sc; 2338 int error; 2339 2340 sc = device_get_softc(dev); 2341 if (pcib_is_resource_managed(sc, type, r)) { 2342 if (rman_get_flags(r) & RF_ACTIVE) { 2343 error = bus_deactivate_resource(child, type, rid, r); 2344 if (error) 2345 return (error); 2346 } 2347 return (rman_release_resource(r)); 2348 } 2349 return (bus_generic_release_resource(dev, child, type, rid, r)); 2350 } 2351 #else 2352 /* 2353 * We have to trap resource allocation requests and ensure that the bridge 2354 * is set up to, or capable of handling them. 2355 */ 2356 struct resource * 2357 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2358 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2359 { 2360 struct pcib_softc *sc = device_get_softc(dev); 2361 const char *name, *suffix; 2362 int ok; 2363 2364 /* 2365 * Fail the allocation for this range if it's not supported. 2366 */ 2367 name = device_get_nameunit(child); 2368 if (name == NULL) { 2369 name = ""; 2370 suffix = ""; 2371 } else 2372 suffix = " "; 2373 switch (type) { 2374 case SYS_RES_IOPORT: 2375 ok = 0; 2376 if (!pcib_is_io_open(sc)) 2377 break; 2378 ok = (start >= sc->iobase && end <= sc->iolimit); 2379 2380 /* 2381 * Make sure we allow access to VGA I/O addresses when the 2382 * bridge has the "VGA Enable" bit set. 2383 */ 2384 if (!ok && pci_is_vga_ioport_range(start, end)) 2385 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2386 2387 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2388 if (!ok) { 2389 if (start < sc->iobase) 2390 start = sc->iobase; 2391 if (end > sc->iolimit) 2392 end = sc->iolimit; 2393 if (start < end) 2394 ok = 1; 2395 } 2396 } else { 2397 ok = 1; 2398 #if 0 2399 /* 2400 * If we overlap with the subtractive range, then 2401 * pick the upper range to use. 2402 */ 2403 if (start < sc->iolimit && end > sc->iobase) 2404 start = sc->iolimit + 1; 2405 #endif 2406 } 2407 if (end < start) { 2408 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2409 end, start); 2410 start = 0; 2411 end = 0; 2412 ok = 0; 2413 } 2414 if (!ok) { 2415 device_printf(dev, "%s%srequested unsupported I/O " 2416 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2417 name, suffix, start, end, sc->iobase, sc->iolimit); 2418 return (NULL); 2419 } 2420 if (bootverbose) 2421 device_printf(dev, 2422 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2423 name, suffix, start, end); 2424 break; 2425 2426 case SYS_RES_MEMORY: 2427 ok = 0; 2428 if (pcib_is_nonprefetch_open(sc)) 2429 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2430 if (pcib_is_prefetch_open(sc)) 2431 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2432 2433 /* 2434 * Make sure we allow access to VGA memory addresses when the 2435 * bridge has the "VGA Enable" bit set. 2436 */ 2437 if (!ok && pci_is_vga_memory_range(start, end)) 2438 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2439 2440 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2441 if (!ok) { 2442 ok = 1; 2443 if (flags & RF_PREFETCHABLE) { 2444 if (pcib_is_prefetch_open(sc)) { 2445 if (start < sc->pmembase) 2446 start = sc->pmembase; 2447 if (end > sc->pmemlimit) 2448 end = sc->pmemlimit; 2449 } else { 2450 ok = 0; 2451 } 2452 } else { /* non-prefetchable */ 2453 if (pcib_is_nonprefetch_open(sc)) { 2454 if (start < sc->membase) 2455 start = sc->membase; 2456 if (end > sc->memlimit) 2457 end = sc->memlimit; 2458 } else { 2459 ok = 0; 2460 } 2461 } 2462 } 2463 } else if (!ok) { 2464 ok = 1; /* subtractive bridge: always ok */ 2465 #if 0 2466 if (pcib_is_nonprefetch_open(sc)) { 2467 if (start < sc->memlimit && end > sc->membase) 2468 start = sc->memlimit + 1; 2469 } 2470 if (pcib_is_prefetch_open(sc)) { 2471 if (start < sc->pmemlimit && end > sc->pmembase) 2472 start = sc->pmemlimit + 1; 2473 } 2474 #endif 2475 } 2476 if (end < start) { 2477 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2478 end, start); 2479 start = 0; 2480 end = 0; 2481 ok = 0; 2482 } 2483 if (!ok && bootverbose) 2484 device_printf(dev, 2485 "%s%srequested unsupported memory range %#jx-%#jx " 2486 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2487 name, suffix, start, end, 2488 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2489 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2490 if (!ok) 2491 return (NULL); 2492 if (bootverbose) 2493 device_printf(dev,"%s%srequested memory range " 2494 "0x%jx-0x%jx: good\n", 2495 name, suffix, start, end); 2496 break; 2497 2498 default: 2499 break; 2500 } 2501 /* 2502 * Bridge is OK decoding this resource, so pass it up. 2503 */ 2504 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2505 count, flags)); 2506 } 2507 #endif 2508 2509 /* 2510 * If ARI is enabled on this downstream port, translate the function number 2511 * to the non-ARI slot/function. The downstream port will convert it back in 2512 * hardware. If ARI is not enabled slot and func are not modified. 2513 */ 2514 static __inline void 2515 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2516 { 2517 struct pcib_softc *sc; 2518 int ari_func; 2519 2520 sc = device_get_softc(pcib); 2521 ari_func = *func; 2522 2523 if (sc->flags & PCIB_ENABLE_ARI) { 2524 KASSERT(*slot == 0, 2525 ("Non-zero slot number with ARI enabled!")); 2526 *slot = PCIE_ARI_SLOT(ari_func); 2527 *func = PCIE_ARI_FUNC(ari_func); 2528 } 2529 } 2530 2531 2532 static void 2533 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2534 { 2535 uint32_t ctl2; 2536 2537 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2538 ctl2 |= PCIEM_CTL2_ARI; 2539 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2540 2541 sc->flags |= PCIB_ENABLE_ARI; 2542 } 2543 2544 /* 2545 * PCIB interface. 2546 */ 2547 int 2548 pcib_maxslots(device_t dev) 2549 { 2550 return (PCI_SLOTMAX); 2551 } 2552 2553 static int 2554 pcib_ari_maxslots(device_t dev) 2555 { 2556 struct pcib_softc *sc; 2557 2558 sc = device_get_softc(dev); 2559 2560 if (sc->flags & PCIB_ENABLE_ARI) 2561 return (PCIE_ARI_SLOTMAX); 2562 else 2563 return (PCI_SLOTMAX); 2564 } 2565 2566 static int 2567 pcib_ari_maxfuncs(device_t dev) 2568 { 2569 struct pcib_softc *sc; 2570 2571 sc = device_get_softc(dev); 2572 2573 if (sc->flags & PCIB_ENABLE_ARI) 2574 return (PCIE_ARI_FUNCMAX); 2575 else 2576 return (PCI_FUNCMAX); 2577 } 2578 2579 static void 2580 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2581 int *func) 2582 { 2583 struct pcib_softc *sc; 2584 2585 sc = device_get_softc(pcib); 2586 2587 *bus = PCI_RID2BUS(rid); 2588 if (sc->flags & PCIB_ENABLE_ARI) { 2589 *slot = PCIE_ARI_RID2SLOT(rid); 2590 *func = PCIE_ARI_RID2FUNC(rid); 2591 } else { 2592 *slot = PCI_RID2SLOT(rid); 2593 *func = PCI_RID2FUNC(rid); 2594 } 2595 } 2596 2597 /* 2598 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2599 */ 2600 static uint32_t 2601 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2602 { 2603 #ifdef PCI_HP 2604 struct pcib_softc *sc; 2605 2606 sc = device_get_softc(dev); 2607 if (!pcib_present(sc)) { 2608 switch (width) { 2609 case 2: 2610 return (0xffff); 2611 case 1: 2612 return (0xff); 2613 default: 2614 return (0xffffffff); 2615 } 2616 } 2617 #endif 2618 pcib_xlate_ari(dev, b, &s, &f); 2619 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2620 f, reg, width)); 2621 } 2622 2623 static void 2624 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2625 { 2626 #ifdef PCI_HP 2627 struct pcib_softc *sc; 2628 2629 sc = device_get_softc(dev); 2630 if (!pcib_present(sc)) 2631 return; 2632 #endif 2633 pcib_xlate_ari(dev, b, &s, &f); 2634 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2635 reg, val, width); 2636 } 2637 2638 /* 2639 * Route an interrupt across a PCI bridge. 2640 */ 2641 int 2642 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2643 { 2644 device_t bus; 2645 int parent_intpin; 2646 int intnum; 2647 2648 /* 2649 * 2650 * The PCI standard defines a swizzle of the child-side device/intpin to 2651 * the parent-side intpin as follows. 2652 * 2653 * device = device on child bus 2654 * child_intpin = intpin on child bus slot (0-3) 2655 * parent_intpin = intpin on parent bus slot (0-3) 2656 * 2657 * parent_intpin = (device + child_intpin) % 4 2658 */ 2659 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2660 2661 /* 2662 * Our parent is a PCI bus. Its parent must export the pcib interface 2663 * which includes the ability to route interrupts. 2664 */ 2665 bus = device_get_parent(pcib); 2666 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2667 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2668 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2669 pci_get_slot(dev), 'A' + pin - 1, intnum); 2670 } 2671 return(intnum); 2672 } 2673 2674 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2675 int 2676 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2677 { 2678 struct pcib_softc *sc = device_get_softc(pcib); 2679 device_t bus; 2680 2681 if (sc->flags & PCIB_DISABLE_MSI) 2682 return (ENXIO); 2683 bus = device_get_parent(pcib); 2684 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2685 irqs)); 2686 } 2687 2688 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2689 int 2690 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2691 { 2692 device_t bus; 2693 2694 bus = device_get_parent(pcib); 2695 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2696 } 2697 2698 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2699 int 2700 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2701 { 2702 struct pcib_softc *sc = device_get_softc(pcib); 2703 device_t bus; 2704 2705 if (sc->flags & PCIB_DISABLE_MSIX) 2706 return (ENXIO); 2707 bus = device_get_parent(pcib); 2708 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2709 } 2710 2711 /* Pass request to release an MSI-X message up to the parent bridge. */ 2712 int 2713 pcib_release_msix(device_t pcib, device_t dev, int irq) 2714 { 2715 device_t bus; 2716 2717 bus = device_get_parent(pcib); 2718 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2719 } 2720 2721 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2722 int 2723 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2724 uint32_t *data) 2725 { 2726 device_t bus; 2727 int error; 2728 2729 bus = device_get_parent(pcib); 2730 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2731 if (error) 2732 return (error); 2733 2734 pci_ht_map_msi(pcib, *addr); 2735 return (0); 2736 } 2737 2738 /* Pass request for device power state up to parent bridge. */ 2739 int 2740 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2741 { 2742 device_t bus; 2743 2744 bus = device_get_parent(pcib); 2745 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2746 } 2747 2748 static int 2749 pcib_ari_enabled(device_t pcib) 2750 { 2751 struct pcib_softc *sc; 2752 2753 sc = device_get_softc(pcib); 2754 2755 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2756 } 2757 2758 static int 2759 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2760 uintptr_t *id) 2761 { 2762 struct pcib_softc *sc; 2763 device_t bus_dev; 2764 uint8_t bus, slot, func; 2765 2766 if (type != PCI_ID_RID) { 2767 bus_dev = device_get_parent(pcib); 2768 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2769 } 2770 2771 sc = device_get_softc(pcib); 2772 2773 if (sc->flags & PCIB_ENABLE_ARI) { 2774 bus = pci_get_bus(dev); 2775 func = pci_get_function(dev); 2776 2777 *id = (PCI_ARI_RID(bus, func)); 2778 } else { 2779 bus = pci_get_bus(dev); 2780 slot = pci_get_slot(dev); 2781 func = pci_get_function(dev); 2782 2783 *id = (PCI_RID(bus, slot, func)); 2784 } 2785 2786 return (0); 2787 } 2788 2789 /* 2790 * Check that the downstream port (pcib) and the endpoint device (dev) both 2791 * support ARI. If so, enable it and return 0, otherwise return an error. 2792 */ 2793 static int 2794 pcib_try_enable_ari(device_t pcib, device_t dev) 2795 { 2796 struct pcib_softc *sc; 2797 int error; 2798 uint32_t cap2; 2799 int ari_cap_off; 2800 uint32_t ari_ver; 2801 uint32_t pcie_pos; 2802 2803 sc = device_get_softc(pcib); 2804 2805 /* 2806 * ARI is controlled in a register in the PCIe capability structure. 2807 * If the downstream port does not have the PCIe capability structure 2808 * then it does not support ARI. 2809 */ 2810 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2811 if (error != 0) 2812 return (ENODEV); 2813 2814 /* Check that the PCIe port advertises ARI support. */ 2815 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2816 if (!(cap2 & PCIEM_CAP2_ARI)) 2817 return (ENODEV); 2818 2819 /* 2820 * Check that the endpoint device advertises ARI support via the ARI 2821 * extended capability structure. 2822 */ 2823 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2824 if (error != 0) 2825 return (ENODEV); 2826 2827 /* 2828 * Finally, check that the endpoint device supports the same version 2829 * of ARI that we do. 2830 */ 2831 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2832 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2833 if (bootverbose) 2834 device_printf(pcib, 2835 "Unsupported version of ARI (%d) detected\n", 2836 PCI_EXTCAP_VER(ari_ver)); 2837 2838 return (ENXIO); 2839 } 2840 2841 pcib_enable_ari(sc, pcie_pos); 2842 2843 return (0); 2844 } 2845 2846 int 2847 pcib_request_feature_allow(device_t pcib, device_t dev, 2848 enum pci_feature feature) 2849 { 2850 /* 2851 * No host firmware we have to negotiate with, so we allow 2852 * every valid feature requested. 2853 */ 2854 switch (feature) { 2855 case PCI_FEATURE_AER: 2856 case PCI_FEATURE_HP: 2857 break; 2858 default: 2859 return (EINVAL); 2860 } 2861 2862 return (0); 2863 } 2864 2865 int 2866 pcib_request_feature(device_t dev, enum pci_feature feature) 2867 { 2868 2869 /* 2870 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2871 * the firmware overrides the method of PCI-PCI bridges. 2872 */ 2873 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2874 } 2875 2876 /* 2877 * Pass the request to use this PCI feature up the tree. Either there's a 2878 * firmware like ACPI that's using this feature that will approve (or deny) the 2879 * request to take it over, or the platform has no such firmware, in which case 2880 * the request will be approved. If the request is approved, the OS is expected 2881 * to make use of the feature or render it harmless. 2882 */ 2883 static int 2884 pcib_request_feature_default(device_t pcib, device_t dev, 2885 enum pci_feature feature) 2886 { 2887 device_t bus; 2888 2889 /* 2890 * Our parent is necessarily a pci bus. Its parent will either be 2891 * another pci bridge (which passes it up) or a host bridge that can 2892 * approve or reject the request. 2893 */ 2894 bus = device_get_parent(pcib); 2895 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2896 } 2897