1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * PCI:PCI bridge support. 38 */ 39 40 #include "opt_pci.h" 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/pciio.h> 50 #include <sys/rman.h> 51 #include <sys/sysctl.h> 52 #include <sys/systm.h> 53 #include <sys/taskqueue.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pci_private.h> 58 #include <dev/pci/pcib_private.h> 59 60 #include "pcib_if.h" 61 62 static int pcib_probe(device_t dev); 63 static int pcib_suspend(device_t dev); 64 static int pcib_resume(device_t dev); 65 static int pcib_power_for_sleep(device_t pcib, device_t dev, 66 int *pstate); 67 static int pcib_ari_get_id(device_t pcib, device_t dev, 68 enum pci_id_type type, uintptr_t *id); 69 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 70 u_int f, u_int reg, int width); 71 static void pcib_write_config(device_t dev, u_int b, u_int s, 72 u_int f, u_int reg, uint32_t val, int width); 73 static int pcib_ari_maxslots(device_t dev); 74 static int pcib_ari_maxfuncs(device_t dev); 75 static int pcib_try_enable_ari(device_t pcib, device_t dev); 76 static int pcib_ari_enabled(device_t pcib); 77 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 78 int *bus, int *slot, int *func); 79 #ifdef PCI_HP 80 static void pcib_pcie_ab_timeout(void *arg); 81 static void pcib_pcie_cc_timeout(void *arg); 82 static void pcib_pcie_dll_timeout(void *arg); 83 #endif 84 static int pcib_request_feature_default(device_t pcib, device_t dev, 85 enum pci_feature feature); 86 static int pcib_reset_child(device_t dev, device_t child, int flags); 87 88 static device_method_t pcib_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, pcib_probe), 91 DEVMETHOD(device_attach, pcib_attach), 92 DEVMETHOD(device_detach, pcib_detach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pcib_suspend), 95 DEVMETHOD(device_resume, pcib_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_child_present, pcib_child_present), 99 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 100 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 101 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 102 #ifdef NEW_PCIB 103 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 104 DEVMETHOD(bus_release_resource, pcib_release_resource), 105 #else 106 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 108 #endif 109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 111 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 112 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 113 DEVMETHOD(bus_reset_child, pcib_reset_child), 114 115 /* pcib interface */ 116 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 117 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 118 DEVMETHOD(pcib_read_config, pcib_read_config), 119 DEVMETHOD(pcib_write_config, pcib_write_config), 120 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 121 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 122 DEVMETHOD(pcib_release_msi, pcib_release_msi), 123 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 124 DEVMETHOD(pcib_release_msix, pcib_release_msix), 125 DEVMETHOD(pcib_map_msi, pcib_map_msi), 126 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 127 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 128 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 129 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 130 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 131 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 132 133 DEVMETHOD_END 134 }; 135 136 static devclass_t pcib_devclass; 137 138 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 139 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL, 140 BUS_PASS_BUS); 141 142 #if defined(NEW_PCIB) || defined(PCI_HP) 143 SYSCTL_DECL(_hw_pci); 144 #endif 145 146 #ifdef NEW_PCIB 147 static int pci_clear_pcib; 148 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 149 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 150 151 /* 152 * Get the corresponding window if this resource from a child device was 153 * sub-allocated from one of our window resource managers. 154 */ 155 static struct pcib_window * 156 pcib_get_resource_window(struct pcib_softc *sc, int type, struct resource *r) 157 { 158 switch (type) { 159 case SYS_RES_IOPORT: 160 if (rman_is_region_manager(r, &sc->io.rman)) 161 return (&sc->io); 162 break; 163 case SYS_RES_MEMORY: 164 /* Prefetchable resources may live in either memory rman. */ 165 if (rman_get_flags(r) & RF_PREFETCHABLE && 166 rman_is_region_manager(r, &sc->pmem.rman)) 167 return (&sc->pmem); 168 if (rman_is_region_manager(r, &sc->mem.rman)) 169 return (&sc->mem); 170 break; 171 } 172 return (NULL); 173 } 174 175 /* 176 * Is a resource from a child device sub-allocated from one of our 177 * resource managers? 178 */ 179 static int 180 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 181 { 182 183 #ifdef PCI_RES_BUS 184 if (type == PCI_RES_BUS) 185 return (rman_is_region_manager(r, &sc->bus.rman)); 186 #endif 187 return (pcib_get_resource_window(sc, type, r) != NULL); 188 } 189 190 static int 191 pcib_is_window_open(struct pcib_window *pw) 192 { 193 194 return (pw->valid && pw->base < pw->limit); 195 } 196 197 /* 198 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 199 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 200 * when allocating the resource windows and rely on the PCI bus driver 201 * to do this for us. 202 */ 203 static void 204 pcib_activate_window(struct pcib_softc *sc, int type) 205 { 206 207 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 208 } 209 210 static void 211 pcib_write_windows(struct pcib_softc *sc, int mask) 212 { 213 device_t dev; 214 uint32_t val; 215 216 dev = sc->dev; 217 if (sc->io.valid && mask & WIN_IO) { 218 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 219 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 220 pci_write_config(dev, PCIR_IOBASEH_1, 221 sc->io.base >> 16, 2); 222 pci_write_config(dev, PCIR_IOLIMITH_1, 223 sc->io.limit >> 16, 2); 224 } 225 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 226 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 227 } 228 229 if (mask & WIN_MEM) { 230 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 231 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 232 } 233 234 if (sc->pmem.valid && mask & WIN_PMEM) { 235 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 236 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 237 pci_write_config(dev, PCIR_PMBASEH_1, 238 sc->pmem.base >> 32, 4); 239 pci_write_config(dev, PCIR_PMLIMITH_1, 240 sc->pmem.limit >> 32, 4); 241 } 242 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 243 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 244 } 245 } 246 247 /* 248 * This is used to reject I/O port allocations that conflict with an 249 * ISA alias range. 250 */ 251 static int 252 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 253 rman_res_t count) 254 { 255 rman_res_t next_alias; 256 257 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 258 return (0); 259 260 /* Only check fixed ranges for overlap. */ 261 if (start + count - 1 != end) 262 return (0); 263 264 /* ISA aliases are only in the lower 64KB of I/O space. */ 265 if (start >= 65536) 266 return (0); 267 268 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 269 if (start < 0x100) 270 goto alias; 271 272 /* 273 * If the start address is an alias, the range is an alias. 274 * Otherwise, compute the start of the next alias range and 275 * check if it is before the end of the candidate range. 276 */ 277 if ((start & 0x300) != 0) 278 goto alias; 279 next_alias = (start & ~0x3fful) | 0x100; 280 if (next_alias <= end) 281 goto alias; 282 return (0); 283 284 alias: 285 if (bootverbose) 286 device_printf(sc->dev, 287 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 288 end); 289 return (1); 290 } 291 292 static void 293 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 294 int count) 295 { 296 struct resource **newarray; 297 int error, i; 298 299 newarray = malloc(sizeof(struct resource *) * (w->count + count), 300 M_DEVBUF, M_WAITOK); 301 if (w->res != NULL) 302 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 303 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 304 free(w->res, M_DEVBUF); 305 w->res = newarray; 306 w->count += count; 307 308 for (i = 0; i < count; i++) { 309 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 310 rman_get_end(res[i])); 311 if (error) 312 panic("Failed to add resource to rman"); 313 } 314 } 315 316 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 317 318 static void 319 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 320 void *arg) 321 { 322 rman_res_t next_end; 323 324 /* 325 * If start is within an ISA alias range, move up to the start 326 * of the next non-alias range. As a special case, addresses 327 * in the range 0x000 - 0x0ff should also be skipped since 328 * those are used for various system I/O devices in ISA 329 * systems. 330 */ 331 if (start <= 65535) { 332 if (start < 0x100 || (start & 0x300) != 0) { 333 start &= ~0x3ff; 334 start += 0x400; 335 } 336 } 337 338 /* ISA aliases are only in the lower 64KB of I/O space. */ 339 while (start <= MIN(end, 65535)) { 340 next_end = MIN(start | 0xff, end); 341 cb(start, next_end, arg); 342 start += 0x400; 343 } 344 345 if (start <= end) 346 cb(start, end, arg); 347 } 348 349 static void 350 count_ranges(rman_res_t start, rman_res_t end, void *arg) 351 { 352 int *countp; 353 354 countp = arg; 355 (*countp)++; 356 } 357 358 struct alloc_state { 359 struct resource **res; 360 struct pcib_softc *sc; 361 int count, error; 362 }; 363 364 static void 365 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 366 { 367 struct alloc_state *as; 368 struct pcib_window *w; 369 int rid; 370 371 as = arg; 372 if (as->error != 0) 373 return; 374 375 w = &as->sc->io; 376 rid = w->reg; 377 if (bootverbose) 378 device_printf(as->sc->dev, 379 "allocating non-ISA range %#jx-%#jx\n", start, end); 380 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 381 &rid, start, end, end - start + 1, 0); 382 if (as->res[as->count] == NULL) 383 as->error = ENXIO; 384 else 385 as->count++; 386 } 387 388 static int 389 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 390 { 391 struct alloc_state as; 392 int i, new_count; 393 394 /* First, see how many ranges we need. */ 395 new_count = 0; 396 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 397 398 /* Second, allocate the ranges. */ 399 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 400 M_WAITOK); 401 as.sc = sc; 402 as.count = 0; 403 as.error = 0; 404 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 405 if (as.error != 0) { 406 for (i = 0; i < as.count; i++) 407 bus_release_resource(sc->dev, SYS_RES_IOPORT, 408 sc->io.reg, as.res[i]); 409 free(as.res, M_DEVBUF); 410 return (as.error); 411 } 412 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 413 414 /* Third, add the ranges to the window. */ 415 pcib_add_window_resources(&sc->io, as.res, as.count); 416 free(as.res, M_DEVBUF); 417 return (0); 418 } 419 420 static void 421 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 422 int flags, pci_addr_t max_address) 423 { 424 struct resource *res; 425 char buf[64]; 426 int error, rid; 427 428 if (max_address != (rman_res_t)max_address) 429 max_address = ~0; 430 w->rman.rm_start = 0; 431 w->rman.rm_end = max_address; 432 w->rman.rm_type = RMAN_ARRAY; 433 snprintf(buf, sizeof(buf), "%s %s window", 434 device_get_nameunit(sc->dev), w->name); 435 w->rman.rm_descr = strdup(buf, M_DEVBUF); 436 error = rman_init(&w->rman); 437 if (error) 438 panic("Failed to initialize %s %s rman", 439 device_get_nameunit(sc->dev), w->name); 440 441 if (!pcib_is_window_open(w)) 442 return; 443 444 if (w->base > max_address || w->limit > max_address) { 445 device_printf(sc->dev, 446 "initial %s window has too many bits, ignoring\n", w->name); 447 return; 448 } 449 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 450 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 451 else { 452 rid = w->reg; 453 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 454 w->limit - w->base + 1, flags); 455 if (res != NULL) 456 pcib_add_window_resources(w, &res, 1); 457 } 458 if (w->res == NULL) { 459 device_printf(sc->dev, 460 "failed to allocate initial %s window: %#jx-%#jx\n", 461 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 462 w->base = max_address; 463 w->limit = 0; 464 pcib_write_windows(sc, w->mask); 465 return; 466 } 467 pcib_activate_window(sc, type); 468 } 469 470 /* 471 * Initialize I/O windows. 472 */ 473 static void 474 pcib_probe_windows(struct pcib_softc *sc) 475 { 476 pci_addr_t max; 477 device_t dev; 478 uint32_t val; 479 480 dev = sc->dev; 481 482 if (pci_clear_pcib) { 483 pcib_bridge_init(dev); 484 } 485 486 /* Determine if the I/O port window is implemented. */ 487 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 488 if (val == 0) { 489 /* 490 * If 'val' is zero, then only 16-bits of I/O space 491 * are supported. 492 */ 493 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 494 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 495 sc->io.valid = 1; 496 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 497 } 498 } else 499 sc->io.valid = 1; 500 501 /* Read the existing I/O port window. */ 502 if (sc->io.valid) { 503 sc->io.reg = PCIR_IOBASEL_1; 504 sc->io.step = 12; 505 sc->io.mask = WIN_IO; 506 sc->io.name = "I/O port"; 507 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 508 sc->io.base = PCI_PPBIOBASE( 509 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 510 sc->io.limit = PCI_PPBIOLIMIT( 511 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 512 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 513 max = 0xffffffff; 514 } else { 515 sc->io.base = PCI_PPBIOBASE(0, val); 516 sc->io.limit = PCI_PPBIOLIMIT(0, 517 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 518 max = 0xffff; 519 } 520 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 521 } 522 523 /* Read the existing memory window. */ 524 sc->mem.valid = 1; 525 sc->mem.reg = PCIR_MEMBASE_1; 526 sc->mem.step = 20; 527 sc->mem.mask = WIN_MEM; 528 sc->mem.name = "memory"; 529 sc->mem.base = PCI_PPBMEMBASE(0, 530 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 531 sc->mem.limit = PCI_PPBMEMLIMIT(0, 532 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 533 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 534 535 /* Determine if the prefetchable memory window is implemented. */ 536 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 537 if (val == 0) { 538 /* 539 * If 'val' is zero, then only 32-bits of memory space 540 * are supported. 541 */ 542 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 543 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 544 sc->pmem.valid = 1; 545 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 546 } 547 } else 548 sc->pmem.valid = 1; 549 550 /* Read the existing prefetchable memory window. */ 551 if (sc->pmem.valid) { 552 sc->pmem.reg = PCIR_PMBASEL_1; 553 sc->pmem.step = 20; 554 sc->pmem.mask = WIN_PMEM; 555 sc->pmem.name = "prefetch"; 556 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 557 sc->pmem.base = PCI_PPBMEMBASE( 558 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 559 sc->pmem.limit = PCI_PPBMEMLIMIT( 560 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 561 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 562 max = 0xffffffffffffffff; 563 } else { 564 sc->pmem.base = PCI_PPBMEMBASE(0, val); 565 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 566 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 567 max = 0xffffffff; 568 } 569 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 570 RF_PREFETCHABLE, max); 571 } 572 } 573 574 static void 575 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 576 { 577 device_t dev; 578 int error, i; 579 580 if (!w->valid) 581 return; 582 583 dev = sc->dev; 584 error = rman_fini(&w->rman); 585 if (error) { 586 device_printf(dev, "failed to release %s rman\n", w->name); 587 return; 588 } 589 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 590 591 for (i = 0; i < w->count; i++) { 592 error = bus_free_resource(dev, type, w->res[i]); 593 if (error) 594 device_printf(dev, 595 "failed to release %s resource: %d\n", w->name, 596 error); 597 } 598 free(w->res, M_DEVBUF); 599 } 600 601 static void 602 pcib_free_windows(struct pcib_softc *sc) 603 { 604 605 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 606 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 607 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 608 } 609 610 #ifdef PCI_RES_BUS 611 /* 612 * Allocate a suitable secondary bus for this bridge if needed and 613 * initialize the resource manager for the secondary bus range. Note 614 * that the minimum count is a desired value and this may allocate a 615 * smaller range. 616 */ 617 void 618 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 619 { 620 char buf[64]; 621 int error, rid, sec_reg; 622 623 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 624 case PCIM_HDRTYPE_BRIDGE: 625 sec_reg = PCIR_SECBUS_1; 626 bus->sub_reg = PCIR_SUBBUS_1; 627 break; 628 case PCIM_HDRTYPE_CARDBUS: 629 sec_reg = PCIR_SECBUS_2; 630 bus->sub_reg = PCIR_SUBBUS_2; 631 break; 632 default: 633 panic("not a PCI bridge"); 634 } 635 bus->sec = pci_read_config(dev, sec_reg, 1); 636 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 637 bus->dev = dev; 638 bus->rman.rm_start = 0; 639 bus->rman.rm_end = PCI_BUSMAX; 640 bus->rman.rm_type = RMAN_ARRAY; 641 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 642 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 643 error = rman_init(&bus->rman); 644 if (error) 645 panic("Failed to initialize %s bus number rman", 646 device_get_nameunit(dev)); 647 648 /* 649 * Allocate a bus range. This will return an existing bus range 650 * if one exists, or a new bus range if one does not. 651 */ 652 rid = 0; 653 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 654 min_count, 0); 655 if (bus->res == NULL) { 656 /* 657 * Fall back to just allocating a range of a single bus 658 * number. 659 */ 660 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 661 1, 0); 662 } else if (rman_get_size(bus->res) < min_count) 663 /* 664 * Attempt to grow the existing range to satisfy the 665 * minimum desired count. 666 */ 667 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 668 rman_get_start(bus->res), rman_get_start(bus->res) + 669 min_count - 1); 670 671 /* 672 * Add the initial resource to the rman. 673 */ 674 if (bus->res != NULL) { 675 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 676 rman_get_end(bus->res)); 677 if (error) 678 panic("Failed to add resource to rman"); 679 bus->sec = rman_get_start(bus->res); 680 bus->sub = rman_get_end(bus->res); 681 } 682 } 683 684 void 685 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 686 { 687 int error; 688 689 error = rman_fini(&bus->rman); 690 if (error) { 691 device_printf(dev, "failed to release bus number rman\n"); 692 return; 693 } 694 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 695 696 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 697 if (error) 698 device_printf(dev, 699 "failed to release bus numbers resource: %d\n", error); 700 } 701 702 static struct resource * 703 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 704 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 705 { 706 struct resource *res; 707 708 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 709 child); 710 if (res == NULL) 711 return (NULL); 712 713 if (bootverbose) 714 device_printf(bus->dev, 715 "allocated bus range (%ju-%ju) for rid %d of %s\n", 716 rman_get_start(res), rman_get_end(res), *rid, 717 pcib_child_name(child)); 718 rman_set_rid(res, *rid); 719 return (res); 720 } 721 722 /* 723 * Attempt to grow the secondary bus range. This is much simpler than 724 * for I/O windows as the range can only be grown by increasing 725 * subbus. 726 */ 727 static int 728 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 729 { 730 rman_res_t old_end; 731 int error; 732 733 old_end = rman_get_end(bus->res); 734 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 735 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 736 rman_get_start(bus->res), new_end); 737 if (error) 738 return (error); 739 if (bootverbose) 740 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 741 rman_get_start(bus->res), rman_get_end(bus->res)); 742 error = rman_manage_region(&bus->rman, old_end + 1, 743 rman_get_end(bus->res)); 744 if (error) 745 panic("Failed to add resource to rman"); 746 bus->sub = rman_get_end(bus->res); 747 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 748 return (0); 749 } 750 751 struct resource * 752 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 753 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 754 { 755 struct resource *res; 756 rman_res_t start_free, end_free, new_end; 757 758 /* 759 * First, see if the request can be satisified by the existing 760 * bus range. 761 */ 762 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 763 if (res != NULL) 764 return (res); 765 766 /* 767 * Figure out a range to grow the bus range. First, find the 768 * first bus number after the last allocated bus in the rman and 769 * enforce that as a minimum starting point for the range. 770 */ 771 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 772 end_free != bus->sub) 773 start_free = bus->sub + 1; 774 if (start_free < start) 775 start_free = start; 776 new_end = start_free + count - 1; 777 778 /* 779 * See if this new range would satisfy the request if it 780 * succeeds. 781 */ 782 if (new_end > end) 783 return (NULL); 784 785 /* Finally, attempt to grow the existing resource. */ 786 if (bootverbose) { 787 device_printf(bus->dev, 788 "attempting to grow bus range for %ju buses\n", count); 789 printf("\tback candidate range: %ju-%ju\n", start_free, 790 new_end); 791 } 792 if (pcib_grow_subbus(bus, new_end) == 0) 793 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 794 flags)); 795 return (NULL); 796 } 797 #endif 798 799 #else 800 801 /* 802 * Is the prefetch window open (eg, can we allocate memory in it?) 803 */ 804 static int 805 pcib_is_prefetch_open(struct pcib_softc *sc) 806 { 807 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 808 } 809 810 /* 811 * Is the nonprefetch window open (eg, can we allocate memory in it?) 812 */ 813 static int 814 pcib_is_nonprefetch_open(struct pcib_softc *sc) 815 { 816 return (sc->membase > 0 && sc->membase < sc->memlimit); 817 } 818 819 /* 820 * Is the io window open (eg, can we allocate ports in it?) 821 */ 822 static int 823 pcib_is_io_open(struct pcib_softc *sc) 824 { 825 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 826 } 827 828 /* 829 * Get current I/O decode. 830 */ 831 static void 832 pcib_get_io_decode(struct pcib_softc *sc) 833 { 834 device_t dev; 835 uint32_t iolow; 836 837 dev = sc->dev; 838 839 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 840 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 841 sc->iobase = PCI_PPBIOBASE( 842 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 843 else 844 sc->iobase = PCI_PPBIOBASE(0, iolow); 845 846 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 847 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 848 sc->iolimit = PCI_PPBIOLIMIT( 849 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 850 else 851 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 852 } 853 854 /* 855 * Get current memory decode. 856 */ 857 static void 858 pcib_get_mem_decode(struct pcib_softc *sc) 859 { 860 device_t dev; 861 pci_addr_t pmemlow; 862 863 dev = sc->dev; 864 865 sc->membase = PCI_PPBMEMBASE(0, 866 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 867 sc->memlimit = PCI_PPBMEMLIMIT(0, 868 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 869 870 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 871 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 872 sc->pmembase = PCI_PPBMEMBASE( 873 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 874 else 875 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 876 877 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 878 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 879 sc->pmemlimit = PCI_PPBMEMLIMIT( 880 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 881 else 882 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 883 } 884 885 /* 886 * Restore previous I/O decode. 887 */ 888 static void 889 pcib_set_io_decode(struct pcib_softc *sc) 890 { 891 device_t dev; 892 uint32_t iohi; 893 894 dev = sc->dev; 895 896 iohi = sc->iobase >> 16; 897 if (iohi > 0) 898 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 899 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 900 901 iohi = sc->iolimit >> 16; 902 if (iohi > 0) 903 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 904 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 905 } 906 907 /* 908 * Restore previous memory decode. 909 */ 910 static void 911 pcib_set_mem_decode(struct pcib_softc *sc) 912 { 913 device_t dev; 914 pci_addr_t pmemhi; 915 916 dev = sc->dev; 917 918 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 919 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 920 921 pmemhi = sc->pmembase >> 32; 922 if (pmemhi > 0) 923 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 924 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 925 926 pmemhi = sc->pmemlimit >> 32; 927 if (pmemhi > 0) 928 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 929 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 930 } 931 #endif 932 933 #ifdef PCI_HP 934 /* 935 * PCI-express HotPlug support. 936 */ 937 static int pci_enable_pcie_hp = 1; 938 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 939 &pci_enable_pcie_hp, 0, 940 "Enable support for native PCI-express HotPlug."); 941 942 TASKQUEUE_DEFINE_THREAD(pci_hp); 943 944 static void 945 pcib_probe_hotplug(struct pcib_softc *sc) 946 { 947 device_t dev; 948 uint32_t link_cap; 949 uint16_t link_sta, slot_sta; 950 951 if (!pci_enable_pcie_hp) 952 return; 953 954 dev = sc->dev; 955 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 956 return; 957 958 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 959 return; 960 961 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 962 963 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 964 return; 965 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 966 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 967 return; 968 969 /* 970 * Some devices report that they have an MRL when they actually 971 * do not. Since they always report that the MRL is open, child 972 * devices would be ignored. Try to detect these devices and 973 * ignore their claim of HotPlug support. 974 * 975 * If there is an open MRL but the Data Link Layer is active, 976 * the MRL is not real. 977 */ 978 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 979 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 980 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 981 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 982 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 983 return; 984 } 985 } 986 987 /* 988 * Now that we're sure we want to do hot plug, ask the 989 * firmware, if any, if that's OK. 990 */ 991 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 992 if (bootverbose) 993 device_printf(dev, "Unable to activate hot plug feature.\n"); 994 return; 995 } 996 997 sc->flags |= PCIB_HOTPLUG; 998 } 999 1000 /* 1001 * Send a HotPlug command to the slot control register. If this slot 1002 * uses command completion interrupts and a previous command is still 1003 * in progress, then the command is dropped. Once the previous 1004 * command completes or times out, pcib_pcie_hotplug_update() will be 1005 * invoked to post a new command based on the slot's state at that 1006 * time. 1007 */ 1008 static void 1009 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 1010 { 1011 device_t dev; 1012 uint16_t ctl, new; 1013 1014 dev = sc->dev; 1015 1016 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 1017 return; 1018 1019 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 1020 new = (ctl & ~mask) | val; 1021 if (new == ctl) 1022 return; 1023 if (bootverbose) 1024 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 1025 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 1026 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 1027 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 1028 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 1029 if (!cold) 1030 callout_reset(&sc->pcie_cc_timer, hz, 1031 pcib_pcie_cc_timeout, sc); 1032 } 1033 } 1034 1035 static void 1036 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 1037 { 1038 device_t dev; 1039 1040 dev = sc->dev; 1041 1042 if (bootverbose) 1043 device_printf(dev, "Command Completed\n"); 1044 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 1045 return; 1046 callout_stop(&sc->pcie_cc_timer); 1047 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1048 wakeup(sc); 1049 } 1050 1051 /* 1052 * Returns true if a card is fully inserted from the user's 1053 * perspective. It may not yet be ready for access, but the driver 1054 * can now start enabling access if necessary. 1055 */ 1056 static bool 1057 pcib_hotplug_inserted(struct pcib_softc *sc) 1058 { 1059 1060 /* Pretend the card isn't present if a detach is forced. */ 1061 if (sc->flags & PCIB_DETACHING) 1062 return (false); 1063 1064 /* Card must be present in the slot. */ 1065 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1066 return (false); 1067 1068 /* A power fault implicitly turns off power to the slot. */ 1069 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1070 return (false); 1071 1072 /* If the MRL is disengaged, the slot is powered off. */ 1073 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1074 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1075 return (false); 1076 1077 return (true); 1078 } 1079 1080 /* 1081 * Returns -1 if the card is fully inserted, powered, and ready for 1082 * access. Otherwise, returns 0. 1083 */ 1084 static int 1085 pcib_hotplug_present(struct pcib_softc *sc) 1086 { 1087 1088 /* Card must be inserted. */ 1089 if (!pcib_hotplug_inserted(sc)) 1090 return (0); 1091 1092 /* Require the Data Link Layer to be active. */ 1093 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1094 return (0); 1095 1096 return (-1); 1097 } 1098 1099 static void 1100 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1101 bool schedule_task) 1102 { 1103 bool card_inserted, ei_engaged; 1104 1105 /* Clear DETACHING if Presence Detect has cleared. */ 1106 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1107 PCIEM_SLOT_STA_PDC) 1108 sc->flags &= ~PCIB_DETACHING; 1109 1110 card_inserted = pcib_hotplug_inserted(sc); 1111 1112 /* Turn the power indicator on if a card is inserted. */ 1113 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1114 mask |= PCIEM_SLOT_CTL_PIC; 1115 if (card_inserted) 1116 val |= PCIEM_SLOT_CTL_PI_ON; 1117 else if (sc->flags & PCIB_DETACH_PENDING) 1118 val |= PCIEM_SLOT_CTL_PI_BLINK; 1119 else 1120 val |= PCIEM_SLOT_CTL_PI_OFF; 1121 } 1122 1123 /* Turn the power on via the Power Controller if a card is inserted. */ 1124 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1125 mask |= PCIEM_SLOT_CTL_PCC; 1126 if (card_inserted) 1127 val |= PCIEM_SLOT_CTL_PC_ON; 1128 else 1129 val |= PCIEM_SLOT_CTL_PC_OFF; 1130 } 1131 1132 /* 1133 * If a card is inserted, enable the Electromechanical 1134 * Interlock. If a card is not inserted (or we are in the 1135 * process of detaching), disable the Electromechanical 1136 * Interlock. 1137 */ 1138 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { 1139 mask |= PCIEM_SLOT_CTL_EIC; 1140 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1141 if (card_inserted != ei_engaged) 1142 val |= PCIEM_SLOT_CTL_EIC; 1143 } 1144 1145 /* 1146 * Start a timer to see if the Data Link Layer times out. 1147 * Note that we only start the timer if Presence Detect or MRL Sensor 1148 * changed on this interrupt. Stop any scheduled timer if 1149 * the Data Link Layer is active. 1150 */ 1151 if (card_inserted && 1152 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1153 sc->pcie_slot_sta & 1154 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1155 if (cold) 1156 device_printf(sc->dev, 1157 "Data Link Layer inactive\n"); 1158 else 1159 callout_reset(&sc->pcie_dll_timer, hz, 1160 pcib_pcie_dll_timeout, sc); 1161 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1162 callout_stop(&sc->pcie_dll_timer); 1163 1164 pcib_pcie_hotplug_command(sc, val, mask); 1165 1166 /* 1167 * During attach the child "pci" device is added synchronously; 1168 * otherwise, the task is scheduled to manage the child 1169 * device. 1170 */ 1171 if (schedule_task && 1172 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1173 taskqueue_enqueue(taskqueue_pci_hp, &sc->pcie_hp_task); 1174 } 1175 1176 static void 1177 pcib_pcie_intr_hotplug(void *arg) 1178 { 1179 struct pcib_softc *sc; 1180 device_t dev; 1181 uint16_t old_slot_sta; 1182 1183 sc = arg; 1184 dev = sc->dev; 1185 PCIB_HP_LOCK(sc); 1186 old_slot_sta = sc->pcie_slot_sta; 1187 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1188 1189 /* Clear the events just reported. */ 1190 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1191 1192 if (bootverbose) 1193 device_printf(dev, "HotPlug interrupt: %#x\n", 1194 sc->pcie_slot_sta); 1195 1196 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1197 if (sc->flags & PCIB_DETACH_PENDING) { 1198 device_printf(dev, 1199 "Attention Button Pressed: Detach Cancelled\n"); 1200 sc->flags &= ~PCIB_DETACH_PENDING; 1201 callout_stop(&sc->pcie_ab_timer); 1202 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) { 1203 /* Only initiate detach sequence if device present. */ 1204 device_printf(dev, 1205 "Attention Button Pressed: Detaching in 5 seconds\n"); 1206 sc->flags |= PCIB_DETACH_PENDING; 1207 callout_reset(&sc->pcie_ab_timer, 5 * hz, 1208 pcib_pcie_ab_timeout, sc); 1209 } 1210 } 1211 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1212 device_printf(dev, "Power Fault Detected\n"); 1213 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1214 device_printf(dev, "MRL Sensor Changed to %s\n", 1215 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1216 "closed"); 1217 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1218 device_printf(dev, "Presence Detect Changed to %s\n", 1219 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1220 "empty"); 1221 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1222 pcib_pcie_hotplug_command_completed(sc); 1223 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1224 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1225 if (bootverbose) 1226 device_printf(dev, 1227 "Data Link Layer State Changed to %s\n", 1228 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1229 "active" : "inactive"); 1230 } 1231 1232 pcib_pcie_hotplug_update(sc, 0, 0, true); 1233 PCIB_HP_UNLOCK(sc); 1234 } 1235 1236 static void 1237 pcib_pcie_hotplug_task(void *context, int pending) 1238 { 1239 struct pcib_softc *sc; 1240 device_t dev; 1241 1242 sc = context; 1243 PCIB_HP_LOCK(sc); 1244 dev = sc->dev; 1245 if (pcib_hotplug_present(sc) != 0) { 1246 if (sc->child == NULL) { 1247 sc->child = device_add_child(dev, "pci", -1); 1248 bus_generic_attach(dev); 1249 } 1250 } else { 1251 if (sc->child != NULL) { 1252 if (device_delete_child(dev, sc->child) == 0) 1253 sc->child = NULL; 1254 } 1255 } 1256 PCIB_HP_UNLOCK(sc); 1257 } 1258 1259 static void 1260 pcib_pcie_ab_timeout(void *arg) 1261 { 1262 struct pcib_softc *sc; 1263 1264 sc = arg; 1265 PCIB_HP_LOCK_ASSERT(sc); 1266 if (sc->flags & PCIB_DETACH_PENDING) { 1267 sc->flags |= PCIB_DETACHING; 1268 sc->flags &= ~PCIB_DETACH_PENDING; 1269 pcib_pcie_hotplug_update(sc, 0, 0, true); 1270 } 1271 } 1272 1273 static void 1274 pcib_pcie_cc_timeout(void *arg) 1275 { 1276 struct pcib_softc *sc; 1277 device_t dev; 1278 uint16_t sta; 1279 1280 sc = arg; 1281 dev = sc->dev; 1282 PCIB_HP_LOCK_ASSERT(sc); 1283 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1284 if (!(sta & PCIEM_SLOT_STA_CC)) { 1285 device_printf(dev, "HotPlug Command Timed Out\n"); 1286 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1287 } else { 1288 device_printf(dev, 1289 "Missed HotPlug interrupt waiting for Command Completion\n"); 1290 pcib_pcie_intr_hotplug(sc); 1291 } 1292 } 1293 1294 static void 1295 pcib_pcie_dll_timeout(void *arg) 1296 { 1297 struct pcib_softc *sc; 1298 device_t dev; 1299 uint16_t sta; 1300 1301 sc = arg; 1302 dev = sc->dev; 1303 PCIB_HP_LOCK_ASSERT(sc); 1304 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1305 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1306 device_printf(dev, 1307 "Timed out waiting for Data Link Layer Active\n"); 1308 sc->flags |= PCIB_DETACHING; 1309 pcib_pcie_hotplug_update(sc, 0, 0, true); 1310 } else if (sta != sc->pcie_link_sta) { 1311 device_printf(dev, 1312 "Missed HotPlug interrupt waiting for DLL Active\n"); 1313 pcib_pcie_intr_hotplug(sc); 1314 } 1315 } 1316 1317 static int 1318 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1319 { 1320 device_t dev; 1321 int count, error, rid; 1322 1323 rid = -1; 1324 dev = sc->dev; 1325 1326 /* 1327 * For simplicity, only use MSI-X if there is a single message. 1328 * To support a device with multiple messages we would have to 1329 * use remap intr if the MSI number is not 0. 1330 */ 1331 count = pci_msix_count(dev); 1332 if (count == 1) { 1333 error = pci_alloc_msix(dev, &count); 1334 if (error == 0) 1335 rid = 1; 1336 } 1337 1338 if (rid < 0 && pci_msi_count(dev) > 0) { 1339 count = 1; 1340 error = pci_alloc_msi(dev, &count); 1341 if (error == 0) 1342 rid = 1; 1343 } 1344 1345 if (rid < 0) 1346 rid = 0; 1347 1348 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1349 RF_ACTIVE | RF_SHAREABLE); 1350 if (sc->pcie_irq == NULL) { 1351 device_printf(dev, 1352 "Failed to allocate interrupt for PCI-e events\n"); 1353 if (rid > 0) 1354 pci_release_msi(dev); 1355 return (ENXIO); 1356 } 1357 1358 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE, 1359 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1360 if (error) { 1361 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1362 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1363 if (rid > 0) 1364 pci_release_msi(dev); 1365 return (error); 1366 } 1367 return (0); 1368 } 1369 1370 static int 1371 pcib_release_pcie_irq(struct pcib_softc *sc) 1372 { 1373 device_t dev; 1374 int error; 1375 1376 dev = sc->dev; 1377 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1378 if (error) 1379 return (error); 1380 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1381 if (error) 1382 return (error); 1383 return (pci_release_msi(dev)); 1384 } 1385 1386 static void 1387 pcib_setup_hotplug(struct pcib_softc *sc) 1388 { 1389 device_t dev; 1390 uint16_t mask, val; 1391 1392 dev = sc->dev; 1393 callout_init(&sc->pcie_ab_timer, 0); 1394 callout_init(&sc->pcie_cc_timer, 0); 1395 callout_init(&sc->pcie_dll_timer, 0); 1396 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1397 sc->pcie_hp_lock = &Giant; 1398 1399 /* Allocate IRQ. */ 1400 if (pcib_alloc_pcie_irq(sc) != 0) 1401 return; 1402 1403 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1404 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1405 1406 /* Clear any events previously pending. */ 1407 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1408 1409 /* Enable HotPlug events. */ 1410 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1411 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1412 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1413 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1414 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1415 val |= PCIEM_SLOT_CTL_ABPE; 1416 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1417 val |= PCIEM_SLOT_CTL_PFDE; 1418 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1419 val |= PCIEM_SLOT_CTL_MRLSCE; 1420 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1421 val |= PCIEM_SLOT_CTL_CCIE; 1422 1423 /* Turn the attention indicator off. */ 1424 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1425 mask |= PCIEM_SLOT_CTL_AIC; 1426 val |= PCIEM_SLOT_CTL_AI_OFF; 1427 } 1428 1429 pcib_pcie_hotplug_update(sc, val, mask, false); 1430 } 1431 1432 static int 1433 pcib_detach_hotplug(struct pcib_softc *sc) 1434 { 1435 uint16_t mask, val; 1436 int error; 1437 1438 /* Disable the card in the slot and force it to detach. */ 1439 if (sc->flags & PCIB_DETACH_PENDING) { 1440 sc->flags &= ~PCIB_DETACH_PENDING; 1441 callout_stop(&sc->pcie_ab_timer); 1442 } 1443 sc->flags |= PCIB_DETACHING; 1444 1445 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1446 callout_stop(&sc->pcie_cc_timer); 1447 tsleep(sc, 0, "hpcmd", hz); 1448 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1449 } 1450 1451 /* Disable HotPlug events. */ 1452 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1453 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1454 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1455 val = 0; 1456 1457 /* Turn the attention indicator off. */ 1458 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1459 mask |= PCIEM_SLOT_CTL_AIC; 1460 val |= PCIEM_SLOT_CTL_AI_OFF; 1461 } 1462 1463 pcib_pcie_hotplug_update(sc, val, mask, false); 1464 1465 error = pcib_release_pcie_irq(sc); 1466 if (error) 1467 return (error); 1468 taskqueue_drain(taskqueue_pci_hp, &sc->pcie_hp_task); 1469 callout_drain(&sc->pcie_ab_timer); 1470 callout_drain(&sc->pcie_cc_timer); 1471 callout_drain(&sc->pcie_dll_timer); 1472 return (0); 1473 } 1474 #endif 1475 1476 /* 1477 * Get current bridge configuration. 1478 */ 1479 static void 1480 pcib_cfg_save(struct pcib_softc *sc) 1481 { 1482 #ifndef NEW_PCIB 1483 device_t dev; 1484 uint16_t command; 1485 1486 dev = sc->dev; 1487 1488 command = pci_read_config(dev, PCIR_COMMAND, 2); 1489 if (command & PCIM_CMD_PORTEN) 1490 pcib_get_io_decode(sc); 1491 if (command & PCIM_CMD_MEMEN) 1492 pcib_get_mem_decode(sc); 1493 #endif 1494 } 1495 1496 /* 1497 * Restore previous bridge configuration. 1498 */ 1499 static void 1500 pcib_cfg_restore(struct pcib_softc *sc) 1501 { 1502 #ifndef NEW_PCIB 1503 uint16_t command; 1504 #endif 1505 1506 #ifdef NEW_PCIB 1507 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1508 #else 1509 command = pci_read_config(sc->dev, PCIR_COMMAND, 2); 1510 if (command & PCIM_CMD_PORTEN) 1511 pcib_set_io_decode(sc); 1512 if (command & PCIM_CMD_MEMEN) 1513 pcib_set_mem_decode(sc); 1514 #endif 1515 } 1516 1517 /* 1518 * Generic device interface 1519 */ 1520 static int 1521 pcib_probe(device_t dev) 1522 { 1523 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1524 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1525 device_set_desc(dev, "PCI-PCI bridge"); 1526 return(-10000); 1527 } 1528 return(ENXIO); 1529 } 1530 1531 void 1532 pcib_attach_common(device_t dev) 1533 { 1534 struct pcib_softc *sc; 1535 struct sysctl_ctx_list *sctx; 1536 struct sysctl_oid *soid; 1537 int comma; 1538 1539 sc = device_get_softc(dev); 1540 sc->dev = dev; 1541 1542 /* 1543 * Get current bridge configuration. 1544 */ 1545 sc->domain = pci_get_domain(dev); 1546 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1547 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1548 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1549 #endif 1550 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1551 pcib_cfg_save(sc); 1552 1553 /* 1554 * The primary bus register should always be the bus of the 1555 * parent. 1556 */ 1557 sc->pribus = pci_get_bus(dev); 1558 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1559 1560 /* 1561 * Setup sysctl reporting nodes 1562 */ 1563 sctx = device_get_sysctl_ctx(dev); 1564 soid = device_get_sysctl_tree(dev); 1565 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1566 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1567 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1568 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1569 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1570 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1571 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1572 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1573 1574 /* 1575 * Quirk handling. 1576 */ 1577 switch (pci_get_devid(dev)) { 1578 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1579 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1580 { 1581 uint8_t supbus; 1582 1583 supbus = pci_read_config(dev, 0x41, 1); 1584 if (supbus != 0xff) { 1585 sc->bus.sec = supbus + 1; 1586 sc->bus.sub = supbus + 1; 1587 } 1588 break; 1589 } 1590 #endif 1591 1592 /* 1593 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1594 * and it is a subtractive bridge. However, the ProgIf is wrong 1595 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1596 * happen. There are also Toshiba and Cavium ThunderX bridges 1597 * that behave this way. 1598 */ 1599 case 0xa002177d: /* Cavium ThunderX */ 1600 case 0x124b8086: /* Intel 82380FB Mobile */ 1601 case 0x060513d7: /* Toshiba ???? */ 1602 sc->flags |= PCIB_SUBTRACTIVE; 1603 break; 1604 1605 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1606 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1607 case 0x00dd10de: 1608 { 1609 char *cp; 1610 1611 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1612 break; 1613 if (strncmp(cp, "Compal", 6) != 0) { 1614 freeenv(cp); 1615 break; 1616 } 1617 freeenv(cp); 1618 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1619 break; 1620 if (strncmp(cp, "08A0", 4) != 0) { 1621 freeenv(cp); 1622 break; 1623 } 1624 freeenv(cp); 1625 if (sc->bus.sub < 0xa) { 1626 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1627 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1628 } 1629 break; 1630 } 1631 #endif 1632 } 1633 1634 if (pci_msi_device_blacklisted(dev)) 1635 sc->flags |= PCIB_DISABLE_MSI; 1636 1637 if (pci_msix_device_blacklisted(dev)) 1638 sc->flags |= PCIB_DISABLE_MSIX; 1639 1640 /* 1641 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1642 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1643 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1644 * This means they act as if they were subtractively decoding 1645 * bridges and pass all transactions. Mark them and real ProgIf 1 1646 * parts as subtractive. 1647 */ 1648 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1649 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1650 sc->flags |= PCIB_SUBTRACTIVE; 1651 1652 #ifdef PCI_HP 1653 pcib_probe_hotplug(sc); 1654 #endif 1655 #ifdef NEW_PCIB 1656 #ifdef PCI_RES_BUS 1657 pcib_setup_secbus(dev, &sc->bus, 1); 1658 #endif 1659 pcib_probe_windows(sc); 1660 #endif 1661 #ifdef PCI_HP 1662 if (sc->flags & PCIB_HOTPLUG) 1663 pcib_setup_hotplug(sc); 1664 #endif 1665 if (bootverbose) { 1666 device_printf(dev, " domain %d\n", sc->domain); 1667 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1668 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1669 #ifdef NEW_PCIB 1670 if (pcib_is_window_open(&sc->io)) 1671 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1672 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1673 if (pcib_is_window_open(&sc->mem)) 1674 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1675 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1676 if (pcib_is_window_open(&sc->pmem)) 1677 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1678 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1679 #else 1680 if (pcib_is_io_open(sc)) 1681 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1682 sc->iobase, sc->iolimit); 1683 if (pcib_is_nonprefetch_open(sc)) 1684 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1685 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1686 if (pcib_is_prefetch_open(sc)) 1687 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1688 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1689 #endif 1690 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1691 sc->flags & PCIB_SUBTRACTIVE) { 1692 device_printf(dev, " special decode "); 1693 comma = 0; 1694 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1695 printf("ISA"); 1696 comma = 1; 1697 } 1698 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1699 printf("%sVGA", comma ? ", " : ""); 1700 comma = 1; 1701 } 1702 if (sc->flags & PCIB_SUBTRACTIVE) 1703 printf("%ssubtractive", comma ? ", " : ""); 1704 printf("\n"); 1705 } 1706 } 1707 1708 /* 1709 * Always enable busmastering on bridges so that transactions 1710 * initiated on the secondary bus are passed through to the 1711 * primary bus. 1712 */ 1713 pci_enable_busmaster(dev); 1714 } 1715 1716 #ifdef PCI_HP 1717 static int 1718 pcib_present(struct pcib_softc *sc) 1719 { 1720 1721 if (sc->flags & PCIB_HOTPLUG) 1722 return (pcib_hotplug_present(sc) != 0); 1723 return (1); 1724 } 1725 #endif 1726 1727 int 1728 pcib_attach_child(device_t dev) 1729 { 1730 struct pcib_softc *sc; 1731 1732 sc = device_get_softc(dev); 1733 if (sc->bus.sec == 0) { 1734 /* no secondary bus; we should have fixed this */ 1735 return(0); 1736 } 1737 1738 #ifdef PCI_HP 1739 if (!pcib_present(sc)) { 1740 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1741 return (0); 1742 } 1743 #endif 1744 1745 sc->child = device_add_child(dev, "pci", -1); 1746 return (bus_generic_attach(dev)); 1747 } 1748 1749 int 1750 pcib_attach(device_t dev) 1751 { 1752 1753 pcib_attach_common(dev); 1754 return (pcib_attach_child(dev)); 1755 } 1756 1757 int 1758 pcib_detach(device_t dev) 1759 { 1760 #if defined(PCI_HP) || defined(NEW_PCIB) 1761 struct pcib_softc *sc; 1762 #endif 1763 int error; 1764 1765 #if defined(PCI_HP) || defined(NEW_PCIB) 1766 sc = device_get_softc(dev); 1767 #endif 1768 error = bus_generic_detach(dev); 1769 if (error) 1770 return (error); 1771 #ifdef PCI_HP 1772 if (sc->flags & PCIB_HOTPLUG) { 1773 error = pcib_detach_hotplug(sc); 1774 if (error) 1775 return (error); 1776 } 1777 #endif 1778 error = device_delete_children(dev); 1779 if (error) 1780 return (error); 1781 #ifdef NEW_PCIB 1782 pcib_free_windows(sc); 1783 #ifdef PCI_RES_BUS 1784 pcib_free_secbus(dev, &sc->bus); 1785 #endif 1786 #endif 1787 return (0); 1788 } 1789 1790 int 1791 pcib_suspend(device_t dev) 1792 { 1793 1794 pcib_cfg_save(device_get_softc(dev)); 1795 return (bus_generic_suspend(dev)); 1796 } 1797 1798 int 1799 pcib_resume(device_t dev) 1800 { 1801 1802 pcib_cfg_restore(device_get_softc(dev)); 1803 1804 /* 1805 * Restore the Command register only after restoring the windows. 1806 * The bridge should not be claiming random windows. 1807 */ 1808 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2); 1809 return (bus_generic_resume(dev)); 1810 } 1811 1812 void 1813 pcib_bridge_init(device_t dev) 1814 { 1815 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1816 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1817 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1818 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1819 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1820 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1821 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1822 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1823 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1824 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1825 } 1826 1827 int 1828 pcib_child_present(device_t dev, device_t child) 1829 { 1830 #ifdef PCI_HP 1831 struct pcib_softc *sc = device_get_softc(dev); 1832 int retval; 1833 1834 retval = bus_child_present(dev); 1835 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1836 retval = pcib_hotplug_present(sc); 1837 return (retval); 1838 #else 1839 return (bus_child_present(dev)); 1840 #endif 1841 } 1842 1843 int 1844 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1845 { 1846 struct pcib_softc *sc = device_get_softc(dev); 1847 1848 switch (which) { 1849 case PCIB_IVAR_DOMAIN: 1850 *result = sc->domain; 1851 return(0); 1852 case PCIB_IVAR_BUS: 1853 *result = sc->bus.sec; 1854 return(0); 1855 } 1856 return(ENOENT); 1857 } 1858 1859 int 1860 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1861 { 1862 1863 switch (which) { 1864 case PCIB_IVAR_DOMAIN: 1865 return(EINVAL); 1866 case PCIB_IVAR_BUS: 1867 return(EINVAL); 1868 } 1869 return(ENOENT); 1870 } 1871 1872 #ifdef NEW_PCIB 1873 /* 1874 * Attempt to allocate a resource from the existing resources assigned 1875 * to a window. 1876 */ 1877 static struct resource * 1878 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1879 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1880 rman_res_t count, u_int flags) 1881 { 1882 struct resource *res; 1883 1884 if (!pcib_is_window_open(w)) 1885 return (NULL); 1886 1887 res = rman_reserve_resource(&w->rman, start, end, count, 1888 flags & ~RF_ACTIVE, child); 1889 if (res == NULL) 1890 return (NULL); 1891 1892 if (bootverbose) 1893 device_printf(sc->dev, 1894 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1895 w->name, rman_get_start(res), rman_get_end(res), *rid, 1896 pcib_child_name(child)); 1897 rman_set_rid(res, *rid); 1898 1899 /* 1900 * If the resource should be active, pass that request up the 1901 * tree. This assumes the parent drivers can handle 1902 * activating sub-allocated resources. 1903 */ 1904 if (flags & RF_ACTIVE) { 1905 if (bus_activate_resource(child, type, *rid, res) != 0) { 1906 rman_release_resource(res); 1907 return (NULL); 1908 } 1909 } 1910 1911 return (res); 1912 } 1913 1914 /* Allocate a fresh resource range for an unconfigured window. */ 1915 static int 1916 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1917 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1918 { 1919 struct resource *res; 1920 rman_res_t base, limit, wmask; 1921 int rid; 1922 1923 /* 1924 * If this is an I/O window on a bridge with ISA enable set 1925 * and the start address is below 64k, then try to allocate an 1926 * initial window of 0x1000 bytes long starting at address 1927 * 0xf000 and walking down. Note that if the original request 1928 * was larger than the non-aliased range size of 0x100 our 1929 * caller would have raised the start address up to 64k 1930 * already. 1931 */ 1932 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1933 start < 65536) { 1934 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1935 limit = base + 0xfff; 1936 1937 /* 1938 * Skip ranges that wouldn't work for the 1939 * original request. Note that the actual 1940 * window that overlaps are the non-alias 1941 * ranges within [base, limit], so this isn't 1942 * quite a simple comparison. 1943 */ 1944 if (start + count > limit - 0x400) 1945 continue; 1946 if (base == 0) { 1947 /* 1948 * The first open region for the window at 1949 * 0 is 0x400-0x4ff. 1950 */ 1951 if (end - count + 1 < 0x400) 1952 continue; 1953 } else { 1954 if (end - count + 1 < base) 1955 continue; 1956 } 1957 1958 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1959 w->base = base; 1960 w->limit = limit; 1961 return (0); 1962 } 1963 } 1964 return (ENOSPC); 1965 } 1966 1967 wmask = ((rman_res_t)1 << w->step) - 1; 1968 if (RF_ALIGNMENT(flags) < w->step) { 1969 flags &= ~RF_ALIGNMENT_MASK; 1970 flags |= RF_ALIGNMENT_LOG2(w->step); 1971 } 1972 start &= ~wmask; 1973 end |= wmask; 1974 count = roundup2(count, (rman_res_t)1 << w->step); 1975 rid = w->reg; 1976 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1977 flags & ~RF_ACTIVE); 1978 if (res == NULL) 1979 return (ENOSPC); 1980 pcib_add_window_resources(w, &res, 1); 1981 pcib_activate_window(sc, type); 1982 w->base = rman_get_start(res); 1983 w->limit = rman_get_end(res); 1984 return (0); 1985 } 1986 1987 /* Try to expand an existing window to the requested base and limit. */ 1988 static int 1989 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1990 rman_res_t base, rman_res_t limit) 1991 { 1992 struct resource *res; 1993 int error, i, force_64k_base; 1994 1995 KASSERT(base <= w->base && limit >= w->limit, 1996 ("attempting to shrink window")); 1997 1998 /* 1999 * XXX: pcib_grow_window() doesn't try to do this anyway and 2000 * the error handling for all the edge cases would be tedious. 2001 */ 2002 KASSERT(limit == w->limit || base == w->base, 2003 ("attempting to grow both ends of a window")); 2004 2005 /* 2006 * Yet more special handling for requests to expand an I/O 2007 * window behind an ISA-enabled bridge. Since I/O windows 2008 * have to grow in 0x1000 increments and the end of the 0xffff 2009 * range is an alias, growing a window below 64k will always 2010 * result in allocating new resources and never adjusting an 2011 * existing resource. 2012 */ 2013 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2014 (limit <= 65535 || (base <= 65535 && base != w->base))) { 2015 KASSERT(limit == w->limit || limit <= 65535, 2016 ("attempting to grow both ends across 64k ISA alias")); 2017 2018 if (base != w->base) 2019 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 2020 else 2021 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 2022 limit); 2023 if (error == 0) { 2024 w->base = base; 2025 w->limit = limit; 2026 } 2027 return (error); 2028 } 2029 2030 /* 2031 * Find the existing resource to adjust. Usually there is only one, 2032 * but for an ISA-enabled bridge we might be growing the I/O window 2033 * above 64k and need to find the existing resource that maps all 2034 * of the area above 64k. 2035 */ 2036 for (i = 0; i < w->count; i++) { 2037 if (rman_get_end(w->res[i]) == w->limit) 2038 break; 2039 } 2040 KASSERT(i != w->count, ("did not find existing resource")); 2041 res = w->res[i]; 2042 2043 /* 2044 * Usually the resource we found should match the window's 2045 * existing range. The one exception is the ISA-enabled case 2046 * mentioned above in which case the resource should start at 2047 * 64k. 2048 */ 2049 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2050 w->base <= 65535) { 2051 KASSERT(rman_get_start(res) == 65536, 2052 ("existing resource mismatch")); 2053 force_64k_base = 1; 2054 } else { 2055 KASSERT(w->base == rman_get_start(res), 2056 ("existing resource mismatch")); 2057 force_64k_base = 0; 2058 } 2059 2060 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2061 rman_get_start(res) : base, limit); 2062 if (error) 2063 return (error); 2064 2065 /* Add the newly allocated region to the resource manager. */ 2066 if (w->base != base) { 2067 error = rman_manage_region(&w->rman, base, w->base - 1); 2068 w->base = base; 2069 } else { 2070 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2071 w->limit = limit; 2072 } 2073 if (error) { 2074 if (bootverbose) 2075 device_printf(sc->dev, 2076 "failed to expand %s resource manager\n", w->name); 2077 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2078 rman_get_start(res) : w->base, w->limit); 2079 } 2080 return (error); 2081 } 2082 2083 /* 2084 * Attempt to grow a window to make room for a given resource request. 2085 */ 2086 static int 2087 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2088 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2089 { 2090 rman_res_t align, start_free, end_free, front, back, wmask; 2091 int error; 2092 2093 /* 2094 * Clamp the desired resource range to the maximum address 2095 * this window supports. Reject impossible requests. 2096 * 2097 * For I/O port requests behind a bridge with the ISA enable 2098 * bit set, force large allocations to start above 64k. 2099 */ 2100 if (!w->valid) 2101 return (EINVAL); 2102 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2103 start < 65536) 2104 start = 65536; 2105 if (end > w->rman.rm_end) 2106 end = w->rman.rm_end; 2107 if (start + count - 1 > end || start + count < start) 2108 return (EINVAL); 2109 wmask = ((rman_res_t)1 << w->step) - 1; 2110 2111 /* 2112 * If there is no resource at all, just try to allocate enough 2113 * aligned space for this resource. 2114 */ 2115 if (w->res == NULL) { 2116 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2117 flags); 2118 if (error) { 2119 if (bootverbose) 2120 device_printf(sc->dev, 2121 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2122 w->name, start, end, count); 2123 return (error); 2124 } 2125 if (bootverbose) 2126 device_printf(sc->dev, 2127 "allocated initial %s window of %#jx-%#jx\n", 2128 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2129 goto updatewin; 2130 } 2131 2132 /* 2133 * See if growing the window would help. Compute the minimum 2134 * amount of address space needed on both the front and back 2135 * ends of the existing window to satisfy the allocation. 2136 * 2137 * For each end, build a candidate region adjusting for the 2138 * required alignment, etc. If there is a free region at the 2139 * edge of the window, grow from the inner edge of the free 2140 * region. Otherwise grow from the window boundary. 2141 * 2142 * Growing an I/O window below 64k for a bridge with the ISA 2143 * enable bit doesn't require any special magic as the step 2144 * size of an I/O window (1k) always includes multiple 2145 * non-alias ranges when it is grown in either direction. 2146 * 2147 * XXX: Special case: if w->res is completely empty and the 2148 * request size is larger than w->res, we should find the 2149 * optimal aligned buffer containing w->res and allocate that. 2150 */ 2151 if (bootverbose) 2152 device_printf(sc->dev, 2153 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2154 w->name, start, end, count); 2155 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2156 if (start < w->base) { 2157 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2158 0 || start_free != w->base) 2159 end_free = w->base; 2160 if (end_free > end) 2161 end_free = end + 1; 2162 2163 /* Move end_free down until it is properly aligned. */ 2164 end_free &= ~(align - 1); 2165 end_free--; 2166 front = end_free - (count - 1); 2167 2168 /* 2169 * The resource would now be allocated at (front, 2170 * end_free). Ensure that fits in the (start, end) 2171 * bounds. end_free is checked above. If 'front' is 2172 * ok, ensure it is properly aligned for this window. 2173 * Also check for underflow. 2174 */ 2175 if (front >= start && front <= end_free) { 2176 if (bootverbose) 2177 printf("\tfront candidate range: %#jx-%#jx\n", 2178 front, end_free); 2179 front &= ~wmask; 2180 front = w->base - front; 2181 } else 2182 front = 0; 2183 } else 2184 front = 0; 2185 if (end > w->limit) { 2186 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2187 0 || end_free != w->limit) 2188 start_free = w->limit + 1; 2189 if (start_free < start) 2190 start_free = start; 2191 2192 /* Move start_free up until it is properly aligned. */ 2193 start_free = roundup2(start_free, align); 2194 back = start_free + count - 1; 2195 2196 /* 2197 * The resource would now be allocated at (start_free, 2198 * back). Ensure that fits in the (start, end) 2199 * bounds. start_free is checked above. If 'back' is 2200 * ok, ensure it is properly aligned for this window. 2201 * Also check for overflow. 2202 */ 2203 if (back <= end && start_free <= back) { 2204 if (bootverbose) 2205 printf("\tback candidate range: %#jx-%#jx\n", 2206 start_free, back); 2207 back |= wmask; 2208 back -= w->limit; 2209 } else 2210 back = 0; 2211 } else 2212 back = 0; 2213 2214 /* 2215 * Try to allocate the smallest needed region first. 2216 * If that fails, fall back to the other region. 2217 */ 2218 error = ENOSPC; 2219 while (front != 0 || back != 0) { 2220 if (front != 0 && (front <= back || back == 0)) { 2221 error = pcib_expand_window(sc, w, type, w->base - front, 2222 w->limit); 2223 if (error == 0) 2224 break; 2225 front = 0; 2226 } else { 2227 error = pcib_expand_window(sc, w, type, w->base, 2228 w->limit + back); 2229 if (error == 0) 2230 break; 2231 back = 0; 2232 } 2233 } 2234 2235 if (error) 2236 return (error); 2237 if (bootverbose) 2238 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2239 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2240 2241 updatewin: 2242 /* Write the new window. */ 2243 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2244 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2245 pcib_write_windows(sc, w->mask); 2246 return (0); 2247 } 2248 2249 /* 2250 * We have to trap resource allocation requests and ensure that the bridge 2251 * is set up to, or capable of handling them. 2252 */ 2253 struct resource * 2254 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2255 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2256 { 2257 struct pcib_softc *sc; 2258 struct resource *r; 2259 2260 sc = device_get_softc(dev); 2261 2262 /* 2263 * VGA resources are decoded iff the VGA enable bit is set in 2264 * the bridge control register. VGA resources do not fall into 2265 * the resource windows and are passed up to the parent. 2266 */ 2267 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2268 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2269 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2270 return (bus_generic_alloc_resource(dev, child, type, 2271 rid, start, end, count, flags)); 2272 else 2273 return (NULL); 2274 } 2275 2276 switch (type) { 2277 #ifdef PCI_RES_BUS 2278 case PCI_RES_BUS: 2279 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2280 count, flags)); 2281 #endif 2282 case SYS_RES_IOPORT: 2283 if (pcib_is_isa_range(sc, start, end, count)) 2284 return (NULL); 2285 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2286 end, count, flags); 2287 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2288 break; 2289 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2290 flags) == 0) 2291 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2292 rid, start, end, count, flags); 2293 break; 2294 case SYS_RES_MEMORY: 2295 /* 2296 * For prefetchable resources, prefer the prefetchable 2297 * memory window, but fall back to the regular memory 2298 * window if that fails. Try both windows before 2299 * attempting to grow a window in case the firmware 2300 * has used a range in the regular memory window to 2301 * map a prefetchable BAR. 2302 */ 2303 if (flags & RF_PREFETCHABLE) { 2304 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2305 rid, start, end, count, flags); 2306 if (r != NULL) 2307 break; 2308 } 2309 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2310 start, end, count, flags); 2311 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2312 break; 2313 if (flags & RF_PREFETCHABLE) { 2314 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2315 count, flags) == 0) { 2316 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2317 type, rid, start, end, count, flags); 2318 if (r != NULL) 2319 break; 2320 } 2321 } 2322 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2323 flags & ~RF_PREFETCHABLE) == 0) 2324 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2325 rid, start, end, count, flags); 2326 break; 2327 default: 2328 return (bus_generic_alloc_resource(dev, child, type, rid, 2329 start, end, count, flags)); 2330 } 2331 2332 /* 2333 * If attempts to suballocate from the window fail but this is a 2334 * subtractive bridge, pass the request up the tree. 2335 */ 2336 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2337 return (bus_generic_alloc_resource(dev, child, type, rid, 2338 start, end, count, flags)); 2339 return (r); 2340 } 2341 2342 int 2343 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2344 rman_res_t start, rman_res_t end) 2345 { 2346 struct pcib_softc *sc; 2347 struct pcib_window *w; 2348 rman_res_t wmask; 2349 int error; 2350 2351 sc = device_get_softc(bus); 2352 2353 /* 2354 * If the resource wasn't sub-allocated from one of our region 2355 * managers then just pass the request up. 2356 */ 2357 if (!pcib_is_resource_managed(sc, type, r)) 2358 return (bus_generic_adjust_resource(bus, child, type, r, 2359 start, end)); 2360 2361 #ifdef PCI_RES_BUS 2362 if (type != PCI_RES_BUS) 2363 #endif 2364 { 2365 /* 2366 * Resource is managed and not a secondary bus number, must 2367 * be from one of our windows. 2368 */ 2369 w = pcib_get_resource_window(sc, type, r); 2370 KASSERT(w != NULL, 2371 ("%s: no window for resource (%#jx-%#jx) type %d", 2372 __func__, rman_get_start(r), rman_get_end(r), type)); 2373 2374 /* 2375 * If our window isn't big enough to grow the sub-allocation 2376 * then we need to expand the window. 2377 */ 2378 if (start < w->base || end > w->limit) { 2379 wmask = ((rman_res_t)1 << w->step) - 1; 2380 error = pcib_expand_window(sc, w, type, 2381 MIN(start & ~wmask, w->base), 2382 MAX(end | wmask, w->limit)); 2383 if (error != 0) 2384 return (error); 2385 if (bootverbose) 2386 device_printf(sc->dev, 2387 "grew %s window to %#jx-%#jx\n", 2388 w->name, (uintmax_t)w->base, 2389 (uintmax_t)w->limit); 2390 pcib_write_windows(sc, w->mask); 2391 } 2392 } 2393 2394 return (rman_adjust_resource(r, start, end)); 2395 } 2396 2397 int 2398 pcib_release_resource(device_t dev, device_t child, int type, int rid, 2399 struct resource *r) 2400 { 2401 struct pcib_softc *sc; 2402 int error; 2403 2404 sc = device_get_softc(dev); 2405 if (pcib_is_resource_managed(sc, type, r)) { 2406 if (rman_get_flags(r) & RF_ACTIVE) { 2407 error = bus_deactivate_resource(child, type, rid, r); 2408 if (error) 2409 return (error); 2410 } 2411 return (rman_release_resource(r)); 2412 } 2413 return (bus_generic_release_resource(dev, child, type, rid, r)); 2414 } 2415 #else 2416 /* 2417 * We have to trap resource allocation requests and ensure that the bridge 2418 * is set up to, or capable of handling them. 2419 */ 2420 struct resource * 2421 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2422 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2423 { 2424 struct pcib_softc *sc = device_get_softc(dev); 2425 const char *name, *suffix; 2426 int ok; 2427 2428 /* 2429 * Fail the allocation for this range if it's not supported. 2430 */ 2431 name = device_get_nameunit(child); 2432 if (name == NULL) { 2433 name = ""; 2434 suffix = ""; 2435 } else 2436 suffix = " "; 2437 switch (type) { 2438 case SYS_RES_IOPORT: 2439 ok = 0; 2440 if (!pcib_is_io_open(sc)) 2441 break; 2442 ok = (start >= sc->iobase && end <= sc->iolimit); 2443 2444 /* 2445 * Make sure we allow access to VGA I/O addresses when the 2446 * bridge has the "VGA Enable" bit set. 2447 */ 2448 if (!ok && pci_is_vga_ioport_range(start, end)) 2449 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2450 2451 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2452 if (!ok) { 2453 if (start < sc->iobase) 2454 start = sc->iobase; 2455 if (end > sc->iolimit) 2456 end = sc->iolimit; 2457 if (start < end) 2458 ok = 1; 2459 } 2460 } else { 2461 ok = 1; 2462 #if 0 2463 /* 2464 * If we overlap with the subtractive range, then 2465 * pick the upper range to use. 2466 */ 2467 if (start < sc->iolimit && end > sc->iobase) 2468 start = sc->iolimit + 1; 2469 #endif 2470 } 2471 if (end < start) { 2472 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2473 end, start); 2474 start = 0; 2475 end = 0; 2476 ok = 0; 2477 } 2478 if (!ok) { 2479 device_printf(dev, "%s%srequested unsupported I/O " 2480 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2481 name, suffix, start, end, sc->iobase, sc->iolimit); 2482 return (NULL); 2483 } 2484 if (bootverbose) 2485 device_printf(dev, 2486 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2487 name, suffix, start, end); 2488 break; 2489 2490 case SYS_RES_MEMORY: 2491 ok = 0; 2492 if (pcib_is_nonprefetch_open(sc)) 2493 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2494 if (pcib_is_prefetch_open(sc)) 2495 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2496 2497 /* 2498 * Make sure we allow access to VGA memory addresses when the 2499 * bridge has the "VGA Enable" bit set. 2500 */ 2501 if (!ok && pci_is_vga_memory_range(start, end)) 2502 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2503 2504 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2505 if (!ok) { 2506 ok = 1; 2507 if (flags & RF_PREFETCHABLE) { 2508 if (pcib_is_prefetch_open(sc)) { 2509 if (start < sc->pmembase) 2510 start = sc->pmembase; 2511 if (end > sc->pmemlimit) 2512 end = sc->pmemlimit; 2513 } else { 2514 ok = 0; 2515 } 2516 } else { /* non-prefetchable */ 2517 if (pcib_is_nonprefetch_open(sc)) { 2518 if (start < sc->membase) 2519 start = sc->membase; 2520 if (end > sc->memlimit) 2521 end = sc->memlimit; 2522 } else { 2523 ok = 0; 2524 } 2525 } 2526 } 2527 } else if (!ok) { 2528 ok = 1; /* subtractive bridge: always ok */ 2529 #if 0 2530 if (pcib_is_nonprefetch_open(sc)) { 2531 if (start < sc->memlimit && end > sc->membase) 2532 start = sc->memlimit + 1; 2533 } 2534 if (pcib_is_prefetch_open(sc)) { 2535 if (start < sc->pmemlimit && end > sc->pmembase) 2536 start = sc->pmemlimit + 1; 2537 } 2538 #endif 2539 } 2540 if (end < start) { 2541 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2542 end, start); 2543 start = 0; 2544 end = 0; 2545 ok = 0; 2546 } 2547 if (!ok && bootverbose) 2548 device_printf(dev, 2549 "%s%srequested unsupported memory range %#jx-%#jx " 2550 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2551 name, suffix, start, end, 2552 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2553 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2554 if (!ok) 2555 return (NULL); 2556 if (bootverbose) 2557 device_printf(dev,"%s%srequested memory range " 2558 "0x%jx-0x%jx: good\n", 2559 name, suffix, start, end); 2560 break; 2561 2562 default: 2563 break; 2564 } 2565 /* 2566 * Bridge is OK decoding this resource, so pass it up. 2567 */ 2568 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2569 count, flags)); 2570 } 2571 #endif 2572 2573 /* 2574 * If ARI is enabled on this downstream port, translate the function number 2575 * to the non-ARI slot/function. The downstream port will convert it back in 2576 * hardware. If ARI is not enabled slot and func are not modified. 2577 */ 2578 static __inline void 2579 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2580 { 2581 struct pcib_softc *sc; 2582 int ari_func; 2583 2584 sc = device_get_softc(pcib); 2585 ari_func = *func; 2586 2587 if (sc->flags & PCIB_ENABLE_ARI) { 2588 KASSERT(*slot == 0, 2589 ("Non-zero slot number with ARI enabled!")); 2590 *slot = PCIE_ARI_SLOT(ari_func); 2591 *func = PCIE_ARI_FUNC(ari_func); 2592 } 2593 } 2594 2595 static void 2596 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2597 { 2598 uint32_t ctl2; 2599 2600 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2601 ctl2 |= PCIEM_CTL2_ARI; 2602 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2603 2604 sc->flags |= PCIB_ENABLE_ARI; 2605 } 2606 2607 /* 2608 * PCIB interface. 2609 */ 2610 int 2611 pcib_maxslots(device_t dev) 2612 { 2613 #if !defined(__amd64__) && !defined(__i386__) 2614 uint32_t pcie_pos; 2615 uint16_t val; 2616 2617 /* 2618 * If this is a PCIe rootport or downstream switch port, there's only 2619 * one slot permitted. 2620 */ 2621 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) { 2622 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2); 2623 val &= PCIEM_FLAGS_TYPE; 2624 if (val == PCIEM_TYPE_ROOT_PORT || 2625 val == PCIEM_TYPE_DOWNSTREAM_PORT) 2626 return (0); 2627 } 2628 #endif 2629 return (PCI_SLOTMAX); 2630 } 2631 2632 static int 2633 pcib_ari_maxslots(device_t dev) 2634 { 2635 struct pcib_softc *sc; 2636 2637 sc = device_get_softc(dev); 2638 2639 if (sc->flags & PCIB_ENABLE_ARI) 2640 return (PCIE_ARI_SLOTMAX); 2641 else 2642 return (pcib_maxslots(dev)); 2643 } 2644 2645 static int 2646 pcib_ari_maxfuncs(device_t dev) 2647 { 2648 struct pcib_softc *sc; 2649 2650 sc = device_get_softc(dev); 2651 2652 if (sc->flags & PCIB_ENABLE_ARI) 2653 return (PCIE_ARI_FUNCMAX); 2654 else 2655 return (PCI_FUNCMAX); 2656 } 2657 2658 static void 2659 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2660 int *func) 2661 { 2662 struct pcib_softc *sc; 2663 2664 sc = device_get_softc(pcib); 2665 2666 *bus = PCI_RID2BUS(rid); 2667 if (sc->flags & PCIB_ENABLE_ARI) { 2668 *slot = PCIE_ARI_RID2SLOT(rid); 2669 *func = PCIE_ARI_RID2FUNC(rid); 2670 } else { 2671 *slot = PCI_RID2SLOT(rid); 2672 *func = PCI_RID2FUNC(rid); 2673 } 2674 } 2675 2676 /* 2677 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2678 */ 2679 static uint32_t 2680 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2681 { 2682 #ifdef PCI_HP 2683 struct pcib_softc *sc; 2684 2685 sc = device_get_softc(dev); 2686 if (!pcib_present(sc)) { 2687 switch (width) { 2688 case 2: 2689 return (0xffff); 2690 case 1: 2691 return (0xff); 2692 default: 2693 return (0xffffffff); 2694 } 2695 } 2696 #endif 2697 pcib_xlate_ari(dev, b, &s, &f); 2698 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2699 f, reg, width)); 2700 } 2701 2702 static void 2703 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2704 { 2705 #ifdef PCI_HP 2706 struct pcib_softc *sc; 2707 2708 sc = device_get_softc(dev); 2709 if (!pcib_present(sc)) 2710 return; 2711 #endif 2712 pcib_xlate_ari(dev, b, &s, &f); 2713 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2714 reg, val, width); 2715 } 2716 2717 /* 2718 * Route an interrupt across a PCI bridge. 2719 */ 2720 int 2721 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2722 { 2723 device_t bus; 2724 int parent_intpin; 2725 int intnum; 2726 2727 /* 2728 * 2729 * The PCI standard defines a swizzle of the child-side device/intpin to 2730 * the parent-side intpin as follows. 2731 * 2732 * device = device on child bus 2733 * child_intpin = intpin on child bus slot (0-3) 2734 * parent_intpin = intpin on parent bus slot (0-3) 2735 * 2736 * parent_intpin = (device + child_intpin) % 4 2737 */ 2738 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2739 2740 /* 2741 * Our parent is a PCI bus. Its parent must export the pcib interface 2742 * which includes the ability to route interrupts. 2743 */ 2744 bus = device_get_parent(pcib); 2745 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2746 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2747 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2748 pci_get_slot(dev), 'A' + pin - 1, intnum); 2749 } 2750 return(intnum); 2751 } 2752 2753 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2754 int 2755 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2756 { 2757 struct pcib_softc *sc = device_get_softc(pcib); 2758 device_t bus; 2759 2760 if (sc->flags & PCIB_DISABLE_MSI) 2761 return (ENXIO); 2762 bus = device_get_parent(pcib); 2763 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2764 irqs)); 2765 } 2766 2767 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2768 int 2769 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2770 { 2771 device_t bus; 2772 2773 bus = device_get_parent(pcib); 2774 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2775 } 2776 2777 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2778 int 2779 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2780 { 2781 struct pcib_softc *sc = device_get_softc(pcib); 2782 device_t bus; 2783 2784 if (sc->flags & PCIB_DISABLE_MSIX) 2785 return (ENXIO); 2786 bus = device_get_parent(pcib); 2787 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2788 } 2789 2790 /* Pass request to release an MSI-X message up to the parent bridge. */ 2791 int 2792 pcib_release_msix(device_t pcib, device_t dev, int irq) 2793 { 2794 device_t bus; 2795 2796 bus = device_get_parent(pcib); 2797 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2798 } 2799 2800 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2801 int 2802 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2803 uint32_t *data) 2804 { 2805 device_t bus; 2806 int error; 2807 2808 bus = device_get_parent(pcib); 2809 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2810 if (error) 2811 return (error); 2812 2813 pci_ht_map_msi(pcib, *addr); 2814 return (0); 2815 } 2816 2817 /* Pass request for device power state up to parent bridge. */ 2818 int 2819 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2820 { 2821 device_t bus; 2822 2823 bus = device_get_parent(pcib); 2824 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2825 } 2826 2827 static int 2828 pcib_ari_enabled(device_t pcib) 2829 { 2830 struct pcib_softc *sc; 2831 2832 sc = device_get_softc(pcib); 2833 2834 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2835 } 2836 2837 static int 2838 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2839 uintptr_t *id) 2840 { 2841 struct pcib_softc *sc; 2842 device_t bus_dev; 2843 uint8_t bus, slot, func; 2844 2845 if (type != PCI_ID_RID) { 2846 bus_dev = device_get_parent(pcib); 2847 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2848 } 2849 2850 sc = device_get_softc(pcib); 2851 2852 if (sc->flags & PCIB_ENABLE_ARI) { 2853 bus = pci_get_bus(dev); 2854 func = pci_get_function(dev); 2855 2856 *id = (PCI_ARI_RID(bus, func)); 2857 } else { 2858 bus = pci_get_bus(dev); 2859 slot = pci_get_slot(dev); 2860 func = pci_get_function(dev); 2861 2862 *id = (PCI_RID(bus, slot, func)); 2863 } 2864 2865 return (0); 2866 } 2867 2868 /* 2869 * Check that the downstream port (pcib) and the endpoint device (dev) both 2870 * support ARI. If so, enable it and return 0, otherwise return an error. 2871 */ 2872 static int 2873 pcib_try_enable_ari(device_t pcib, device_t dev) 2874 { 2875 struct pcib_softc *sc; 2876 int error; 2877 uint32_t cap2; 2878 int ari_cap_off; 2879 uint32_t ari_ver; 2880 uint32_t pcie_pos; 2881 2882 sc = device_get_softc(pcib); 2883 2884 /* 2885 * ARI is controlled in a register in the PCIe capability structure. 2886 * If the downstream port does not have the PCIe capability structure 2887 * then it does not support ARI. 2888 */ 2889 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2890 if (error != 0) 2891 return (ENODEV); 2892 2893 /* Check that the PCIe port advertises ARI support. */ 2894 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2895 if (!(cap2 & PCIEM_CAP2_ARI)) 2896 return (ENODEV); 2897 2898 /* 2899 * Check that the endpoint device advertises ARI support via the ARI 2900 * extended capability structure. 2901 */ 2902 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2903 if (error != 0) 2904 return (ENODEV); 2905 2906 /* 2907 * Finally, check that the endpoint device supports the same version 2908 * of ARI that we do. 2909 */ 2910 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2911 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2912 if (bootverbose) 2913 device_printf(pcib, 2914 "Unsupported version of ARI (%d) detected\n", 2915 PCI_EXTCAP_VER(ari_ver)); 2916 2917 return (ENXIO); 2918 } 2919 2920 pcib_enable_ari(sc, pcie_pos); 2921 2922 return (0); 2923 } 2924 2925 int 2926 pcib_request_feature_allow(device_t pcib, device_t dev, 2927 enum pci_feature feature) 2928 { 2929 /* 2930 * No host firmware we have to negotiate with, so we allow 2931 * every valid feature requested. 2932 */ 2933 switch (feature) { 2934 case PCI_FEATURE_AER: 2935 case PCI_FEATURE_HP: 2936 break; 2937 default: 2938 return (EINVAL); 2939 } 2940 2941 return (0); 2942 } 2943 2944 int 2945 pcib_request_feature(device_t dev, enum pci_feature feature) 2946 { 2947 2948 /* 2949 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2950 * the firmware overrides the method of PCI-PCI bridges. 2951 */ 2952 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2953 } 2954 2955 /* 2956 * Pass the request to use this PCI feature up the tree. Either there's a 2957 * firmware like ACPI that's using this feature that will approve (or deny) the 2958 * request to take it over, or the platform has no such firmware, in which case 2959 * the request will be approved. If the request is approved, the OS is expected 2960 * to make use of the feature or render it harmless. 2961 */ 2962 static int 2963 pcib_request_feature_default(device_t pcib, device_t dev, 2964 enum pci_feature feature) 2965 { 2966 device_t bus; 2967 2968 /* 2969 * Our parent is necessarily a pci bus. Its parent will either be 2970 * another pci bridge (which passes it up) or a host bridge that can 2971 * approve or reject the request. 2972 */ 2973 bus = device_get_parent(pcib); 2974 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2975 } 2976 2977 static int 2978 pcib_reset_child(device_t dev, device_t child, int flags) 2979 { 2980 struct pci_devinfo *pdinfo; 2981 int error; 2982 2983 error = 0; 2984 if (dev == NULL || device_get_parent(child) != dev) 2985 goto out; 2986 error = ENXIO; 2987 if (device_get_devclass(child) != devclass_find("pci")) 2988 goto out; 2989 pdinfo = device_get_ivars(dev); 2990 if (pdinfo->cfg.pcie.pcie_location != 0 && 2991 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT || 2992 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) { 2993 error = bus_helper_reset_prepare(child, flags); 2994 if (error == 0) { 2995 error = pcie_link_reset(dev, 2996 pdinfo->cfg.pcie.pcie_location); 2997 /* XXXKIB call _post even if error != 0 ? */ 2998 bus_helper_reset_post(child, flags); 2999 } 3000 } 3001 out: 3002 return (error); 3003 } 3004