xref: /freebsd/sys/dev/pci/pci_pci.c (revision b59017c5cad90d0f09a59e68c00457b7faf93e7c)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5  * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6  * Copyright (c) 2000 BSDi
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. The name of the author may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 /*
35  * PCI:PCI bridge support.
36  */
37 
38 #include "opt_pci.h"
39 
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/lock.h>
44 #include <sys/malloc.h>
45 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/pciio.h>
48 #include <sys/rman.h>
49 #include <sys/sysctl.h>
50 #include <sys/systm.h>
51 #include <sys/taskqueue.h>
52 
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pci_private.h>
56 #include <dev/pci/pcib_private.h>
57 
58 #include "pcib_if.h"
59 
60 static int		pcib_probe(device_t dev);
61 static int		pcib_resume(device_t dev);
62 
63 static bus_child_present_t	pcib_child_present;
64 static bus_alloc_resource_t	pcib_alloc_resource;
65 static bus_adjust_resource_t	pcib_adjust_resource;
66 static bus_release_resource_t	pcib_release_resource;
67 static bus_activate_resource_t	pcib_activate_resource;
68 static bus_deactivate_resource_t pcib_deactivate_resource;
69 static bus_map_resource_t	pcib_map_resource;
70 static bus_unmap_resource_t	pcib_unmap_resource;
71 static int		pcib_reset_child(device_t dev, device_t child, int flags);
72 
73 static int		pcib_power_for_sleep(device_t pcib, device_t dev,
74 			    int *pstate);
75 static int		pcib_ari_get_id(device_t pcib, device_t dev,
76     enum pci_id_type type, uintptr_t *id);
77 static uint32_t		pcib_read_config(device_t dev, u_int b, u_int s,
78     u_int f, u_int reg, int width);
79 static void		pcib_write_config(device_t dev, u_int b, u_int s,
80     u_int f, u_int reg, uint32_t val, int width);
81 static int		pcib_ari_maxslots(device_t dev);
82 static int		pcib_ari_maxfuncs(device_t dev);
83 static int		pcib_try_enable_ari(device_t pcib, device_t dev);
84 static int		pcib_ari_enabled(device_t pcib);
85 static void		pcib_ari_decode_rid(device_t pcib, uint16_t rid,
86 			    int *bus, int *slot, int *func);
87 #ifdef PCI_HP
88 static void		pcib_pcie_ab_timeout(void *arg, int pending);
89 static void		pcib_pcie_cc_timeout(void *arg, int pending);
90 static void		pcib_pcie_dll_timeout(void *arg, int pending);
91 #endif
92 static int		pcib_request_feature_default(device_t pcib, device_t dev,
93 			    enum pci_feature feature);
94 
95 static device_method_t pcib_methods[] = {
96     /* Device interface */
97     DEVMETHOD(device_probe,		pcib_probe),
98     DEVMETHOD(device_attach,		pcib_attach),
99     DEVMETHOD(device_detach,		pcib_detach),
100     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
101     DEVMETHOD(device_suspend,		bus_generic_suspend),
102     DEVMETHOD(device_resume,		pcib_resume),
103 
104     /* Bus interface */
105     DEVMETHOD(bus_child_present,	pcib_child_present),
106     DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
107     DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
108     DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
109     DEVMETHOD(bus_adjust_resource,	pcib_adjust_resource),
110     DEVMETHOD(bus_release_resource,	pcib_release_resource),
111     DEVMETHOD(bus_activate_resource,	pcib_activate_resource),
112     DEVMETHOD(bus_deactivate_resource,	pcib_deactivate_resource),
113     DEVMETHOD(bus_map_resource,		pcib_map_resource),
114     DEVMETHOD(bus_unmap_resource,	pcib_unmap_resource),
115     DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
116     DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
117     DEVMETHOD(bus_reset_child,		pcib_reset_child),
118 
119     /* pcib interface */
120     DEVMETHOD(pcib_maxslots,		pcib_ari_maxslots),
121     DEVMETHOD(pcib_maxfuncs,		pcib_ari_maxfuncs),
122     DEVMETHOD(pcib_read_config,		pcib_read_config),
123     DEVMETHOD(pcib_write_config,	pcib_write_config),
124     DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
125     DEVMETHOD(pcib_alloc_msi,		pcib_alloc_msi),
126     DEVMETHOD(pcib_release_msi,		pcib_release_msi),
127     DEVMETHOD(pcib_alloc_msix,		pcib_alloc_msix),
128     DEVMETHOD(pcib_release_msix,	pcib_release_msix),
129     DEVMETHOD(pcib_map_msi,		pcib_map_msi),
130     DEVMETHOD(pcib_power_for_sleep,	pcib_power_for_sleep),
131     DEVMETHOD(pcib_get_id,		pcib_ari_get_id),
132     DEVMETHOD(pcib_try_enable_ari,	pcib_try_enable_ari),
133     DEVMETHOD(pcib_ari_enabled,		pcib_ari_enabled),
134     DEVMETHOD(pcib_decode_rid,		pcib_ari_decode_rid),
135     DEVMETHOD(pcib_request_feature,	pcib_request_feature_default),
136 
137     DEVMETHOD_END
138 };
139 
140 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
141 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, NULL, NULL, BUS_PASS_BUS);
142 
143 SYSCTL_DECL(_hw_pci);
144 
145 static int pci_clear_pcib;
146 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
147     "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
148 
149 /*
150  * Get the corresponding window if this resource from a child device was
151  * sub-allocated from one of our window resource managers.
152  */
153 static struct pcib_window *
154 pcib_get_resource_window(struct pcib_softc *sc, struct resource *r)
155 {
156 	switch (rman_get_type(r)) {
157 	case SYS_RES_IOPORT:
158 		if (rman_is_region_manager(r, &sc->io.rman))
159 			return (&sc->io);
160 		break;
161 	case SYS_RES_MEMORY:
162 		/* Prefetchable resources may live in either memory rman. */
163 		if (rman_get_flags(r) & RF_PREFETCHABLE &&
164 		    rman_is_region_manager(r, &sc->pmem.rman))
165 			return (&sc->pmem);
166 		if (rman_is_region_manager(r, &sc->mem.rman))
167 			return (&sc->mem);
168 		break;
169 	}
170 	return (NULL);
171 }
172 
173 /*
174  * Is a resource from a child device sub-allocated from one of our
175  * resource managers?
176  */
177 static int
178 pcib_is_resource_managed(struct pcib_softc *sc, struct resource *r)
179 {
180 
181 	if (rman_get_type(r) == PCI_RES_BUS)
182 		return (rman_is_region_manager(r, &sc->bus.rman));
183 	return (pcib_get_resource_window(sc, r) != NULL);
184 }
185 
186 static int
187 pcib_is_window_open(struct pcib_window *pw)
188 {
189 
190 	return (pw->valid && pw->base < pw->limit);
191 }
192 
193 /*
194  * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
195  * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
196  * when allocating the resource windows and rely on the PCI bus driver
197  * to do this for us.
198  */
199 static void
200 pcib_activate_window(struct pcib_softc *sc, int type)
201 {
202 
203 	PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
204 }
205 
206 static void
207 pcib_write_windows(struct pcib_softc *sc, int mask)
208 {
209 	device_t dev;
210 	uint32_t val;
211 
212 	dev = sc->dev;
213 	if (sc->io.valid && mask & WIN_IO) {
214 		val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
215 		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
216 			pci_write_config(dev, PCIR_IOBASEH_1,
217 			    sc->io.base >> 16, 2);
218 			pci_write_config(dev, PCIR_IOLIMITH_1,
219 			    sc->io.limit >> 16, 2);
220 		}
221 		pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
222 		pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
223 	}
224 
225 	if (mask & WIN_MEM) {
226 		pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
227 		pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
228 	}
229 
230 	if (sc->pmem.valid && mask & WIN_PMEM) {
231 		val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
232 		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
233 			pci_write_config(dev, PCIR_PMBASEH_1,
234 			    sc->pmem.base >> 32, 4);
235 			pci_write_config(dev, PCIR_PMLIMITH_1,
236 			    sc->pmem.limit >> 32, 4);
237 		}
238 		pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
239 		pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
240 	}
241 }
242 
243 /*
244  * This is used to reject I/O port allocations that conflict with an
245  * ISA alias range.
246  */
247 static int
248 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
249     rman_res_t count)
250 {
251 	rman_res_t next_alias;
252 
253 	if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
254 		return (0);
255 
256 	/* Only check fixed ranges for overlap. */
257 	if (start + count - 1 != end)
258 		return (0);
259 
260 	/* ISA aliases are only in the lower 64KB of I/O space. */
261 	if (start >= 65536)
262 		return (0);
263 
264 	/* Check for overlap with 0x000 - 0x0ff as a special case. */
265 	if (start < 0x100)
266 		goto alias;
267 
268 	/*
269 	 * If the start address is an alias, the range is an alias.
270 	 * Otherwise, compute the start of the next alias range and
271 	 * check if it is before the end of the candidate range.
272 	 */
273 	if ((start & 0x300) != 0)
274 		goto alias;
275 	next_alias = (start & ~0x3fful) | 0x100;
276 	if (next_alias <= end)
277 		goto alias;
278 	return (0);
279 
280 alias:
281 	if (bootverbose)
282 		device_printf(sc->dev,
283 		    "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
284 		    end);
285 	return (1);
286 }
287 
288 static void
289 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
290     int count)
291 {
292 	struct resource **newarray;
293 	int error, i;
294 
295 	newarray = malloc(sizeof(struct resource *) * (w->count + count),
296 	    M_DEVBUF, M_WAITOK);
297 	if (w->res != NULL)
298 		bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
299 	bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
300 	free(w->res, M_DEVBUF);
301 	w->res = newarray;
302 	w->count += count;
303 
304 	for (i = 0; i < count; i++) {
305 		error = rman_manage_region(&w->rman, rman_get_start(res[i]),
306 		    rman_get_end(res[i]));
307 		if (error)
308 			panic("Failed to add resource to rman");
309 	}
310 }
311 
312 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
313 
314 static void
315 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
316     void *arg)
317 {
318 	rman_res_t next_end;
319 
320 	/*
321 	 * If start is within an ISA alias range, move up to the start
322 	 * of the next non-alias range.  As a special case, addresses
323 	 * in the range 0x000 - 0x0ff should also be skipped since
324 	 * those are used for various system I/O devices in ISA
325 	 * systems.
326 	 */
327 	if (start <= 65535) {
328 		if (start < 0x100 || (start & 0x300) != 0) {
329 			start &= ~0x3ff;
330 			start += 0x400;
331 		}
332 	}
333 
334 	/* ISA aliases are only in the lower 64KB of I/O space. */
335 	while (start <= MIN(end, 65535)) {
336 		next_end = MIN(start | 0xff, end);
337 		cb(start, next_end, arg);
338 		start += 0x400;
339 	}
340 
341 	if (start <= end)
342 		cb(start, end, arg);
343 }
344 
345 static void
346 count_ranges(rman_res_t start, rman_res_t end, void *arg)
347 {
348 	int *countp;
349 
350 	countp = arg;
351 	(*countp)++;
352 }
353 
354 struct alloc_state {
355 	struct resource **res;
356 	struct pcib_softc *sc;
357 	int count, error;
358 };
359 
360 static void
361 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
362 {
363 	struct alloc_state *as;
364 	struct pcib_window *w;
365 	int rid;
366 
367 	as = arg;
368 	if (as->error != 0)
369 		return;
370 
371 	w = &as->sc->io;
372 	rid = w->reg;
373 	if (bootverbose)
374 		device_printf(as->sc->dev,
375 		    "allocating non-ISA range %#jx-%#jx\n", start, end);
376 	as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
377 	    &rid, start, end, end - start + 1, RF_ACTIVE | RF_UNMAPPED);
378 	if (as->res[as->count] == NULL)
379 		as->error = ENXIO;
380 	else
381 		as->count++;
382 }
383 
384 static int
385 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
386 {
387 	struct alloc_state as;
388 	int i, new_count;
389 
390 	/* First, see how many ranges we need. */
391 	new_count = 0;
392 	pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
393 
394 	/* Second, allocate the ranges. */
395 	as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
396 	    M_WAITOK);
397 	as.sc = sc;
398 	as.count = 0;
399 	as.error = 0;
400 	pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
401 	if (as.error != 0) {
402 		for (i = 0; i < as.count; i++)
403 			bus_release_resource(sc->dev, SYS_RES_IOPORT,
404 			    sc->io.reg, as.res[i]);
405 		free(as.res, M_DEVBUF);
406 		return (as.error);
407 	}
408 	KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
409 
410 	/* Third, add the ranges to the window. */
411 	pcib_add_window_resources(&sc->io, as.res, as.count);
412 	free(as.res, M_DEVBUF);
413 	return (0);
414 }
415 
416 static void
417 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
418     int flags, pci_addr_t max_address)
419 {
420 	struct resource *res;
421 	char buf[64];
422 	int error, rid;
423 
424 	if (max_address != (rman_res_t)max_address)
425 		max_address = ~0;
426 	w->rman.rm_start = 0;
427 	w->rman.rm_end = max_address;
428 	w->rman.rm_type = RMAN_ARRAY;
429 	snprintf(buf, sizeof(buf), "%s %s window",
430 	    device_get_nameunit(sc->dev), w->name);
431 	w->rman.rm_descr = strdup(buf, M_DEVBUF);
432 	error = rman_init(&w->rman);
433 	if (error)
434 		panic("Failed to initialize %s %s rman",
435 		    device_get_nameunit(sc->dev), w->name);
436 
437 	if (!pcib_is_window_open(w))
438 		return;
439 
440 	if (w->base > max_address || w->limit > max_address) {
441 		device_printf(sc->dev,
442 		    "initial %s window has too many bits, ignoring\n", w->name);
443 		return;
444 	}
445 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
446 		(void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
447 	else {
448 		rid = w->reg;
449 		res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
450 		    w->limit - w->base + 1, flags | RF_ACTIVE | RF_UNMAPPED);
451 		if (res != NULL)
452 			pcib_add_window_resources(w, &res, 1);
453 	}
454 	if (w->res == NULL) {
455 		device_printf(sc->dev,
456 		    "failed to allocate initial %s window: %#jx-%#jx\n",
457 		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
458 		w->base = max_address;
459 		w->limit = 0;
460 		pcib_write_windows(sc, w->mask);
461 		return;
462 	}
463 	pcib_activate_window(sc, type);
464 }
465 
466 /*
467  * Initialize I/O windows.
468  */
469 static void
470 pcib_probe_windows(struct pcib_softc *sc)
471 {
472 	pci_addr_t max;
473 	device_t dev;
474 	uint32_t val;
475 
476 	dev = sc->dev;
477 
478 	if (pci_clear_pcib) {
479 		pcib_bridge_init(dev);
480 	}
481 
482 	/* Determine if the I/O port window is implemented. */
483 	val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
484 	if (val == 0) {
485 		/*
486 		 * If 'val' is zero, then only 16-bits of I/O space
487 		 * are supported.
488 		 */
489 		pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
490 		if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
491 			sc->io.valid = 1;
492 			pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
493 		}
494 	} else
495 		sc->io.valid = 1;
496 
497 	/* Read the existing I/O port window. */
498 	if (sc->io.valid) {
499 		sc->io.reg = PCIR_IOBASEL_1;
500 		sc->io.step = 12;
501 		sc->io.mask = WIN_IO;
502 		sc->io.name = "I/O port";
503 		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
504 			sc->io.base = PCI_PPBIOBASE(
505 			    pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
506 			sc->io.limit = PCI_PPBIOLIMIT(
507 			    pci_read_config(dev, PCIR_IOLIMITH_1, 2),
508 			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
509 			max = 0xffffffff;
510 		} else {
511 			sc->io.base = PCI_PPBIOBASE(0, val);
512 			sc->io.limit = PCI_PPBIOLIMIT(0,
513 			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
514 			max = 0xffff;
515 		}
516 		pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
517 	}
518 
519 	/* Read the existing memory window. */
520 	sc->mem.valid = 1;
521 	sc->mem.reg = PCIR_MEMBASE_1;
522 	sc->mem.step = 20;
523 	sc->mem.mask = WIN_MEM;
524 	sc->mem.name = "memory";
525 	sc->mem.base = PCI_PPBMEMBASE(0,
526 	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
527 	sc->mem.limit = PCI_PPBMEMLIMIT(0,
528 	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
529 	pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
530 
531 	/* Determine if the prefetchable memory window is implemented. */
532 	val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
533 	if (val == 0) {
534 		/*
535 		 * If 'val' is zero, then only 32-bits of memory space
536 		 * are supported.
537 		 */
538 		pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
539 		if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
540 			sc->pmem.valid = 1;
541 			pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
542 		}
543 	} else
544 		sc->pmem.valid = 1;
545 
546 	/* Read the existing prefetchable memory window. */
547 	if (sc->pmem.valid) {
548 		sc->pmem.reg = PCIR_PMBASEL_1;
549 		sc->pmem.step = 20;
550 		sc->pmem.mask = WIN_PMEM;
551 		sc->pmem.name = "prefetch";
552 		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
553 			sc->pmem.base = PCI_PPBMEMBASE(
554 			    pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
555 			sc->pmem.limit = PCI_PPBMEMLIMIT(
556 			    pci_read_config(dev, PCIR_PMLIMITH_1, 4),
557 			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
558 			max = 0xffffffffffffffff;
559 		} else {
560 			sc->pmem.base = PCI_PPBMEMBASE(0, val);
561 			sc->pmem.limit = PCI_PPBMEMLIMIT(0,
562 			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
563 			max = 0xffffffff;
564 		}
565 		pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
566 		    RF_PREFETCHABLE, max);
567 	}
568 }
569 
570 static void
571 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
572 {
573 	device_t dev;
574 	int error, i;
575 
576 	if (!w->valid)
577 		return;
578 
579 	dev = sc->dev;
580 	error = rman_fini(&w->rman);
581 	if (error) {
582 		device_printf(dev, "failed to release %s rman\n", w->name);
583 		return;
584 	}
585 	free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
586 
587 	for (i = 0; i < w->count; i++) {
588 		error = bus_free_resource(dev, type, w->res[i]);
589 		if (error)
590 			device_printf(dev,
591 			    "failed to release %s resource: %d\n", w->name,
592 			    error);
593 	}
594 	free(w->res, M_DEVBUF);
595 }
596 
597 static void
598 pcib_free_windows(struct pcib_softc *sc)
599 {
600 
601 	pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
602 	pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
603 	pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
604 }
605 
606 /*
607  * Allocate a suitable secondary bus for this bridge if needed and
608  * initialize the resource manager for the secondary bus range.  Note
609  * that the minimum count is a desired value and this may allocate a
610  * smaller range.
611  */
612 void
613 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
614 {
615 	char buf[64];
616 	int error, rid, sec_reg;
617 
618 	switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
619 	case PCIM_HDRTYPE_BRIDGE:
620 		sec_reg = PCIR_SECBUS_1;
621 		bus->sub_reg = PCIR_SUBBUS_1;
622 		break;
623 	case PCIM_HDRTYPE_CARDBUS:
624 		sec_reg = PCIR_SECBUS_2;
625 		bus->sub_reg = PCIR_SUBBUS_2;
626 		break;
627 	default:
628 		panic("not a PCI bridge");
629 	}
630 	bus->sec = pci_read_config(dev, sec_reg, 1);
631 	bus->sub = pci_read_config(dev, bus->sub_reg, 1);
632 	bus->dev = dev;
633 	bus->rman.rm_start = 0;
634 	bus->rman.rm_end = PCI_BUSMAX;
635 	bus->rman.rm_type = RMAN_ARRAY;
636 	snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
637 	bus->rman.rm_descr = strdup(buf, M_DEVBUF);
638 	error = rman_init(&bus->rman);
639 	if (error)
640 		panic("Failed to initialize %s bus number rman",
641 		    device_get_nameunit(dev));
642 
643 	/*
644 	 * Allocate a bus range.  This will return an existing bus range
645 	 * if one exists, or a new bus range if one does not.
646 	 */
647 	rid = 0;
648 	bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
649 	    min_count, RF_ACTIVE);
650 	if (bus->res == NULL) {
651 		/*
652 		 * Fall back to just allocating a range of a single bus
653 		 * number.
654 		 */
655 		bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
656 		    1, RF_ACTIVE);
657 	} else if (rman_get_size(bus->res) < min_count)
658 		/*
659 		 * Attempt to grow the existing range to satisfy the
660 		 * minimum desired count.
661 		 */
662 		(void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
663 		    rman_get_start(bus->res), rman_get_start(bus->res) +
664 		    min_count - 1);
665 
666 	/*
667 	 * Add the initial resource to the rman.
668 	 */
669 	if (bus->res != NULL) {
670 		error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
671 		    rman_get_end(bus->res));
672 		if (error)
673 			panic("Failed to add resource to rman");
674 		bus->sec = rman_get_start(bus->res);
675 		bus->sub = rman_get_end(bus->res);
676 	}
677 }
678 
679 void
680 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
681 {
682 	int error;
683 
684 	error = rman_fini(&bus->rman);
685 	if (error) {
686 		device_printf(dev, "failed to release bus number rman\n");
687 		return;
688 	}
689 	free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
690 
691 	error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
692 	if (error)
693 		device_printf(dev,
694 		    "failed to release bus numbers resource: %d\n", error);
695 }
696 
697 static struct resource *
698 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
699     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
700 {
701 	struct resource *res;
702 
703 	res = rman_reserve_resource(&bus->rman, start, end, count, flags,
704 	    child);
705 	if (res == NULL)
706 		return (NULL);
707 
708 	if (bootverbose)
709 		device_printf(bus->dev,
710 		    "allocated bus range (%ju-%ju) for rid %d of %s\n",
711 		    rman_get_start(res), rman_get_end(res), *rid,
712 		    pcib_child_name(child));
713 	rman_set_rid(res, *rid);
714 	rman_set_type(res, PCI_RES_BUS);
715 	return (res);
716 }
717 
718 /*
719  * Attempt to grow the secondary bus range.  This is much simpler than
720  * for I/O windows as the range can only be grown by increasing
721  * subbus.
722  */
723 static int
724 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
725 {
726 	rman_res_t old_end;
727 	int error;
728 
729 	old_end = rman_get_end(bus->res);
730 	KASSERT(new_end > old_end, ("attempt to shrink subbus"));
731 	error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
732 	    rman_get_start(bus->res), new_end);
733 	if (error)
734 		return (error);
735 	if (bootverbose)
736 		device_printf(bus->dev, "grew bus range to %ju-%ju\n",
737 		    rman_get_start(bus->res), rman_get_end(bus->res));
738 	error = rman_manage_region(&bus->rman, old_end + 1,
739 	    rman_get_end(bus->res));
740 	if (error)
741 		panic("Failed to add resource to rman");
742 	bus->sub = rman_get_end(bus->res);
743 	pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
744 	return (0);
745 }
746 
747 struct resource *
748 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
749     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
750 {
751 	struct resource *res;
752 	rman_res_t start_free, end_free, new_end;
753 
754 	/*
755 	 * First, see if the request can be satisified by the existing
756 	 * bus range.
757 	 */
758 	res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
759 	if (res != NULL)
760 		return (res);
761 
762 	/*
763 	 * Figure out a range to grow the bus range.  First, find the
764 	 * first bus number after the last allocated bus in the rman and
765 	 * enforce that as a minimum starting point for the range.
766 	 */
767 	if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
768 	    end_free != bus->sub)
769 		start_free = bus->sub + 1;
770 	if (start_free < start)
771 		start_free = start;
772 	new_end = start_free + count - 1;
773 
774 	/*
775 	 * See if this new range would satisfy the request if it
776 	 * succeeds.
777 	 */
778 	if (new_end > end)
779 		return (NULL);
780 
781 	/* Finally, attempt to grow the existing resource. */
782 	if (bootverbose) {
783 		device_printf(bus->dev,
784 		    "attempting to grow bus range for %ju buses\n", count);
785 		printf("\tback candidate range: %ju-%ju\n", start_free,
786 		    new_end);
787 	}
788 	if (pcib_grow_subbus(bus, new_end) == 0)
789 		return (pcib_suballoc_bus(bus, child, rid, start, end, count,
790 		    flags));
791 	return (NULL);
792 }
793 
794 #ifdef PCI_HP
795 /*
796  * PCI-express HotPlug support.
797  */
798 static int pci_enable_pcie_hp = 1;
799 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
800     &pci_enable_pcie_hp, 0,
801     "Enable support for native PCI-express HotPlug.");
802 
803 TASKQUEUE_DEFINE_THREAD(pci_hp);
804 
805 static void
806 pcib_probe_hotplug(struct pcib_softc *sc)
807 {
808 	device_t dev;
809 	uint32_t link_cap;
810 	uint16_t link_sta, slot_sta;
811 
812 	if (!pci_enable_pcie_hp)
813 		return;
814 
815 	dev = sc->dev;
816 	if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
817 		return;
818 
819 	if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
820 		return;
821 
822 	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
823 
824 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
825 		return;
826 	link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
827 	if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
828 		return;
829 
830 	/*
831 	 * Some devices report that they have an MRL when they actually
832 	 * do not.  Since they always report that the MRL is open, child
833 	 * devices would be ignored.  Try to detect these devices and
834 	 * ignore their claim of HotPlug support.
835 	 *
836 	 * If there is an open MRL but the Data Link Layer is active,
837 	 * the MRL is not real.
838 	 */
839 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
840 		link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
841 		slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
842 		if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
843 		    (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
844 			return;
845 		}
846 	}
847 
848 	/*
849 	 * Now that we're sure we want to do hot plug, ask the
850 	 * firmware, if any, if that's OK.
851 	 */
852 	if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
853 		if (bootverbose)
854 			device_printf(dev, "Unable to activate hot plug feature.\n");
855 		return;
856 	}
857 
858 	sc->flags |= PCIB_HOTPLUG;
859 }
860 
861 /*
862  * Send a HotPlug command to the slot control register.  If this slot
863  * uses command completion interrupts and a previous command is still
864  * in progress, then the command is dropped.  Once the previous
865  * command completes or times out, pcib_pcie_hotplug_update() will be
866  * invoked to post a new command based on the slot's state at that
867  * time.
868  */
869 static void
870 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
871 {
872 	device_t dev;
873 	uint16_t ctl, new;
874 
875 	dev = sc->dev;
876 
877 	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
878 		return;
879 
880 	ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
881 	new = (ctl & ~mask) | val;
882 	if (new == ctl)
883 		return;
884 	if (bootverbose)
885 		device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
886 	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
887 	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
888 	    (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
889 		sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
890 		if (!cold)
891 			taskqueue_enqueue_timeout(taskqueue_pci_hp,
892 			    &sc->pcie_cc_task, hz);
893 	}
894 }
895 
896 static void
897 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
898 {
899 	device_t dev;
900 
901 	dev = sc->dev;
902 
903 	if (bootverbose)
904 		device_printf(dev, "Command Completed\n");
905 	if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
906 		return;
907 	taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task, NULL);
908 	sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
909 	wakeup(sc);
910 }
911 
912 /*
913  * Returns true if a card is fully inserted from the user's
914  * perspective.  It may not yet be ready for access, but the driver
915  * can now start enabling access if necessary.
916  */
917 static bool
918 pcib_hotplug_inserted(struct pcib_softc *sc)
919 {
920 
921 	/* Pretend the card isn't present if a detach is forced. */
922 	if (sc->flags & PCIB_DETACHING)
923 		return (false);
924 
925 	/* Card must be present in the slot. */
926 	if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
927 		return (false);
928 
929 	/* A power fault implicitly turns off power to the slot. */
930 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
931 		return (false);
932 
933 	/* If the MRL is disengaged, the slot is powered off. */
934 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
935 	    (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
936 		return (false);
937 
938 	return (true);
939 }
940 
941 /*
942  * Returns -1 if the card is fully inserted, powered, and ready for
943  * access.  Otherwise, returns 0.
944  */
945 static int
946 pcib_hotplug_present(struct pcib_softc *sc)
947 {
948 
949 	/* Card must be inserted. */
950 	if (!pcib_hotplug_inserted(sc))
951 		return (0);
952 
953 	/* Require the Data Link Layer to be active. */
954 	if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
955 		return (0);
956 
957 	return (-1);
958 }
959 
960 static int pci_enable_pcie_ei = 0;
961 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_ei, CTLFLAG_RWTUN,
962     &pci_enable_pcie_ei, 0,
963     "Enable support for PCI-express Electromechanical Interlock.");
964 
965 static void
966 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
967     bool schedule_task)
968 {
969 	bool card_inserted, ei_engaged;
970 
971 	/* Clear DETACHING if Presence Detect has cleared. */
972 	if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
973 	    PCIEM_SLOT_STA_PDC)
974 		sc->flags &= ~PCIB_DETACHING;
975 
976 	card_inserted = pcib_hotplug_inserted(sc);
977 
978 	/* Turn the power indicator on if a card is inserted. */
979 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
980 		mask |= PCIEM_SLOT_CTL_PIC;
981 		if (card_inserted)
982 			val |= PCIEM_SLOT_CTL_PI_ON;
983 		else if (sc->flags & PCIB_DETACH_PENDING)
984 			val |= PCIEM_SLOT_CTL_PI_BLINK;
985 		else
986 			val |= PCIEM_SLOT_CTL_PI_OFF;
987 	}
988 
989 	/* Turn the power on via the Power Controller if a card is inserted. */
990 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
991 		mask |= PCIEM_SLOT_CTL_PCC;
992 		if (card_inserted)
993 			val |= PCIEM_SLOT_CTL_PC_ON;
994 		else
995 			val |= PCIEM_SLOT_CTL_PC_OFF;
996 	}
997 
998 	/*
999 	 * If a card is inserted, enable the Electromechanical
1000 	 * Interlock.  If a card is not inserted (or we are in the
1001 	 * process of detaching), disable the Electromechanical
1002 	 * Interlock.
1003 	 */
1004 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) &&
1005 	    pci_enable_pcie_ei) {
1006 		mask |= PCIEM_SLOT_CTL_EIC;
1007 		ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1008 		if (card_inserted != ei_engaged)
1009 			val |= PCIEM_SLOT_CTL_EIC;
1010 	}
1011 
1012 	/*
1013 	 * Start a timer to see if the Data Link Layer times out.
1014 	 * Note that we only start the timer if Presence Detect or MRL Sensor
1015 	 * changed on this interrupt.  Stop any scheduled timer if
1016 	 * the Data Link Layer is active.
1017 	 */
1018 	if (card_inserted &&
1019 	    !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1020 	    sc->pcie_slot_sta &
1021 	    (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1022 		if (cold)
1023 			device_printf(sc->dev,
1024 			    "Data Link Layer inactive\n");
1025 		else
1026 			taskqueue_enqueue_timeout(taskqueue_pci_hp,
1027 			    &sc->pcie_dll_task, hz);
1028 	} else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1029 		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_dll_task,
1030 		    NULL);
1031 
1032 	pcib_pcie_hotplug_command(sc, val, mask);
1033 
1034 	/*
1035 	 * During attach the child "pci" device is added synchronously;
1036 	 * otherwise, the task is scheduled to manage the child
1037 	 * device.
1038 	 */
1039 	if (schedule_task &&
1040 	    (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1041 		taskqueue_enqueue(taskqueue_pci_hp, &sc->pcie_hp_task);
1042 }
1043 
1044 static void
1045 pcib_pcie_intr_hotplug(void *arg)
1046 {
1047 	struct pcib_softc *sc;
1048 	device_t dev;
1049 	uint16_t old_slot_sta;
1050 
1051 	sc = arg;
1052 	dev = sc->dev;
1053 	PCIB_HP_LOCK(sc);
1054 	old_slot_sta = sc->pcie_slot_sta;
1055 	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1056 
1057 	/* Clear the events just reported. */
1058 	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1059 
1060 	if (bootverbose)
1061 		device_printf(dev, "HotPlug interrupt: %#x\n",
1062 		    sc->pcie_slot_sta);
1063 
1064 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1065 		if (sc->flags & PCIB_DETACH_PENDING) {
1066 			device_printf(dev,
1067 			    "Attention Button Pressed: Detach Cancelled\n");
1068 			sc->flags &= ~PCIB_DETACH_PENDING;
1069 			taskqueue_cancel_timeout(taskqueue_pci_hp,
1070 			    &sc->pcie_ab_task, NULL);
1071 		} else if (old_slot_sta & PCIEM_SLOT_STA_PDS) {
1072 			/* Only initiate detach sequence if device present. */
1073 			device_printf(dev,
1074 		    "Attention Button Pressed: Detaching in 5 seconds\n");
1075 			sc->flags |= PCIB_DETACH_PENDING;
1076 			taskqueue_enqueue_timeout(taskqueue_pci_hp,
1077 			    &sc->pcie_ab_task, 5 * hz);
1078 		}
1079 	}
1080 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1081 		device_printf(dev, "Power Fault Detected\n");
1082 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1083 		device_printf(dev, "MRL Sensor Changed to %s\n",
1084 		    sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1085 		    "closed");
1086 	if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1087 		device_printf(dev, "Presence Detect Changed to %s\n",
1088 		    sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1089 		    "empty");
1090 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1091 		pcib_pcie_hotplug_command_completed(sc);
1092 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1093 		sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1094 		if (bootverbose)
1095 			device_printf(dev,
1096 			    "Data Link Layer State Changed to %s\n",
1097 			    sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1098 			    "active" : "inactive");
1099 	}
1100 
1101 	pcib_pcie_hotplug_update(sc, 0, 0, true);
1102 	PCIB_HP_UNLOCK(sc);
1103 }
1104 
1105 static void
1106 pcib_pcie_hotplug_task(void *context, int pending)
1107 {
1108 	struct pcib_softc *sc;
1109 	device_t dev;
1110 
1111 	sc = context;
1112 	PCIB_HP_LOCK(sc);
1113 	dev = sc->dev;
1114 	if (pcib_hotplug_present(sc) != 0) {
1115 		if (sc->child == NULL) {
1116 			sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY);
1117 			bus_attach_children(dev);
1118 		}
1119 	} else {
1120 		if (sc->child != NULL) {
1121 			if (device_delete_child(dev, sc->child) == 0)
1122 				sc->child = NULL;
1123 		}
1124 	}
1125 	PCIB_HP_UNLOCK(sc);
1126 }
1127 
1128 static void
1129 pcib_pcie_ab_timeout(void *arg, int pending)
1130 {
1131 	struct pcib_softc *sc = arg;
1132 
1133 	PCIB_HP_LOCK(sc);
1134 	if (sc->flags & PCIB_DETACH_PENDING) {
1135 		sc->flags |= PCIB_DETACHING;
1136 		sc->flags &= ~PCIB_DETACH_PENDING;
1137 		pcib_pcie_hotplug_update(sc, 0, 0, true);
1138 	}
1139 	PCIB_HP_UNLOCK(sc);
1140 }
1141 
1142 static void
1143 pcib_pcie_cc_timeout(void *arg, int pending)
1144 {
1145 	struct pcib_softc *sc = arg;
1146 	device_t dev = sc->dev;
1147 	uint16_t sta;
1148 
1149 	PCIB_HP_LOCK(sc);
1150 	sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1151 	if (!(sta & PCIEM_SLOT_STA_CC)) {
1152 		device_printf(dev, "HotPlug Command Timed Out\n");
1153 		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1154 	} else {
1155 		device_printf(dev,
1156 	    "Missed HotPlug interrupt waiting for Command Completion\n");
1157 		pcib_pcie_intr_hotplug(sc);
1158 	}
1159 	PCIB_HP_UNLOCK(sc);
1160 }
1161 
1162 static void
1163 pcib_pcie_dll_timeout(void *arg, int pending)
1164 {
1165 	struct pcib_softc *sc = arg;
1166 	device_t dev = sc->dev;
1167 	uint16_t sta;
1168 
1169 	PCIB_HP_LOCK(sc);
1170 	sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1171 	if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1172 		device_printf(dev,
1173 		    "Timed out waiting for Data Link Layer Active\n");
1174 		sc->flags |= PCIB_DETACHING;
1175 		pcib_pcie_hotplug_update(sc, 0, 0, true);
1176 	} else if (sta != sc->pcie_link_sta) {
1177 		device_printf(dev,
1178 		    "Missed HotPlug interrupt waiting for DLL Active\n");
1179 		pcib_pcie_intr_hotplug(sc);
1180 	}
1181 	PCIB_HP_UNLOCK(sc);
1182 }
1183 
1184 static int
1185 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1186 {
1187 	device_t dev;
1188 	int count, error, mem_rid, rid;
1189 
1190 	rid = -1;
1191 	dev = sc->dev;
1192 
1193 	/*
1194 	 * For simplicity, only use MSI-X if there is a single message.
1195 	 * To support a device with multiple messages we would have to
1196 	 * use remap intr if the MSI number is not 0.
1197 	 */
1198 	count = pci_msix_count(dev);
1199 	if (count == 1) {
1200 		mem_rid = pci_msix_table_bar(dev);
1201 		sc->pcie_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1202 		    &mem_rid, RF_ACTIVE);
1203 		if (sc->pcie_mem == NULL) {
1204 			device_printf(dev,
1205 			    "Failed to allocate BAR for MSI-X table\n");
1206 		} else {
1207 			error = pci_alloc_msix(dev, &count);
1208 			if (error == 0)
1209 				rid = 1;
1210 		}
1211 	}
1212 
1213 	if (rid < 0 && pci_msi_count(dev) > 0) {
1214 		count = 1;
1215 		error = pci_alloc_msi(dev, &count);
1216 		if (error == 0)
1217 			rid = 1;
1218 	}
1219 
1220 	if (rid < 0)
1221 		rid = 0;
1222 
1223 	sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1224 	    RF_ACTIVE | RF_SHAREABLE);
1225 	if (sc->pcie_irq == NULL) {
1226 		device_printf(dev,
1227 		    "Failed to allocate interrupt for PCI-e events\n");
1228 		if (rid > 0)
1229 			pci_release_msi(dev);
1230 		return (ENXIO);
1231 	}
1232 
1233 	error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE,
1234 	    NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1235 	if (error) {
1236 		device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1237 		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1238 		if (rid > 0)
1239 			pci_release_msi(dev);
1240 		return (error);
1241 	}
1242 	return (0);
1243 }
1244 
1245 static int
1246 pcib_release_pcie_irq(struct pcib_softc *sc)
1247 {
1248 	device_t dev;
1249 	int error;
1250 
1251 	dev = sc->dev;
1252 	error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1253 	if (error)
1254 		return (error);
1255 	error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1256 	if (error)
1257 		return (error);
1258 	error = pci_release_msi(dev);
1259 	if (error)
1260 		return (error);
1261 	if (sc->pcie_mem != NULL)
1262 		error = bus_free_resource(dev, SYS_RES_MEMORY, sc->pcie_mem);
1263 	return (error);
1264 }
1265 
1266 static void
1267 pcib_setup_hotplug(struct pcib_softc *sc)
1268 {
1269 	device_t dev;
1270 	uint16_t mask, val;
1271 
1272 	dev = sc->dev;
1273 	TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1274 	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_ab_task, 0,
1275 	    pcib_pcie_ab_timeout, sc);
1276 	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_cc_task, 0,
1277 	    pcib_pcie_cc_timeout, sc);
1278 	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_dll_task, 0,
1279 	    pcib_pcie_dll_timeout, sc);
1280 	sc->pcie_hp_lock = bus_topo_mtx();
1281 
1282 	/* Allocate IRQ. */
1283 	if (pcib_alloc_pcie_irq(sc) != 0)
1284 		return;
1285 
1286 	sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1287 	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1288 
1289 	/* Clear any events previously pending. */
1290 	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1291 
1292 	/* Enable HotPlug events. */
1293 	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1294 	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1295 	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1296 	val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1297 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1298 		val |= PCIEM_SLOT_CTL_ABPE;
1299 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1300 		val |= PCIEM_SLOT_CTL_PFDE;
1301 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1302 		val |= PCIEM_SLOT_CTL_MRLSCE;
1303 	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1304 		val |= PCIEM_SLOT_CTL_CCIE;
1305 
1306 	/* Turn the attention indicator off. */
1307 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1308 		mask |= PCIEM_SLOT_CTL_AIC;
1309 		val |= PCIEM_SLOT_CTL_AI_OFF;
1310 	}
1311 
1312 	pcib_pcie_hotplug_update(sc, val, mask, false);
1313 }
1314 
1315 static int
1316 pcib_detach_hotplug(struct pcib_softc *sc)
1317 {
1318 	uint16_t mask, val;
1319 	int error;
1320 
1321 	/* Disable the card in the slot and force it to detach. */
1322 	if (sc->flags & PCIB_DETACH_PENDING) {
1323 		sc->flags &= ~PCIB_DETACH_PENDING;
1324 		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_ab_task,
1325 		    NULL);
1326 	}
1327 	sc->flags |= PCIB_DETACHING;
1328 
1329 	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1330 		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task,
1331 		    NULL);
1332 		tsleep(sc, 0, "hpcmd", hz);
1333 		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1334 	}
1335 
1336 	/* Disable HotPlug events. */
1337 	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1338 	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1339 	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1340 	val = 0;
1341 
1342 	/* Turn the attention indicator off. */
1343 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1344 		mask |= PCIEM_SLOT_CTL_AIC;
1345 		val |= PCIEM_SLOT_CTL_AI_OFF;
1346 	}
1347 
1348 	pcib_pcie_hotplug_update(sc, val, mask, false);
1349 
1350 	error = pcib_release_pcie_irq(sc);
1351 	if (error)
1352 		return (error);
1353 	taskqueue_drain(taskqueue_pci_hp, &sc->pcie_hp_task);
1354 	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_ab_task);
1355 	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_cc_task);
1356 	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_dll_task);
1357 	return (0);
1358 }
1359 #endif
1360 
1361 /*
1362  * Restore previous bridge configuration.
1363  */
1364 static void
1365 pcib_cfg_restore(struct pcib_softc *sc)
1366 {
1367 	pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1368 }
1369 
1370 /*
1371  * Generic device interface
1372  */
1373 static int
1374 pcib_probe(device_t dev)
1375 {
1376     if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1377 	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1378 	device_set_desc(dev, "PCI-PCI bridge");
1379 	return(-10000);
1380     }
1381     return(ENXIO);
1382 }
1383 
1384 void
1385 pcib_attach_common(device_t dev)
1386 {
1387     struct pcib_softc	*sc;
1388     struct sysctl_ctx_list *sctx;
1389     struct sysctl_oid	*soid;
1390     int comma;
1391 
1392     sc = device_get_softc(dev);
1393     sc->dev = dev;
1394 
1395     /*
1396      * Get current bridge configuration.
1397      */
1398     sc->domain = pci_get_domain(dev);
1399     sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1400 
1401     /*
1402      * The primary bus register should always be the bus of the
1403      * parent.
1404      */
1405     sc->pribus = pci_get_bus(dev);
1406     pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1407 
1408     /*
1409      * Setup sysctl reporting nodes
1410      */
1411     sctx = device_get_sysctl_ctx(dev);
1412     soid = device_get_sysctl_tree(dev);
1413     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1414       CTLFLAG_RD, &sc->domain, 0, "Domain number");
1415     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1416       CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1417     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1418       CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1419     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1420       CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1421 
1422     /*
1423      * Quirk handling.
1424      */
1425     switch (pci_get_devid(dev)) {
1426     /*
1427      * The i82380FB mobile docking controller is a PCI-PCI bridge,
1428      * and it is a subtractive bridge.  However, the ProgIf is wrong
1429      * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1430      * happen.  There are also Toshiba and Cavium ThunderX bridges
1431      * that behave this way.
1432      */
1433     case 0xa002177d:		/* Cavium ThunderX */
1434     case 0x124b8086:		/* Intel 82380FB Mobile */
1435     case 0x060513d7:		/* Toshiba ???? */
1436 	sc->flags |= PCIB_SUBTRACTIVE;
1437 	break;
1438     }
1439 
1440     if (pci_msi_device_blacklisted(dev))
1441 	sc->flags |= PCIB_DISABLE_MSI;
1442 
1443     if (pci_msix_device_blacklisted(dev))
1444 	sc->flags |= PCIB_DISABLE_MSIX;
1445 
1446     /*
1447      * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1448      * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
1449      * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1450      * This means they act as if they were subtractively decoding
1451      * bridges and pass all transactions.  Mark them and real ProgIf 1
1452      * parts as subtractive.
1453      */
1454     if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1455       pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1456 	sc->flags |= PCIB_SUBTRACTIVE;
1457 
1458 #ifdef PCI_HP
1459     pcib_probe_hotplug(sc);
1460 #endif
1461     pcib_setup_secbus(dev, &sc->bus, 1);
1462     pcib_probe_windows(sc);
1463 #ifdef PCI_HP
1464     if (sc->flags & PCIB_HOTPLUG)
1465 	    pcib_setup_hotplug(sc);
1466 #endif
1467     if (bootverbose) {
1468 	device_printf(dev, "  domain            %d\n", sc->domain);
1469 	device_printf(dev, "  secondary bus     %d\n", sc->bus.sec);
1470 	device_printf(dev, "  subordinate bus   %d\n", sc->bus.sub);
1471 	if (pcib_is_window_open(&sc->io))
1472 	    device_printf(dev, "  I/O decode        0x%jx-0x%jx\n",
1473 	      (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1474 	if (pcib_is_window_open(&sc->mem))
1475 	    device_printf(dev, "  memory decode     0x%jx-0x%jx\n",
1476 	      (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1477 	if (pcib_is_window_open(&sc->pmem))
1478 	    device_printf(dev, "  prefetched decode 0x%jx-0x%jx\n",
1479 	      (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1480 	if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1481 	    sc->flags & PCIB_SUBTRACTIVE) {
1482 		device_printf(dev, "  special decode    ");
1483 		comma = 0;
1484 		if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1485 			printf("ISA");
1486 			comma = 1;
1487 		}
1488 		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1489 			printf("%sVGA", comma ? ", " : "");
1490 			comma = 1;
1491 		}
1492 		if (sc->flags & PCIB_SUBTRACTIVE)
1493 			printf("%ssubtractive", comma ? ", " : "");
1494 		printf("\n");
1495 	}
1496     }
1497 
1498     /*
1499      * Always enable busmastering on bridges so that transactions
1500      * initiated on the secondary bus are passed through to the
1501      * primary bus.
1502      */
1503     pci_enable_busmaster(dev);
1504 }
1505 
1506 #ifdef PCI_HP
1507 static int
1508 pcib_present(struct pcib_softc *sc)
1509 {
1510 
1511 	if (sc->flags & PCIB_HOTPLUG)
1512 		return (pcib_hotplug_present(sc) != 0);
1513 	return (1);
1514 }
1515 #endif
1516 
1517 int
1518 pcib_attach_child(device_t dev)
1519 {
1520 	struct pcib_softc *sc;
1521 
1522 	sc = device_get_softc(dev);
1523 	if (sc->bus.sec == 0) {
1524 		/* no secondary bus; we should have fixed this */
1525 		return(0);
1526 	}
1527 
1528 #ifdef PCI_HP
1529 	if (!pcib_present(sc)) {
1530 		/* An empty HotPlug slot, so don't add a PCI bus yet. */
1531 		return (0);
1532 	}
1533 #endif
1534 
1535 	sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY);
1536 	bus_attach_children(dev);
1537 	return (0);
1538 }
1539 
1540 int
1541 pcib_attach(device_t dev)
1542 {
1543 
1544     pcib_attach_common(dev);
1545     return (pcib_attach_child(dev));
1546 }
1547 
1548 int
1549 pcib_detach(device_t dev)
1550 {
1551 	struct pcib_softc *sc;
1552 	int error;
1553 
1554 	sc = device_get_softc(dev);
1555 	error = bus_generic_detach(dev);
1556 	if (error)
1557 		return (error);
1558 #ifdef PCI_HP
1559 	if (sc->flags & PCIB_HOTPLUG) {
1560 		error = pcib_detach_hotplug(sc);
1561 		if (error)
1562 			return (error);
1563 	}
1564 #endif
1565 	error = device_delete_children(dev);
1566 	if (error)
1567 		return (error);
1568 	pcib_free_windows(sc);
1569 	pcib_free_secbus(dev, &sc->bus);
1570 	return (0);
1571 }
1572 
1573 int
1574 pcib_resume(device_t dev)
1575 {
1576 
1577 	pcib_cfg_restore(device_get_softc(dev));
1578 
1579 	/*
1580 	 * Restore the Command register only after restoring the windows.
1581 	 * The bridge should not be claiming random windows.
1582 	 */
1583 	pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2);
1584 	return (bus_generic_resume(dev));
1585 }
1586 
1587 void
1588 pcib_bridge_init(device_t dev)
1589 {
1590 	pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1591 	pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1592 	pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1593 	pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1594 	pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1595 	pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1596 	pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1597 	pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1598 	pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1599 	pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1600 }
1601 
1602 int
1603 pcib_child_present(device_t dev, device_t child)
1604 {
1605 #ifdef PCI_HP
1606 	struct pcib_softc *sc = device_get_softc(dev);
1607 	int retval;
1608 
1609 	retval = bus_child_present(dev);
1610 	if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1611 		retval = pcib_hotplug_present(sc);
1612 	return (retval);
1613 #else
1614 	return (bus_child_present(dev));
1615 #endif
1616 }
1617 
1618 int
1619 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1620 {
1621     struct pcib_softc	*sc = device_get_softc(dev);
1622 
1623     switch (which) {
1624     case PCIB_IVAR_DOMAIN:
1625 	*result = sc->domain;
1626 	return(0);
1627     case PCIB_IVAR_BUS:
1628 	*result = sc->bus.sec;
1629 	return(0);
1630     }
1631     return(ENOENT);
1632 }
1633 
1634 int
1635 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1636 {
1637 
1638     switch (which) {
1639     case PCIB_IVAR_DOMAIN:
1640 	return(EINVAL);
1641     case PCIB_IVAR_BUS:
1642 	return(EINVAL);
1643     }
1644     return(ENOENT);
1645 }
1646 
1647 /*
1648  * Attempt to allocate a resource from the existing resources assigned
1649  * to a window.
1650  */
1651 static struct resource *
1652 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1653     device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1654     rman_res_t count, u_int flags)
1655 {
1656 	struct resource *res;
1657 
1658 	if (!pcib_is_window_open(w))
1659 		return (NULL);
1660 
1661 	res = rman_reserve_resource(&w->rman, start, end, count,
1662 	    flags & ~RF_ACTIVE, child);
1663 	if (res == NULL)
1664 		return (NULL);
1665 
1666 	if (bootverbose)
1667 		device_printf(sc->dev,
1668 		    "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1669 		    w->name, rman_get_start(res), rman_get_end(res), *rid,
1670 		    pcib_child_name(child));
1671 	rman_set_rid(res, *rid);
1672 	rman_set_type(res, type);
1673 
1674 	if (flags & RF_ACTIVE) {
1675 		if (bus_activate_resource(child, type, *rid, res) != 0) {
1676 			rman_release_resource(res);
1677 			return (NULL);
1678 		}
1679 	}
1680 
1681 	return (res);
1682 }
1683 
1684 /* Allocate a fresh resource range for an unconfigured window. */
1685 static int
1686 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1687     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1688 {
1689 	struct resource *res;
1690 	rman_res_t base, limit, wmask;
1691 	int rid;
1692 
1693 	/*
1694 	 * If this is an I/O window on a bridge with ISA enable set
1695 	 * and the start address is below 64k, then try to allocate an
1696 	 * initial window of 0x1000 bytes long starting at address
1697 	 * 0xf000 and walking down.  Note that if the original request
1698 	 * was larger than the non-aliased range size of 0x100 our
1699 	 * caller would have raised the start address up to 64k
1700 	 * already.
1701 	 */
1702 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1703 	    start < 65536) {
1704 		for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1705 			limit = base + 0xfff;
1706 
1707 			/*
1708 			 * Skip ranges that wouldn't work for the
1709 			 * original request.  Note that the actual
1710 			 * window that overlaps are the non-alias
1711 			 * ranges within [base, limit], so this isn't
1712 			 * quite a simple comparison.
1713 			 */
1714 			if (start + count > limit - 0x400)
1715 				continue;
1716 			if (base == 0) {
1717 				/*
1718 				 * The first open region for the window at
1719 				 * 0 is 0x400-0x4ff.
1720 				 */
1721 				if (end - count + 1 < 0x400)
1722 					continue;
1723 			} else {
1724 				if (end - count + 1 < base)
1725 					continue;
1726 			}
1727 
1728 			if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1729 				w->base = base;
1730 				w->limit = limit;
1731 				return (0);
1732 			}
1733 		}
1734 		return (ENOSPC);
1735 	}
1736 
1737 	wmask = ((rman_res_t)1 << w->step) - 1;
1738 	if (RF_ALIGNMENT(flags) < w->step) {
1739 		flags &= ~RF_ALIGNMENT_MASK;
1740 		flags |= RF_ALIGNMENT_LOG2(w->step);
1741 	}
1742 	start &= ~wmask;
1743 	end |= wmask;
1744 	count = roundup2(count, (rman_res_t)1 << w->step);
1745 	rid = w->reg;
1746 	res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1747 	    flags | RF_ACTIVE | RF_UNMAPPED);
1748 	if (res == NULL)
1749 		return (ENOSPC);
1750 	pcib_add_window_resources(w, &res, 1);
1751 	pcib_activate_window(sc, type);
1752 	w->base = rman_get_start(res);
1753 	w->limit = rman_get_end(res);
1754 	return (0);
1755 }
1756 
1757 /* Try to expand an existing window to the requested base and limit. */
1758 static int
1759 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1760     rman_res_t base, rman_res_t limit)
1761 {
1762 	struct resource *res;
1763 	int error, i, force_64k_base;
1764 
1765 	KASSERT(base <= w->base && limit >= w->limit,
1766 	    ("attempting to shrink window"));
1767 
1768 	/*
1769 	 * XXX: pcib_grow_window() doesn't try to do this anyway and
1770 	 * the error handling for all the edge cases would be tedious.
1771 	 */
1772 	KASSERT(limit == w->limit || base == w->base,
1773 	    ("attempting to grow both ends of a window"));
1774 
1775 	/*
1776 	 * Yet more special handling for requests to expand an I/O
1777 	 * window behind an ISA-enabled bridge.  Since I/O windows
1778 	 * have to grow in 0x1000 increments and the end of the 0xffff
1779 	 * range is an alias, growing a window below 64k will always
1780 	 * result in allocating new resources and never adjusting an
1781 	 * existing resource.
1782 	 */
1783 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1784 	    (limit <= 65535 || (base <= 65535 && base != w->base))) {
1785 		KASSERT(limit == w->limit || limit <= 65535,
1786 		    ("attempting to grow both ends across 64k ISA alias"));
1787 
1788 		if (base != w->base)
1789 			error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1790 		else
1791 			error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1792 			    limit);
1793 		if (error == 0) {
1794 			w->base = base;
1795 			w->limit = limit;
1796 		}
1797 		return (error);
1798 	}
1799 
1800 	/*
1801 	 * Find the existing resource to adjust.  Usually there is only one,
1802 	 * but for an ISA-enabled bridge we might be growing the I/O window
1803 	 * above 64k and need to find the existing resource that maps all
1804 	 * of the area above 64k.
1805 	 */
1806 	for (i = 0; i < w->count; i++) {
1807 		if (rman_get_end(w->res[i]) == w->limit)
1808 			break;
1809 	}
1810 	KASSERT(i != w->count, ("did not find existing resource"));
1811 	res = w->res[i];
1812 
1813 	/*
1814 	 * Usually the resource we found should match the window's
1815 	 * existing range.  The one exception is the ISA-enabled case
1816 	 * mentioned above in which case the resource should start at
1817 	 * 64k.
1818 	 */
1819 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1820 	    w->base <= 65535) {
1821 		KASSERT(rman_get_start(res) == 65536,
1822 		    ("existing resource mismatch"));
1823 		force_64k_base = 1;
1824 	} else {
1825 		KASSERT(w->base == rman_get_start(res),
1826 		    ("existing resource mismatch"));
1827 		force_64k_base = 0;
1828 	}
1829 
1830 	error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1831 	    rman_get_start(res) : base, limit);
1832 	if (error)
1833 		return (error);
1834 
1835 	/* Add the newly allocated region to the resource manager. */
1836 	if (w->base != base) {
1837 		error = rman_manage_region(&w->rman, base, w->base - 1);
1838 		w->base = base;
1839 	} else {
1840 		error = rman_manage_region(&w->rman, w->limit + 1, limit);
1841 		w->limit = limit;
1842 	}
1843 	if (error) {
1844 		if (bootverbose)
1845 			device_printf(sc->dev,
1846 			    "failed to expand %s resource manager\n", w->name);
1847 		(void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1848 		    rman_get_start(res) : w->base, w->limit);
1849 	}
1850 	return (error);
1851 }
1852 
1853 /*
1854  * Attempt to grow a window to make room for a given resource request.
1855  */
1856 static int
1857 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1858     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1859 {
1860 	rman_res_t align, start_free, end_free, front, back, wmask;
1861 	int error;
1862 
1863 	/*
1864 	 * Clamp the desired resource range to the maximum address
1865 	 * this window supports.  Reject impossible requests.
1866 	 *
1867 	 * For I/O port requests behind a bridge with the ISA enable
1868 	 * bit set, force large allocations to start above 64k.
1869 	 */
1870 	if (!w->valid)
1871 		return (EINVAL);
1872 	if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
1873 	    start < 65536)
1874 		start = 65536;
1875 	if (end > w->rman.rm_end)
1876 		end = w->rman.rm_end;
1877 	if (start + count - 1 > end || start + count < start)
1878 		return (EINVAL);
1879 	wmask = ((rman_res_t)1 << w->step) - 1;
1880 
1881 	/*
1882 	 * If there is no resource at all, just try to allocate enough
1883 	 * aligned space for this resource.
1884 	 */
1885 	if (w->res == NULL) {
1886 		error = pcib_alloc_new_window(sc, w, type, start, end, count,
1887 		    flags);
1888 		if (error) {
1889 			if (bootverbose)
1890 				device_printf(sc->dev,
1891 		    "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
1892 				    w->name, start, end, count);
1893 			return (error);
1894 		}
1895 		if (bootverbose)
1896 			device_printf(sc->dev,
1897 			    "allocated initial %s window of %#jx-%#jx\n",
1898 			    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1899 		goto updatewin;
1900 	}
1901 
1902 	/*
1903 	 * See if growing the window would help.  Compute the minimum
1904 	 * amount of address space needed on both the front and back
1905 	 * ends of the existing window to satisfy the allocation.
1906 	 *
1907 	 * For each end, build a candidate region adjusting for the
1908 	 * required alignment, etc.  If there is a free region at the
1909 	 * edge of the window, grow from the inner edge of the free
1910 	 * region.  Otherwise grow from the window boundary.
1911 	 *
1912 	 * Growing an I/O window below 64k for a bridge with the ISA
1913 	 * enable bit doesn't require any special magic as the step
1914 	 * size of an I/O window (1k) always includes multiple
1915 	 * non-alias ranges when it is grown in either direction.
1916 	 *
1917 	 * XXX: Special case: if w->res is completely empty and the
1918 	 * request size is larger than w->res, we should find the
1919 	 * optimal aligned buffer containing w->res and allocate that.
1920 	 */
1921 	if (bootverbose)
1922 		device_printf(sc->dev,
1923 		    "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
1924 		    w->name, start, end, count);
1925 	align = (rman_res_t)1 << RF_ALIGNMENT(flags);
1926 	if (start < w->base) {
1927 		if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
1928 		    0 || start_free != w->base)
1929 			end_free = w->base;
1930 		if (end_free > end)
1931 			end_free = end + 1;
1932 
1933 		/* Move end_free down until it is properly aligned. */
1934 		end_free &= ~(align - 1);
1935 		end_free--;
1936 		front = end_free - (count - 1);
1937 
1938 		/*
1939 		 * The resource would now be allocated at (front,
1940 		 * end_free).  Ensure that fits in the (start, end)
1941 		 * bounds.  end_free is checked above.  If 'front' is
1942 		 * ok, ensure it is properly aligned for this window.
1943 		 * Also check for underflow.
1944 		 */
1945 		if (front >= start && front <= end_free) {
1946 			if (bootverbose)
1947 				printf("\tfront candidate range: %#jx-%#jx\n",
1948 				    front, end_free);
1949 			front &= ~wmask;
1950 			front = w->base - front;
1951 		} else
1952 			front = 0;
1953 	} else
1954 		front = 0;
1955 	if (end > w->limit) {
1956 		if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
1957 		    0 || end_free != w->limit)
1958 			start_free = w->limit + 1;
1959 		if (start_free < start)
1960 			start_free = start;
1961 
1962 		/* Move start_free up until it is properly aligned. */
1963 		start_free = roundup2(start_free, align);
1964 		back = start_free + count - 1;
1965 
1966 		/*
1967 		 * The resource would now be allocated at (start_free,
1968 		 * back).  Ensure that fits in the (start, end)
1969 		 * bounds.  start_free is checked above.  If 'back' is
1970 		 * ok, ensure it is properly aligned for this window.
1971 		 * Also check for overflow.
1972 		 */
1973 		if (back <= end && start_free <= back) {
1974 			if (bootverbose)
1975 				printf("\tback candidate range: %#jx-%#jx\n",
1976 				    start_free, back);
1977 			back |= wmask;
1978 			back -= w->limit;
1979 		} else
1980 			back = 0;
1981 	} else
1982 		back = 0;
1983 
1984 	/*
1985 	 * Try to allocate the smallest needed region first.
1986 	 * If that fails, fall back to the other region.
1987 	 */
1988 	error = ENOSPC;
1989 	while (front != 0 || back != 0) {
1990 		if (front != 0 && (front <= back || back == 0)) {
1991 			error = pcib_expand_window(sc, w, type, w->base - front,
1992 			    w->limit);
1993 			if (error == 0)
1994 				break;
1995 			front = 0;
1996 		} else {
1997 			error = pcib_expand_window(sc, w, type, w->base,
1998 			    w->limit + back);
1999 			if (error == 0)
2000 				break;
2001 			back = 0;
2002 		}
2003 	}
2004 
2005 	if (error)
2006 		return (error);
2007 	if (bootverbose)
2008 		device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2009 		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2010 
2011 updatewin:
2012 	/* Write the new window. */
2013 	KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2014 	KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2015 	pcib_write_windows(sc, w->mask);
2016 	return (0);
2017 }
2018 
2019 /*
2020  * We have to trap resource allocation requests and ensure that the bridge
2021  * is set up to, or capable of handling them.
2022  */
2023 static struct resource *
2024 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2025     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2026 {
2027 	struct pcib_softc *sc;
2028 	struct resource *r;
2029 
2030 	sc = device_get_softc(dev);
2031 
2032 	/*
2033 	 * VGA resources are decoded iff the VGA enable bit is set in
2034 	 * the bridge control register.  VGA resources do not fall into
2035 	 * the resource windows and are passed up to the parent.
2036 	 */
2037 	if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2038 	    (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2039 		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2040 			return (bus_generic_alloc_resource(dev, child, type,
2041 			    rid, start, end, count, flags));
2042 		else
2043 			return (NULL);
2044 	}
2045 
2046 	switch (type) {
2047 	case PCI_RES_BUS:
2048 		return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2049 		    count, flags));
2050 	case SYS_RES_IOPORT:
2051 		if (pcib_is_isa_range(sc, start, end, count))
2052 			return (NULL);
2053 		r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2054 		    end, count, flags);
2055 		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2056 			break;
2057 		if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2058 		    flags) == 0)
2059 			r = pcib_suballoc_resource(sc, &sc->io, child, type,
2060 			    rid, start, end, count, flags);
2061 		break;
2062 	case SYS_RES_MEMORY:
2063 		/*
2064 		 * For prefetchable resources, prefer the prefetchable
2065 		 * memory window, but fall back to the regular memory
2066 		 * window if that fails.  Try both windows before
2067 		 * attempting to grow a window in case the firmware
2068 		 * has used a range in the regular memory window to
2069 		 * map a prefetchable BAR.
2070 		 */
2071 		if (flags & RF_PREFETCHABLE) {
2072 			r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2073 			    rid, start, end, count, flags);
2074 			if (r != NULL)
2075 				break;
2076 		}
2077 		r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2078 		    start, end, count, flags);
2079 		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2080 			break;
2081 		if (flags & RF_PREFETCHABLE) {
2082 			if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2083 			    count, flags) == 0) {
2084 				r = pcib_suballoc_resource(sc, &sc->pmem, child,
2085 				    type, rid, start, end, count, flags);
2086 				if (r != NULL)
2087 					break;
2088 			}
2089 		}
2090 		if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2091 		    flags & ~RF_PREFETCHABLE) == 0)
2092 			r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2093 			    rid, start, end, count, flags);
2094 		break;
2095 	default:
2096 		return (bus_generic_alloc_resource(dev, child, type, rid,
2097 		    start, end, count, flags));
2098 	}
2099 
2100 	/*
2101 	 * If attempts to suballocate from the window fail but this is a
2102 	 * subtractive bridge, pass the request up the tree.
2103 	 */
2104 	if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2105 		return (bus_generic_alloc_resource(dev, child, type, rid,
2106 		    start, end, count, flags));
2107 	return (r);
2108 }
2109 
2110 static int
2111 pcib_adjust_resource(device_t bus, device_t child, struct resource *r,
2112     rman_res_t start, rman_res_t end)
2113 {
2114 	struct pcib_softc *sc;
2115 	struct pcib_window *w;
2116 	rman_res_t wmask;
2117 	int error, type;
2118 
2119 	sc = device_get_softc(bus);
2120 	type = rman_get_type(r);
2121 
2122 	/*
2123 	 * If the resource wasn't sub-allocated from one of our region
2124 	 * managers then just pass the request up.
2125 	 */
2126 	if (!pcib_is_resource_managed(sc, r))
2127 		return (bus_generic_adjust_resource(bus, child, r, start, end));
2128 
2129 	if (type == PCI_RES_BUS) {
2130 		/*
2131 		 * If our bus range isn't big enough to grow the sub-allocation
2132 		 * then we need to grow our bus range. Any request that would
2133 		 * require us to decrease the start of our own bus range is
2134 		 * invalid, we can only extend the end; ignore such requests
2135 		 * and let rman_adjust_resource fail below.
2136 		 */
2137 		if (start >= sc->bus.sec && end > sc->bus.sub) {
2138 			error = pcib_grow_subbus(&sc->bus, end);
2139 			if (error != 0)
2140 				return (error);
2141 		}
2142 	} else {
2143 		/*
2144 		 * Resource is managed and not a secondary bus number, must
2145 		 * be from one of our windows.
2146 		 */
2147 		w = pcib_get_resource_window(sc, r);
2148 		KASSERT(w != NULL,
2149 		    ("%s: no window for resource (%#jx-%#jx) type %d",
2150 		    __func__, rman_get_start(r), rman_get_end(r), type));
2151 
2152 		/*
2153 		 * If our window isn't big enough to grow the sub-allocation
2154 		 * then we need to expand the window.
2155 		 */
2156 		if (start < w->base || end > w->limit) {
2157 			wmask = ((rman_res_t)1 << w->step) - 1;
2158 			error = pcib_expand_window(sc, w, type,
2159 			    MIN(start & ~wmask, w->base),
2160 			    MAX(end | wmask, w->limit));
2161 			if (error != 0)
2162 				return (error);
2163 			if (bootverbose)
2164 				device_printf(sc->dev,
2165 				    "grew %s window to %#jx-%#jx\n",
2166 				    w->name, (uintmax_t)w->base,
2167 				    (uintmax_t)w->limit);
2168 			pcib_write_windows(sc, w->mask);
2169 		}
2170 	}
2171 
2172 	return (rman_adjust_resource(r, start, end));
2173 }
2174 
2175 static int
2176 pcib_release_resource(device_t dev, device_t child, struct resource *r)
2177 {
2178 	struct pcib_softc *sc;
2179 	int error;
2180 
2181 	sc = device_get_softc(dev);
2182 	if (pcib_is_resource_managed(sc, r)) {
2183 		if (rman_get_flags(r) & RF_ACTIVE) {
2184 			error = bus_deactivate_resource(child, r);
2185 			if (error)
2186 				return (error);
2187 		}
2188 		return (rman_release_resource(r));
2189 	}
2190 	return (bus_generic_release_resource(dev, child, r));
2191 }
2192 
2193 static int
2194 pcib_activate_resource(device_t dev, device_t child, struct resource *r)
2195 {
2196 	struct pcib_softc *sc = device_get_softc(dev);
2197 	struct resource_map map;
2198 	int error, type;
2199 
2200 	if (!pcib_is_resource_managed(sc, r))
2201 		return (bus_generic_activate_resource(dev, child, r));
2202 
2203 	error = rman_activate_resource(r);
2204 	if (error != 0)
2205 		return (error);
2206 
2207 	type = rman_get_type(r);
2208 	if ((rman_get_flags(r) & RF_UNMAPPED) == 0 &&
2209 	    (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) {
2210 		error = BUS_MAP_RESOURCE(dev, child, r, NULL, &map);
2211 		if (error != 0) {
2212 			rman_deactivate_resource(r);
2213 			return (error);
2214 		}
2215 
2216 		rman_set_mapping(r, &map);
2217 	}
2218 	return (0);
2219 }
2220 
2221 static int
2222 pcib_deactivate_resource(device_t dev, device_t child, struct resource *r)
2223 {
2224 	struct pcib_softc *sc = device_get_softc(dev);
2225 	struct resource_map map;
2226 	int error, type;
2227 
2228 	if (!pcib_is_resource_managed(sc, r))
2229 		return (bus_generic_deactivate_resource(dev, child, r));
2230 
2231 	error = rman_deactivate_resource(r);
2232 	if (error != 0)
2233 		return (error);
2234 
2235 	type = rman_get_type(r);
2236 	if ((rman_get_flags(r) & RF_UNMAPPED) == 0 &&
2237 	    (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) {
2238 		rman_get_mapping(r, &map);
2239 		BUS_UNMAP_RESOURCE(dev, child, r, &map);
2240 	}
2241 	return (0);
2242 }
2243 
2244 static struct resource *
2245 pcib_find_parent_resource(struct pcib_window *w, struct resource *r)
2246 {
2247 	for (int i = 0; i < w->count; i++) {
2248 		if (rman_get_start(w->res[i]) <= rman_get_start(r) &&
2249 		    rman_get_end(w->res[i]) >= rman_get_end(r))
2250 			return (w->res[i]);
2251 	}
2252 	return (NULL);
2253 }
2254 
2255 static int
2256 pcib_map_resource(device_t dev, device_t child, struct resource *r,
2257     struct resource_map_request *argsp, struct resource_map *map)
2258 {
2259 	struct pcib_softc *sc = device_get_softc(dev);
2260 	struct resource_map_request args;
2261 	struct pcib_window *w;
2262 	struct resource *pres;
2263 	rman_res_t length, start;
2264 	int error;
2265 
2266 	w = pcib_get_resource_window(sc, r);
2267 	if (w == NULL)
2268 		return (bus_generic_map_resource(dev, child, r, argsp, map));
2269 
2270 	/* Resources must be active to be mapped. */
2271 	if (!(rman_get_flags(r) & RF_ACTIVE))
2272 		return (ENXIO);
2273 
2274 	resource_init_map_request(&args);
2275 	error = resource_validate_map_request(r, argsp, &args, &start, &length);
2276 	if (error)
2277 		return (error);
2278 
2279 	pres = pcib_find_parent_resource(w, r);
2280 	if (pres == NULL)
2281 		return (ENOENT);
2282 
2283 	args.offset = start - rman_get_start(pres);
2284 	args.length = length;
2285 	return (bus_map_resource(dev, pres, &args, map));
2286 }
2287 
2288 static int
2289 pcib_unmap_resource(device_t dev, device_t child, struct resource *r,
2290     struct resource_map *map)
2291 {
2292 	struct pcib_softc *sc = device_get_softc(dev);
2293 	struct pcib_window *w;
2294 	struct resource *pres;
2295 
2296 	w = pcib_get_resource_window(sc, r);
2297 	if (w == NULL)
2298 		return (bus_generic_unmap_resource(dev, child, r, map));
2299 
2300 	pres = pcib_find_parent_resource(w, r);
2301 	if (pres == NULL)
2302 		return (ENOENT);
2303 	return (bus_unmap_resource(dev, pres, map));
2304 }
2305 
2306 /*
2307  * If ARI is enabled on this downstream port, translate the function number
2308  * to the non-ARI slot/function.  The downstream port will convert it back in
2309  * hardware.  If ARI is not enabled slot and func are not modified.
2310  */
2311 static __inline void
2312 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2313 {
2314 	struct pcib_softc *sc;
2315 	int ari_func;
2316 
2317 	sc = device_get_softc(pcib);
2318 	ari_func = *func;
2319 
2320 	if (sc->flags & PCIB_ENABLE_ARI) {
2321 		KASSERT(*slot == 0,
2322 		    ("Non-zero slot number with ARI enabled!"));
2323 		*slot = PCIE_ARI_SLOT(ari_func);
2324 		*func = PCIE_ARI_FUNC(ari_func);
2325 	}
2326 }
2327 
2328 static void
2329 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2330 {
2331 	uint32_t ctl2;
2332 
2333 	ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2334 	ctl2 |= PCIEM_CTL2_ARI;
2335 	pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2336 
2337 	sc->flags |= PCIB_ENABLE_ARI;
2338 }
2339 
2340 /*
2341  * PCIB interface.
2342  */
2343 int
2344 pcib_maxslots(device_t dev)
2345 {
2346 #if !defined(__amd64__) && !defined(__i386__)
2347 	uint32_t pcie_pos;
2348 	uint16_t val;
2349 
2350 	/*
2351 	 * If this is a PCIe rootport or downstream switch port, there's only
2352 	 * one slot permitted.
2353 	 */
2354 	if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2355 		val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2356 		val &= PCIEM_FLAGS_TYPE;
2357 		if (val == PCIEM_TYPE_ROOT_PORT ||
2358 		    val == PCIEM_TYPE_DOWNSTREAM_PORT)
2359 			return (0);
2360 	}
2361 #endif
2362 	return (PCI_SLOTMAX);
2363 }
2364 
2365 static int
2366 pcib_ari_maxslots(device_t dev)
2367 {
2368 	struct pcib_softc *sc;
2369 
2370 	sc = device_get_softc(dev);
2371 
2372 	if (sc->flags & PCIB_ENABLE_ARI)
2373 		return (PCIE_ARI_SLOTMAX);
2374 	else
2375 		return (pcib_maxslots(dev));
2376 }
2377 
2378 static int
2379 pcib_ari_maxfuncs(device_t dev)
2380 {
2381 	struct pcib_softc *sc;
2382 
2383 	sc = device_get_softc(dev);
2384 
2385 	if (sc->flags & PCIB_ENABLE_ARI)
2386 		return (PCIE_ARI_FUNCMAX);
2387 	else
2388 		return (PCI_FUNCMAX);
2389 }
2390 
2391 static void
2392 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2393     int *func)
2394 {
2395 	struct pcib_softc *sc;
2396 
2397 	sc = device_get_softc(pcib);
2398 
2399 	*bus = PCI_RID2BUS(rid);
2400 	if (sc->flags & PCIB_ENABLE_ARI) {
2401 		*slot = PCIE_ARI_RID2SLOT(rid);
2402 		*func = PCIE_ARI_RID2FUNC(rid);
2403 	} else {
2404 		*slot = PCI_RID2SLOT(rid);
2405 		*func = PCI_RID2FUNC(rid);
2406 	}
2407 }
2408 
2409 /*
2410  * Since we are a child of a PCI bus, its parent must support the pcib interface.
2411  */
2412 static uint32_t
2413 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2414 {
2415 #ifdef PCI_HP
2416 	struct pcib_softc *sc;
2417 
2418 	sc = device_get_softc(dev);
2419 	if (!pcib_present(sc)) {
2420 		switch (width) {
2421 		case 2:
2422 			return (0xffff);
2423 		case 1:
2424 			return (0xff);
2425 		default:
2426 			return (0xffffffff);
2427 		}
2428 	}
2429 #endif
2430 	pcib_xlate_ari(dev, b, &s, &f);
2431 	return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2432 	    f, reg, width));
2433 }
2434 
2435 static void
2436 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2437 {
2438 #ifdef PCI_HP
2439 	struct pcib_softc *sc;
2440 
2441 	sc = device_get_softc(dev);
2442 	if (!pcib_present(sc))
2443 		return;
2444 #endif
2445 	pcib_xlate_ari(dev, b, &s, &f);
2446 	PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2447 	    reg, val, width);
2448 }
2449 
2450 /*
2451  * Route an interrupt across a PCI bridge.
2452  */
2453 int
2454 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2455 {
2456     device_t	bus;
2457     int		parent_intpin;
2458     int		intnum;
2459 
2460     /*
2461      *
2462      * The PCI standard defines a swizzle of the child-side device/intpin to
2463      * the parent-side intpin as follows.
2464      *
2465      * device = device on child bus
2466      * child_intpin = intpin on child bus slot (0-3)
2467      * parent_intpin = intpin on parent bus slot (0-3)
2468      *
2469      * parent_intpin = (device + child_intpin) % 4
2470      */
2471     parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2472 
2473     /*
2474      * Our parent is a PCI bus.  Its parent must export the pcib interface
2475      * which includes the ability to route interrupts.
2476      */
2477     bus = device_get_parent(pcib);
2478     intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2479     if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2480 	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2481 	    pci_get_slot(dev), 'A' + pin - 1, intnum);
2482     }
2483     return(intnum);
2484 }
2485 
2486 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2487 int
2488 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2489 {
2490 	struct pcib_softc *sc = device_get_softc(pcib);
2491 	device_t bus;
2492 
2493 	if (sc->flags & PCIB_DISABLE_MSI)
2494 		return (ENXIO);
2495 	bus = device_get_parent(pcib);
2496 	return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2497 	    irqs));
2498 }
2499 
2500 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2501 int
2502 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2503 {
2504 	device_t bus;
2505 
2506 	bus = device_get_parent(pcib);
2507 	return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2508 }
2509 
2510 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2511 int
2512 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2513 {
2514 	struct pcib_softc *sc = device_get_softc(pcib);
2515 	device_t bus;
2516 
2517 	if (sc->flags & PCIB_DISABLE_MSIX)
2518 		return (ENXIO);
2519 	bus = device_get_parent(pcib);
2520 	return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2521 }
2522 
2523 /* Pass request to release an MSI-X message up to the parent bridge. */
2524 int
2525 pcib_release_msix(device_t pcib, device_t dev, int irq)
2526 {
2527 	device_t bus;
2528 
2529 	bus = device_get_parent(pcib);
2530 	return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2531 }
2532 
2533 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2534 int
2535 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2536     uint32_t *data)
2537 {
2538 	device_t bus;
2539 	int error;
2540 
2541 	bus = device_get_parent(pcib);
2542 	error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2543 	if (error)
2544 		return (error);
2545 
2546 	pci_ht_map_msi(pcib, *addr);
2547 	return (0);
2548 }
2549 
2550 /* Pass request for device power state up to parent bridge. */
2551 int
2552 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2553 {
2554 	device_t bus;
2555 
2556 	bus = device_get_parent(pcib);
2557 	return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2558 }
2559 
2560 static int
2561 pcib_ari_enabled(device_t pcib)
2562 {
2563 	struct pcib_softc *sc;
2564 
2565 	sc = device_get_softc(pcib);
2566 
2567 	return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2568 }
2569 
2570 static int
2571 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2572     uintptr_t *id)
2573 {
2574 	struct pcib_softc *sc;
2575 	device_t bus_dev;
2576 	uint8_t bus, slot, func;
2577 
2578 	if (type != PCI_ID_RID) {
2579 		bus_dev = device_get_parent(pcib);
2580 		return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2581 	}
2582 
2583 	sc = device_get_softc(pcib);
2584 
2585 	if (sc->flags & PCIB_ENABLE_ARI) {
2586 		bus = pci_get_bus(dev);
2587 		func = pci_get_function(dev);
2588 
2589 		*id = (PCI_ARI_RID(bus, func));
2590 	} else {
2591 		bus = pci_get_bus(dev);
2592 		slot = pci_get_slot(dev);
2593 		func = pci_get_function(dev);
2594 
2595 		*id = (PCI_RID(bus, slot, func));
2596 	}
2597 
2598 	return (0);
2599 }
2600 
2601 /*
2602  * Check that the downstream port (pcib) and the endpoint device (dev) both
2603  * support ARI.  If so, enable it and return 0, otherwise return an error.
2604  */
2605 static int
2606 pcib_try_enable_ari(device_t pcib, device_t dev)
2607 {
2608 	struct pcib_softc *sc;
2609 	int error;
2610 	uint32_t cap2;
2611 	int ari_cap_off;
2612 	uint32_t ari_ver;
2613 	uint32_t pcie_pos;
2614 
2615 	sc = device_get_softc(pcib);
2616 
2617 	/*
2618 	 * ARI is controlled in a register in the PCIe capability structure.
2619 	 * If the downstream port does not have the PCIe capability structure
2620 	 * then it does not support ARI.
2621 	 */
2622 	error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2623 	if (error != 0)
2624 		return (ENODEV);
2625 
2626 	/* Check that the PCIe port advertises ARI support. */
2627 	cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2628 	if (!(cap2 & PCIEM_CAP2_ARI))
2629 		return (ENODEV);
2630 
2631 	/*
2632 	 * Check that the endpoint device advertises ARI support via the ARI
2633 	 * extended capability structure.
2634 	 */
2635 	error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2636 	if (error != 0)
2637 		return (ENODEV);
2638 
2639 	/*
2640 	 * Finally, check that the endpoint device supports the same version
2641 	 * of ARI that we do.
2642 	 */
2643 	ari_ver = pci_read_config(dev, ari_cap_off, 4);
2644 	if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2645 		if (bootverbose)
2646 			device_printf(pcib,
2647 			    "Unsupported version of ARI (%d) detected\n",
2648 			    PCI_EXTCAP_VER(ari_ver));
2649 
2650 		return (ENXIO);
2651 	}
2652 
2653 	pcib_enable_ari(sc, pcie_pos);
2654 
2655 	return (0);
2656 }
2657 
2658 int
2659 pcib_request_feature_allow(device_t pcib, device_t dev,
2660     enum pci_feature feature)
2661 {
2662 	/*
2663 	 * No host firmware we have to negotiate with, so we allow
2664 	 * every valid feature requested.
2665 	 */
2666 	switch (feature) {
2667 	case PCI_FEATURE_AER:
2668 	case PCI_FEATURE_HP:
2669 		break;
2670 	default:
2671 		return (EINVAL);
2672 	}
2673 
2674 	return (0);
2675 }
2676 
2677 int
2678 pcib_request_feature(device_t dev, enum pci_feature feature)
2679 {
2680 
2681 	/*
2682 	 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2683 	 * the firmware overrides the method of PCI-PCI bridges.
2684 	 */
2685 	return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2686 }
2687 
2688 /*
2689  * Pass the request to use this PCI feature up the tree. Either there's a
2690  * firmware like ACPI that's using this feature that will approve (or deny) the
2691  * request to take it over, or the platform has no such firmware, in which case
2692  * the request will be approved. If the request is approved, the OS is expected
2693  * to make use of the feature or render it harmless.
2694  */
2695 static int
2696 pcib_request_feature_default(device_t pcib, device_t dev,
2697     enum pci_feature feature)
2698 {
2699 	device_t bus;
2700 
2701 	/*
2702 	 * Our parent is necessarily a pci bus. Its parent will either be
2703 	 * another pci bridge (which passes it up) or a host bridge that can
2704 	 * approve or reject the request.
2705 	 */
2706 	bus = device_get_parent(pcib);
2707 	return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
2708 }
2709 
2710 static int
2711 pcib_reset_child(device_t dev, device_t child, int flags)
2712 {
2713 	struct pci_devinfo *pdinfo;
2714 	int error;
2715 
2716 	error = 0;
2717 	if (dev == NULL || device_get_parent(child) != dev)
2718 		goto out;
2719 	error = ENXIO;
2720 	if (device_get_devclass(child) != devclass_find("pci"))
2721 		goto out;
2722 	pdinfo = device_get_ivars(dev);
2723 	if (pdinfo->cfg.pcie.pcie_location != 0 &&
2724 	    (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
2725 	    pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
2726 		error = bus_helper_reset_prepare(child, flags);
2727 		if (error == 0) {
2728 			error = pcie_link_reset(dev,
2729 			    pdinfo->cfg.pcie.pcie_location);
2730 			/* XXXKIB call _post even if error != 0 ? */
2731 			bus_helper_reset_post(child, flags);
2732 		}
2733 	}
2734 out:
2735 	return (error);
2736 }
2737