1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pci_private.h> 52 #include <dev/pci/pcib_private.h> 53 54 #include "pcib_if.h" 55 56 static int pcib_probe(device_t dev); 57 static int pcib_suspend(device_t dev); 58 static int pcib_resume(device_t dev); 59 static int pcib_power_for_sleep(device_t pcib, device_t dev, 60 int *pstate); 61 62 static device_method_t pcib_methods[] = { 63 /* Device interface */ 64 DEVMETHOD(device_probe, pcib_probe), 65 DEVMETHOD(device_attach, pcib_attach), 66 DEVMETHOD(device_detach, bus_generic_detach), 67 DEVMETHOD(device_shutdown, bus_generic_shutdown), 68 DEVMETHOD(device_suspend, pcib_suspend), 69 DEVMETHOD(device_resume, pcib_resume), 70 71 /* Bus interface */ 72 DEVMETHOD(bus_print_child, bus_generic_print_child), 73 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 74 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 75 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 76 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 77 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 78 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 79 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 80 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 81 82 /* pcib interface */ 83 DEVMETHOD(pcib_maxslots, pcib_maxslots), 84 DEVMETHOD(pcib_read_config, pcib_read_config), 85 DEVMETHOD(pcib_write_config, pcib_write_config), 86 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 87 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 88 DEVMETHOD(pcib_release_msi, pcib_release_msi), 89 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 90 DEVMETHOD(pcib_release_msix, pcib_release_msix), 91 DEVMETHOD(pcib_map_msi, pcib_map_msi), 92 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 93 94 { 0, 0 } 95 }; 96 97 static devclass_t pcib_devclass; 98 99 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 100 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 101 102 /* 103 * Is the prefetch window open (eg, can we allocate memory in it?) 104 */ 105 static int 106 pcib_is_prefetch_open(struct pcib_softc *sc) 107 { 108 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 109 } 110 111 /* 112 * Is the nonprefetch window open (eg, can we allocate memory in it?) 113 */ 114 static int 115 pcib_is_nonprefetch_open(struct pcib_softc *sc) 116 { 117 return (sc->membase > 0 && sc->membase < sc->memlimit); 118 } 119 120 /* 121 * Is the io window open (eg, can we allocate ports in it?) 122 */ 123 static int 124 pcib_is_io_open(struct pcib_softc *sc) 125 { 126 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 127 } 128 129 /* 130 * Get current I/O decode. 131 */ 132 static void 133 pcib_get_io_decode(struct pcib_softc *sc) 134 { 135 device_t dev; 136 uint32_t iolow; 137 138 dev = sc->dev; 139 140 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 141 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 142 sc->iobase = PCI_PPBIOBASE( 143 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 144 else 145 sc->iobase = PCI_PPBIOBASE(0, iolow); 146 147 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 148 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 149 sc->iolimit = PCI_PPBIOLIMIT( 150 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 151 else 152 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 153 } 154 155 /* 156 * Get current memory decode. 157 */ 158 static void 159 pcib_get_mem_decode(struct pcib_softc *sc) 160 { 161 device_t dev; 162 pci_addr_t pmemlow; 163 164 dev = sc->dev; 165 166 sc->membase = PCI_PPBMEMBASE(0, 167 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 168 sc->memlimit = PCI_PPBMEMLIMIT(0, 169 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 170 171 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 172 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 173 sc->pmembase = PCI_PPBMEMBASE( 174 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 175 else 176 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 177 178 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 179 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 180 sc->pmemlimit = PCI_PPBMEMLIMIT( 181 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 182 else 183 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 184 } 185 186 /* 187 * Restore previous I/O decode. 188 */ 189 static void 190 pcib_set_io_decode(struct pcib_softc *sc) 191 { 192 device_t dev; 193 uint32_t iohi; 194 195 dev = sc->dev; 196 197 iohi = sc->iobase >> 16; 198 if (iohi > 0) 199 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 200 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 201 202 iohi = sc->iolimit >> 16; 203 if (iohi > 0) 204 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 205 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 206 } 207 208 /* 209 * Restore previous memory decode. 210 */ 211 static void 212 pcib_set_mem_decode(struct pcib_softc *sc) 213 { 214 device_t dev; 215 pci_addr_t pmemhi; 216 217 dev = sc->dev; 218 219 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 220 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 221 222 pmemhi = sc->pmembase >> 32; 223 if (pmemhi > 0) 224 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 225 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 226 227 pmemhi = sc->pmemlimit >> 32; 228 if (pmemhi > 0) 229 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 230 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 231 } 232 233 /* 234 * Get current bridge configuration. 235 */ 236 static void 237 pcib_cfg_save(struct pcib_softc *sc) 238 { 239 device_t dev; 240 241 dev = sc->dev; 242 243 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 244 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 245 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 246 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 247 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 248 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 249 if (sc->command & PCIM_CMD_PORTEN) 250 pcib_get_io_decode(sc); 251 if (sc->command & PCIM_CMD_MEMEN) 252 pcib_get_mem_decode(sc); 253 } 254 255 /* 256 * Restore previous bridge configuration. 257 */ 258 static void 259 pcib_cfg_restore(struct pcib_softc *sc) 260 { 261 device_t dev; 262 263 dev = sc->dev; 264 265 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 266 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 267 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 268 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 269 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 270 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 271 if (sc->command & PCIM_CMD_PORTEN) 272 pcib_set_io_decode(sc); 273 if (sc->command & PCIM_CMD_MEMEN) 274 pcib_set_mem_decode(sc); 275 } 276 277 /* 278 * Generic device interface 279 */ 280 static int 281 pcib_probe(device_t dev) 282 { 283 if ((pci_get_class(dev) == PCIC_BRIDGE) && 284 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 285 device_set_desc(dev, "PCI-PCI bridge"); 286 return(-10000); 287 } 288 return(ENXIO); 289 } 290 291 void 292 pcib_attach_common(device_t dev) 293 { 294 struct pcib_softc *sc; 295 struct sysctl_ctx_list *sctx; 296 struct sysctl_oid *soid; 297 298 sc = device_get_softc(dev); 299 sc->dev = dev; 300 301 /* 302 * Get current bridge configuration. 303 */ 304 sc->domain = pci_get_domain(dev); 305 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 306 pcib_cfg_save(sc); 307 308 /* 309 * Setup sysctl reporting nodes 310 */ 311 sctx = device_get_sysctl_ctx(dev); 312 soid = device_get_sysctl_tree(dev); 313 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 314 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 315 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 316 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 317 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 318 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 319 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 320 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 321 322 /* 323 * Quirk handling. 324 */ 325 switch (pci_get_devid(dev)) { 326 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 327 { 328 uint8_t supbus; 329 330 supbus = pci_read_config(dev, 0x41, 1); 331 if (supbus != 0xff) { 332 sc->secbus = supbus + 1; 333 sc->subbus = supbus + 1; 334 } 335 break; 336 } 337 338 /* 339 * The i82380FB mobile docking controller is a PCI-PCI bridge, 340 * and it is a subtractive bridge. However, the ProgIf is wrong 341 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 342 * happen. There's also a Toshiba bridge that behaves this 343 * way. 344 */ 345 case 0x124b8086: /* Intel 82380FB Mobile */ 346 case 0x060513d7: /* Toshiba ???? */ 347 sc->flags |= PCIB_SUBTRACTIVE; 348 break; 349 350 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 351 case 0x00dd10de: 352 { 353 char *cp; 354 355 if ((cp = getenv("smbios.planar.maker")) == NULL) 356 break; 357 if (strncmp(cp, "Compal", 6) != 0) { 358 freeenv(cp); 359 break; 360 } 361 freeenv(cp); 362 if ((cp = getenv("smbios.planar.product")) == NULL) 363 break; 364 if (strncmp(cp, "08A0", 4) != 0) { 365 freeenv(cp); 366 break; 367 } 368 freeenv(cp); 369 if (sc->subbus < 0xa) { 370 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 371 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 372 } 373 break; 374 } 375 } 376 377 if (pci_msi_device_blacklisted(dev)) 378 sc->flags |= PCIB_DISABLE_MSI; 379 380 /* 381 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 382 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 383 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 384 * This means they act as if they were subtractively decoding 385 * bridges and pass all transactions. Mark them and real ProgIf 1 386 * parts as subtractive. 387 */ 388 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 389 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 390 sc->flags |= PCIB_SUBTRACTIVE; 391 392 if (bootverbose) { 393 device_printf(dev, " domain %d\n", sc->domain); 394 device_printf(dev, " secondary bus %d\n", sc->secbus); 395 device_printf(dev, " subordinate bus %d\n", sc->subbus); 396 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 397 if (pcib_is_nonprefetch_open(sc)) 398 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 399 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 400 if (pcib_is_prefetch_open(sc)) 401 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 402 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 403 else 404 device_printf(dev, " no prefetched decode\n"); 405 if (sc->flags & PCIB_SUBTRACTIVE) 406 device_printf(dev, " Subtractively decoded bridge.\n"); 407 } 408 409 /* 410 * XXX If the secondary bus number is zero, we should assign a bus number 411 * since the BIOS hasn't, then initialise the bridge. A simple 412 * bus_alloc_resource with the a couple of busses seems like the right 413 * approach, but we don't know what busses the BIOS might have already 414 * assigned to other bridges on this bus that probe later than we do. 415 * 416 * If the subordinate bus number is less than the secondary bus number, 417 * we should pick a better value. One sensible alternative would be to 418 * pick 255; the only tradeoff here is that configuration transactions 419 * would be more widely routed than absolutely necessary. We could 420 * then do a walk of the tree later and fix it. 421 */ 422 } 423 424 int 425 pcib_attach(device_t dev) 426 { 427 struct pcib_softc *sc; 428 device_t child; 429 430 pcib_attach_common(dev); 431 sc = device_get_softc(dev); 432 if (sc->secbus != 0) { 433 child = device_add_child(dev, "pci", sc->secbus); 434 if (child != NULL) 435 return(bus_generic_attach(dev)); 436 } 437 438 /* no secondary bus; we should have fixed this */ 439 return(0); 440 } 441 442 int 443 pcib_suspend(device_t dev) 444 { 445 device_t pcib; 446 int dstate, error; 447 448 pcib_cfg_save(device_get_softc(dev)); 449 error = bus_generic_suspend(dev); 450 if (error == 0 && pci_do_power_suspend) { 451 dstate = PCI_POWERSTATE_D3; 452 pcib = device_get_parent(device_get_parent(dev)); 453 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 454 pci_set_powerstate(dev, dstate); 455 } 456 return (error); 457 } 458 459 int 460 pcib_resume(device_t dev) 461 { 462 device_t pcib; 463 464 if (pci_do_power_resume) { 465 pcib = device_get_parent(device_get_parent(dev)); 466 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 467 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 468 } 469 pcib_cfg_restore(device_get_softc(dev)); 470 return (bus_generic_resume(dev)); 471 } 472 473 int 474 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 475 { 476 struct pcib_softc *sc = device_get_softc(dev); 477 478 switch (which) { 479 case PCIB_IVAR_DOMAIN: 480 *result = sc->domain; 481 return(0); 482 case PCIB_IVAR_BUS: 483 *result = sc->secbus; 484 return(0); 485 } 486 return(ENOENT); 487 } 488 489 int 490 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 491 { 492 struct pcib_softc *sc = device_get_softc(dev); 493 494 switch (which) { 495 case PCIB_IVAR_DOMAIN: 496 return(EINVAL); 497 case PCIB_IVAR_BUS: 498 sc->secbus = value; 499 return(0); 500 } 501 return(ENOENT); 502 } 503 504 /* 505 * We have to trap resource allocation requests and ensure that the bridge 506 * is set up to, or capable of handling them. 507 */ 508 struct resource * 509 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 510 u_long start, u_long end, u_long count, u_int flags) 511 { 512 struct pcib_softc *sc = device_get_softc(dev); 513 const char *name, *suffix; 514 int ok; 515 516 /* 517 * Fail the allocation for this range if it's not supported. 518 */ 519 name = device_get_nameunit(child); 520 if (name == NULL) { 521 name = ""; 522 suffix = ""; 523 } else 524 suffix = " "; 525 switch (type) { 526 case SYS_RES_IOPORT: 527 ok = 0; 528 if (!pcib_is_io_open(sc)) 529 break; 530 ok = (start >= sc->iobase && end <= sc->iolimit); 531 532 /* 533 * Make sure we allow access to VGA I/O addresses when the 534 * bridge has the "VGA Enable" bit set. 535 */ 536 if (!ok && pci_is_vga_ioport_range(start, end)) 537 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 538 539 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 540 if (!ok) { 541 if (start < sc->iobase) 542 start = sc->iobase; 543 if (end > sc->iolimit) 544 end = sc->iolimit; 545 if (start < end) 546 ok = 1; 547 } 548 } else { 549 ok = 1; 550 #if 0 551 /* 552 * If we overlap with the subtractive range, then 553 * pick the upper range to use. 554 */ 555 if (start < sc->iolimit && end > sc->iobase) 556 start = sc->iolimit + 1; 557 #endif 558 } 559 if (end < start) { 560 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 561 end, start); 562 start = 0; 563 end = 0; 564 ok = 0; 565 } 566 if (!ok) { 567 device_printf(dev, "%s%srequested unsupported I/O " 568 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 569 name, suffix, start, end, sc->iobase, sc->iolimit); 570 return (NULL); 571 } 572 if (bootverbose) 573 device_printf(dev, 574 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 575 name, suffix, start, end); 576 break; 577 578 case SYS_RES_MEMORY: 579 ok = 0; 580 if (pcib_is_nonprefetch_open(sc)) 581 ok = ok || (start >= sc->membase && end <= sc->memlimit); 582 if (pcib_is_prefetch_open(sc)) 583 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 584 585 /* 586 * Make sure we allow access to VGA memory addresses when the 587 * bridge has the "VGA Enable" bit set. 588 */ 589 if (!ok && pci_is_vga_memory_range(start, end)) 590 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 591 592 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 593 if (!ok) { 594 ok = 1; 595 if (flags & RF_PREFETCHABLE) { 596 if (pcib_is_prefetch_open(sc)) { 597 if (start < sc->pmembase) 598 start = sc->pmembase; 599 if (end > sc->pmemlimit) 600 end = sc->pmemlimit; 601 } else { 602 ok = 0; 603 } 604 } else { /* non-prefetchable */ 605 if (pcib_is_nonprefetch_open(sc)) { 606 if (start < sc->membase) 607 start = sc->membase; 608 if (end > sc->memlimit) 609 end = sc->memlimit; 610 } else { 611 ok = 0; 612 } 613 } 614 } 615 } else if (!ok) { 616 ok = 1; /* subtractive bridge: always ok */ 617 #if 0 618 if (pcib_is_nonprefetch_open(sc)) { 619 if (start < sc->memlimit && end > sc->membase) 620 start = sc->memlimit + 1; 621 } 622 if (pcib_is_prefetch_open(sc)) { 623 if (start < sc->pmemlimit && end > sc->pmembase) 624 start = sc->pmemlimit + 1; 625 } 626 #endif 627 } 628 if (end < start) { 629 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 630 end, start); 631 start = 0; 632 end = 0; 633 ok = 0; 634 } 635 if (!ok && bootverbose) 636 device_printf(dev, 637 "%s%srequested unsupported memory range %#lx-%#lx " 638 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 639 name, suffix, start, end, 640 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 641 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 642 if (!ok) 643 return (NULL); 644 if (bootverbose) 645 device_printf(dev,"%s%srequested memory range " 646 "0x%lx-0x%lx: good\n", 647 name, suffix, start, end); 648 break; 649 650 default: 651 break; 652 } 653 /* 654 * Bridge is OK decoding this resource, so pass it up. 655 */ 656 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 657 count, flags)); 658 } 659 660 /* 661 * PCIB interface. 662 */ 663 int 664 pcib_maxslots(device_t dev) 665 { 666 return(PCI_SLOTMAX); 667 } 668 669 /* 670 * Since we are a child of a PCI bus, its parent must support the pcib interface. 671 */ 672 uint32_t 673 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 674 { 675 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 676 } 677 678 void 679 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 680 { 681 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 682 } 683 684 /* 685 * Route an interrupt across a PCI bridge. 686 */ 687 int 688 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 689 { 690 device_t bus; 691 int parent_intpin; 692 int intnum; 693 694 /* 695 * 696 * The PCI standard defines a swizzle of the child-side device/intpin to 697 * the parent-side intpin as follows. 698 * 699 * device = device on child bus 700 * child_intpin = intpin on child bus slot (0-3) 701 * parent_intpin = intpin on parent bus slot (0-3) 702 * 703 * parent_intpin = (device + child_intpin) % 4 704 */ 705 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 706 707 /* 708 * Our parent is a PCI bus. Its parent must export the pcib interface 709 * which includes the ability to route interrupts. 710 */ 711 bus = device_get_parent(pcib); 712 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 713 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 714 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 715 pci_get_slot(dev), 'A' + pin - 1, intnum); 716 } 717 return(intnum); 718 } 719 720 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 721 int 722 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 723 { 724 struct pcib_softc *sc = device_get_softc(pcib); 725 device_t bus; 726 727 if (sc->flags & PCIB_DISABLE_MSI) 728 return (ENXIO); 729 bus = device_get_parent(pcib); 730 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 731 irqs)); 732 } 733 734 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 735 int 736 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 737 { 738 device_t bus; 739 740 bus = device_get_parent(pcib); 741 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 742 } 743 744 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 745 int 746 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 747 { 748 struct pcib_softc *sc = device_get_softc(pcib); 749 device_t bus; 750 751 if (sc->flags & PCIB_DISABLE_MSI) 752 return (ENXIO); 753 bus = device_get_parent(pcib); 754 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 755 } 756 757 /* Pass request to release an MSI-X message up to the parent bridge. */ 758 int 759 pcib_release_msix(device_t pcib, device_t dev, int irq) 760 { 761 device_t bus; 762 763 bus = device_get_parent(pcib); 764 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 765 } 766 767 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 768 int 769 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 770 uint32_t *data) 771 { 772 device_t bus; 773 int error; 774 775 bus = device_get_parent(pcib); 776 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 777 if (error) 778 return (error); 779 780 pci_ht_map_msi(pcib, *addr); 781 return (0); 782 } 783 784 /* Pass request for device power state up to parent bridge. */ 785 int 786 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 787 { 788 device_t bus; 789 790 bus = device_get_parent(pcib); 791 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 792 } 793 794 /* 795 * Try to read the bus number of a host-PCI bridge using appropriate config 796 * registers. 797 */ 798 int 799 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 800 uint8_t *busnum) 801 { 802 uint32_t id; 803 804 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 805 if (id == 0xffffffff) 806 return (0); 807 808 switch (id) { 809 case 0x12258086: 810 /* Intel 824?? */ 811 /* XXX This is a guess */ 812 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 813 *busnum = bus; 814 break; 815 case 0x84c48086: 816 /* Intel 82454KX/GX (Orion) */ 817 *busnum = read_config(bus, slot, func, 0x4a, 1); 818 break; 819 case 0x84ca8086: 820 /* 821 * For the 450nx chipset, there is a whole bundle of 822 * things pretending to be host bridges. The MIOC will 823 * be seen first and isn't really a pci bridge (the 824 * actual busses are attached to the PXB's). We need to 825 * read the registers of the MIOC to figure out the 826 * bus numbers for the PXB channels. 827 * 828 * Since the MIOC doesn't have a pci bus attached, we 829 * pretend it wasn't there. 830 */ 831 return (0); 832 case 0x84cb8086: 833 switch (slot) { 834 case 0x12: 835 /* Intel 82454NX PXB#0, Bus#A */ 836 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 837 break; 838 case 0x13: 839 /* Intel 82454NX PXB#0, Bus#B */ 840 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 841 break; 842 case 0x14: 843 /* Intel 82454NX PXB#1, Bus#A */ 844 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 845 break; 846 case 0x15: 847 /* Intel 82454NX PXB#1, Bus#B */ 848 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 849 break; 850 } 851 break; 852 853 /* ServerWorks -- vendor 0x1166 */ 854 case 0x00051166: 855 case 0x00061166: 856 case 0x00081166: 857 case 0x00091166: 858 case 0x00101166: 859 case 0x00111166: 860 case 0x00171166: 861 case 0x01011166: 862 case 0x010f1014: 863 case 0x01101166: 864 case 0x02011166: 865 case 0x02251166: 866 case 0x03021014: 867 *busnum = read_config(bus, slot, func, 0x44, 1); 868 break; 869 870 /* Compaq/HP -- vendor 0x0e11 */ 871 case 0x60100e11: 872 *busnum = read_config(bus, slot, func, 0xc8, 1); 873 break; 874 default: 875 /* Don't know how to read bus number. */ 876 return 0; 877 } 878 879 return 1; 880 } 881