1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "pcib_if.h" 54 55 static int pcib_probe(device_t dev); 56 57 static device_method_t pcib_methods[] = { 58 /* Device interface */ 59 DEVMETHOD(device_probe, pcib_probe), 60 DEVMETHOD(device_attach, pcib_attach), 61 DEVMETHOD(device_detach, bus_generic_detach), 62 DEVMETHOD(device_shutdown, bus_generic_shutdown), 63 DEVMETHOD(device_suspend, bus_generic_suspend), 64 DEVMETHOD(device_resume, bus_generic_resume), 65 66 /* Bus interface */ 67 DEVMETHOD(bus_print_child, bus_generic_print_child), 68 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 69 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 71 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 76 77 /* pcib interface */ 78 DEVMETHOD(pcib_maxslots, pcib_maxslots), 79 DEVMETHOD(pcib_read_config, pcib_read_config), 80 DEVMETHOD(pcib_write_config, pcib_write_config), 81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 82 83 { 0, 0 } 84 }; 85 86 static devclass_t pcib_devclass; 87 88 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 89 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 90 91 /* 92 * Is the prefetch window open (eg, can we allocate memory in it?) 93 */ 94 static int 95 pcib_is_prefetch_open(struct pcib_softc *sc) 96 { 97 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 98 } 99 100 /* 101 * Is the nonprefetch window open (eg, can we allocate memory in it?) 102 */ 103 static int 104 pcib_is_nonprefetch_open(struct pcib_softc *sc) 105 { 106 return (sc->membase > 0 && sc->membase < sc->memlimit); 107 } 108 109 /* 110 * Is the io window open (eg, can we allocate ports in it?) 111 */ 112 static int 113 pcib_is_io_open(struct pcib_softc *sc) 114 { 115 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 116 } 117 118 /* 119 * Generic device interface 120 */ 121 static int 122 pcib_probe(device_t dev) 123 { 124 if ((pci_get_class(dev) == PCIC_BRIDGE) && 125 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 126 device_set_desc(dev, "PCI-PCI bridge"); 127 return(-10000); 128 } 129 return(ENXIO); 130 } 131 132 void 133 pcib_attach_common(device_t dev) 134 { 135 struct pcib_softc *sc; 136 uint8_t iolow; 137 138 sc = device_get_softc(dev); 139 sc->dev = dev; 140 141 /* 142 * Get current bridge configuration. 143 */ 144 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 145 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 146 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 147 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 148 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 149 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 150 151 /* 152 * Determine current I/O decode. 153 */ 154 if (sc->command & PCIM_CMD_PORTEN) { 155 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 156 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 157 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 158 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 159 } else { 160 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 161 } 162 163 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 164 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 165 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 166 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 167 } else { 168 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 169 } 170 } 171 172 /* 173 * Determine current memory decode. 174 */ 175 if (sc->command & PCIM_CMD_MEMEN) { 176 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 177 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 178 sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4), 179 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 180 sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4), 181 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 182 } 183 184 /* 185 * Quirk handling. 186 */ 187 switch (pci_get_devid(dev)) { 188 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 189 { 190 uint8_t supbus; 191 192 supbus = pci_read_config(dev, 0x41, 1); 193 if (supbus != 0xff) { 194 sc->secbus = supbus + 1; 195 sc->subbus = supbus + 1; 196 } 197 break; 198 } 199 200 /* 201 * The i82380FB mobile docking controller is a PCI-PCI bridge, 202 * and it is a subtractive bridge. However, the ProgIf is wrong 203 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 204 * happen. There's also a Toshiba bridge that behaves this 205 * way. 206 */ 207 case 0x124b8086: /* Intel 82380FB Mobile */ 208 case 0x060513d7: /* Toshiba ???? */ 209 sc->flags |= PCIB_SUBTRACTIVE; 210 break; 211 212 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 213 case 0x00dd10de: 214 { 215 char *cp; 216 217 if ((cp = getenv("smbios.planar.maker")) == NULL) 218 break; 219 if (strncmp(cp, "Compal", 6) != 0) { 220 freeenv(cp); 221 break; 222 } 223 freeenv(cp); 224 if ((cp = getenv("smbios.planar.product")) == NULL) 225 break; 226 if (strncmp(cp, "08A0", 4) != 0) { 227 freeenv(cp); 228 break; 229 } 230 freeenv(cp); 231 if (sc->subbus < 0xa) { 232 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 233 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 234 } 235 break; 236 } 237 } 238 239 /* 240 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 241 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 242 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 243 * This means they act as if they were subtractively decoding 244 * bridges and pass all transactions. Mark them and real ProgIf 1 245 * parts as subtractive. 246 */ 247 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 248 pci_read_config(dev, PCIR_PROGIF, 1) == 1) 249 sc->flags |= PCIB_SUBTRACTIVE; 250 251 if (bootverbose) { 252 device_printf(dev, " secondary bus %d\n", sc->secbus); 253 device_printf(dev, " subordinate bus %d\n", sc->subbus); 254 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 255 if (pcib_is_nonprefetch_open(sc)) 256 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 257 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 258 if (pcib_is_prefetch_open(sc)) 259 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 260 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 261 else 262 device_printf(dev, " no prefetched decode\n"); 263 if (sc->flags & PCIB_SUBTRACTIVE) 264 device_printf(dev, " Subtractively decoded bridge.\n"); 265 } 266 267 /* 268 * XXX If the secondary bus number is zero, we should assign a bus number 269 * since the BIOS hasn't, then initialise the bridge. 270 */ 271 272 /* 273 * XXX If the subordinate bus number is less than the secondary bus number, 274 * we should pick a better value. One sensible alternative would be to 275 * pick 255; the only tradeoff here is that configuration transactions 276 * would be more widely routed than absolutely necessary. 277 */ 278 } 279 280 int 281 pcib_attach(device_t dev) 282 { 283 struct pcib_softc *sc; 284 device_t child; 285 286 pcib_attach_common(dev); 287 sc = device_get_softc(dev); 288 if (sc->secbus != 0) { 289 child = device_add_child(dev, "pci", sc->secbus); 290 if (child != NULL) 291 return(bus_generic_attach(dev)); 292 } 293 294 /* no secondary bus; we should have fixed this */ 295 return(0); 296 } 297 298 int 299 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 300 { 301 struct pcib_softc *sc = device_get_softc(dev); 302 303 switch (which) { 304 case PCIB_IVAR_BUS: 305 *result = sc->secbus; 306 return(0); 307 } 308 return(ENOENT); 309 } 310 311 int 312 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 313 { 314 struct pcib_softc *sc = device_get_softc(dev); 315 316 switch (which) { 317 case PCIB_IVAR_BUS: 318 sc->secbus = value; 319 break; 320 } 321 return(ENOENT); 322 } 323 324 /* 325 * We have to trap resource allocation requests and ensure that the bridge 326 * is set up to, or capable of handling them. 327 */ 328 struct resource * 329 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 330 u_long start, u_long end, u_long count, u_int flags) 331 { 332 struct pcib_softc *sc = device_get_softc(dev); 333 int ok; 334 335 /* 336 * Fail the allocation for this range if it's not supported. 337 */ 338 switch (type) { 339 case SYS_RES_IOPORT: 340 ok = 0; 341 if (!pcib_is_io_open(sc)) 342 break; 343 ok = (start >= sc->iobase && end <= sc->iolimit); 344 345 /* 346 * Make sure we allow access to VGA I/O addresses when the 347 * bridge has the "VGA Enable" bit set. 348 */ 349 if (!ok && pci_is_vga_ioport_range(start, end)) 350 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 351 352 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 353 if (!ok) { 354 if (start < sc->iobase) 355 start = sc->iobase; 356 if (end > sc->iolimit) 357 end = sc->iolimit; 358 if (start < end) 359 ok = 1; 360 } 361 } else { 362 ok = 1; 363 #if 1 364 if (start < sc->iobase && end > sc->iolimit) { 365 start = sc->iobase; 366 end = sc->iolimit; 367 } 368 #endif 369 } 370 if (end < start) { 371 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 372 end, start); 373 start = 0; 374 end = 0; 375 ok = 0; 376 } 377 if (!ok) { 378 device_printf(dev, "%s requested unsupported I/O " 379 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 380 device_get_nameunit(child), start, end, 381 sc->iobase, sc->iolimit); 382 return (NULL); 383 } 384 if (bootverbose) 385 device_printf(dev, 386 "%s requested I/O range 0x%lx-0x%lx: in range\n", 387 device_get_nameunit(child), start, end); 388 break; 389 390 case SYS_RES_MEMORY: 391 ok = 0; 392 if (pcib_is_nonprefetch_open(sc)) 393 ok = ok || (start >= sc->membase && end <= sc->memlimit); 394 if (pcib_is_prefetch_open(sc)) 395 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 396 397 /* 398 * Make sure we allow access to VGA memory addresses when the 399 * bridge has the "VGA Enable" bit set. 400 */ 401 if (!ok && pci_is_vga_memory_range(start, end)) 402 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 403 404 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 405 if (!ok) { 406 ok = 1; 407 if (flags & RF_PREFETCHABLE) { 408 if (pcib_is_prefetch_open(sc)) { 409 if (start < sc->pmembase) 410 start = sc->pmembase; 411 if (end > sc->pmemlimit) 412 end = sc->pmemlimit; 413 } else { 414 ok = 0; 415 } 416 } else { /* non-prefetchable */ 417 if (pcib_is_nonprefetch_open(sc)) { 418 if (start < sc->membase) 419 start = sc->membase; 420 if (end > sc->memlimit) 421 end = sc->memlimit; 422 } else { 423 ok = 0; 424 } 425 } 426 } 427 } else if (!ok) { 428 ok = 1; /* subtractive bridge: always ok */ 429 #if 1 430 if (pcib_is_nonprefetch_open(sc)) { 431 if (start < sc->membase && end > sc->memlimit) { 432 start = sc->membase; 433 end = sc->memlimit; 434 } 435 } 436 if (pcib_is_prefetch_open(sc)) { 437 if (start < sc->pmembase && end > sc->pmemlimit) { 438 start = sc->pmembase; 439 end = sc->pmemlimit; 440 } 441 } 442 #endif 443 } 444 if (end < start) { 445 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 446 end, start); 447 start = 0; 448 end = 0; 449 ok = 0; 450 } 451 if (!ok && bootverbose) 452 device_printf(dev, 453 "%s requested unsupported memory range %#lx-%#lx " 454 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 455 device_get_nameunit(child), start, end, 456 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 457 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 458 if (!ok) 459 return (NULL); 460 if (bootverbose) 461 device_printf(dev,"%s requested memory range " 462 "0x%lx-0x%lx: good\n", 463 device_get_nameunit(child), start, end); 464 break; 465 466 default: 467 break; 468 } 469 /* 470 * Bridge is OK decoding this resource, so pass it up. 471 */ 472 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 473 count, flags)); 474 } 475 476 /* 477 * PCIB interface. 478 */ 479 int 480 pcib_maxslots(device_t dev) 481 { 482 return(PCI_SLOTMAX); 483 } 484 485 /* 486 * Since we are a child of a PCI bus, its parent must support the pcib interface. 487 */ 488 uint32_t 489 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 490 { 491 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 492 } 493 494 void 495 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 496 { 497 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 498 } 499 500 /* 501 * Route an interrupt across a PCI bridge. 502 */ 503 int 504 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 505 { 506 device_t bus; 507 int parent_intpin; 508 int intnum; 509 510 /* 511 * 512 * The PCI standard defines a swizzle of the child-side device/intpin to 513 * the parent-side intpin as follows. 514 * 515 * device = device on child bus 516 * child_intpin = intpin on child bus slot (0-3) 517 * parent_intpin = intpin on parent bus slot (0-3) 518 * 519 * parent_intpin = (device + child_intpin) % 4 520 */ 521 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 522 523 /* 524 * Our parent is a PCI bus. Its parent must export the pcib interface 525 * which includes the ability to route interrupts. 526 */ 527 bus = device_get_parent(pcib); 528 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 529 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 530 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 531 pci_get_slot(dev), 'A' + pin - 1, intnum); 532 } 533 return(intnum); 534 } 535 536 /* 537 * Try to read the bus number of a host-PCI bridge using appropriate config 538 * registers. 539 */ 540 int 541 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 542 uint8_t *busnum) 543 { 544 uint32_t id; 545 546 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 547 if (id == 0xffffffff) 548 return (0); 549 550 switch (id) { 551 case 0x12258086: 552 /* Intel 824?? */ 553 /* XXX This is a guess */ 554 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 555 *busnum = bus; 556 break; 557 case 0x84c48086: 558 /* Intel 82454KX/GX (Orion) */ 559 *busnum = read_config(bus, slot, func, 0x4a, 1); 560 break; 561 case 0x84ca8086: 562 /* 563 * For the 450nx chipset, there is a whole bundle of 564 * things pretending to be host bridges. The MIOC will 565 * be seen first and isn't really a pci bridge (the 566 * actual busses are attached to the PXB's). We need to 567 * read the registers of the MIOC to figure out the 568 * bus numbers for the PXB channels. 569 * 570 * Since the MIOC doesn't have a pci bus attached, we 571 * pretend it wasn't there. 572 */ 573 return (0); 574 case 0x84cb8086: 575 switch (slot) { 576 case 0x12: 577 /* Intel 82454NX PXB#0, Bus#A */ 578 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 579 break; 580 case 0x13: 581 /* Intel 82454NX PXB#0, Bus#B */ 582 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 583 break; 584 case 0x14: 585 /* Intel 82454NX PXB#1, Bus#A */ 586 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 587 break; 588 case 0x15: 589 /* Intel 82454NX PXB#1, Bus#B */ 590 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 591 break; 592 } 593 break; 594 595 /* ServerWorks -- vendor 0x1166 */ 596 case 0x00051166: 597 case 0x00061166: 598 case 0x00081166: 599 case 0x00091166: 600 case 0x00101166: 601 case 0x00111166: 602 case 0x00171166: 603 case 0x01011166: 604 case 0x010f1014: 605 case 0x02011166: 606 case 0x03021014: 607 *busnum = read_config(bus, slot, func, 0x44, 1); 608 break; 609 610 /* Compaq/HP -- vendor 0x0e11 */ 611 case 0x60100e11: 612 *busnum = read_config(bus, slot, func, 0xc8, 1); 613 break; 614 default: 615 /* Don't know how to read bus number. */ 616 return 0; 617 } 618 619 return 1; 620 } 621