1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * PCI:PCI bridge support. 38 */ 39 40 #include "opt_pci.h" 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/pciio.h> 50 #include <sys/rman.h> 51 #include <sys/sysctl.h> 52 #include <sys/systm.h> 53 #include <sys/taskqueue.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pci_private.h> 58 #include <dev/pci/pcib_private.h> 59 60 #include "pcib_if.h" 61 62 static int pcib_probe(device_t dev); 63 static int pcib_suspend(device_t dev); 64 static int pcib_resume(device_t dev); 65 static int pcib_power_for_sleep(device_t pcib, device_t dev, 66 int *pstate); 67 static int pcib_ari_get_id(device_t pcib, device_t dev, 68 enum pci_id_type type, uintptr_t *id); 69 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 70 u_int f, u_int reg, int width); 71 static void pcib_write_config(device_t dev, u_int b, u_int s, 72 u_int f, u_int reg, uint32_t val, int width); 73 static int pcib_ari_maxslots(device_t dev); 74 static int pcib_ari_maxfuncs(device_t dev); 75 static int pcib_try_enable_ari(device_t pcib, device_t dev); 76 static int pcib_ari_enabled(device_t pcib); 77 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 78 int *bus, int *slot, int *func); 79 #ifdef PCI_HP 80 static void pcib_pcie_ab_timeout(void *arg, int pending); 81 static void pcib_pcie_cc_timeout(void *arg, int pending); 82 static void pcib_pcie_dll_timeout(void *arg, int pending); 83 #endif 84 static int pcib_request_feature_default(device_t pcib, device_t dev, 85 enum pci_feature feature); 86 static int pcib_reset_child(device_t dev, device_t child, int flags); 87 88 static device_method_t pcib_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, pcib_probe), 91 DEVMETHOD(device_attach, pcib_attach), 92 DEVMETHOD(device_detach, pcib_detach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pcib_suspend), 95 DEVMETHOD(device_resume, pcib_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_child_present, pcib_child_present), 99 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 100 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 101 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 102 #ifdef NEW_PCIB 103 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 104 DEVMETHOD(bus_release_resource, pcib_release_resource), 105 #else 106 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 108 #endif 109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 111 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 112 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 113 DEVMETHOD(bus_reset_child, pcib_reset_child), 114 115 /* pcib interface */ 116 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 117 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 118 DEVMETHOD(pcib_read_config, pcib_read_config), 119 DEVMETHOD(pcib_write_config, pcib_write_config), 120 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 121 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 122 DEVMETHOD(pcib_release_msi, pcib_release_msi), 123 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 124 DEVMETHOD(pcib_release_msix, pcib_release_msix), 125 DEVMETHOD(pcib_map_msi, pcib_map_msi), 126 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 127 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 128 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 129 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 130 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 131 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 132 133 DEVMETHOD_END 134 }; 135 136 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 137 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, NULL, NULL, BUS_PASS_BUS); 138 139 #if defined(NEW_PCIB) || defined(PCI_HP) 140 SYSCTL_DECL(_hw_pci); 141 #endif 142 143 #ifdef NEW_PCIB 144 static int pci_clear_pcib; 145 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 146 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 147 148 /* 149 * Get the corresponding window if this resource from a child device was 150 * sub-allocated from one of our window resource managers. 151 */ 152 static struct pcib_window * 153 pcib_get_resource_window(struct pcib_softc *sc, int type, struct resource *r) 154 { 155 switch (type) { 156 case SYS_RES_IOPORT: 157 if (rman_is_region_manager(r, &sc->io.rman)) 158 return (&sc->io); 159 break; 160 case SYS_RES_MEMORY: 161 /* Prefetchable resources may live in either memory rman. */ 162 if (rman_get_flags(r) & RF_PREFETCHABLE && 163 rman_is_region_manager(r, &sc->pmem.rman)) 164 return (&sc->pmem); 165 if (rman_is_region_manager(r, &sc->mem.rman)) 166 return (&sc->mem); 167 break; 168 } 169 return (NULL); 170 } 171 172 /* 173 * Is a resource from a child device sub-allocated from one of our 174 * resource managers? 175 */ 176 static int 177 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 178 { 179 180 #ifdef PCI_RES_BUS 181 if (type == PCI_RES_BUS) 182 return (rman_is_region_manager(r, &sc->bus.rman)); 183 #endif 184 return (pcib_get_resource_window(sc, type, r) != NULL); 185 } 186 187 static int 188 pcib_is_window_open(struct pcib_window *pw) 189 { 190 191 return (pw->valid && pw->base < pw->limit); 192 } 193 194 /* 195 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 196 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 197 * when allocating the resource windows and rely on the PCI bus driver 198 * to do this for us. 199 */ 200 static void 201 pcib_activate_window(struct pcib_softc *sc, int type) 202 { 203 204 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 205 } 206 207 static void 208 pcib_write_windows(struct pcib_softc *sc, int mask) 209 { 210 device_t dev; 211 uint32_t val; 212 213 dev = sc->dev; 214 if (sc->io.valid && mask & WIN_IO) { 215 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 216 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 217 pci_write_config(dev, PCIR_IOBASEH_1, 218 sc->io.base >> 16, 2); 219 pci_write_config(dev, PCIR_IOLIMITH_1, 220 sc->io.limit >> 16, 2); 221 } 222 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 223 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 224 } 225 226 if (mask & WIN_MEM) { 227 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 228 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 229 } 230 231 if (sc->pmem.valid && mask & WIN_PMEM) { 232 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 233 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 234 pci_write_config(dev, PCIR_PMBASEH_1, 235 sc->pmem.base >> 32, 4); 236 pci_write_config(dev, PCIR_PMLIMITH_1, 237 sc->pmem.limit >> 32, 4); 238 } 239 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 240 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 241 } 242 } 243 244 /* 245 * This is used to reject I/O port allocations that conflict with an 246 * ISA alias range. 247 */ 248 static int 249 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 250 rman_res_t count) 251 { 252 rman_res_t next_alias; 253 254 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 255 return (0); 256 257 /* Only check fixed ranges for overlap. */ 258 if (start + count - 1 != end) 259 return (0); 260 261 /* ISA aliases are only in the lower 64KB of I/O space. */ 262 if (start >= 65536) 263 return (0); 264 265 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 266 if (start < 0x100) 267 goto alias; 268 269 /* 270 * If the start address is an alias, the range is an alias. 271 * Otherwise, compute the start of the next alias range and 272 * check if it is before the end of the candidate range. 273 */ 274 if ((start & 0x300) != 0) 275 goto alias; 276 next_alias = (start & ~0x3fful) | 0x100; 277 if (next_alias <= end) 278 goto alias; 279 return (0); 280 281 alias: 282 if (bootverbose) 283 device_printf(sc->dev, 284 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 285 end); 286 return (1); 287 } 288 289 static void 290 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 291 int count) 292 { 293 struct resource **newarray; 294 int error, i; 295 296 newarray = malloc(sizeof(struct resource *) * (w->count + count), 297 M_DEVBUF, M_WAITOK); 298 if (w->res != NULL) 299 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 300 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 301 free(w->res, M_DEVBUF); 302 w->res = newarray; 303 w->count += count; 304 305 for (i = 0; i < count; i++) { 306 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 307 rman_get_end(res[i])); 308 if (error) 309 panic("Failed to add resource to rman"); 310 } 311 } 312 313 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 314 315 static void 316 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 317 void *arg) 318 { 319 rman_res_t next_end; 320 321 /* 322 * If start is within an ISA alias range, move up to the start 323 * of the next non-alias range. As a special case, addresses 324 * in the range 0x000 - 0x0ff should also be skipped since 325 * those are used for various system I/O devices in ISA 326 * systems. 327 */ 328 if (start <= 65535) { 329 if (start < 0x100 || (start & 0x300) != 0) { 330 start &= ~0x3ff; 331 start += 0x400; 332 } 333 } 334 335 /* ISA aliases are only in the lower 64KB of I/O space. */ 336 while (start <= MIN(end, 65535)) { 337 next_end = MIN(start | 0xff, end); 338 cb(start, next_end, arg); 339 start += 0x400; 340 } 341 342 if (start <= end) 343 cb(start, end, arg); 344 } 345 346 static void 347 count_ranges(rman_res_t start, rman_res_t end, void *arg) 348 { 349 int *countp; 350 351 countp = arg; 352 (*countp)++; 353 } 354 355 struct alloc_state { 356 struct resource **res; 357 struct pcib_softc *sc; 358 int count, error; 359 }; 360 361 static void 362 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 363 { 364 struct alloc_state *as; 365 struct pcib_window *w; 366 int rid; 367 368 as = arg; 369 if (as->error != 0) 370 return; 371 372 w = &as->sc->io; 373 rid = w->reg; 374 if (bootverbose) 375 device_printf(as->sc->dev, 376 "allocating non-ISA range %#jx-%#jx\n", start, end); 377 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 378 &rid, start, end, end - start + 1, 0); 379 if (as->res[as->count] == NULL) 380 as->error = ENXIO; 381 else 382 as->count++; 383 } 384 385 static int 386 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 387 { 388 struct alloc_state as; 389 int i, new_count; 390 391 /* First, see how many ranges we need. */ 392 new_count = 0; 393 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 394 395 /* Second, allocate the ranges. */ 396 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 397 M_WAITOK); 398 as.sc = sc; 399 as.count = 0; 400 as.error = 0; 401 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 402 if (as.error != 0) { 403 for (i = 0; i < as.count; i++) 404 bus_release_resource(sc->dev, SYS_RES_IOPORT, 405 sc->io.reg, as.res[i]); 406 free(as.res, M_DEVBUF); 407 return (as.error); 408 } 409 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 410 411 /* Third, add the ranges to the window. */ 412 pcib_add_window_resources(&sc->io, as.res, as.count); 413 free(as.res, M_DEVBUF); 414 return (0); 415 } 416 417 static void 418 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 419 int flags, pci_addr_t max_address) 420 { 421 struct resource *res; 422 char buf[64]; 423 int error, rid; 424 425 if (max_address != (rman_res_t)max_address) 426 max_address = ~0; 427 w->rman.rm_start = 0; 428 w->rman.rm_end = max_address; 429 w->rman.rm_type = RMAN_ARRAY; 430 snprintf(buf, sizeof(buf), "%s %s window", 431 device_get_nameunit(sc->dev), w->name); 432 w->rman.rm_descr = strdup(buf, M_DEVBUF); 433 error = rman_init(&w->rman); 434 if (error) 435 panic("Failed to initialize %s %s rman", 436 device_get_nameunit(sc->dev), w->name); 437 438 if (!pcib_is_window_open(w)) 439 return; 440 441 if (w->base > max_address || w->limit > max_address) { 442 device_printf(sc->dev, 443 "initial %s window has too many bits, ignoring\n", w->name); 444 return; 445 } 446 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 447 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 448 else { 449 rid = w->reg; 450 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 451 w->limit - w->base + 1, flags); 452 if (res != NULL) 453 pcib_add_window_resources(w, &res, 1); 454 } 455 if (w->res == NULL) { 456 device_printf(sc->dev, 457 "failed to allocate initial %s window: %#jx-%#jx\n", 458 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 459 w->base = max_address; 460 w->limit = 0; 461 pcib_write_windows(sc, w->mask); 462 return; 463 } 464 pcib_activate_window(sc, type); 465 } 466 467 /* 468 * Initialize I/O windows. 469 */ 470 static void 471 pcib_probe_windows(struct pcib_softc *sc) 472 { 473 pci_addr_t max; 474 device_t dev; 475 uint32_t val; 476 477 dev = sc->dev; 478 479 if (pci_clear_pcib) { 480 pcib_bridge_init(dev); 481 } 482 483 /* Determine if the I/O port window is implemented. */ 484 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 485 if (val == 0) { 486 /* 487 * If 'val' is zero, then only 16-bits of I/O space 488 * are supported. 489 */ 490 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 491 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 492 sc->io.valid = 1; 493 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 494 } 495 } else 496 sc->io.valid = 1; 497 498 /* Read the existing I/O port window. */ 499 if (sc->io.valid) { 500 sc->io.reg = PCIR_IOBASEL_1; 501 sc->io.step = 12; 502 sc->io.mask = WIN_IO; 503 sc->io.name = "I/O port"; 504 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 505 sc->io.base = PCI_PPBIOBASE( 506 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 507 sc->io.limit = PCI_PPBIOLIMIT( 508 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 509 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 510 max = 0xffffffff; 511 } else { 512 sc->io.base = PCI_PPBIOBASE(0, val); 513 sc->io.limit = PCI_PPBIOLIMIT(0, 514 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 515 max = 0xffff; 516 } 517 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 518 } 519 520 /* Read the existing memory window. */ 521 sc->mem.valid = 1; 522 sc->mem.reg = PCIR_MEMBASE_1; 523 sc->mem.step = 20; 524 sc->mem.mask = WIN_MEM; 525 sc->mem.name = "memory"; 526 sc->mem.base = PCI_PPBMEMBASE(0, 527 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 528 sc->mem.limit = PCI_PPBMEMLIMIT(0, 529 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 530 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 531 532 /* Determine if the prefetchable memory window is implemented. */ 533 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 534 if (val == 0) { 535 /* 536 * If 'val' is zero, then only 32-bits of memory space 537 * are supported. 538 */ 539 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 540 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 541 sc->pmem.valid = 1; 542 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 543 } 544 } else 545 sc->pmem.valid = 1; 546 547 /* Read the existing prefetchable memory window. */ 548 if (sc->pmem.valid) { 549 sc->pmem.reg = PCIR_PMBASEL_1; 550 sc->pmem.step = 20; 551 sc->pmem.mask = WIN_PMEM; 552 sc->pmem.name = "prefetch"; 553 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 554 sc->pmem.base = PCI_PPBMEMBASE( 555 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 556 sc->pmem.limit = PCI_PPBMEMLIMIT( 557 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 558 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 559 max = 0xffffffffffffffff; 560 } else { 561 sc->pmem.base = PCI_PPBMEMBASE(0, val); 562 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 563 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 564 max = 0xffffffff; 565 } 566 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 567 RF_PREFETCHABLE, max); 568 } 569 } 570 571 static void 572 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 573 { 574 device_t dev; 575 int error, i; 576 577 if (!w->valid) 578 return; 579 580 dev = sc->dev; 581 error = rman_fini(&w->rman); 582 if (error) { 583 device_printf(dev, "failed to release %s rman\n", w->name); 584 return; 585 } 586 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 587 588 for (i = 0; i < w->count; i++) { 589 error = bus_free_resource(dev, type, w->res[i]); 590 if (error) 591 device_printf(dev, 592 "failed to release %s resource: %d\n", w->name, 593 error); 594 } 595 free(w->res, M_DEVBUF); 596 } 597 598 static void 599 pcib_free_windows(struct pcib_softc *sc) 600 { 601 602 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 603 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 604 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 605 } 606 607 #ifdef PCI_RES_BUS 608 /* 609 * Allocate a suitable secondary bus for this bridge if needed and 610 * initialize the resource manager for the secondary bus range. Note 611 * that the minimum count is a desired value and this may allocate a 612 * smaller range. 613 */ 614 void 615 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 616 { 617 char buf[64]; 618 int error, rid, sec_reg; 619 620 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 621 case PCIM_HDRTYPE_BRIDGE: 622 sec_reg = PCIR_SECBUS_1; 623 bus->sub_reg = PCIR_SUBBUS_1; 624 break; 625 case PCIM_HDRTYPE_CARDBUS: 626 sec_reg = PCIR_SECBUS_2; 627 bus->sub_reg = PCIR_SUBBUS_2; 628 break; 629 default: 630 panic("not a PCI bridge"); 631 } 632 bus->sec = pci_read_config(dev, sec_reg, 1); 633 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 634 bus->dev = dev; 635 bus->rman.rm_start = 0; 636 bus->rman.rm_end = PCI_BUSMAX; 637 bus->rman.rm_type = RMAN_ARRAY; 638 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 639 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 640 error = rman_init(&bus->rman); 641 if (error) 642 panic("Failed to initialize %s bus number rman", 643 device_get_nameunit(dev)); 644 645 /* 646 * Allocate a bus range. This will return an existing bus range 647 * if one exists, or a new bus range if one does not. 648 */ 649 rid = 0; 650 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 651 min_count, 0); 652 if (bus->res == NULL) { 653 /* 654 * Fall back to just allocating a range of a single bus 655 * number. 656 */ 657 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 658 1, 0); 659 } else if (rman_get_size(bus->res) < min_count) 660 /* 661 * Attempt to grow the existing range to satisfy the 662 * minimum desired count. 663 */ 664 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 665 rman_get_start(bus->res), rman_get_start(bus->res) + 666 min_count - 1); 667 668 /* 669 * Add the initial resource to the rman. 670 */ 671 if (bus->res != NULL) { 672 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 673 rman_get_end(bus->res)); 674 if (error) 675 panic("Failed to add resource to rman"); 676 bus->sec = rman_get_start(bus->res); 677 bus->sub = rman_get_end(bus->res); 678 } 679 } 680 681 void 682 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 683 { 684 int error; 685 686 error = rman_fini(&bus->rman); 687 if (error) { 688 device_printf(dev, "failed to release bus number rman\n"); 689 return; 690 } 691 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 692 693 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 694 if (error) 695 device_printf(dev, 696 "failed to release bus numbers resource: %d\n", error); 697 } 698 699 static struct resource * 700 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 701 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 702 { 703 struct resource *res; 704 705 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 706 child); 707 if (res == NULL) 708 return (NULL); 709 710 if (bootverbose) 711 device_printf(bus->dev, 712 "allocated bus range (%ju-%ju) for rid %d of %s\n", 713 rman_get_start(res), rman_get_end(res), *rid, 714 pcib_child_name(child)); 715 rman_set_rid(res, *rid); 716 return (res); 717 } 718 719 /* 720 * Attempt to grow the secondary bus range. This is much simpler than 721 * for I/O windows as the range can only be grown by increasing 722 * subbus. 723 */ 724 static int 725 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 726 { 727 rman_res_t old_end; 728 int error; 729 730 old_end = rman_get_end(bus->res); 731 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 732 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 733 rman_get_start(bus->res), new_end); 734 if (error) 735 return (error); 736 if (bootverbose) 737 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 738 rman_get_start(bus->res), rman_get_end(bus->res)); 739 error = rman_manage_region(&bus->rman, old_end + 1, 740 rman_get_end(bus->res)); 741 if (error) 742 panic("Failed to add resource to rman"); 743 bus->sub = rman_get_end(bus->res); 744 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 745 return (0); 746 } 747 748 struct resource * 749 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 750 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 751 { 752 struct resource *res; 753 rman_res_t start_free, end_free, new_end; 754 755 /* 756 * First, see if the request can be satisified by the existing 757 * bus range. 758 */ 759 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 760 if (res != NULL) 761 return (res); 762 763 /* 764 * Figure out a range to grow the bus range. First, find the 765 * first bus number after the last allocated bus in the rman and 766 * enforce that as a minimum starting point for the range. 767 */ 768 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 769 end_free != bus->sub) 770 start_free = bus->sub + 1; 771 if (start_free < start) 772 start_free = start; 773 new_end = start_free + count - 1; 774 775 /* 776 * See if this new range would satisfy the request if it 777 * succeeds. 778 */ 779 if (new_end > end) 780 return (NULL); 781 782 /* Finally, attempt to grow the existing resource. */ 783 if (bootverbose) { 784 device_printf(bus->dev, 785 "attempting to grow bus range for %ju buses\n", count); 786 printf("\tback candidate range: %ju-%ju\n", start_free, 787 new_end); 788 } 789 if (pcib_grow_subbus(bus, new_end) == 0) 790 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 791 flags)); 792 return (NULL); 793 } 794 #endif 795 796 #else 797 798 /* 799 * Is the prefetch window open (eg, can we allocate memory in it?) 800 */ 801 static int 802 pcib_is_prefetch_open(struct pcib_softc *sc) 803 { 804 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 805 } 806 807 /* 808 * Is the nonprefetch window open (eg, can we allocate memory in it?) 809 */ 810 static int 811 pcib_is_nonprefetch_open(struct pcib_softc *sc) 812 { 813 return (sc->membase > 0 && sc->membase < sc->memlimit); 814 } 815 816 /* 817 * Is the io window open (eg, can we allocate ports in it?) 818 */ 819 static int 820 pcib_is_io_open(struct pcib_softc *sc) 821 { 822 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 823 } 824 825 /* 826 * Get current I/O decode. 827 */ 828 static void 829 pcib_get_io_decode(struct pcib_softc *sc) 830 { 831 device_t dev; 832 uint32_t iolow; 833 834 dev = sc->dev; 835 836 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 837 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 838 sc->iobase = PCI_PPBIOBASE( 839 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 840 else 841 sc->iobase = PCI_PPBIOBASE(0, iolow); 842 843 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 844 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 845 sc->iolimit = PCI_PPBIOLIMIT( 846 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 847 else 848 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 849 } 850 851 /* 852 * Get current memory decode. 853 */ 854 static void 855 pcib_get_mem_decode(struct pcib_softc *sc) 856 { 857 device_t dev; 858 pci_addr_t pmemlow; 859 860 dev = sc->dev; 861 862 sc->membase = PCI_PPBMEMBASE(0, 863 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 864 sc->memlimit = PCI_PPBMEMLIMIT(0, 865 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 866 867 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 868 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 869 sc->pmembase = PCI_PPBMEMBASE( 870 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 871 else 872 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 873 874 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 875 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 876 sc->pmemlimit = PCI_PPBMEMLIMIT( 877 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 878 else 879 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 880 } 881 882 /* 883 * Restore previous I/O decode. 884 */ 885 static void 886 pcib_set_io_decode(struct pcib_softc *sc) 887 { 888 device_t dev; 889 uint32_t iohi; 890 891 dev = sc->dev; 892 893 iohi = sc->iobase >> 16; 894 if (iohi > 0) 895 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 896 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 897 898 iohi = sc->iolimit >> 16; 899 if (iohi > 0) 900 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 901 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 902 } 903 904 /* 905 * Restore previous memory decode. 906 */ 907 static void 908 pcib_set_mem_decode(struct pcib_softc *sc) 909 { 910 device_t dev; 911 pci_addr_t pmemhi; 912 913 dev = sc->dev; 914 915 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 916 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 917 918 pmemhi = sc->pmembase >> 32; 919 if (pmemhi > 0) 920 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 921 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 922 923 pmemhi = sc->pmemlimit >> 32; 924 if (pmemhi > 0) 925 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 926 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 927 } 928 #endif 929 930 #ifdef PCI_HP 931 /* 932 * PCI-express HotPlug support. 933 */ 934 static int pci_enable_pcie_hp = 1; 935 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 936 &pci_enable_pcie_hp, 0, 937 "Enable support for native PCI-express HotPlug."); 938 939 TASKQUEUE_DEFINE_THREAD(pci_hp); 940 941 static void 942 pcib_probe_hotplug(struct pcib_softc *sc) 943 { 944 device_t dev; 945 uint32_t link_cap; 946 uint16_t link_sta, slot_sta; 947 948 if (!pci_enable_pcie_hp) 949 return; 950 951 dev = sc->dev; 952 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 953 return; 954 955 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 956 return; 957 958 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 959 960 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 961 return; 962 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 963 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 964 return; 965 966 /* 967 * Some devices report that they have an MRL when they actually 968 * do not. Since they always report that the MRL is open, child 969 * devices would be ignored. Try to detect these devices and 970 * ignore their claim of HotPlug support. 971 * 972 * If there is an open MRL but the Data Link Layer is active, 973 * the MRL is not real. 974 */ 975 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 976 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 977 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 978 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 979 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 980 return; 981 } 982 } 983 984 /* 985 * Now that we're sure we want to do hot plug, ask the 986 * firmware, if any, if that's OK. 987 */ 988 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 989 if (bootverbose) 990 device_printf(dev, "Unable to activate hot plug feature.\n"); 991 return; 992 } 993 994 sc->flags |= PCIB_HOTPLUG; 995 } 996 997 /* 998 * Send a HotPlug command to the slot control register. If this slot 999 * uses command completion interrupts and a previous command is still 1000 * in progress, then the command is dropped. Once the previous 1001 * command completes or times out, pcib_pcie_hotplug_update() will be 1002 * invoked to post a new command based on the slot's state at that 1003 * time. 1004 */ 1005 static void 1006 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 1007 { 1008 device_t dev; 1009 uint16_t ctl, new; 1010 1011 dev = sc->dev; 1012 1013 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 1014 return; 1015 1016 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 1017 new = (ctl & ~mask) | val; 1018 if (new == ctl) 1019 return; 1020 if (bootverbose) 1021 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 1022 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 1023 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 1024 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 1025 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 1026 if (!cold) 1027 taskqueue_enqueue_timeout(taskqueue_pci_hp, 1028 &sc->pcie_cc_task, hz); 1029 } 1030 } 1031 1032 static void 1033 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 1034 { 1035 device_t dev; 1036 1037 dev = sc->dev; 1038 1039 if (bootverbose) 1040 device_printf(dev, "Command Completed\n"); 1041 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 1042 return; 1043 taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task, NULL); 1044 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1045 wakeup(sc); 1046 } 1047 1048 /* 1049 * Returns true if a card is fully inserted from the user's 1050 * perspective. It may not yet be ready for access, but the driver 1051 * can now start enabling access if necessary. 1052 */ 1053 static bool 1054 pcib_hotplug_inserted(struct pcib_softc *sc) 1055 { 1056 1057 /* Pretend the card isn't present if a detach is forced. */ 1058 if (sc->flags & PCIB_DETACHING) 1059 return (false); 1060 1061 /* Card must be present in the slot. */ 1062 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1063 return (false); 1064 1065 /* A power fault implicitly turns off power to the slot. */ 1066 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1067 return (false); 1068 1069 /* If the MRL is disengaged, the slot is powered off. */ 1070 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1071 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1072 return (false); 1073 1074 return (true); 1075 } 1076 1077 /* 1078 * Returns -1 if the card is fully inserted, powered, and ready for 1079 * access. Otherwise, returns 0. 1080 */ 1081 static int 1082 pcib_hotplug_present(struct pcib_softc *sc) 1083 { 1084 1085 /* Card must be inserted. */ 1086 if (!pcib_hotplug_inserted(sc)) 1087 return (0); 1088 1089 /* Require the Data Link Layer to be active. */ 1090 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1091 return (0); 1092 1093 return (-1); 1094 } 1095 1096 static int pci_enable_pcie_ei = 0; 1097 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_ei, CTLFLAG_RWTUN, 1098 &pci_enable_pcie_ei, 0, 1099 "Enable support for PCI-express Electromechanical Interlock."); 1100 1101 static void 1102 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1103 bool schedule_task) 1104 { 1105 bool card_inserted, ei_engaged; 1106 1107 /* Clear DETACHING if Presence Detect has cleared. */ 1108 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1109 PCIEM_SLOT_STA_PDC) 1110 sc->flags &= ~PCIB_DETACHING; 1111 1112 card_inserted = pcib_hotplug_inserted(sc); 1113 1114 /* Turn the power indicator on if a card is inserted. */ 1115 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1116 mask |= PCIEM_SLOT_CTL_PIC; 1117 if (card_inserted) 1118 val |= PCIEM_SLOT_CTL_PI_ON; 1119 else if (sc->flags & PCIB_DETACH_PENDING) 1120 val |= PCIEM_SLOT_CTL_PI_BLINK; 1121 else 1122 val |= PCIEM_SLOT_CTL_PI_OFF; 1123 } 1124 1125 /* Turn the power on via the Power Controller if a card is inserted. */ 1126 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1127 mask |= PCIEM_SLOT_CTL_PCC; 1128 if (card_inserted) 1129 val |= PCIEM_SLOT_CTL_PC_ON; 1130 else 1131 val |= PCIEM_SLOT_CTL_PC_OFF; 1132 } 1133 1134 /* 1135 * If a card is inserted, enable the Electromechanical 1136 * Interlock. If a card is not inserted (or we are in the 1137 * process of detaching), disable the Electromechanical 1138 * Interlock. 1139 */ 1140 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) && 1141 pci_enable_pcie_ei) { 1142 mask |= PCIEM_SLOT_CTL_EIC; 1143 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1144 if (card_inserted != ei_engaged) 1145 val |= PCIEM_SLOT_CTL_EIC; 1146 } 1147 1148 /* 1149 * Start a timer to see if the Data Link Layer times out. 1150 * Note that we only start the timer if Presence Detect or MRL Sensor 1151 * changed on this interrupt. Stop any scheduled timer if 1152 * the Data Link Layer is active. 1153 */ 1154 if (card_inserted && 1155 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1156 sc->pcie_slot_sta & 1157 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1158 if (cold) 1159 device_printf(sc->dev, 1160 "Data Link Layer inactive\n"); 1161 else 1162 taskqueue_enqueue_timeout(taskqueue_pci_hp, 1163 &sc->pcie_dll_task, hz); 1164 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1165 taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_dll_task, 1166 NULL); 1167 1168 pcib_pcie_hotplug_command(sc, val, mask); 1169 1170 /* 1171 * During attach the child "pci" device is added synchronously; 1172 * otherwise, the task is scheduled to manage the child 1173 * device. 1174 */ 1175 if (schedule_task && 1176 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1177 taskqueue_enqueue(taskqueue_pci_hp, &sc->pcie_hp_task); 1178 } 1179 1180 static void 1181 pcib_pcie_intr_hotplug(void *arg) 1182 { 1183 struct pcib_softc *sc; 1184 device_t dev; 1185 uint16_t old_slot_sta; 1186 1187 sc = arg; 1188 dev = sc->dev; 1189 PCIB_HP_LOCK(sc); 1190 old_slot_sta = sc->pcie_slot_sta; 1191 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1192 1193 /* Clear the events just reported. */ 1194 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1195 1196 if (bootverbose) 1197 device_printf(dev, "HotPlug interrupt: %#x\n", 1198 sc->pcie_slot_sta); 1199 1200 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1201 if (sc->flags & PCIB_DETACH_PENDING) { 1202 device_printf(dev, 1203 "Attention Button Pressed: Detach Cancelled\n"); 1204 sc->flags &= ~PCIB_DETACH_PENDING; 1205 taskqueue_cancel_timeout(taskqueue_pci_hp, 1206 &sc->pcie_ab_task, NULL); 1207 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) { 1208 /* Only initiate detach sequence if device present. */ 1209 device_printf(dev, 1210 "Attention Button Pressed: Detaching in 5 seconds\n"); 1211 sc->flags |= PCIB_DETACH_PENDING; 1212 taskqueue_enqueue_timeout(taskqueue_pci_hp, 1213 &sc->pcie_ab_task, 5 * hz); 1214 } 1215 } 1216 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1217 device_printf(dev, "Power Fault Detected\n"); 1218 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1219 device_printf(dev, "MRL Sensor Changed to %s\n", 1220 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1221 "closed"); 1222 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1223 device_printf(dev, "Presence Detect Changed to %s\n", 1224 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1225 "empty"); 1226 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1227 pcib_pcie_hotplug_command_completed(sc); 1228 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1229 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1230 if (bootverbose) 1231 device_printf(dev, 1232 "Data Link Layer State Changed to %s\n", 1233 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1234 "active" : "inactive"); 1235 } 1236 1237 pcib_pcie_hotplug_update(sc, 0, 0, true); 1238 PCIB_HP_UNLOCK(sc); 1239 } 1240 1241 static void 1242 pcib_pcie_hotplug_task(void *context, int pending) 1243 { 1244 struct pcib_softc *sc; 1245 device_t dev; 1246 1247 sc = context; 1248 PCIB_HP_LOCK(sc); 1249 dev = sc->dev; 1250 if (pcib_hotplug_present(sc) != 0) { 1251 if (sc->child == NULL) { 1252 sc->child = device_add_child(dev, "pci", -1); 1253 bus_generic_attach(dev); 1254 } 1255 } else { 1256 if (sc->child != NULL) { 1257 if (device_delete_child(dev, sc->child) == 0) 1258 sc->child = NULL; 1259 } 1260 } 1261 PCIB_HP_UNLOCK(sc); 1262 } 1263 1264 static void 1265 pcib_pcie_ab_timeout(void *arg, int pending) 1266 { 1267 struct pcib_softc *sc = arg; 1268 1269 PCIB_HP_LOCK(sc); 1270 if (sc->flags & PCIB_DETACH_PENDING) { 1271 sc->flags |= PCIB_DETACHING; 1272 sc->flags &= ~PCIB_DETACH_PENDING; 1273 pcib_pcie_hotplug_update(sc, 0, 0, true); 1274 } 1275 PCIB_HP_UNLOCK(sc); 1276 } 1277 1278 static void 1279 pcib_pcie_cc_timeout(void *arg, int pending) 1280 { 1281 struct pcib_softc *sc = arg; 1282 device_t dev = sc->dev; 1283 uint16_t sta; 1284 1285 PCIB_HP_LOCK(sc); 1286 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1287 if (!(sta & PCIEM_SLOT_STA_CC)) { 1288 device_printf(dev, "HotPlug Command Timed Out\n"); 1289 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1290 } else { 1291 device_printf(dev, 1292 "Missed HotPlug interrupt waiting for Command Completion\n"); 1293 pcib_pcie_intr_hotplug(sc); 1294 } 1295 PCIB_HP_UNLOCK(sc); 1296 } 1297 1298 static void 1299 pcib_pcie_dll_timeout(void *arg, int pending) 1300 { 1301 struct pcib_softc *sc = arg; 1302 device_t dev = sc->dev; 1303 uint16_t sta; 1304 1305 PCIB_HP_LOCK(sc); 1306 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1307 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1308 device_printf(dev, 1309 "Timed out waiting for Data Link Layer Active\n"); 1310 sc->flags |= PCIB_DETACHING; 1311 pcib_pcie_hotplug_update(sc, 0, 0, true); 1312 } else if (sta != sc->pcie_link_sta) { 1313 device_printf(dev, 1314 "Missed HotPlug interrupt waiting for DLL Active\n"); 1315 pcib_pcie_intr_hotplug(sc); 1316 } 1317 PCIB_HP_UNLOCK(sc); 1318 } 1319 1320 static int 1321 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1322 { 1323 device_t dev; 1324 int count, error, rid; 1325 1326 rid = -1; 1327 dev = sc->dev; 1328 1329 /* 1330 * For simplicity, only use MSI-X if there is a single message. 1331 * To support a device with multiple messages we would have to 1332 * use remap intr if the MSI number is not 0. 1333 */ 1334 count = pci_msix_count(dev); 1335 if (count == 1) { 1336 error = pci_alloc_msix(dev, &count); 1337 if (error == 0) 1338 rid = 1; 1339 } 1340 1341 if (rid < 0 && pci_msi_count(dev) > 0) { 1342 count = 1; 1343 error = pci_alloc_msi(dev, &count); 1344 if (error == 0) 1345 rid = 1; 1346 } 1347 1348 if (rid < 0) 1349 rid = 0; 1350 1351 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1352 RF_ACTIVE | RF_SHAREABLE); 1353 if (sc->pcie_irq == NULL) { 1354 device_printf(dev, 1355 "Failed to allocate interrupt for PCI-e events\n"); 1356 if (rid > 0) 1357 pci_release_msi(dev); 1358 return (ENXIO); 1359 } 1360 1361 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE, 1362 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1363 if (error) { 1364 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1365 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1366 if (rid > 0) 1367 pci_release_msi(dev); 1368 return (error); 1369 } 1370 return (0); 1371 } 1372 1373 static int 1374 pcib_release_pcie_irq(struct pcib_softc *sc) 1375 { 1376 device_t dev; 1377 int error; 1378 1379 dev = sc->dev; 1380 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1381 if (error) 1382 return (error); 1383 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1384 if (error) 1385 return (error); 1386 return (pci_release_msi(dev)); 1387 } 1388 1389 static void 1390 pcib_setup_hotplug(struct pcib_softc *sc) 1391 { 1392 device_t dev; 1393 uint16_t mask, val; 1394 1395 dev = sc->dev; 1396 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1397 TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_ab_task, 0, 1398 pcib_pcie_ab_timeout, sc); 1399 TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_cc_task, 0, 1400 pcib_pcie_cc_timeout, sc); 1401 TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_dll_task, 0, 1402 pcib_pcie_dll_timeout, sc); 1403 sc->pcie_hp_lock = bus_topo_mtx(); 1404 1405 /* Allocate IRQ. */ 1406 if (pcib_alloc_pcie_irq(sc) != 0) 1407 return; 1408 1409 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1410 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1411 1412 /* Clear any events previously pending. */ 1413 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1414 1415 /* Enable HotPlug events. */ 1416 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1417 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1418 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1419 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1420 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1421 val |= PCIEM_SLOT_CTL_ABPE; 1422 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1423 val |= PCIEM_SLOT_CTL_PFDE; 1424 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1425 val |= PCIEM_SLOT_CTL_MRLSCE; 1426 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1427 val |= PCIEM_SLOT_CTL_CCIE; 1428 1429 /* Turn the attention indicator off. */ 1430 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1431 mask |= PCIEM_SLOT_CTL_AIC; 1432 val |= PCIEM_SLOT_CTL_AI_OFF; 1433 } 1434 1435 pcib_pcie_hotplug_update(sc, val, mask, false); 1436 } 1437 1438 static int 1439 pcib_detach_hotplug(struct pcib_softc *sc) 1440 { 1441 uint16_t mask, val; 1442 int error; 1443 1444 /* Disable the card in the slot and force it to detach. */ 1445 if (sc->flags & PCIB_DETACH_PENDING) { 1446 sc->flags &= ~PCIB_DETACH_PENDING; 1447 taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_ab_task, 1448 NULL); 1449 } 1450 sc->flags |= PCIB_DETACHING; 1451 1452 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1453 taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task, 1454 NULL); 1455 tsleep(sc, 0, "hpcmd", hz); 1456 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1457 } 1458 1459 /* Disable HotPlug events. */ 1460 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1461 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1462 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1463 val = 0; 1464 1465 /* Turn the attention indicator off. */ 1466 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1467 mask |= PCIEM_SLOT_CTL_AIC; 1468 val |= PCIEM_SLOT_CTL_AI_OFF; 1469 } 1470 1471 pcib_pcie_hotplug_update(sc, val, mask, false); 1472 1473 error = pcib_release_pcie_irq(sc); 1474 if (error) 1475 return (error); 1476 taskqueue_drain(taskqueue_pci_hp, &sc->pcie_hp_task); 1477 taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_ab_task); 1478 taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_cc_task); 1479 taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_dll_task); 1480 return (0); 1481 } 1482 #endif 1483 1484 /* 1485 * Get current bridge configuration. 1486 */ 1487 static void 1488 pcib_cfg_save(struct pcib_softc *sc) 1489 { 1490 #ifndef NEW_PCIB 1491 device_t dev; 1492 uint16_t command; 1493 1494 dev = sc->dev; 1495 1496 command = pci_read_config(dev, PCIR_COMMAND, 2); 1497 if (command & PCIM_CMD_PORTEN) 1498 pcib_get_io_decode(sc); 1499 if (command & PCIM_CMD_MEMEN) 1500 pcib_get_mem_decode(sc); 1501 #endif 1502 } 1503 1504 /* 1505 * Restore previous bridge configuration. 1506 */ 1507 static void 1508 pcib_cfg_restore(struct pcib_softc *sc) 1509 { 1510 #ifndef NEW_PCIB 1511 uint16_t command; 1512 #endif 1513 1514 #ifdef NEW_PCIB 1515 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1516 #else 1517 command = pci_read_config(sc->dev, PCIR_COMMAND, 2); 1518 if (command & PCIM_CMD_PORTEN) 1519 pcib_set_io_decode(sc); 1520 if (command & PCIM_CMD_MEMEN) 1521 pcib_set_mem_decode(sc); 1522 #endif 1523 } 1524 1525 /* 1526 * Generic device interface 1527 */ 1528 static int 1529 pcib_probe(device_t dev) 1530 { 1531 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1532 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1533 device_set_desc(dev, "PCI-PCI bridge"); 1534 return(-10000); 1535 } 1536 return(ENXIO); 1537 } 1538 1539 void 1540 pcib_attach_common(device_t dev) 1541 { 1542 struct pcib_softc *sc; 1543 struct sysctl_ctx_list *sctx; 1544 struct sysctl_oid *soid; 1545 int comma; 1546 1547 sc = device_get_softc(dev); 1548 sc->dev = dev; 1549 1550 /* 1551 * Get current bridge configuration. 1552 */ 1553 sc->domain = pci_get_domain(dev); 1554 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1555 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1556 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1557 #endif 1558 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1559 pcib_cfg_save(sc); 1560 1561 /* 1562 * The primary bus register should always be the bus of the 1563 * parent. 1564 */ 1565 sc->pribus = pci_get_bus(dev); 1566 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1567 1568 /* 1569 * Setup sysctl reporting nodes 1570 */ 1571 sctx = device_get_sysctl_ctx(dev); 1572 soid = device_get_sysctl_tree(dev); 1573 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1574 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1575 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1576 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1577 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1578 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1579 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1580 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1581 1582 /* 1583 * Quirk handling. 1584 */ 1585 switch (pci_get_devid(dev)) { 1586 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1587 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1588 { 1589 uint8_t supbus; 1590 1591 supbus = pci_read_config(dev, 0x41, 1); 1592 if (supbus != 0xff) { 1593 sc->bus.sec = supbus + 1; 1594 sc->bus.sub = supbus + 1; 1595 } 1596 break; 1597 } 1598 #endif 1599 1600 /* 1601 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1602 * and it is a subtractive bridge. However, the ProgIf is wrong 1603 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1604 * happen. There are also Toshiba and Cavium ThunderX bridges 1605 * that behave this way. 1606 */ 1607 case 0xa002177d: /* Cavium ThunderX */ 1608 case 0x124b8086: /* Intel 82380FB Mobile */ 1609 case 0x060513d7: /* Toshiba ???? */ 1610 sc->flags |= PCIB_SUBTRACTIVE; 1611 break; 1612 1613 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1614 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1615 case 0x00dd10de: 1616 { 1617 char *cp; 1618 1619 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1620 break; 1621 if (strncmp(cp, "Compal", 6) != 0) { 1622 freeenv(cp); 1623 break; 1624 } 1625 freeenv(cp); 1626 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1627 break; 1628 if (strncmp(cp, "08A0", 4) != 0) { 1629 freeenv(cp); 1630 break; 1631 } 1632 freeenv(cp); 1633 if (sc->bus.sub < 0xa) { 1634 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1635 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1636 } 1637 break; 1638 } 1639 #endif 1640 } 1641 1642 if (pci_msi_device_blacklisted(dev)) 1643 sc->flags |= PCIB_DISABLE_MSI; 1644 1645 if (pci_msix_device_blacklisted(dev)) 1646 sc->flags |= PCIB_DISABLE_MSIX; 1647 1648 /* 1649 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1650 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1651 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1652 * This means they act as if they were subtractively decoding 1653 * bridges and pass all transactions. Mark them and real ProgIf 1 1654 * parts as subtractive. 1655 */ 1656 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1657 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1658 sc->flags |= PCIB_SUBTRACTIVE; 1659 1660 #ifdef PCI_HP 1661 pcib_probe_hotplug(sc); 1662 #endif 1663 #ifdef NEW_PCIB 1664 #ifdef PCI_RES_BUS 1665 pcib_setup_secbus(dev, &sc->bus, 1); 1666 #endif 1667 pcib_probe_windows(sc); 1668 #endif 1669 #ifdef PCI_HP 1670 if (sc->flags & PCIB_HOTPLUG) 1671 pcib_setup_hotplug(sc); 1672 #endif 1673 if (bootverbose) { 1674 device_printf(dev, " domain %d\n", sc->domain); 1675 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1676 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1677 #ifdef NEW_PCIB 1678 if (pcib_is_window_open(&sc->io)) 1679 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1680 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1681 if (pcib_is_window_open(&sc->mem)) 1682 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1683 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1684 if (pcib_is_window_open(&sc->pmem)) 1685 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1686 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1687 #else 1688 if (pcib_is_io_open(sc)) 1689 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1690 sc->iobase, sc->iolimit); 1691 if (pcib_is_nonprefetch_open(sc)) 1692 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1693 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1694 if (pcib_is_prefetch_open(sc)) 1695 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1696 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1697 #endif 1698 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1699 sc->flags & PCIB_SUBTRACTIVE) { 1700 device_printf(dev, " special decode "); 1701 comma = 0; 1702 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1703 printf("ISA"); 1704 comma = 1; 1705 } 1706 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1707 printf("%sVGA", comma ? ", " : ""); 1708 comma = 1; 1709 } 1710 if (sc->flags & PCIB_SUBTRACTIVE) 1711 printf("%ssubtractive", comma ? ", " : ""); 1712 printf("\n"); 1713 } 1714 } 1715 1716 /* 1717 * Always enable busmastering on bridges so that transactions 1718 * initiated on the secondary bus are passed through to the 1719 * primary bus. 1720 */ 1721 pci_enable_busmaster(dev); 1722 } 1723 1724 #ifdef PCI_HP 1725 static int 1726 pcib_present(struct pcib_softc *sc) 1727 { 1728 1729 if (sc->flags & PCIB_HOTPLUG) 1730 return (pcib_hotplug_present(sc) != 0); 1731 return (1); 1732 } 1733 #endif 1734 1735 int 1736 pcib_attach_child(device_t dev) 1737 { 1738 struct pcib_softc *sc; 1739 1740 sc = device_get_softc(dev); 1741 if (sc->bus.sec == 0) { 1742 /* no secondary bus; we should have fixed this */ 1743 return(0); 1744 } 1745 1746 #ifdef PCI_HP 1747 if (!pcib_present(sc)) { 1748 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1749 return (0); 1750 } 1751 #endif 1752 1753 sc->child = device_add_child(dev, "pci", -1); 1754 return (bus_generic_attach(dev)); 1755 } 1756 1757 int 1758 pcib_attach(device_t dev) 1759 { 1760 1761 pcib_attach_common(dev); 1762 return (pcib_attach_child(dev)); 1763 } 1764 1765 int 1766 pcib_detach(device_t dev) 1767 { 1768 #if defined(PCI_HP) || defined(NEW_PCIB) 1769 struct pcib_softc *sc; 1770 #endif 1771 int error; 1772 1773 #if defined(PCI_HP) || defined(NEW_PCIB) 1774 sc = device_get_softc(dev); 1775 #endif 1776 error = bus_generic_detach(dev); 1777 if (error) 1778 return (error); 1779 #ifdef PCI_HP 1780 if (sc->flags & PCIB_HOTPLUG) { 1781 error = pcib_detach_hotplug(sc); 1782 if (error) 1783 return (error); 1784 } 1785 #endif 1786 error = device_delete_children(dev); 1787 if (error) 1788 return (error); 1789 #ifdef NEW_PCIB 1790 pcib_free_windows(sc); 1791 #ifdef PCI_RES_BUS 1792 pcib_free_secbus(dev, &sc->bus); 1793 #endif 1794 #endif 1795 return (0); 1796 } 1797 1798 int 1799 pcib_suspend(device_t dev) 1800 { 1801 1802 pcib_cfg_save(device_get_softc(dev)); 1803 return (bus_generic_suspend(dev)); 1804 } 1805 1806 int 1807 pcib_resume(device_t dev) 1808 { 1809 1810 pcib_cfg_restore(device_get_softc(dev)); 1811 1812 /* 1813 * Restore the Command register only after restoring the windows. 1814 * The bridge should not be claiming random windows. 1815 */ 1816 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2); 1817 return (bus_generic_resume(dev)); 1818 } 1819 1820 void 1821 pcib_bridge_init(device_t dev) 1822 { 1823 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1824 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1825 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1826 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1827 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1828 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1829 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1830 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1831 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1832 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1833 } 1834 1835 int 1836 pcib_child_present(device_t dev, device_t child) 1837 { 1838 #ifdef PCI_HP 1839 struct pcib_softc *sc = device_get_softc(dev); 1840 int retval; 1841 1842 retval = bus_child_present(dev); 1843 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1844 retval = pcib_hotplug_present(sc); 1845 return (retval); 1846 #else 1847 return (bus_child_present(dev)); 1848 #endif 1849 } 1850 1851 int 1852 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1853 { 1854 struct pcib_softc *sc = device_get_softc(dev); 1855 1856 switch (which) { 1857 case PCIB_IVAR_DOMAIN: 1858 *result = sc->domain; 1859 return(0); 1860 case PCIB_IVAR_BUS: 1861 *result = sc->bus.sec; 1862 return(0); 1863 } 1864 return(ENOENT); 1865 } 1866 1867 int 1868 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1869 { 1870 1871 switch (which) { 1872 case PCIB_IVAR_DOMAIN: 1873 return(EINVAL); 1874 case PCIB_IVAR_BUS: 1875 return(EINVAL); 1876 } 1877 return(ENOENT); 1878 } 1879 1880 #ifdef NEW_PCIB 1881 /* 1882 * Attempt to allocate a resource from the existing resources assigned 1883 * to a window. 1884 */ 1885 static struct resource * 1886 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1887 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1888 rman_res_t count, u_int flags) 1889 { 1890 struct resource *res; 1891 1892 if (!pcib_is_window_open(w)) 1893 return (NULL); 1894 1895 res = rman_reserve_resource(&w->rman, start, end, count, 1896 flags & ~RF_ACTIVE, child); 1897 if (res == NULL) 1898 return (NULL); 1899 1900 if (bootverbose) 1901 device_printf(sc->dev, 1902 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1903 w->name, rman_get_start(res), rman_get_end(res), *rid, 1904 pcib_child_name(child)); 1905 rman_set_rid(res, *rid); 1906 1907 /* 1908 * If the resource should be active, pass that request up the 1909 * tree. This assumes the parent drivers can handle 1910 * activating sub-allocated resources. 1911 */ 1912 if (flags & RF_ACTIVE) { 1913 if (bus_activate_resource(child, type, *rid, res) != 0) { 1914 rman_release_resource(res); 1915 return (NULL); 1916 } 1917 } 1918 1919 return (res); 1920 } 1921 1922 /* Allocate a fresh resource range for an unconfigured window. */ 1923 static int 1924 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1925 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1926 { 1927 struct resource *res; 1928 rman_res_t base, limit, wmask; 1929 int rid; 1930 1931 /* 1932 * If this is an I/O window on a bridge with ISA enable set 1933 * and the start address is below 64k, then try to allocate an 1934 * initial window of 0x1000 bytes long starting at address 1935 * 0xf000 and walking down. Note that if the original request 1936 * was larger than the non-aliased range size of 0x100 our 1937 * caller would have raised the start address up to 64k 1938 * already. 1939 */ 1940 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1941 start < 65536) { 1942 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1943 limit = base + 0xfff; 1944 1945 /* 1946 * Skip ranges that wouldn't work for the 1947 * original request. Note that the actual 1948 * window that overlaps are the non-alias 1949 * ranges within [base, limit], so this isn't 1950 * quite a simple comparison. 1951 */ 1952 if (start + count > limit - 0x400) 1953 continue; 1954 if (base == 0) { 1955 /* 1956 * The first open region for the window at 1957 * 0 is 0x400-0x4ff. 1958 */ 1959 if (end - count + 1 < 0x400) 1960 continue; 1961 } else { 1962 if (end - count + 1 < base) 1963 continue; 1964 } 1965 1966 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1967 w->base = base; 1968 w->limit = limit; 1969 return (0); 1970 } 1971 } 1972 return (ENOSPC); 1973 } 1974 1975 wmask = ((rman_res_t)1 << w->step) - 1; 1976 if (RF_ALIGNMENT(flags) < w->step) { 1977 flags &= ~RF_ALIGNMENT_MASK; 1978 flags |= RF_ALIGNMENT_LOG2(w->step); 1979 } 1980 start &= ~wmask; 1981 end |= wmask; 1982 count = roundup2(count, (rman_res_t)1 << w->step); 1983 rid = w->reg; 1984 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1985 flags & ~RF_ACTIVE); 1986 if (res == NULL) 1987 return (ENOSPC); 1988 pcib_add_window_resources(w, &res, 1); 1989 pcib_activate_window(sc, type); 1990 w->base = rman_get_start(res); 1991 w->limit = rman_get_end(res); 1992 return (0); 1993 } 1994 1995 /* Try to expand an existing window to the requested base and limit. */ 1996 static int 1997 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1998 rman_res_t base, rman_res_t limit) 1999 { 2000 struct resource *res; 2001 int error, i, force_64k_base; 2002 2003 KASSERT(base <= w->base && limit >= w->limit, 2004 ("attempting to shrink window")); 2005 2006 /* 2007 * XXX: pcib_grow_window() doesn't try to do this anyway and 2008 * the error handling for all the edge cases would be tedious. 2009 */ 2010 KASSERT(limit == w->limit || base == w->base, 2011 ("attempting to grow both ends of a window")); 2012 2013 /* 2014 * Yet more special handling for requests to expand an I/O 2015 * window behind an ISA-enabled bridge. Since I/O windows 2016 * have to grow in 0x1000 increments and the end of the 0xffff 2017 * range is an alias, growing a window below 64k will always 2018 * result in allocating new resources and never adjusting an 2019 * existing resource. 2020 */ 2021 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2022 (limit <= 65535 || (base <= 65535 && base != w->base))) { 2023 KASSERT(limit == w->limit || limit <= 65535, 2024 ("attempting to grow both ends across 64k ISA alias")); 2025 2026 if (base != w->base) 2027 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 2028 else 2029 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 2030 limit); 2031 if (error == 0) { 2032 w->base = base; 2033 w->limit = limit; 2034 } 2035 return (error); 2036 } 2037 2038 /* 2039 * Find the existing resource to adjust. Usually there is only one, 2040 * but for an ISA-enabled bridge we might be growing the I/O window 2041 * above 64k and need to find the existing resource that maps all 2042 * of the area above 64k. 2043 */ 2044 for (i = 0; i < w->count; i++) { 2045 if (rman_get_end(w->res[i]) == w->limit) 2046 break; 2047 } 2048 KASSERT(i != w->count, ("did not find existing resource")); 2049 res = w->res[i]; 2050 2051 /* 2052 * Usually the resource we found should match the window's 2053 * existing range. The one exception is the ISA-enabled case 2054 * mentioned above in which case the resource should start at 2055 * 64k. 2056 */ 2057 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2058 w->base <= 65535) { 2059 KASSERT(rman_get_start(res) == 65536, 2060 ("existing resource mismatch")); 2061 force_64k_base = 1; 2062 } else { 2063 KASSERT(w->base == rman_get_start(res), 2064 ("existing resource mismatch")); 2065 force_64k_base = 0; 2066 } 2067 2068 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2069 rman_get_start(res) : base, limit); 2070 if (error) 2071 return (error); 2072 2073 /* Add the newly allocated region to the resource manager. */ 2074 if (w->base != base) { 2075 error = rman_manage_region(&w->rman, base, w->base - 1); 2076 w->base = base; 2077 } else { 2078 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2079 w->limit = limit; 2080 } 2081 if (error) { 2082 if (bootverbose) 2083 device_printf(sc->dev, 2084 "failed to expand %s resource manager\n", w->name); 2085 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2086 rman_get_start(res) : w->base, w->limit); 2087 } 2088 return (error); 2089 } 2090 2091 /* 2092 * Attempt to grow a window to make room for a given resource request. 2093 */ 2094 static int 2095 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2096 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2097 { 2098 rman_res_t align, start_free, end_free, front, back, wmask; 2099 int error; 2100 2101 /* 2102 * Clamp the desired resource range to the maximum address 2103 * this window supports. Reject impossible requests. 2104 * 2105 * For I/O port requests behind a bridge with the ISA enable 2106 * bit set, force large allocations to start above 64k. 2107 */ 2108 if (!w->valid) 2109 return (EINVAL); 2110 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2111 start < 65536) 2112 start = 65536; 2113 if (end > w->rman.rm_end) 2114 end = w->rman.rm_end; 2115 if (start + count - 1 > end || start + count < start) 2116 return (EINVAL); 2117 wmask = ((rman_res_t)1 << w->step) - 1; 2118 2119 /* 2120 * If there is no resource at all, just try to allocate enough 2121 * aligned space for this resource. 2122 */ 2123 if (w->res == NULL) { 2124 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2125 flags); 2126 if (error) { 2127 if (bootverbose) 2128 device_printf(sc->dev, 2129 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2130 w->name, start, end, count); 2131 return (error); 2132 } 2133 if (bootverbose) 2134 device_printf(sc->dev, 2135 "allocated initial %s window of %#jx-%#jx\n", 2136 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2137 goto updatewin; 2138 } 2139 2140 /* 2141 * See if growing the window would help. Compute the minimum 2142 * amount of address space needed on both the front and back 2143 * ends of the existing window to satisfy the allocation. 2144 * 2145 * For each end, build a candidate region adjusting for the 2146 * required alignment, etc. If there is a free region at the 2147 * edge of the window, grow from the inner edge of the free 2148 * region. Otherwise grow from the window boundary. 2149 * 2150 * Growing an I/O window below 64k for a bridge with the ISA 2151 * enable bit doesn't require any special magic as the step 2152 * size of an I/O window (1k) always includes multiple 2153 * non-alias ranges when it is grown in either direction. 2154 * 2155 * XXX: Special case: if w->res is completely empty and the 2156 * request size is larger than w->res, we should find the 2157 * optimal aligned buffer containing w->res and allocate that. 2158 */ 2159 if (bootverbose) 2160 device_printf(sc->dev, 2161 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2162 w->name, start, end, count); 2163 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2164 if (start < w->base) { 2165 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2166 0 || start_free != w->base) 2167 end_free = w->base; 2168 if (end_free > end) 2169 end_free = end + 1; 2170 2171 /* Move end_free down until it is properly aligned. */ 2172 end_free &= ~(align - 1); 2173 end_free--; 2174 front = end_free - (count - 1); 2175 2176 /* 2177 * The resource would now be allocated at (front, 2178 * end_free). Ensure that fits in the (start, end) 2179 * bounds. end_free is checked above. If 'front' is 2180 * ok, ensure it is properly aligned for this window. 2181 * Also check for underflow. 2182 */ 2183 if (front >= start && front <= end_free) { 2184 if (bootverbose) 2185 printf("\tfront candidate range: %#jx-%#jx\n", 2186 front, end_free); 2187 front &= ~wmask; 2188 front = w->base - front; 2189 } else 2190 front = 0; 2191 } else 2192 front = 0; 2193 if (end > w->limit) { 2194 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2195 0 || end_free != w->limit) 2196 start_free = w->limit + 1; 2197 if (start_free < start) 2198 start_free = start; 2199 2200 /* Move start_free up until it is properly aligned. */ 2201 start_free = roundup2(start_free, align); 2202 back = start_free + count - 1; 2203 2204 /* 2205 * The resource would now be allocated at (start_free, 2206 * back). Ensure that fits in the (start, end) 2207 * bounds. start_free is checked above. If 'back' is 2208 * ok, ensure it is properly aligned for this window. 2209 * Also check for overflow. 2210 */ 2211 if (back <= end && start_free <= back) { 2212 if (bootverbose) 2213 printf("\tback candidate range: %#jx-%#jx\n", 2214 start_free, back); 2215 back |= wmask; 2216 back -= w->limit; 2217 } else 2218 back = 0; 2219 } else 2220 back = 0; 2221 2222 /* 2223 * Try to allocate the smallest needed region first. 2224 * If that fails, fall back to the other region. 2225 */ 2226 error = ENOSPC; 2227 while (front != 0 || back != 0) { 2228 if (front != 0 && (front <= back || back == 0)) { 2229 error = pcib_expand_window(sc, w, type, w->base - front, 2230 w->limit); 2231 if (error == 0) 2232 break; 2233 front = 0; 2234 } else { 2235 error = pcib_expand_window(sc, w, type, w->base, 2236 w->limit + back); 2237 if (error == 0) 2238 break; 2239 back = 0; 2240 } 2241 } 2242 2243 if (error) 2244 return (error); 2245 if (bootverbose) 2246 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2247 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2248 2249 updatewin: 2250 /* Write the new window. */ 2251 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2252 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2253 pcib_write_windows(sc, w->mask); 2254 return (0); 2255 } 2256 2257 /* 2258 * We have to trap resource allocation requests and ensure that the bridge 2259 * is set up to, or capable of handling them. 2260 */ 2261 struct resource * 2262 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2263 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2264 { 2265 struct pcib_softc *sc; 2266 struct resource *r; 2267 2268 sc = device_get_softc(dev); 2269 2270 /* 2271 * VGA resources are decoded iff the VGA enable bit is set in 2272 * the bridge control register. VGA resources do not fall into 2273 * the resource windows and are passed up to the parent. 2274 */ 2275 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2276 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2277 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2278 return (bus_generic_alloc_resource(dev, child, type, 2279 rid, start, end, count, flags)); 2280 else 2281 return (NULL); 2282 } 2283 2284 switch (type) { 2285 #ifdef PCI_RES_BUS 2286 case PCI_RES_BUS: 2287 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2288 count, flags)); 2289 #endif 2290 case SYS_RES_IOPORT: 2291 if (pcib_is_isa_range(sc, start, end, count)) 2292 return (NULL); 2293 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2294 end, count, flags); 2295 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2296 break; 2297 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2298 flags) == 0) 2299 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2300 rid, start, end, count, flags); 2301 break; 2302 case SYS_RES_MEMORY: 2303 /* 2304 * For prefetchable resources, prefer the prefetchable 2305 * memory window, but fall back to the regular memory 2306 * window if that fails. Try both windows before 2307 * attempting to grow a window in case the firmware 2308 * has used a range in the regular memory window to 2309 * map a prefetchable BAR. 2310 */ 2311 if (flags & RF_PREFETCHABLE) { 2312 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2313 rid, start, end, count, flags); 2314 if (r != NULL) 2315 break; 2316 } 2317 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2318 start, end, count, flags); 2319 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2320 break; 2321 if (flags & RF_PREFETCHABLE) { 2322 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2323 count, flags) == 0) { 2324 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2325 type, rid, start, end, count, flags); 2326 if (r != NULL) 2327 break; 2328 } 2329 } 2330 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2331 flags & ~RF_PREFETCHABLE) == 0) 2332 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2333 rid, start, end, count, flags); 2334 break; 2335 default: 2336 return (bus_generic_alloc_resource(dev, child, type, rid, 2337 start, end, count, flags)); 2338 } 2339 2340 /* 2341 * If attempts to suballocate from the window fail but this is a 2342 * subtractive bridge, pass the request up the tree. 2343 */ 2344 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2345 return (bus_generic_alloc_resource(dev, child, type, rid, 2346 start, end, count, flags)); 2347 return (r); 2348 } 2349 2350 int 2351 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2352 rman_res_t start, rman_res_t end) 2353 { 2354 struct pcib_softc *sc; 2355 struct pcib_window *w; 2356 rman_res_t wmask; 2357 int error; 2358 2359 sc = device_get_softc(bus); 2360 2361 /* 2362 * If the resource wasn't sub-allocated from one of our region 2363 * managers then just pass the request up. 2364 */ 2365 if (!pcib_is_resource_managed(sc, type, r)) 2366 return (bus_generic_adjust_resource(bus, child, type, r, 2367 start, end)); 2368 2369 #ifdef PCI_RES_BUS 2370 if (type == PCI_RES_BUS) { 2371 /* 2372 * If our bus range isn't big enough to grow the sub-allocation 2373 * then we need to grow our bus range. Any request that would 2374 * require us to decrease the start of our own bus range is 2375 * invalid, we can only extend the end; ignore such requests 2376 * and let rman_adjust_resource fail below. 2377 */ 2378 if (start >= sc->bus.sec && end > sc->bus.sub) { 2379 error = pcib_grow_subbus(&sc->bus, end); 2380 if (error != 0) 2381 return (error); 2382 } 2383 } else 2384 #endif 2385 { 2386 /* 2387 * Resource is managed and not a secondary bus number, must 2388 * be from one of our windows. 2389 */ 2390 w = pcib_get_resource_window(sc, type, r); 2391 KASSERT(w != NULL, 2392 ("%s: no window for resource (%#jx-%#jx) type %d", 2393 __func__, rman_get_start(r), rman_get_end(r), type)); 2394 2395 /* 2396 * If our window isn't big enough to grow the sub-allocation 2397 * then we need to expand the window. 2398 */ 2399 if (start < w->base || end > w->limit) { 2400 wmask = ((rman_res_t)1 << w->step) - 1; 2401 error = pcib_expand_window(sc, w, type, 2402 MIN(start & ~wmask, w->base), 2403 MAX(end | wmask, w->limit)); 2404 if (error != 0) 2405 return (error); 2406 if (bootverbose) 2407 device_printf(sc->dev, 2408 "grew %s window to %#jx-%#jx\n", 2409 w->name, (uintmax_t)w->base, 2410 (uintmax_t)w->limit); 2411 pcib_write_windows(sc, w->mask); 2412 } 2413 } 2414 2415 return (rman_adjust_resource(r, start, end)); 2416 } 2417 2418 int 2419 pcib_release_resource(device_t dev, device_t child, int type, int rid, 2420 struct resource *r) 2421 { 2422 struct pcib_softc *sc; 2423 int error; 2424 2425 sc = device_get_softc(dev); 2426 if (pcib_is_resource_managed(sc, type, r)) { 2427 if (rman_get_flags(r) & RF_ACTIVE) { 2428 error = bus_deactivate_resource(child, type, rid, r); 2429 if (error) 2430 return (error); 2431 } 2432 return (rman_release_resource(r)); 2433 } 2434 return (bus_generic_release_resource(dev, child, type, rid, r)); 2435 } 2436 #else 2437 /* 2438 * We have to trap resource allocation requests and ensure that the bridge 2439 * is set up to, or capable of handling them. 2440 */ 2441 struct resource * 2442 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2443 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2444 { 2445 struct pcib_softc *sc = device_get_softc(dev); 2446 const char *name, *suffix; 2447 int ok; 2448 2449 /* 2450 * Fail the allocation for this range if it's not supported. 2451 */ 2452 name = device_get_nameunit(child); 2453 if (name == NULL) { 2454 name = ""; 2455 suffix = ""; 2456 } else 2457 suffix = " "; 2458 switch (type) { 2459 case SYS_RES_IOPORT: 2460 ok = 0; 2461 if (!pcib_is_io_open(sc)) 2462 break; 2463 ok = (start >= sc->iobase && end <= sc->iolimit); 2464 2465 /* 2466 * Make sure we allow access to VGA I/O addresses when the 2467 * bridge has the "VGA Enable" bit set. 2468 */ 2469 if (!ok && pci_is_vga_ioport_range(start, end)) 2470 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2471 2472 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2473 if (!ok) { 2474 if (start < sc->iobase) 2475 start = sc->iobase; 2476 if (end > sc->iolimit) 2477 end = sc->iolimit; 2478 if (start < end) 2479 ok = 1; 2480 } 2481 } else { 2482 ok = 1; 2483 #if 0 2484 /* 2485 * If we overlap with the subtractive range, then 2486 * pick the upper range to use. 2487 */ 2488 if (start < sc->iolimit && end > sc->iobase) 2489 start = sc->iolimit + 1; 2490 #endif 2491 } 2492 if (end < start) { 2493 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2494 end, start); 2495 start = 0; 2496 end = 0; 2497 ok = 0; 2498 } 2499 if (!ok) { 2500 device_printf(dev, "%s%srequested unsupported I/O " 2501 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2502 name, suffix, start, end, sc->iobase, sc->iolimit); 2503 return (NULL); 2504 } 2505 if (bootverbose) 2506 device_printf(dev, 2507 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2508 name, suffix, start, end); 2509 break; 2510 2511 case SYS_RES_MEMORY: 2512 ok = 0; 2513 if (pcib_is_nonprefetch_open(sc)) 2514 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2515 if (pcib_is_prefetch_open(sc)) 2516 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2517 2518 /* 2519 * Make sure we allow access to VGA memory addresses when the 2520 * bridge has the "VGA Enable" bit set. 2521 */ 2522 if (!ok && pci_is_vga_memory_range(start, end)) 2523 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2524 2525 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2526 if (!ok) { 2527 ok = 1; 2528 if (flags & RF_PREFETCHABLE) { 2529 if (pcib_is_prefetch_open(sc)) { 2530 if (start < sc->pmembase) 2531 start = sc->pmembase; 2532 if (end > sc->pmemlimit) 2533 end = sc->pmemlimit; 2534 } else { 2535 ok = 0; 2536 } 2537 } else { /* non-prefetchable */ 2538 if (pcib_is_nonprefetch_open(sc)) { 2539 if (start < sc->membase) 2540 start = sc->membase; 2541 if (end > sc->memlimit) 2542 end = sc->memlimit; 2543 } else { 2544 ok = 0; 2545 } 2546 } 2547 } 2548 } else if (!ok) { 2549 ok = 1; /* subtractive bridge: always ok */ 2550 #if 0 2551 if (pcib_is_nonprefetch_open(sc)) { 2552 if (start < sc->memlimit && end > sc->membase) 2553 start = sc->memlimit + 1; 2554 } 2555 if (pcib_is_prefetch_open(sc)) { 2556 if (start < sc->pmemlimit && end > sc->pmembase) 2557 start = sc->pmemlimit + 1; 2558 } 2559 #endif 2560 } 2561 if (end < start) { 2562 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2563 end, start); 2564 start = 0; 2565 end = 0; 2566 ok = 0; 2567 } 2568 if (!ok && bootverbose) 2569 device_printf(dev, 2570 "%s%srequested unsupported memory range %#jx-%#jx " 2571 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2572 name, suffix, start, end, 2573 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2574 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2575 if (!ok) 2576 return (NULL); 2577 if (bootverbose) 2578 device_printf(dev,"%s%srequested memory range " 2579 "0x%jx-0x%jx: good\n", 2580 name, suffix, start, end); 2581 break; 2582 2583 default: 2584 break; 2585 } 2586 /* 2587 * Bridge is OK decoding this resource, so pass it up. 2588 */ 2589 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2590 count, flags)); 2591 } 2592 #endif 2593 2594 /* 2595 * If ARI is enabled on this downstream port, translate the function number 2596 * to the non-ARI slot/function. The downstream port will convert it back in 2597 * hardware. If ARI is not enabled slot and func are not modified. 2598 */ 2599 static __inline void 2600 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2601 { 2602 struct pcib_softc *sc; 2603 int ari_func; 2604 2605 sc = device_get_softc(pcib); 2606 ari_func = *func; 2607 2608 if (sc->flags & PCIB_ENABLE_ARI) { 2609 KASSERT(*slot == 0, 2610 ("Non-zero slot number with ARI enabled!")); 2611 *slot = PCIE_ARI_SLOT(ari_func); 2612 *func = PCIE_ARI_FUNC(ari_func); 2613 } 2614 } 2615 2616 static void 2617 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2618 { 2619 uint32_t ctl2; 2620 2621 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2622 ctl2 |= PCIEM_CTL2_ARI; 2623 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2624 2625 sc->flags |= PCIB_ENABLE_ARI; 2626 } 2627 2628 /* 2629 * PCIB interface. 2630 */ 2631 int 2632 pcib_maxslots(device_t dev) 2633 { 2634 #if !defined(__amd64__) && !defined(__i386__) 2635 uint32_t pcie_pos; 2636 uint16_t val; 2637 2638 /* 2639 * If this is a PCIe rootport or downstream switch port, there's only 2640 * one slot permitted. 2641 */ 2642 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) { 2643 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2); 2644 val &= PCIEM_FLAGS_TYPE; 2645 if (val == PCIEM_TYPE_ROOT_PORT || 2646 val == PCIEM_TYPE_DOWNSTREAM_PORT) 2647 return (0); 2648 } 2649 #endif 2650 return (PCI_SLOTMAX); 2651 } 2652 2653 static int 2654 pcib_ari_maxslots(device_t dev) 2655 { 2656 struct pcib_softc *sc; 2657 2658 sc = device_get_softc(dev); 2659 2660 if (sc->flags & PCIB_ENABLE_ARI) 2661 return (PCIE_ARI_SLOTMAX); 2662 else 2663 return (pcib_maxslots(dev)); 2664 } 2665 2666 static int 2667 pcib_ari_maxfuncs(device_t dev) 2668 { 2669 struct pcib_softc *sc; 2670 2671 sc = device_get_softc(dev); 2672 2673 if (sc->flags & PCIB_ENABLE_ARI) 2674 return (PCIE_ARI_FUNCMAX); 2675 else 2676 return (PCI_FUNCMAX); 2677 } 2678 2679 static void 2680 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2681 int *func) 2682 { 2683 struct pcib_softc *sc; 2684 2685 sc = device_get_softc(pcib); 2686 2687 *bus = PCI_RID2BUS(rid); 2688 if (sc->flags & PCIB_ENABLE_ARI) { 2689 *slot = PCIE_ARI_RID2SLOT(rid); 2690 *func = PCIE_ARI_RID2FUNC(rid); 2691 } else { 2692 *slot = PCI_RID2SLOT(rid); 2693 *func = PCI_RID2FUNC(rid); 2694 } 2695 } 2696 2697 /* 2698 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2699 */ 2700 static uint32_t 2701 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2702 { 2703 #ifdef PCI_HP 2704 struct pcib_softc *sc; 2705 2706 sc = device_get_softc(dev); 2707 if (!pcib_present(sc)) { 2708 switch (width) { 2709 case 2: 2710 return (0xffff); 2711 case 1: 2712 return (0xff); 2713 default: 2714 return (0xffffffff); 2715 } 2716 } 2717 #endif 2718 pcib_xlate_ari(dev, b, &s, &f); 2719 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2720 f, reg, width)); 2721 } 2722 2723 static void 2724 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2725 { 2726 #ifdef PCI_HP 2727 struct pcib_softc *sc; 2728 2729 sc = device_get_softc(dev); 2730 if (!pcib_present(sc)) 2731 return; 2732 #endif 2733 pcib_xlate_ari(dev, b, &s, &f); 2734 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2735 reg, val, width); 2736 } 2737 2738 /* 2739 * Route an interrupt across a PCI bridge. 2740 */ 2741 int 2742 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2743 { 2744 device_t bus; 2745 int parent_intpin; 2746 int intnum; 2747 2748 /* 2749 * 2750 * The PCI standard defines a swizzle of the child-side device/intpin to 2751 * the parent-side intpin as follows. 2752 * 2753 * device = device on child bus 2754 * child_intpin = intpin on child bus slot (0-3) 2755 * parent_intpin = intpin on parent bus slot (0-3) 2756 * 2757 * parent_intpin = (device + child_intpin) % 4 2758 */ 2759 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2760 2761 /* 2762 * Our parent is a PCI bus. Its parent must export the pcib interface 2763 * which includes the ability to route interrupts. 2764 */ 2765 bus = device_get_parent(pcib); 2766 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2767 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2768 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2769 pci_get_slot(dev), 'A' + pin - 1, intnum); 2770 } 2771 return(intnum); 2772 } 2773 2774 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2775 int 2776 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2777 { 2778 struct pcib_softc *sc = device_get_softc(pcib); 2779 device_t bus; 2780 2781 if (sc->flags & PCIB_DISABLE_MSI) 2782 return (ENXIO); 2783 bus = device_get_parent(pcib); 2784 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2785 irqs)); 2786 } 2787 2788 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2789 int 2790 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2791 { 2792 device_t bus; 2793 2794 bus = device_get_parent(pcib); 2795 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2796 } 2797 2798 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2799 int 2800 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2801 { 2802 struct pcib_softc *sc = device_get_softc(pcib); 2803 device_t bus; 2804 2805 if (sc->flags & PCIB_DISABLE_MSIX) 2806 return (ENXIO); 2807 bus = device_get_parent(pcib); 2808 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2809 } 2810 2811 /* Pass request to release an MSI-X message up to the parent bridge. */ 2812 int 2813 pcib_release_msix(device_t pcib, device_t dev, int irq) 2814 { 2815 device_t bus; 2816 2817 bus = device_get_parent(pcib); 2818 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2819 } 2820 2821 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2822 int 2823 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2824 uint32_t *data) 2825 { 2826 device_t bus; 2827 int error; 2828 2829 bus = device_get_parent(pcib); 2830 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2831 if (error) 2832 return (error); 2833 2834 pci_ht_map_msi(pcib, *addr); 2835 return (0); 2836 } 2837 2838 /* Pass request for device power state up to parent bridge. */ 2839 int 2840 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2841 { 2842 device_t bus; 2843 2844 bus = device_get_parent(pcib); 2845 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2846 } 2847 2848 static int 2849 pcib_ari_enabled(device_t pcib) 2850 { 2851 struct pcib_softc *sc; 2852 2853 sc = device_get_softc(pcib); 2854 2855 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2856 } 2857 2858 static int 2859 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2860 uintptr_t *id) 2861 { 2862 struct pcib_softc *sc; 2863 device_t bus_dev; 2864 uint8_t bus, slot, func; 2865 2866 if (type != PCI_ID_RID) { 2867 bus_dev = device_get_parent(pcib); 2868 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2869 } 2870 2871 sc = device_get_softc(pcib); 2872 2873 if (sc->flags & PCIB_ENABLE_ARI) { 2874 bus = pci_get_bus(dev); 2875 func = pci_get_function(dev); 2876 2877 *id = (PCI_ARI_RID(bus, func)); 2878 } else { 2879 bus = pci_get_bus(dev); 2880 slot = pci_get_slot(dev); 2881 func = pci_get_function(dev); 2882 2883 *id = (PCI_RID(bus, slot, func)); 2884 } 2885 2886 return (0); 2887 } 2888 2889 /* 2890 * Check that the downstream port (pcib) and the endpoint device (dev) both 2891 * support ARI. If so, enable it and return 0, otherwise return an error. 2892 */ 2893 static int 2894 pcib_try_enable_ari(device_t pcib, device_t dev) 2895 { 2896 struct pcib_softc *sc; 2897 int error; 2898 uint32_t cap2; 2899 int ari_cap_off; 2900 uint32_t ari_ver; 2901 uint32_t pcie_pos; 2902 2903 sc = device_get_softc(pcib); 2904 2905 /* 2906 * ARI is controlled in a register in the PCIe capability structure. 2907 * If the downstream port does not have the PCIe capability structure 2908 * then it does not support ARI. 2909 */ 2910 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2911 if (error != 0) 2912 return (ENODEV); 2913 2914 /* Check that the PCIe port advertises ARI support. */ 2915 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2916 if (!(cap2 & PCIEM_CAP2_ARI)) 2917 return (ENODEV); 2918 2919 /* 2920 * Check that the endpoint device advertises ARI support via the ARI 2921 * extended capability structure. 2922 */ 2923 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2924 if (error != 0) 2925 return (ENODEV); 2926 2927 /* 2928 * Finally, check that the endpoint device supports the same version 2929 * of ARI that we do. 2930 */ 2931 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2932 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2933 if (bootverbose) 2934 device_printf(pcib, 2935 "Unsupported version of ARI (%d) detected\n", 2936 PCI_EXTCAP_VER(ari_ver)); 2937 2938 return (ENXIO); 2939 } 2940 2941 pcib_enable_ari(sc, pcie_pos); 2942 2943 return (0); 2944 } 2945 2946 int 2947 pcib_request_feature_allow(device_t pcib, device_t dev, 2948 enum pci_feature feature) 2949 { 2950 /* 2951 * No host firmware we have to negotiate with, so we allow 2952 * every valid feature requested. 2953 */ 2954 switch (feature) { 2955 case PCI_FEATURE_AER: 2956 case PCI_FEATURE_HP: 2957 break; 2958 default: 2959 return (EINVAL); 2960 } 2961 2962 return (0); 2963 } 2964 2965 int 2966 pcib_request_feature(device_t dev, enum pci_feature feature) 2967 { 2968 2969 /* 2970 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2971 * the firmware overrides the method of PCI-PCI bridges. 2972 */ 2973 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2974 } 2975 2976 /* 2977 * Pass the request to use this PCI feature up the tree. Either there's a 2978 * firmware like ACPI that's using this feature that will approve (or deny) the 2979 * request to take it over, or the platform has no such firmware, in which case 2980 * the request will be approved. If the request is approved, the OS is expected 2981 * to make use of the feature or render it harmless. 2982 */ 2983 static int 2984 pcib_request_feature_default(device_t pcib, device_t dev, 2985 enum pci_feature feature) 2986 { 2987 device_t bus; 2988 2989 /* 2990 * Our parent is necessarily a pci bus. Its parent will either be 2991 * another pci bridge (which passes it up) or a host bridge that can 2992 * approve or reject the request. 2993 */ 2994 bus = device_get_parent(pcib); 2995 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2996 } 2997 2998 static int 2999 pcib_reset_child(device_t dev, device_t child, int flags) 3000 { 3001 struct pci_devinfo *pdinfo; 3002 int error; 3003 3004 error = 0; 3005 if (dev == NULL || device_get_parent(child) != dev) 3006 goto out; 3007 error = ENXIO; 3008 if (device_get_devclass(child) != devclass_find("pci")) 3009 goto out; 3010 pdinfo = device_get_ivars(dev); 3011 if (pdinfo->cfg.pcie.pcie_location != 0 && 3012 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT || 3013 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) { 3014 error = bus_helper_reset_prepare(child, flags); 3015 if (error == 0) { 3016 error = pcie_link_reset(dev, 3017 pdinfo->cfg.pcie.pcie_location); 3018 /* XXXKIB call _post even if error != 0 ? */ 3019 bus_helper_reset_post(child, flags); 3020 } 3021 } 3022 out: 3023 return (error); 3024 } 3025