1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 #include <sys/taskqueue.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pci_private.h> 53 #include <dev/pci/pcib_private.h> 54 55 #include "pcib_if.h" 56 57 static int pcib_probe(device_t dev); 58 static int pcib_suspend(device_t dev); 59 static int pcib_resume(device_t dev); 60 static int pcib_power_for_sleep(device_t pcib, device_t dev, 61 int *pstate); 62 static int pcib_ari_get_id(device_t pcib, device_t dev, 63 enum pci_id_type type, uintptr_t *id); 64 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 65 u_int f, u_int reg, int width); 66 static void pcib_write_config(device_t dev, u_int b, u_int s, 67 u_int f, u_int reg, uint32_t val, int width); 68 static int pcib_ari_maxslots(device_t dev); 69 static int pcib_ari_maxfuncs(device_t dev); 70 static int pcib_try_enable_ari(device_t pcib, device_t dev); 71 static int pcib_ari_enabled(device_t pcib); 72 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 73 int *bus, int *slot, int *func); 74 #ifdef PCI_HP 75 static void pcib_pcie_ab_timeout(void *arg); 76 static void pcib_pcie_cc_timeout(void *arg); 77 static void pcib_pcie_dll_timeout(void *arg); 78 #endif 79 80 static device_method_t pcib_methods[] = { 81 /* Device interface */ 82 DEVMETHOD(device_probe, pcib_probe), 83 DEVMETHOD(device_attach, pcib_attach), 84 DEVMETHOD(device_detach, pcib_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 DEVMETHOD(device_suspend, pcib_suspend), 87 DEVMETHOD(device_resume, pcib_resume), 88 89 /* Bus interface */ 90 DEVMETHOD(bus_child_present, pcib_child_present), 91 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 92 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 94 #ifdef NEW_PCIB 95 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 96 DEVMETHOD(bus_release_resource, pcib_release_resource), 97 #else 98 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 99 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 100 #endif 101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 /* pcib interface */ 107 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 108 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 109 DEVMETHOD(pcib_read_config, pcib_read_config), 110 DEVMETHOD(pcib_write_config, pcib_write_config), 111 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 112 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 113 DEVMETHOD(pcib_release_msi, pcib_release_msi), 114 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 115 DEVMETHOD(pcib_release_msix, pcib_release_msix), 116 DEVMETHOD(pcib_map_msi, pcib_map_msi), 117 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 118 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 119 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 120 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 121 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 122 123 DEVMETHOD_END 124 }; 125 126 static devclass_t pcib_devclass; 127 128 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 129 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 130 131 #ifdef NEW_PCIB 132 SYSCTL_DECL(_hw_pci); 133 134 static int pci_clear_pcib; 135 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 136 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 137 138 /* 139 * Is a resource from a child device sub-allocated from one of our 140 * resource managers? 141 */ 142 static int 143 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 144 { 145 146 switch (type) { 147 #ifdef PCI_RES_BUS 148 case PCI_RES_BUS: 149 return (rman_is_region_manager(r, &sc->bus.rman)); 150 #endif 151 case SYS_RES_IOPORT: 152 return (rman_is_region_manager(r, &sc->io.rman)); 153 case SYS_RES_MEMORY: 154 /* Prefetchable resources may live in either memory rman. */ 155 if (rman_get_flags(r) & RF_PREFETCHABLE && 156 rman_is_region_manager(r, &sc->pmem.rman)) 157 return (1); 158 return (rman_is_region_manager(r, &sc->mem.rman)); 159 } 160 return (0); 161 } 162 163 static int 164 pcib_is_window_open(struct pcib_window *pw) 165 { 166 167 return (pw->valid && pw->base < pw->limit); 168 } 169 170 /* 171 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 172 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 173 * when allocating the resource windows and rely on the PCI bus driver 174 * to do this for us. 175 */ 176 static void 177 pcib_activate_window(struct pcib_softc *sc, int type) 178 { 179 180 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 181 } 182 183 static void 184 pcib_write_windows(struct pcib_softc *sc, int mask) 185 { 186 device_t dev; 187 uint32_t val; 188 189 dev = sc->dev; 190 if (sc->io.valid && mask & WIN_IO) { 191 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 192 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 193 pci_write_config(dev, PCIR_IOBASEH_1, 194 sc->io.base >> 16, 2); 195 pci_write_config(dev, PCIR_IOLIMITH_1, 196 sc->io.limit >> 16, 2); 197 } 198 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 199 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 200 } 201 202 if (mask & WIN_MEM) { 203 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 204 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 205 } 206 207 if (sc->pmem.valid && mask & WIN_PMEM) { 208 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 209 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 210 pci_write_config(dev, PCIR_PMBASEH_1, 211 sc->pmem.base >> 32, 4); 212 pci_write_config(dev, PCIR_PMLIMITH_1, 213 sc->pmem.limit >> 32, 4); 214 } 215 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 216 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 217 } 218 } 219 220 /* 221 * This is used to reject I/O port allocations that conflict with an 222 * ISA alias range. 223 */ 224 static int 225 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 226 rman_res_t count) 227 { 228 rman_res_t next_alias; 229 230 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 231 return (0); 232 233 /* Only check fixed ranges for overlap. */ 234 if (start + count - 1 != end) 235 return (0); 236 237 /* ISA aliases are only in the lower 64KB of I/O space. */ 238 if (start >= 65536) 239 return (0); 240 241 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 242 if (start < 0x100) 243 goto alias; 244 245 /* 246 * If the start address is an alias, the range is an alias. 247 * Otherwise, compute the start of the next alias range and 248 * check if it is before the end of the candidate range. 249 */ 250 if ((start & 0x300) != 0) 251 goto alias; 252 next_alias = (start & ~0x3fful) | 0x100; 253 if (next_alias <= end) 254 goto alias; 255 return (0); 256 257 alias: 258 if (bootverbose) 259 device_printf(sc->dev, 260 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 261 end); 262 return (1); 263 } 264 265 static void 266 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 267 int count) 268 { 269 struct resource **newarray; 270 int error, i; 271 272 newarray = malloc(sizeof(struct resource *) * (w->count + count), 273 M_DEVBUF, M_WAITOK); 274 if (w->res != NULL) 275 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 276 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 277 free(w->res, M_DEVBUF); 278 w->res = newarray; 279 w->count += count; 280 281 for (i = 0; i < count; i++) { 282 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 283 rman_get_end(res[i])); 284 if (error) 285 panic("Failed to add resource to rman"); 286 } 287 } 288 289 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 290 291 static void 292 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 293 void *arg) 294 { 295 rman_res_t next_end; 296 297 /* 298 * If start is within an ISA alias range, move up to the start 299 * of the next non-alias range. As a special case, addresses 300 * in the range 0x000 - 0x0ff should also be skipped since 301 * those are used for various system I/O devices in ISA 302 * systems. 303 */ 304 if (start <= 65535) { 305 if (start < 0x100 || (start & 0x300) != 0) { 306 start &= ~0x3ff; 307 start += 0x400; 308 } 309 } 310 311 /* ISA aliases are only in the lower 64KB of I/O space. */ 312 while (start <= MIN(end, 65535)) { 313 next_end = MIN(start | 0xff, end); 314 cb(start, next_end, arg); 315 start += 0x400; 316 } 317 318 if (start <= end) 319 cb(start, end, arg); 320 } 321 322 static void 323 count_ranges(rman_res_t start, rman_res_t end, void *arg) 324 { 325 int *countp; 326 327 countp = arg; 328 (*countp)++; 329 } 330 331 struct alloc_state { 332 struct resource **res; 333 struct pcib_softc *sc; 334 int count, error; 335 }; 336 337 static void 338 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 339 { 340 struct alloc_state *as; 341 struct pcib_window *w; 342 int rid; 343 344 as = arg; 345 if (as->error != 0) 346 return; 347 348 w = &as->sc->io; 349 rid = w->reg; 350 if (bootverbose) 351 device_printf(as->sc->dev, 352 "allocating non-ISA range %#jx-%#jx\n", start, end); 353 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 354 &rid, start, end, end - start + 1, 0); 355 if (as->res[as->count] == NULL) 356 as->error = ENXIO; 357 else 358 as->count++; 359 } 360 361 static int 362 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 363 { 364 struct alloc_state as; 365 int i, new_count; 366 367 /* First, see how many ranges we need. */ 368 new_count = 0; 369 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 370 371 /* Second, allocate the ranges. */ 372 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 373 M_WAITOK); 374 as.sc = sc; 375 as.count = 0; 376 as.error = 0; 377 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 378 if (as.error != 0) { 379 for (i = 0; i < as.count; i++) 380 bus_release_resource(sc->dev, SYS_RES_IOPORT, 381 sc->io.reg, as.res[i]); 382 free(as.res, M_DEVBUF); 383 return (as.error); 384 } 385 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 386 387 /* Third, add the ranges to the window. */ 388 pcib_add_window_resources(&sc->io, as.res, as.count); 389 free(as.res, M_DEVBUF); 390 return (0); 391 } 392 393 static void 394 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 395 int flags, pci_addr_t max_address) 396 { 397 struct resource *res; 398 char buf[64]; 399 int error, rid; 400 401 if (max_address != (rman_res_t)max_address) 402 max_address = ~0; 403 w->rman.rm_start = 0; 404 w->rman.rm_end = max_address; 405 w->rman.rm_type = RMAN_ARRAY; 406 snprintf(buf, sizeof(buf), "%s %s window", 407 device_get_nameunit(sc->dev), w->name); 408 w->rman.rm_descr = strdup(buf, M_DEVBUF); 409 error = rman_init(&w->rman); 410 if (error) 411 panic("Failed to initialize %s %s rman", 412 device_get_nameunit(sc->dev), w->name); 413 414 if (!pcib_is_window_open(w)) 415 return; 416 417 if (w->base > max_address || w->limit > max_address) { 418 device_printf(sc->dev, 419 "initial %s window has too many bits, ignoring\n", w->name); 420 return; 421 } 422 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 423 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 424 else { 425 rid = w->reg; 426 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 427 w->limit - w->base + 1, flags); 428 if (res != NULL) 429 pcib_add_window_resources(w, &res, 1); 430 } 431 if (w->res == NULL) { 432 device_printf(sc->dev, 433 "failed to allocate initial %s window: %#jx-%#jx\n", 434 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 435 w->base = max_address; 436 w->limit = 0; 437 pcib_write_windows(sc, w->mask); 438 return; 439 } 440 pcib_activate_window(sc, type); 441 } 442 443 /* 444 * Initialize I/O windows. 445 */ 446 static void 447 pcib_probe_windows(struct pcib_softc *sc) 448 { 449 pci_addr_t max; 450 device_t dev; 451 uint32_t val; 452 453 dev = sc->dev; 454 455 if (pci_clear_pcib) { 456 pcib_bridge_init(dev); 457 } 458 459 /* Determine if the I/O port window is implemented. */ 460 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 461 if (val == 0) { 462 /* 463 * If 'val' is zero, then only 16-bits of I/O space 464 * are supported. 465 */ 466 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 467 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 468 sc->io.valid = 1; 469 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 470 } 471 } else 472 sc->io.valid = 1; 473 474 /* Read the existing I/O port window. */ 475 if (sc->io.valid) { 476 sc->io.reg = PCIR_IOBASEL_1; 477 sc->io.step = 12; 478 sc->io.mask = WIN_IO; 479 sc->io.name = "I/O port"; 480 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 481 sc->io.base = PCI_PPBIOBASE( 482 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 483 sc->io.limit = PCI_PPBIOLIMIT( 484 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 485 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 486 max = 0xffffffff; 487 } else { 488 sc->io.base = PCI_PPBIOBASE(0, val); 489 sc->io.limit = PCI_PPBIOLIMIT(0, 490 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 491 max = 0xffff; 492 } 493 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 494 } 495 496 /* Read the existing memory window. */ 497 sc->mem.valid = 1; 498 sc->mem.reg = PCIR_MEMBASE_1; 499 sc->mem.step = 20; 500 sc->mem.mask = WIN_MEM; 501 sc->mem.name = "memory"; 502 sc->mem.base = PCI_PPBMEMBASE(0, 503 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 504 sc->mem.limit = PCI_PPBMEMLIMIT(0, 505 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 506 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 507 508 /* Determine if the prefetchable memory window is implemented. */ 509 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 510 if (val == 0) { 511 /* 512 * If 'val' is zero, then only 32-bits of memory space 513 * are supported. 514 */ 515 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 516 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 517 sc->pmem.valid = 1; 518 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 519 } 520 } else 521 sc->pmem.valid = 1; 522 523 /* Read the existing prefetchable memory window. */ 524 if (sc->pmem.valid) { 525 sc->pmem.reg = PCIR_PMBASEL_1; 526 sc->pmem.step = 20; 527 sc->pmem.mask = WIN_PMEM; 528 sc->pmem.name = "prefetch"; 529 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 530 sc->pmem.base = PCI_PPBMEMBASE( 531 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 532 sc->pmem.limit = PCI_PPBMEMLIMIT( 533 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 534 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 535 max = 0xffffffffffffffff; 536 } else { 537 sc->pmem.base = PCI_PPBMEMBASE(0, val); 538 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 539 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 540 max = 0xffffffff; 541 } 542 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 543 RF_PREFETCHABLE, max); 544 } 545 } 546 547 static void 548 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 549 { 550 device_t dev; 551 int error, i; 552 553 if (!w->valid) 554 return; 555 556 dev = sc->dev; 557 error = rman_fini(&w->rman); 558 if (error) { 559 device_printf(dev, "failed to release %s rman\n", w->name); 560 return; 561 } 562 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 563 564 for (i = 0; i < w->count; i++) { 565 error = bus_free_resource(dev, type, w->res[i]); 566 if (error) 567 device_printf(dev, 568 "failed to release %s resource: %d\n", w->name, 569 error); 570 } 571 free(w->res, M_DEVBUF); 572 } 573 574 static void 575 pcib_free_windows(struct pcib_softc *sc) 576 { 577 578 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 579 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 580 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 581 } 582 583 #ifdef PCI_RES_BUS 584 /* 585 * Allocate a suitable secondary bus for this bridge if needed and 586 * initialize the resource manager for the secondary bus range. Note 587 * that the minimum count is a desired value and this may allocate a 588 * smaller range. 589 */ 590 void 591 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 592 { 593 char buf[64]; 594 int error, rid, sec_reg; 595 596 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 597 case PCIM_HDRTYPE_BRIDGE: 598 sec_reg = PCIR_SECBUS_1; 599 bus->sub_reg = PCIR_SUBBUS_1; 600 break; 601 case PCIM_HDRTYPE_CARDBUS: 602 sec_reg = PCIR_SECBUS_2; 603 bus->sub_reg = PCIR_SUBBUS_2; 604 break; 605 default: 606 panic("not a PCI bridge"); 607 } 608 bus->sec = pci_read_config(dev, sec_reg, 1); 609 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 610 bus->dev = dev; 611 bus->rman.rm_start = 0; 612 bus->rman.rm_end = PCI_BUSMAX; 613 bus->rman.rm_type = RMAN_ARRAY; 614 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 615 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 616 error = rman_init(&bus->rman); 617 if (error) 618 panic("Failed to initialize %s bus number rman", 619 device_get_nameunit(dev)); 620 621 /* 622 * Allocate a bus range. This will return an existing bus range 623 * if one exists, or a new bus range if one does not. 624 */ 625 rid = 0; 626 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 627 min_count, 0); 628 if (bus->res == NULL) { 629 /* 630 * Fall back to just allocating a range of a single bus 631 * number. 632 */ 633 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 634 1, 0); 635 } else if (rman_get_size(bus->res) < min_count) 636 /* 637 * Attempt to grow the existing range to satisfy the 638 * minimum desired count. 639 */ 640 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 641 rman_get_start(bus->res), rman_get_start(bus->res) + 642 min_count - 1); 643 644 /* 645 * Add the initial resource to the rman. 646 */ 647 if (bus->res != NULL) { 648 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 649 rman_get_end(bus->res)); 650 if (error) 651 panic("Failed to add resource to rman"); 652 bus->sec = rman_get_start(bus->res); 653 bus->sub = rman_get_end(bus->res); 654 } 655 } 656 657 void 658 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 659 { 660 int error; 661 662 error = rman_fini(&bus->rman); 663 if (error) { 664 device_printf(dev, "failed to release bus number rman\n"); 665 return; 666 } 667 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 668 669 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 670 if (error) 671 device_printf(dev, 672 "failed to release bus numbers resource: %d\n", error); 673 } 674 675 static struct resource * 676 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 677 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 678 { 679 struct resource *res; 680 681 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 682 child); 683 if (res == NULL) 684 return (NULL); 685 686 if (bootverbose) 687 device_printf(bus->dev, 688 "allocated bus range (%ju-%ju) for rid %d of %s\n", 689 rman_get_start(res), rman_get_end(res), *rid, 690 pcib_child_name(child)); 691 rman_set_rid(res, *rid); 692 return (res); 693 } 694 695 /* 696 * Attempt to grow the secondary bus range. This is much simpler than 697 * for I/O windows as the range can only be grown by increasing 698 * subbus. 699 */ 700 static int 701 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 702 { 703 rman_res_t old_end; 704 int error; 705 706 old_end = rman_get_end(bus->res); 707 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 708 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 709 rman_get_start(bus->res), new_end); 710 if (error) 711 return (error); 712 if (bootverbose) 713 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 714 rman_get_start(bus->res), rman_get_end(bus->res)); 715 error = rman_manage_region(&bus->rman, old_end + 1, 716 rman_get_end(bus->res)); 717 if (error) 718 panic("Failed to add resource to rman"); 719 bus->sub = rman_get_end(bus->res); 720 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 721 return (0); 722 } 723 724 struct resource * 725 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 726 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 727 { 728 struct resource *res; 729 rman_res_t start_free, end_free, new_end; 730 731 /* 732 * First, see if the request can be satisified by the existing 733 * bus range. 734 */ 735 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 736 if (res != NULL) 737 return (res); 738 739 /* 740 * Figure out a range to grow the bus range. First, find the 741 * first bus number after the last allocated bus in the rman and 742 * enforce that as a minimum starting point for the range. 743 */ 744 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 745 end_free != bus->sub) 746 start_free = bus->sub + 1; 747 if (start_free < start) 748 start_free = start; 749 new_end = start_free + count - 1; 750 751 /* 752 * See if this new range would satisfy the request if it 753 * succeeds. 754 */ 755 if (new_end > end) 756 return (NULL); 757 758 /* Finally, attempt to grow the existing resource. */ 759 if (bootverbose) { 760 device_printf(bus->dev, 761 "attempting to grow bus range for %ju buses\n", count); 762 printf("\tback candidate range: %ju-%ju\n", start_free, 763 new_end); 764 } 765 if (pcib_grow_subbus(bus, new_end) == 0) 766 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 767 flags)); 768 return (NULL); 769 } 770 #endif 771 772 #else 773 774 /* 775 * Is the prefetch window open (eg, can we allocate memory in it?) 776 */ 777 static int 778 pcib_is_prefetch_open(struct pcib_softc *sc) 779 { 780 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 781 } 782 783 /* 784 * Is the nonprefetch window open (eg, can we allocate memory in it?) 785 */ 786 static int 787 pcib_is_nonprefetch_open(struct pcib_softc *sc) 788 { 789 return (sc->membase > 0 && sc->membase < sc->memlimit); 790 } 791 792 /* 793 * Is the io window open (eg, can we allocate ports in it?) 794 */ 795 static int 796 pcib_is_io_open(struct pcib_softc *sc) 797 { 798 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 799 } 800 801 /* 802 * Get current I/O decode. 803 */ 804 static void 805 pcib_get_io_decode(struct pcib_softc *sc) 806 { 807 device_t dev; 808 uint32_t iolow; 809 810 dev = sc->dev; 811 812 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 813 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 814 sc->iobase = PCI_PPBIOBASE( 815 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 816 else 817 sc->iobase = PCI_PPBIOBASE(0, iolow); 818 819 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 820 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 821 sc->iolimit = PCI_PPBIOLIMIT( 822 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 823 else 824 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 825 } 826 827 /* 828 * Get current memory decode. 829 */ 830 static void 831 pcib_get_mem_decode(struct pcib_softc *sc) 832 { 833 device_t dev; 834 pci_addr_t pmemlow; 835 836 dev = sc->dev; 837 838 sc->membase = PCI_PPBMEMBASE(0, 839 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 840 sc->memlimit = PCI_PPBMEMLIMIT(0, 841 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 842 843 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 844 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 845 sc->pmembase = PCI_PPBMEMBASE( 846 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 847 else 848 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 849 850 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 851 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 852 sc->pmemlimit = PCI_PPBMEMLIMIT( 853 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 854 else 855 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 856 } 857 858 /* 859 * Restore previous I/O decode. 860 */ 861 static void 862 pcib_set_io_decode(struct pcib_softc *sc) 863 { 864 device_t dev; 865 uint32_t iohi; 866 867 dev = sc->dev; 868 869 iohi = sc->iobase >> 16; 870 if (iohi > 0) 871 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 872 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 873 874 iohi = sc->iolimit >> 16; 875 if (iohi > 0) 876 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 877 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 878 } 879 880 /* 881 * Restore previous memory decode. 882 */ 883 static void 884 pcib_set_mem_decode(struct pcib_softc *sc) 885 { 886 device_t dev; 887 pci_addr_t pmemhi; 888 889 dev = sc->dev; 890 891 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 892 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 893 894 pmemhi = sc->pmembase >> 32; 895 if (pmemhi > 0) 896 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 897 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 898 899 pmemhi = sc->pmemlimit >> 32; 900 if (pmemhi > 0) 901 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 902 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 903 } 904 #endif 905 906 #ifdef PCI_HP 907 /* 908 * PCI-express HotPlug support. 909 */ 910 static int pci_enable_pcie_hp = 1; 911 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 912 &pci_enable_pcie_hp, 0, 913 "Enable support for native PCI-express HotPlug."); 914 915 static void 916 pcib_probe_hotplug(struct pcib_softc *sc) 917 { 918 device_t dev; 919 920 if (!pci_enable_pcie_hp) 921 return; 922 923 dev = sc->dev; 924 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 925 return; 926 927 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 928 return; 929 930 sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 931 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 932 933 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) 934 sc->flags |= PCIB_HOTPLUG; 935 } 936 937 /* 938 * Send a HotPlug command to the slot control register. If this slot 939 * uses command completion interrupts and a previous command is still 940 * in progress, then the command is dropped. Once the previous 941 * command completes or times out, pcib_pcie_hotplug_update() will be 942 * invoked to post a new command based on the slot's state at that 943 * time. 944 */ 945 static void 946 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 947 { 948 device_t dev; 949 uint16_t ctl, new; 950 951 dev = sc->dev; 952 953 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 954 return; 955 956 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 957 new = (ctl & ~mask) | val; 958 if (new == ctl) 959 return; 960 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 961 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 962 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 963 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 964 if (!cold) 965 callout_reset(&sc->pcie_cc_timer, hz, 966 pcib_pcie_cc_timeout, sc); 967 } 968 } 969 970 static void 971 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 972 { 973 device_t dev; 974 975 dev = sc->dev; 976 977 if (bootverbose) 978 device_printf(dev, "Command Completed\n"); 979 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 980 return; 981 callout_stop(&sc->pcie_cc_timer); 982 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 983 wakeup(sc); 984 } 985 986 /* 987 * Returns true if a card is fully inserted from the user's 988 * perspective. It may not yet be ready for access, but the driver 989 * can now start enabling access if necessary. 990 */ 991 static bool 992 pcib_hotplug_inserted(struct pcib_softc *sc) 993 { 994 995 /* Pretend the card isn't present if a detach is forced. */ 996 if (sc->flags & PCIB_DETACHING) 997 return (false); 998 999 /* Card must be present in the slot. */ 1000 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1001 return (false); 1002 1003 /* A power fault implicitly turns off power to the slot. */ 1004 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1005 return (false); 1006 1007 /* If the MRL is disengaged, the slot is powered off. */ 1008 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1009 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1010 return (false); 1011 1012 return (true); 1013 } 1014 1015 /* 1016 * Returns -1 if the card is fully inserted, powered, and ready for 1017 * access. Otherwise, returns 0. 1018 */ 1019 static int 1020 pcib_hotplug_present(struct pcib_softc *sc) 1021 { 1022 device_t dev; 1023 1024 dev = sc->dev; 1025 1026 /* Card must be inserted. */ 1027 if (!pcib_hotplug_inserted(sc)) 1028 return (0); 1029 1030 /* 1031 * Require the Electromechanical Interlock to be engaged if 1032 * present. 1033 */ 1034 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP && 1035 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0) 1036 return (0); 1037 1038 /* Require the Data Link Layer to be active. */ 1039 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1040 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1041 return (0); 1042 } 1043 1044 return (-1); 1045 } 1046 1047 static void 1048 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1049 bool schedule_task) 1050 { 1051 bool card_inserted; 1052 1053 /* Clear DETACHING if Present Detect has cleared. */ 1054 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1055 PCIEM_SLOT_STA_PDC) 1056 sc->flags &= ~PCIB_DETACHING; 1057 1058 card_inserted = pcib_hotplug_inserted(sc); 1059 1060 /* Turn the power indicator on if a card is inserted. */ 1061 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1062 mask |= PCIEM_SLOT_CTL_PIC; 1063 if (card_inserted) 1064 val |= PCIEM_SLOT_CTL_PI_ON; 1065 else if (sc->flags & PCIB_DETACH_PENDING) 1066 val |= PCIEM_SLOT_CTL_PI_BLINK; 1067 else 1068 val |= PCIEM_SLOT_CTL_PI_OFF; 1069 } 1070 1071 /* Turn the power on via the Power Controller if a card is inserted. */ 1072 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1073 mask |= PCIEM_SLOT_CTL_PCC; 1074 if (card_inserted) 1075 val |= PCIEM_SLOT_CTL_PC_ON; 1076 else 1077 val |= PCIEM_SLOT_CTL_PC_OFF; 1078 } 1079 1080 /* 1081 * If a card is inserted, enable the Electromechanical 1082 * Interlock. If a card is not inserted (or we are in the 1083 * process of detaching), disable the Electromechanical 1084 * Interlock. 1085 */ 1086 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { 1087 mask |= PCIEM_SLOT_CTL_EIC; 1088 if (card_inserted != 1089 !(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS)) 1090 val |= PCIEM_SLOT_CTL_EIC; 1091 } 1092 1093 /* 1094 * Start a timer to see if the Data Link Layer times out. 1095 * Note that we only start the timer if Presence Detect 1096 * changed on this interrupt. Stop any scheduled timer if 1097 * the Data Link Layer is active. 1098 */ 1099 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1100 if (card_inserted && 1101 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1102 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) { 1103 if (cold) 1104 device_printf(sc->dev, 1105 "Data Link Layer inactive\n"); 1106 else 1107 callout_reset(&sc->pcie_dll_timer, hz, 1108 pcib_pcie_dll_timeout, sc); 1109 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1110 callout_stop(&sc->pcie_dll_timer); 1111 } 1112 1113 pcib_pcie_hotplug_command(sc, val, mask); 1114 1115 /* 1116 * During attach the child "pci" device is added sychronously; 1117 * otherwise, the task is scheduled to manage the child 1118 * device. 1119 */ 1120 if (schedule_task && 1121 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1122 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task); 1123 } 1124 1125 static void 1126 pcib_pcie_intr(void *arg) 1127 { 1128 struct pcib_softc *sc; 1129 device_t dev; 1130 1131 sc = arg; 1132 dev = sc->dev; 1133 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1134 1135 /* Clear the events just reported. */ 1136 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1137 1138 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1139 if (sc->flags & PCIB_DETACH_PENDING) { 1140 device_printf(dev, 1141 "Attention Button Pressed: Detach Cancelled\n"); 1142 sc->flags &= ~PCIB_DETACH_PENDING; 1143 callout_stop(&sc->pcie_ab_timer); 1144 } else { 1145 device_printf(dev, 1146 "Attention Button Pressed: Detaching in 5 seconds\n"); 1147 sc->flags |= PCIB_DETACH_PENDING; 1148 callout_reset(&sc->pcie_ab_timer, 5 * hz, 1149 pcib_pcie_ab_timeout, sc); 1150 } 1151 } 1152 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1153 device_printf(dev, "Power Fault Detected\n"); 1154 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1155 device_printf(dev, "MRL Sensor Changed to %s\n", 1156 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1157 "closed"); 1158 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1159 device_printf(dev, "Present Detect Changed to %s\n", 1160 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1161 "empty"); 1162 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1163 pcib_pcie_hotplug_command_completed(sc); 1164 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1165 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1166 if (bootverbose) 1167 device_printf(dev, 1168 "Data Link Layer State Changed to %s\n", 1169 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1170 "active" : "inactive"); 1171 } 1172 1173 pcib_pcie_hotplug_update(sc, 0, 0, true); 1174 } 1175 1176 static void 1177 pcib_pcie_hotplug_task(void *context, int pending) 1178 { 1179 struct pcib_softc *sc; 1180 device_t dev; 1181 1182 sc = context; 1183 mtx_lock(&Giant); 1184 dev = sc->dev; 1185 if (pcib_hotplug_present(sc) != 0) { 1186 if (sc->child == NULL) { 1187 sc->child = device_add_child(dev, "pci", -1); 1188 bus_generic_attach(dev); 1189 } 1190 } else { 1191 if (sc->child != NULL) { 1192 if (device_delete_child(dev, sc->child) == 0) 1193 sc->child = NULL; 1194 } 1195 } 1196 mtx_unlock(&Giant); 1197 } 1198 1199 static void 1200 pcib_pcie_ab_timeout(void *arg) 1201 { 1202 struct pcib_softc *sc; 1203 device_t dev; 1204 1205 sc = arg; 1206 dev = sc->dev; 1207 mtx_assert(&Giant, MA_OWNED); 1208 if (sc->flags & PCIB_DETACH_PENDING) { 1209 sc->flags |= PCIB_DETACHING; 1210 sc->flags &= ~PCIB_DETACH_PENDING; 1211 pcib_pcie_hotplug_update(sc, 0, 0, true); 1212 } 1213 } 1214 1215 static void 1216 pcib_pcie_cc_timeout(void *arg) 1217 { 1218 struct pcib_softc *sc; 1219 device_t dev; 1220 uint16_t sta; 1221 1222 sc = arg; 1223 dev = sc->dev; 1224 mtx_assert(&Giant, MA_OWNED); 1225 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1226 if (!(sta & PCIEM_SLOT_STA_CC)) { 1227 device_printf(dev, 1228 "Hotplug Command Timed Out - forcing detach\n"); 1229 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING); 1230 sc->flags |= PCIB_DETACHING; 1231 pcib_pcie_hotplug_update(sc, 0, 0, true); 1232 } else { 1233 device_printf(dev, 1234 "Missed HotPlug interrupt waiting for Command Completion\n"); 1235 pcib_pcie_intr(sc); 1236 } 1237 } 1238 1239 static void 1240 pcib_pcie_dll_timeout(void *arg) 1241 { 1242 struct pcib_softc *sc; 1243 device_t dev; 1244 uint16_t sta; 1245 1246 sc = arg; 1247 dev = sc->dev; 1248 mtx_assert(&Giant, MA_OWNED); 1249 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1250 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1251 device_printf(dev, 1252 "Timed out waiting for Data Link Layer Active\n"); 1253 sc->flags |= PCIB_DETACHING; 1254 pcib_pcie_hotplug_update(sc, 0, 0, true); 1255 } else if (sta != sc->pcie_link_sta) { 1256 device_printf(dev, 1257 "Missed HotPlug interrupt waiting for DLL Active\n"); 1258 pcib_pcie_intr(sc); 1259 } 1260 } 1261 1262 static int 1263 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1264 { 1265 device_t dev; 1266 int count, error, rid; 1267 1268 rid = -1; 1269 dev = sc->dev; 1270 1271 /* 1272 * For simplicity, only use MSI-X if there is a single message. 1273 * To support a device with multiple messages we would have to 1274 * use remap intr if the MSI number is not 0. 1275 */ 1276 count = pci_msix_count(dev); 1277 if (count == 1) { 1278 error = pci_alloc_msix(dev, &count); 1279 if (error == 0) 1280 rid = 1; 1281 } 1282 1283 if (rid < 0 && pci_msi_count(dev) > 0) { 1284 count = 1; 1285 error = pci_alloc_msi(dev, &count); 1286 if (error == 0) 1287 rid = 1; 1288 } 1289 1290 if (rid < 0) 1291 rid = 0; 1292 1293 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1294 RF_ACTIVE); 1295 if (sc->pcie_irq == NULL) { 1296 device_printf(dev, 1297 "Failed to allocate interrupt for PCI-e events\n"); 1298 if (rid > 0) 1299 pci_release_msi(dev); 1300 return (ENXIO); 1301 } 1302 1303 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC, 1304 NULL, pcib_pcie_intr, sc, &sc->pcie_ihand); 1305 if (error) { 1306 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1307 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1308 if (rid > 0) 1309 pci_release_msi(dev); 1310 return (error); 1311 } 1312 return (0); 1313 } 1314 1315 static int 1316 pcib_release_pcie_irq(struct pcib_softc *sc) 1317 { 1318 device_t dev; 1319 int error; 1320 1321 dev = sc->dev; 1322 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1323 if (error) 1324 return (error); 1325 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1326 if (error) 1327 return (error); 1328 return (pci_release_msi(dev)); 1329 } 1330 1331 static void 1332 pcib_setup_hotplug(struct pcib_softc *sc) 1333 { 1334 device_t dev; 1335 uint16_t mask, val; 1336 1337 dev = sc->dev; 1338 callout_init(&sc->pcie_ab_timer, 0); 1339 callout_init(&sc->pcie_cc_timer, 0); 1340 callout_init(&sc->pcie_dll_timer, 0); 1341 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1342 1343 /* Allocate IRQ. */ 1344 if (pcib_alloc_pcie_irq(sc) != 0) 1345 return; 1346 1347 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1348 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1349 1350 /* Clear any events previously pending. */ 1351 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1352 1353 /* Enable HotPlug events. */ 1354 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1355 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1356 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1357 val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE; 1358 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1359 val |= PCIEM_SLOT_CTL_ABPE; 1360 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1361 val |= PCIEM_SLOT_CTL_PFDE; 1362 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1363 val |= PCIEM_SLOT_CTL_MRLSCE; 1364 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1365 val |= PCIEM_SLOT_CTL_CCIE; 1366 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) 1367 val |= PCIEM_SLOT_CTL_DLLSCE; 1368 1369 /* Turn the attention indicator off. */ 1370 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1371 mask |= PCIEM_SLOT_CTL_AIC; 1372 val |= PCIEM_SLOT_CTL_AI_OFF; 1373 } 1374 1375 pcib_pcie_hotplug_update(sc, val, mask, false); 1376 } 1377 1378 static int 1379 pcib_detach_hotplug(struct pcib_softc *sc) 1380 { 1381 uint16_t mask, val; 1382 int error; 1383 1384 /* Disable the card in the slot and force it to detach. */ 1385 if (sc->flags & PCIB_DETACH_PENDING) { 1386 sc->flags &= ~PCIB_DETACH_PENDING; 1387 callout_stop(&sc->pcie_ab_timer); 1388 } 1389 sc->flags |= PCIB_DETACHING; 1390 1391 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1392 callout_stop(&sc->pcie_cc_timer); 1393 tsleep(sc, 0, "hpcmd", hz); 1394 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1395 } 1396 1397 /* Disable HotPlug events. */ 1398 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1399 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1400 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1401 val = 0; 1402 1403 /* Turn the attention indicator off. */ 1404 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1405 mask |= PCIEM_SLOT_CTL_AIC; 1406 val |= PCIEM_SLOT_CTL_AI_OFF; 1407 } 1408 1409 pcib_pcie_hotplug_update(sc, val, mask, false); 1410 1411 error = pcib_release_pcie_irq(sc); 1412 if (error) 1413 return (error); 1414 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task); 1415 callout_drain(&sc->pcie_ab_timer); 1416 callout_drain(&sc->pcie_cc_timer); 1417 callout_drain(&sc->pcie_dll_timer); 1418 return (0); 1419 } 1420 #endif 1421 1422 /* 1423 * Get current bridge configuration. 1424 */ 1425 static void 1426 pcib_cfg_save(struct pcib_softc *sc) 1427 { 1428 #ifndef NEW_PCIB 1429 device_t dev; 1430 uint16_t command; 1431 1432 dev = sc->dev; 1433 1434 command = pci_read_config(dev, PCIR_COMMAND, 2); 1435 if (command & PCIM_CMD_PORTEN) 1436 pcib_get_io_decode(sc); 1437 if (command & PCIM_CMD_MEMEN) 1438 pcib_get_mem_decode(sc); 1439 #endif 1440 } 1441 1442 /* 1443 * Restore previous bridge configuration. 1444 */ 1445 static void 1446 pcib_cfg_restore(struct pcib_softc *sc) 1447 { 1448 device_t dev; 1449 #ifndef NEW_PCIB 1450 uint16_t command; 1451 #endif 1452 dev = sc->dev; 1453 1454 #ifdef NEW_PCIB 1455 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1456 #else 1457 command = pci_read_config(dev, PCIR_COMMAND, 2); 1458 if (command & PCIM_CMD_PORTEN) 1459 pcib_set_io_decode(sc); 1460 if (command & PCIM_CMD_MEMEN) 1461 pcib_set_mem_decode(sc); 1462 #endif 1463 } 1464 1465 /* 1466 * Generic device interface 1467 */ 1468 static int 1469 pcib_probe(device_t dev) 1470 { 1471 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1472 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1473 device_set_desc(dev, "PCI-PCI bridge"); 1474 return(-10000); 1475 } 1476 return(ENXIO); 1477 } 1478 1479 void 1480 pcib_attach_common(device_t dev) 1481 { 1482 struct pcib_softc *sc; 1483 struct sysctl_ctx_list *sctx; 1484 struct sysctl_oid *soid; 1485 int comma; 1486 1487 sc = device_get_softc(dev); 1488 sc->dev = dev; 1489 1490 /* 1491 * Get current bridge configuration. 1492 */ 1493 sc->domain = pci_get_domain(dev); 1494 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1495 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1496 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1497 #endif 1498 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1499 pcib_cfg_save(sc); 1500 1501 /* 1502 * The primary bus register should always be the bus of the 1503 * parent. 1504 */ 1505 sc->pribus = pci_get_bus(dev); 1506 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1507 1508 /* 1509 * Setup sysctl reporting nodes 1510 */ 1511 sctx = device_get_sysctl_ctx(dev); 1512 soid = device_get_sysctl_tree(dev); 1513 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1514 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1515 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1516 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1517 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1518 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1519 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1520 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1521 1522 /* 1523 * Quirk handling. 1524 */ 1525 switch (pci_get_devid(dev)) { 1526 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1527 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1528 { 1529 uint8_t supbus; 1530 1531 supbus = pci_read_config(dev, 0x41, 1); 1532 if (supbus != 0xff) { 1533 sc->bus.sec = supbus + 1; 1534 sc->bus.sub = supbus + 1; 1535 } 1536 break; 1537 } 1538 #endif 1539 1540 /* 1541 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1542 * and it is a subtractive bridge. However, the ProgIf is wrong 1543 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1544 * happen. There are also Toshiba and Cavium ThunderX bridges 1545 * that behave this way. 1546 */ 1547 case 0xa002177d: /* Cavium ThunderX */ 1548 case 0x124b8086: /* Intel 82380FB Mobile */ 1549 case 0x060513d7: /* Toshiba ???? */ 1550 sc->flags |= PCIB_SUBTRACTIVE; 1551 break; 1552 1553 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1554 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1555 case 0x00dd10de: 1556 { 1557 char *cp; 1558 1559 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1560 break; 1561 if (strncmp(cp, "Compal", 6) != 0) { 1562 freeenv(cp); 1563 break; 1564 } 1565 freeenv(cp); 1566 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1567 break; 1568 if (strncmp(cp, "08A0", 4) != 0) { 1569 freeenv(cp); 1570 break; 1571 } 1572 freeenv(cp); 1573 if (sc->bus.sub < 0xa) { 1574 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1575 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1576 } 1577 break; 1578 } 1579 #endif 1580 } 1581 1582 if (pci_msi_device_blacklisted(dev)) 1583 sc->flags |= PCIB_DISABLE_MSI; 1584 1585 if (pci_msix_device_blacklisted(dev)) 1586 sc->flags |= PCIB_DISABLE_MSIX; 1587 1588 /* 1589 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1590 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1591 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1592 * This means they act as if they were subtractively decoding 1593 * bridges and pass all transactions. Mark them and real ProgIf 1 1594 * parts as subtractive. 1595 */ 1596 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1597 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1598 sc->flags |= PCIB_SUBTRACTIVE; 1599 1600 #ifdef PCI_HP 1601 pcib_probe_hotplug(sc); 1602 #endif 1603 #ifdef NEW_PCIB 1604 #ifdef PCI_RES_BUS 1605 pcib_setup_secbus(dev, &sc->bus, 1); 1606 #endif 1607 pcib_probe_windows(sc); 1608 #endif 1609 #ifdef PCI_HP 1610 if (sc->flags & PCIB_HOTPLUG) 1611 pcib_setup_hotplug(sc); 1612 #endif 1613 if (bootverbose) { 1614 device_printf(dev, " domain %d\n", sc->domain); 1615 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1616 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1617 #ifdef NEW_PCIB 1618 if (pcib_is_window_open(&sc->io)) 1619 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1620 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1621 if (pcib_is_window_open(&sc->mem)) 1622 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1623 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1624 if (pcib_is_window_open(&sc->pmem)) 1625 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1626 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1627 #else 1628 if (pcib_is_io_open(sc)) 1629 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1630 sc->iobase, sc->iolimit); 1631 if (pcib_is_nonprefetch_open(sc)) 1632 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1633 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1634 if (pcib_is_prefetch_open(sc)) 1635 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1636 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1637 #endif 1638 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1639 sc->flags & PCIB_SUBTRACTIVE) { 1640 device_printf(dev, " special decode "); 1641 comma = 0; 1642 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1643 printf("ISA"); 1644 comma = 1; 1645 } 1646 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1647 printf("%sVGA", comma ? ", " : ""); 1648 comma = 1; 1649 } 1650 if (sc->flags & PCIB_SUBTRACTIVE) 1651 printf("%ssubtractive", comma ? ", " : ""); 1652 printf("\n"); 1653 } 1654 } 1655 1656 /* 1657 * Always enable busmastering on bridges so that transactions 1658 * initiated on the secondary bus are passed through to the 1659 * primary bus. 1660 */ 1661 pci_enable_busmaster(dev); 1662 } 1663 1664 #ifdef PCI_HP 1665 static int 1666 pcib_present(struct pcib_softc *sc) 1667 { 1668 1669 if (sc->flags & PCIB_HOTPLUG) 1670 return (pcib_hotplug_present(sc) != 0); 1671 return (1); 1672 } 1673 #endif 1674 1675 int 1676 pcib_attach_child(device_t dev) 1677 { 1678 struct pcib_softc *sc; 1679 1680 sc = device_get_softc(dev); 1681 if (sc->bus.sec == 0) { 1682 /* no secondary bus; we should have fixed this */ 1683 return(0); 1684 } 1685 1686 #ifdef PCI_HP 1687 if (!pcib_present(sc)) { 1688 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1689 return (0); 1690 } 1691 #endif 1692 1693 sc->child = device_add_child(dev, "pci", -1); 1694 return (bus_generic_attach(dev)); 1695 } 1696 1697 int 1698 pcib_attach(device_t dev) 1699 { 1700 1701 pcib_attach_common(dev); 1702 return (pcib_attach_child(dev)); 1703 } 1704 1705 int 1706 pcib_detach(device_t dev) 1707 { 1708 #if defined(PCI_HP) || defined(NEW_PCIB) 1709 struct pcib_softc *sc; 1710 #endif 1711 int error; 1712 1713 #if defined(PCI_HP) || defined(NEW_PCIB) 1714 sc = device_get_softc(dev); 1715 #endif 1716 error = bus_generic_detach(dev); 1717 if (error) 1718 return (error); 1719 #ifdef PCI_HP 1720 if (sc->flags & PCIB_HOTPLUG) { 1721 error = pcib_detach_hotplug(sc); 1722 if (error) 1723 return (error); 1724 } 1725 #endif 1726 error = device_delete_children(dev); 1727 if (error) 1728 return (error); 1729 #ifdef NEW_PCIB 1730 pcib_free_windows(sc); 1731 #ifdef PCI_RES_BUS 1732 pcib_free_secbus(dev, &sc->bus); 1733 #endif 1734 #endif 1735 return (0); 1736 } 1737 1738 int 1739 pcib_suspend(device_t dev) 1740 { 1741 1742 pcib_cfg_save(device_get_softc(dev)); 1743 return (bus_generic_suspend(dev)); 1744 } 1745 1746 int 1747 pcib_resume(device_t dev) 1748 { 1749 1750 pcib_cfg_restore(device_get_softc(dev)); 1751 return (bus_generic_resume(dev)); 1752 } 1753 1754 void 1755 pcib_bridge_init(device_t dev) 1756 { 1757 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1758 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1759 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1760 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1761 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1762 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1763 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1764 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1765 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1766 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1767 } 1768 1769 int 1770 pcib_child_present(device_t dev, device_t child) 1771 { 1772 #ifdef PCI_HP 1773 struct pcib_softc *sc = device_get_softc(dev); 1774 int retval; 1775 1776 retval = bus_child_present(dev); 1777 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1778 retval = pcib_hotplug_present(sc); 1779 return (retval); 1780 #else 1781 return (bus_child_present(dev)); 1782 #endif 1783 } 1784 1785 int 1786 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1787 { 1788 struct pcib_softc *sc = device_get_softc(dev); 1789 1790 switch (which) { 1791 case PCIB_IVAR_DOMAIN: 1792 *result = sc->domain; 1793 return(0); 1794 case PCIB_IVAR_BUS: 1795 *result = sc->bus.sec; 1796 return(0); 1797 } 1798 return(ENOENT); 1799 } 1800 1801 int 1802 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1803 { 1804 1805 switch (which) { 1806 case PCIB_IVAR_DOMAIN: 1807 return(EINVAL); 1808 case PCIB_IVAR_BUS: 1809 return(EINVAL); 1810 } 1811 return(ENOENT); 1812 } 1813 1814 #ifdef NEW_PCIB 1815 /* 1816 * Attempt to allocate a resource from the existing resources assigned 1817 * to a window. 1818 */ 1819 static struct resource * 1820 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1821 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1822 rman_res_t count, u_int flags) 1823 { 1824 struct resource *res; 1825 1826 if (!pcib_is_window_open(w)) 1827 return (NULL); 1828 1829 res = rman_reserve_resource(&w->rman, start, end, count, 1830 flags & ~RF_ACTIVE, child); 1831 if (res == NULL) 1832 return (NULL); 1833 1834 if (bootverbose) 1835 device_printf(sc->dev, 1836 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1837 w->name, rman_get_start(res), rman_get_end(res), *rid, 1838 pcib_child_name(child)); 1839 rman_set_rid(res, *rid); 1840 1841 /* 1842 * If the resource should be active, pass that request up the 1843 * tree. This assumes the parent drivers can handle 1844 * activating sub-allocated resources. 1845 */ 1846 if (flags & RF_ACTIVE) { 1847 if (bus_activate_resource(child, type, *rid, res) != 0) { 1848 rman_release_resource(res); 1849 return (NULL); 1850 } 1851 } 1852 1853 return (res); 1854 } 1855 1856 /* Allocate a fresh resource range for an unconfigured window. */ 1857 static int 1858 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1859 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1860 { 1861 struct resource *res; 1862 rman_res_t base, limit, wmask; 1863 int rid; 1864 1865 /* 1866 * If this is an I/O window on a bridge with ISA enable set 1867 * and the start address is below 64k, then try to allocate an 1868 * initial window of 0x1000 bytes long starting at address 1869 * 0xf000 and walking down. Note that if the original request 1870 * was larger than the non-aliased range size of 0x100 our 1871 * caller would have raised the start address up to 64k 1872 * already. 1873 */ 1874 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1875 start < 65536) { 1876 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1877 limit = base + 0xfff; 1878 1879 /* 1880 * Skip ranges that wouldn't work for the 1881 * original request. Note that the actual 1882 * window that overlaps are the non-alias 1883 * ranges within [base, limit], so this isn't 1884 * quite a simple comparison. 1885 */ 1886 if (start + count > limit - 0x400) 1887 continue; 1888 if (base == 0) { 1889 /* 1890 * The first open region for the window at 1891 * 0 is 0x400-0x4ff. 1892 */ 1893 if (end - count + 1 < 0x400) 1894 continue; 1895 } else { 1896 if (end - count + 1 < base) 1897 continue; 1898 } 1899 1900 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1901 w->base = base; 1902 w->limit = limit; 1903 return (0); 1904 } 1905 } 1906 return (ENOSPC); 1907 } 1908 1909 wmask = ((rman_res_t)1 << w->step) - 1; 1910 if (RF_ALIGNMENT(flags) < w->step) { 1911 flags &= ~RF_ALIGNMENT_MASK; 1912 flags |= RF_ALIGNMENT_LOG2(w->step); 1913 } 1914 start &= ~wmask; 1915 end |= wmask; 1916 count = roundup2(count, (rman_res_t)1 << w->step); 1917 rid = w->reg; 1918 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1919 flags & ~RF_ACTIVE); 1920 if (res == NULL) 1921 return (ENOSPC); 1922 pcib_add_window_resources(w, &res, 1); 1923 pcib_activate_window(sc, type); 1924 w->base = rman_get_start(res); 1925 w->limit = rman_get_end(res); 1926 return (0); 1927 } 1928 1929 /* Try to expand an existing window to the requested base and limit. */ 1930 static int 1931 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1932 rman_res_t base, rman_res_t limit) 1933 { 1934 struct resource *res; 1935 int error, i, force_64k_base; 1936 1937 KASSERT(base <= w->base && limit >= w->limit, 1938 ("attempting to shrink window")); 1939 1940 /* 1941 * XXX: pcib_grow_window() doesn't try to do this anyway and 1942 * the error handling for all the edge cases would be tedious. 1943 */ 1944 KASSERT(limit == w->limit || base == w->base, 1945 ("attempting to grow both ends of a window")); 1946 1947 /* 1948 * Yet more special handling for requests to expand an I/O 1949 * window behind an ISA-enabled bridge. Since I/O windows 1950 * have to grow in 0x1000 increments and the end of the 0xffff 1951 * range is an alias, growing a window below 64k will always 1952 * result in allocating new resources and never adjusting an 1953 * existing resource. 1954 */ 1955 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1956 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1957 KASSERT(limit == w->limit || limit <= 65535, 1958 ("attempting to grow both ends across 64k ISA alias")); 1959 1960 if (base != w->base) 1961 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1962 else 1963 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1964 limit); 1965 if (error == 0) { 1966 w->base = base; 1967 w->limit = limit; 1968 } 1969 return (error); 1970 } 1971 1972 /* 1973 * Find the existing resource to adjust. Usually there is only one, 1974 * but for an ISA-enabled bridge we might be growing the I/O window 1975 * above 64k and need to find the existing resource that maps all 1976 * of the area above 64k. 1977 */ 1978 for (i = 0; i < w->count; i++) { 1979 if (rman_get_end(w->res[i]) == w->limit) 1980 break; 1981 } 1982 KASSERT(i != w->count, ("did not find existing resource")); 1983 res = w->res[i]; 1984 1985 /* 1986 * Usually the resource we found should match the window's 1987 * existing range. The one exception is the ISA-enabled case 1988 * mentioned above in which case the resource should start at 1989 * 64k. 1990 */ 1991 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1992 w->base <= 65535) { 1993 KASSERT(rman_get_start(res) == 65536, 1994 ("existing resource mismatch")); 1995 force_64k_base = 1; 1996 } else { 1997 KASSERT(w->base == rman_get_start(res), 1998 ("existing resource mismatch")); 1999 force_64k_base = 0; 2000 } 2001 2002 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2003 rman_get_start(res) : base, limit); 2004 if (error) 2005 return (error); 2006 2007 /* Add the newly allocated region to the resource manager. */ 2008 if (w->base != base) { 2009 error = rman_manage_region(&w->rman, base, w->base - 1); 2010 w->base = base; 2011 } else { 2012 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2013 w->limit = limit; 2014 } 2015 if (error) { 2016 if (bootverbose) 2017 device_printf(sc->dev, 2018 "failed to expand %s resource manager\n", w->name); 2019 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2020 rman_get_start(res) : w->base, w->limit); 2021 } 2022 return (error); 2023 } 2024 2025 /* 2026 * Attempt to grow a window to make room for a given resource request. 2027 */ 2028 static int 2029 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2030 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2031 { 2032 rman_res_t align, start_free, end_free, front, back, wmask; 2033 int error; 2034 2035 /* 2036 * Clamp the desired resource range to the maximum address 2037 * this window supports. Reject impossible requests. 2038 * 2039 * For I/O port requests behind a bridge with the ISA enable 2040 * bit set, force large allocations to start above 64k. 2041 */ 2042 if (!w->valid) 2043 return (EINVAL); 2044 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2045 start < 65536) 2046 start = 65536; 2047 if (end > w->rman.rm_end) 2048 end = w->rman.rm_end; 2049 if (start + count - 1 > end || start + count < start) 2050 return (EINVAL); 2051 wmask = ((rman_res_t)1 << w->step) - 1; 2052 2053 /* 2054 * If there is no resource at all, just try to allocate enough 2055 * aligned space for this resource. 2056 */ 2057 if (w->res == NULL) { 2058 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2059 flags); 2060 if (error) { 2061 if (bootverbose) 2062 device_printf(sc->dev, 2063 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2064 w->name, start, end, count); 2065 return (error); 2066 } 2067 if (bootverbose) 2068 device_printf(sc->dev, 2069 "allocated initial %s window of %#jx-%#jx\n", 2070 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2071 goto updatewin; 2072 } 2073 2074 /* 2075 * See if growing the window would help. Compute the minimum 2076 * amount of address space needed on both the front and back 2077 * ends of the existing window to satisfy the allocation. 2078 * 2079 * For each end, build a candidate region adjusting for the 2080 * required alignment, etc. If there is a free region at the 2081 * edge of the window, grow from the inner edge of the free 2082 * region. Otherwise grow from the window boundary. 2083 * 2084 * Growing an I/O window below 64k for a bridge with the ISA 2085 * enable bit doesn't require any special magic as the step 2086 * size of an I/O window (1k) always includes multiple 2087 * non-alias ranges when it is grown in either direction. 2088 * 2089 * XXX: Special case: if w->res is completely empty and the 2090 * request size is larger than w->res, we should find the 2091 * optimal aligned buffer containing w->res and allocate that. 2092 */ 2093 if (bootverbose) 2094 device_printf(sc->dev, 2095 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2096 w->name, start, end, count); 2097 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2098 if (start < w->base) { 2099 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2100 0 || start_free != w->base) 2101 end_free = w->base; 2102 if (end_free > end) 2103 end_free = end + 1; 2104 2105 /* Move end_free down until it is properly aligned. */ 2106 end_free &= ~(align - 1); 2107 end_free--; 2108 front = end_free - (count - 1); 2109 2110 /* 2111 * The resource would now be allocated at (front, 2112 * end_free). Ensure that fits in the (start, end) 2113 * bounds. end_free is checked above. If 'front' is 2114 * ok, ensure it is properly aligned for this window. 2115 * Also check for underflow. 2116 */ 2117 if (front >= start && front <= end_free) { 2118 if (bootverbose) 2119 printf("\tfront candidate range: %#jx-%#jx\n", 2120 front, end_free); 2121 front &= ~wmask; 2122 front = w->base - front; 2123 } else 2124 front = 0; 2125 } else 2126 front = 0; 2127 if (end > w->limit) { 2128 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2129 0 || end_free != w->limit) 2130 start_free = w->limit + 1; 2131 if (start_free < start) 2132 start_free = start; 2133 2134 /* Move start_free up until it is properly aligned. */ 2135 start_free = roundup2(start_free, align); 2136 back = start_free + count - 1; 2137 2138 /* 2139 * The resource would now be allocated at (start_free, 2140 * back). Ensure that fits in the (start, end) 2141 * bounds. start_free is checked above. If 'back' is 2142 * ok, ensure it is properly aligned for this window. 2143 * Also check for overflow. 2144 */ 2145 if (back <= end && start_free <= back) { 2146 if (bootverbose) 2147 printf("\tback candidate range: %#jx-%#jx\n", 2148 start_free, back); 2149 back |= wmask; 2150 back -= w->limit; 2151 } else 2152 back = 0; 2153 } else 2154 back = 0; 2155 2156 /* 2157 * Try to allocate the smallest needed region first. 2158 * If that fails, fall back to the other region. 2159 */ 2160 error = ENOSPC; 2161 while (front != 0 || back != 0) { 2162 if (front != 0 && (front <= back || back == 0)) { 2163 error = pcib_expand_window(sc, w, type, w->base - front, 2164 w->limit); 2165 if (error == 0) 2166 break; 2167 front = 0; 2168 } else { 2169 error = pcib_expand_window(sc, w, type, w->base, 2170 w->limit + back); 2171 if (error == 0) 2172 break; 2173 back = 0; 2174 } 2175 } 2176 2177 if (error) 2178 return (error); 2179 if (bootverbose) 2180 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2181 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2182 2183 updatewin: 2184 /* Write the new window. */ 2185 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2186 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2187 pcib_write_windows(sc, w->mask); 2188 return (0); 2189 } 2190 2191 /* 2192 * We have to trap resource allocation requests and ensure that the bridge 2193 * is set up to, or capable of handling them. 2194 */ 2195 struct resource * 2196 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2197 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2198 { 2199 struct pcib_softc *sc; 2200 struct resource *r; 2201 2202 sc = device_get_softc(dev); 2203 2204 /* 2205 * VGA resources are decoded iff the VGA enable bit is set in 2206 * the bridge control register. VGA resources do not fall into 2207 * the resource windows and are passed up to the parent. 2208 */ 2209 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2210 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2211 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2212 return (bus_generic_alloc_resource(dev, child, type, 2213 rid, start, end, count, flags)); 2214 else 2215 return (NULL); 2216 } 2217 2218 switch (type) { 2219 #ifdef PCI_RES_BUS 2220 case PCI_RES_BUS: 2221 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2222 count, flags)); 2223 #endif 2224 case SYS_RES_IOPORT: 2225 if (pcib_is_isa_range(sc, start, end, count)) 2226 return (NULL); 2227 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2228 end, count, flags); 2229 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2230 break; 2231 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2232 flags) == 0) 2233 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2234 rid, start, end, count, flags); 2235 break; 2236 case SYS_RES_MEMORY: 2237 /* 2238 * For prefetchable resources, prefer the prefetchable 2239 * memory window, but fall back to the regular memory 2240 * window if that fails. Try both windows before 2241 * attempting to grow a window in case the firmware 2242 * has used a range in the regular memory window to 2243 * map a prefetchable BAR. 2244 */ 2245 if (flags & RF_PREFETCHABLE) { 2246 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2247 rid, start, end, count, flags); 2248 if (r != NULL) 2249 break; 2250 } 2251 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2252 start, end, count, flags); 2253 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2254 break; 2255 if (flags & RF_PREFETCHABLE) { 2256 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2257 count, flags) == 0) { 2258 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2259 type, rid, start, end, count, flags); 2260 if (r != NULL) 2261 break; 2262 } 2263 } 2264 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2265 flags & ~RF_PREFETCHABLE) == 0) 2266 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2267 rid, start, end, count, flags); 2268 break; 2269 default: 2270 return (bus_generic_alloc_resource(dev, child, type, rid, 2271 start, end, count, flags)); 2272 } 2273 2274 /* 2275 * If attempts to suballocate from the window fail but this is a 2276 * subtractive bridge, pass the request up the tree. 2277 */ 2278 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2279 return (bus_generic_alloc_resource(dev, child, type, rid, 2280 start, end, count, flags)); 2281 return (r); 2282 } 2283 2284 int 2285 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2286 rman_res_t start, rman_res_t end) 2287 { 2288 struct pcib_softc *sc; 2289 2290 sc = device_get_softc(bus); 2291 if (pcib_is_resource_managed(sc, type, r)) 2292 return (rman_adjust_resource(r, start, end)); 2293 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 2294 } 2295 2296 int 2297 pcib_release_resource(device_t dev, device_t child, int type, int rid, 2298 struct resource *r) 2299 { 2300 struct pcib_softc *sc; 2301 int error; 2302 2303 sc = device_get_softc(dev); 2304 if (pcib_is_resource_managed(sc, type, r)) { 2305 if (rman_get_flags(r) & RF_ACTIVE) { 2306 error = bus_deactivate_resource(child, type, rid, r); 2307 if (error) 2308 return (error); 2309 } 2310 return (rman_release_resource(r)); 2311 } 2312 return (bus_generic_release_resource(dev, child, type, rid, r)); 2313 } 2314 #else 2315 /* 2316 * We have to trap resource allocation requests and ensure that the bridge 2317 * is set up to, or capable of handling them. 2318 */ 2319 struct resource * 2320 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2321 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2322 { 2323 struct pcib_softc *sc = device_get_softc(dev); 2324 const char *name, *suffix; 2325 int ok; 2326 2327 /* 2328 * Fail the allocation for this range if it's not supported. 2329 */ 2330 name = device_get_nameunit(child); 2331 if (name == NULL) { 2332 name = ""; 2333 suffix = ""; 2334 } else 2335 suffix = " "; 2336 switch (type) { 2337 case SYS_RES_IOPORT: 2338 ok = 0; 2339 if (!pcib_is_io_open(sc)) 2340 break; 2341 ok = (start >= sc->iobase && end <= sc->iolimit); 2342 2343 /* 2344 * Make sure we allow access to VGA I/O addresses when the 2345 * bridge has the "VGA Enable" bit set. 2346 */ 2347 if (!ok && pci_is_vga_ioport_range(start, end)) 2348 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2349 2350 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2351 if (!ok) { 2352 if (start < sc->iobase) 2353 start = sc->iobase; 2354 if (end > sc->iolimit) 2355 end = sc->iolimit; 2356 if (start < end) 2357 ok = 1; 2358 } 2359 } else { 2360 ok = 1; 2361 #if 0 2362 /* 2363 * If we overlap with the subtractive range, then 2364 * pick the upper range to use. 2365 */ 2366 if (start < sc->iolimit && end > sc->iobase) 2367 start = sc->iolimit + 1; 2368 #endif 2369 } 2370 if (end < start) { 2371 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2372 end, start); 2373 start = 0; 2374 end = 0; 2375 ok = 0; 2376 } 2377 if (!ok) { 2378 device_printf(dev, "%s%srequested unsupported I/O " 2379 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2380 name, suffix, start, end, sc->iobase, sc->iolimit); 2381 return (NULL); 2382 } 2383 if (bootverbose) 2384 device_printf(dev, 2385 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2386 name, suffix, start, end); 2387 break; 2388 2389 case SYS_RES_MEMORY: 2390 ok = 0; 2391 if (pcib_is_nonprefetch_open(sc)) 2392 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2393 if (pcib_is_prefetch_open(sc)) 2394 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2395 2396 /* 2397 * Make sure we allow access to VGA memory addresses when the 2398 * bridge has the "VGA Enable" bit set. 2399 */ 2400 if (!ok && pci_is_vga_memory_range(start, end)) 2401 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2402 2403 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2404 if (!ok) { 2405 ok = 1; 2406 if (flags & RF_PREFETCHABLE) { 2407 if (pcib_is_prefetch_open(sc)) { 2408 if (start < sc->pmembase) 2409 start = sc->pmembase; 2410 if (end > sc->pmemlimit) 2411 end = sc->pmemlimit; 2412 } else { 2413 ok = 0; 2414 } 2415 } else { /* non-prefetchable */ 2416 if (pcib_is_nonprefetch_open(sc)) { 2417 if (start < sc->membase) 2418 start = sc->membase; 2419 if (end > sc->memlimit) 2420 end = sc->memlimit; 2421 } else { 2422 ok = 0; 2423 } 2424 } 2425 } 2426 } else if (!ok) { 2427 ok = 1; /* subtractive bridge: always ok */ 2428 #if 0 2429 if (pcib_is_nonprefetch_open(sc)) { 2430 if (start < sc->memlimit && end > sc->membase) 2431 start = sc->memlimit + 1; 2432 } 2433 if (pcib_is_prefetch_open(sc)) { 2434 if (start < sc->pmemlimit && end > sc->pmembase) 2435 start = sc->pmemlimit + 1; 2436 } 2437 #endif 2438 } 2439 if (end < start) { 2440 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2441 end, start); 2442 start = 0; 2443 end = 0; 2444 ok = 0; 2445 } 2446 if (!ok && bootverbose) 2447 device_printf(dev, 2448 "%s%srequested unsupported memory range %#jx-%#jx " 2449 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2450 name, suffix, start, end, 2451 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2452 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2453 if (!ok) 2454 return (NULL); 2455 if (bootverbose) 2456 device_printf(dev,"%s%srequested memory range " 2457 "0x%jx-0x%jx: good\n", 2458 name, suffix, start, end); 2459 break; 2460 2461 default: 2462 break; 2463 } 2464 /* 2465 * Bridge is OK decoding this resource, so pass it up. 2466 */ 2467 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2468 count, flags)); 2469 } 2470 #endif 2471 2472 /* 2473 * If ARI is enabled on this downstream port, translate the function number 2474 * to the non-ARI slot/function. The downstream port will convert it back in 2475 * hardware. If ARI is not enabled slot and func are not modified. 2476 */ 2477 static __inline void 2478 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2479 { 2480 struct pcib_softc *sc; 2481 int ari_func; 2482 2483 sc = device_get_softc(pcib); 2484 ari_func = *func; 2485 2486 if (sc->flags & PCIB_ENABLE_ARI) { 2487 KASSERT(*slot == 0, 2488 ("Non-zero slot number with ARI enabled!")); 2489 *slot = PCIE_ARI_SLOT(ari_func); 2490 *func = PCIE_ARI_FUNC(ari_func); 2491 } 2492 } 2493 2494 2495 static void 2496 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2497 { 2498 uint32_t ctl2; 2499 2500 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2501 ctl2 |= PCIEM_CTL2_ARI; 2502 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2503 2504 sc->flags |= PCIB_ENABLE_ARI; 2505 } 2506 2507 /* 2508 * PCIB interface. 2509 */ 2510 int 2511 pcib_maxslots(device_t dev) 2512 { 2513 return (PCI_SLOTMAX); 2514 } 2515 2516 static int 2517 pcib_ari_maxslots(device_t dev) 2518 { 2519 struct pcib_softc *sc; 2520 2521 sc = device_get_softc(dev); 2522 2523 if (sc->flags & PCIB_ENABLE_ARI) 2524 return (PCIE_ARI_SLOTMAX); 2525 else 2526 return (PCI_SLOTMAX); 2527 } 2528 2529 static int 2530 pcib_ari_maxfuncs(device_t dev) 2531 { 2532 struct pcib_softc *sc; 2533 2534 sc = device_get_softc(dev); 2535 2536 if (sc->flags & PCIB_ENABLE_ARI) 2537 return (PCIE_ARI_FUNCMAX); 2538 else 2539 return (PCI_FUNCMAX); 2540 } 2541 2542 static void 2543 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2544 int *func) 2545 { 2546 struct pcib_softc *sc; 2547 2548 sc = device_get_softc(pcib); 2549 2550 *bus = PCI_RID2BUS(rid); 2551 if (sc->flags & PCIB_ENABLE_ARI) { 2552 *slot = PCIE_ARI_RID2SLOT(rid); 2553 *func = PCIE_ARI_RID2FUNC(rid); 2554 } else { 2555 *slot = PCI_RID2SLOT(rid); 2556 *func = PCI_RID2FUNC(rid); 2557 } 2558 } 2559 2560 /* 2561 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2562 */ 2563 static uint32_t 2564 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2565 { 2566 #ifdef PCI_HP 2567 struct pcib_softc *sc; 2568 2569 sc = device_get_softc(dev); 2570 if (!pcib_present(sc)) { 2571 switch (width) { 2572 case 2: 2573 return (0xffff); 2574 case 1: 2575 return (0xff); 2576 default: 2577 return (0xffffffff); 2578 } 2579 } 2580 #endif 2581 pcib_xlate_ari(dev, b, &s, &f); 2582 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2583 f, reg, width)); 2584 } 2585 2586 static void 2587 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2588 { 2589 #ifdef PCI_HP 2590 struct pcib_softc *sc; 2591 2592 sc = device_get_softc(dev); 2593 if (!pcib_present(sc)) 2594 return; 2595 #endif 2596 pcib_xlate_ari(dev, b, &s, &f); 2597 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2598 reg, val, width); 2599 } 2600 2601 /* 2602 * Route an interrupt across a PCI bridge. 2603 */ 2604 int 2605 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2606 { 2607 device_t bus; 2608 int parent_intpin; 2609 int intnum; 2610 2611 /* 2612 * 2613 * The PCI standard defines a swizzle of the child-side device/intpin to 2614 * the parent-side intpin as follows. 2615 * 2616 * device = device on child bus 2617 * child_intpin = intpin on child bus slot (0-3) 2618 * parent_intpin = intpin on parent bus slot (0-3) 2619 * 2620 * parent_intpin = (device + child_intpin) % 4 2621 */ 2622 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2623 2624 /* 2625 * Our parent is a PCI bus. Its parent must export the pcib interface 2626 * which includes the ability to route interrupts. 2627 */ 2628 bus = device_get_parent(pcib); 2629 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2630 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2631 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2632 pci_get_slot(dev), 'A' + pin - 1, intnum); 2633 } 2634 return(intnum); 2635 } 2636 2637 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2638 int 2639 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2640 { 2641 struct pcib_softc *sc = device_get_softc(pcib); 2642 device_t bus; 2643 2644 if (sc->flags & PCIB_DISABLE_MSI) 2645 return (ENXIO); 2646 bus = device_get_parent(pcib); 2647 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2648 irqs)); 2649 } 2650 2651 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2652 int 2653 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2654 { 2655 device_t bus; 2656 2657 bus = device_get_parent(pcib); 2658 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2659 } 2660 2661 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2662 int 2663 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2664 { 2665 struct pcib_softc *sc = device_get_softc(pcib); 2666 device_t bus; 2667 2668 if (sc->flags & PCIB_DISABLE_MSIX) 2669 return (ENXIO); 2670 bus = device_get_parent(pcib); 2671 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2672 } 2673 2674 /* Pass request to release an MSI-X message up to the parent bridge. */ 2675 int 2676 pcib_release_msix(device_t pcib, device_t dev, int irq) 2677 { 2678 device_t bus; 2679 2680 bus = device_get_parent(pcib); 2681 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2682 } 2683 2684 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2685 int 2686 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2687 uint32_t *data) 2688 { 2689 device_t bus; 2690 int error; 2691 2692 bus = device_get_parent(pcib); 2693 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2694 if (error) 2695 return (error); 2696 2697 pci_ht_map_msi(pcib, *addr); 2698 return (0); 2699 } 2700 2701 /* Pass request for device power state up to parent bridge. */ 2702 int 2703 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2704 { 2705 device_t bus; 2706 2707 bus = device_get_parent(pcib); 2708 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2709 } 2710 2711 static int 2712 pcib_ari_enabled(device_t pcib) 2713 { 2714 struct pcib_softc *sc; 2715 2716 sc = device_get_softc(pcib); 2717 2718 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2719 } 2720 2721 static int 2722 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2723 uintptr_t *id) 2724 { 2725 struct pcib_softc *sc; 2726 device_t bus_dev; 2727 uint8_t bus, slot, func; 2728 2729 if (type != PCI_ID_RID) { 2730 bus_dev = device_get_parent(pcib); 2731 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2732 } 2733 2734 sc = device_get_softc(pcib); 2735 2736 if (sc->flags & PCIB_ENABLE_ARI) { 2737 bus = pci_get_bus(dev); 2738 func = pci_get_function(dev); 2739 2740 *id = (PCI_ARI_RID(bus, func)); 2741 } else { 2742 bus = pci_get_bus(dev); 2743 slot = pci_get_slot(dev); 2744 func = pci_get_function(dev); 2745 2746 *id = (PCI_RID(bus, slot, func)); 2747 } 2748 2749 return (0); 2750 } 2751 2752 /* 2753 * Check that the downstream port (pcib) and the endpoint device (dev) both 2754 * support ARI. If so, enable it and return 0, otherwise return an error. 2755 */ 2756 static int 2757 pcib_try_enable_ari(device_t pcib, device_t dev) 2758 { 2759 struct pcib_softc *sc; 2760 int error; 2761 uint32_t cap2; 2762 int ari_cap_off; 2763 uint32_t ari_ver; 2764 uint32_t pcie_pos; 2765 2766 sc = device_get_softc(pcib); 2767 2768 /* 2769 * ARI is controlled in a register in the PCIe capability structure. 2770 * If the downstream port does not have the PCIe capability structure 2771 * then it does not support ARI. 2772 */ 2773 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2774 if (error != 0) 2775 return (ENODEV); 2776 2777 /* Check that the PCIe port advertises ARI support. */ 2778 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2779 if (!(cap2 & PCIEM_CAP2_ARI)) 2780 return (ENODEV); 2781 2782 /* 2783 * Check that the endpoint device advertises ARI support via the ARI 2784 * extended capability structure. 2785 */ 2786 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2787 if (error != 0) 2788 return (ENODEV); 2789 2790 /* 2791 * Finally, check that the endpoint device supports the same version 2792 * of ARI that we do. 2793 */ 2794 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2795 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2796 if (bootverbose) 2797 device_printf(pcib, 2798 "Unsupported version of ARI (%d) detected\n", 2799 PCI_EXTCAP_VER(ari_ver)); 2800 2801 return (ENXIO); 2802 } 2803 2804 pcib_enable_ari(sc, pcie_pos); 2805 2806 return (0); 2807 } 2808