1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pci_private.h> 50 #include <dev/pci/pcib_private.h> 51 52 #include "pcib_if.h" 53 54 static int pcib_probe(device_t dev); 55 static int pcib_suspend(device_t dev); 56 static int pcib_resume(device_t dev); 57 static int pcib_power_for_sleep(device_t pcib, device_t dev, 58 int *pstate); 59 60 static device_method_t pcib_methods[] = { 61 /* Device interface */ 62 DEVMETHOD(device_probe, pcib_probe), 63 DEVMETHOD(device_attach, pcib_attach), 64 DEVMETHOD(device_detach, bus_generic_detach), 65 DEVMETHOD(device_shutdown, bus_generic_shutdown), 66 DEVMETHOD(device_suspend, pcib_suspend), 67 DEVMETHOD(device_resume, pcib_resume), 68 69 /* Bus interface */ 70 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 71 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 72 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 73 #ifdef NEW_PCIB 74 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 75 DEVMETHOD(bus_release_resource, pcib_release_resource), 76 #else 77 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 78 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 79 #endif 80 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 81 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 82 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 83 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 84 85 /* pcib interface */ 86 DEVMETHOD(pcib_maxslots, pcib_maxslots), 87 DEVMETHOD(pcib_read_config, pcib_read_config), 88 DEVMETHOD(pcib_write_config, pcib_write_config), 89 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 90 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 91 DEVMETHOD(pcib_release_msi, pcib_release_msi), 92 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 93 DEVMETHOD(pcib_release_msix, pcib_release_msix), 94 DEVMETHOD(pcib_map_msi, pcib_map_msi), 95 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 96 97 DEVMETHOD_END 98 }; 99 100 static devclass_t pcib_devclass; 101 102 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 103 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 104 105 #ifdef NEW_PCIB 106 /* 107 * XXX Todo: 108 * - properly handle the ISA enable bit. If it is set, we should change 109 * the behavior of the I/O window resource and rman to not allocate the 110 * blocked ranges (upper 768 bytes of each 1K in the first 64k of the 111 * I/O port address space). 112 */ 113 114 /* 115 * Is a resource from a child device sub-allocated from one of our 116 * resource managers? 117 */ 118 static int 119 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 120 { 121 122 switch (type) { 123 case SYS_RES_IOPORT: 124 return (rman_is_region_manager(r, &sc->io.rman)); 125 case SYS_RES_MEMORY: 126 /* Prefetchable resources may live in either memory rman. */ 127 if (rman_get_flags(r) & RF_PREFETCHABLE && 128 rman_is_region_manager(r, &sc->pmem.rman)) 129 return (1); 130 return (rman_is_region_manager(r, &sc->mem.rman)); 131 } 132 return (0); 133 } 134 135 static int 136 pcib_is_window_open(struct pcib_window *pw) 137 { 138 139 return (pw->valid && pw->base < pw->limit); 140 } 141 142 /* 143 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 144 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 145 * when allocating the resource windows and rely on the PCI bus driver 146 * to do this for us. 147 */ 148 static void 149 pcib_activate_window(struct pcib_softc *sc, int type) 150 { 151 152 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 153 } 154 155 static void 156 pcib_write_windows(struct pcib_softc *sc, int mask) 157 { 158 device_t dev; 159 uint32_t val; 160 161 dev = sc->dev; 162 if (sc->io.valid && mask & WIN_IO) { 163 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 164 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 165 pci_write_config(dev, PCIR_IOBASEH_1, 166 sc->io.base >> 16, 2); 167 pci_write_config(dev, PCIR_IOLIMITH_1, 168 sc->io.limit >> 16, 2); 169 } 170 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 171 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 172 } 173 174 if (mask & WIN_MEM) { 175 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 176 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 177 } 178 179 if (sc->pmem.valid && mask & WIN_PMEM) { 180 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 181 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 182 pci_write_config(dev, PCIR_PMBASEH_1, 183 sc->pmem.base >> 32, 4); 184 pci_write_config(dev, PCIR_PMLIMITH_1, 185 sc->pmem.limit >> 32, 4); 186 } 187 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 188 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 189 } 190 } 191 192 static void 193 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 194 int flags, pci_addr_t max_address) 195 { 196 char buf[64]; 197 int error, rid; 198 199 if (max_address != (u_long)max_address) 200 max_address = ~0ul; 201 w->rman.rm_start = 0; 202 w->rman.rm_end = max_address; 203 w->rman.rm_type = RMAN_ARRAY; 204 snprintf(buf, sizeof(buf), "%s %s window", 205 device_get_nameunit(sc->dev), w->name); 206 w->rman.rm_descr = strdup(buf, M_DEVBUF); 207 error = rman_init(&w->rman); 208 if (error) 209 panic("Failed to initialize %s %s rman", 210 device_get_nameunit(sc->dev), w->name); 211 212 if (!pcib_is_window_open(w)) 213 return; 214 215 if (w->base > max_address || w->limit > max_address) { 216 device_printf(sc->dev, 217 "initial %s window has too many bits, ignoring\n", w->name); 218 return; 219 } 220 rid = w->reg; 221 w->res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 222 w->limit - w->base + 1, flags); 223 if (w->res == NULL) { 224 device_printf(sc->dev, 225 "failed to allocate initial %s window: %#jx-%#jx\n", 226 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 227 w->base = max_address; 228 w->limit = 0; 229 pcib_write_windows(sc, w->mask); 230 return; 231 } 232 pcib_activate_window(sc, type); 233 234 error = rman_manage_region(&w->rman, rman_get_start(w->res), 235 rman_get_end(w->res)); 236 if (error) 237 panic("Failed to initialize rman with resource"); 238 } 239 240 /* 241 * Initialize I/O windows. 242 */ 243 static void 244 pcib_probe_windows(struct pcib_softc *sc) 245 { 246 pci_addr_t max; 247 device_t dev; 248 uint32_t val; 249 250 dev = sc->dev; 251 252 /* Determine if the I/O port window is implemented. */ 253 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 254 if (val == 0) { 255 /* 256 * If 'val' is zero, then only 16-bits of I/O space 257 * are supported. 258 */ 259 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 260 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 261 sc->io.valid = 1; 262 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 263 } 264 } else 265 sc->io.valid = 1; 266 267 /* Read the existing I/O port window. */ 268 if (sc->io.valid) { 269 sc->io.reg = PCIR_IOBASEL_1; 270 sc->io.step = 12; 271 sc->io.mask = WIN_IO; 272 sc->io.name = "I/O port"; 273 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 274 sc->io.base = PCI_PPBIOBASE( 275 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 276 sc->io.limit = PCI_PPBIOLIMIT( 277 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 278 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 279 max = 0xffffffff; 280 } else { 281 sc->io.base = PCI_PPBIOBASE(0, val); 282 sc->io.limit = PCI_PPBIOLIMIT(0, 283 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 284 max = 0xffff; 285 } 286 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 287 } 288 289 /* Read the existing memory window. */ 290 sc->mem.valid = 1; 291 sc->mem.reg = PCIR_MEMBASE_1; 292 sc->mem.step = 20; 293 sc->mem.mask = WIN_MEM; 294 sc->mem.name = "memory"; 295 sc->mem.base = PCI_PPBMEMBASE(0, 296 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 297 sc->mem.limit = PCI_PPBMEMLIMIT(0, 298 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 299 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 300 301 /* Determine if the prefetchable memory window is implemented. */ 302 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 303 if (val == 0) { 304 /* 305 * If 'val' is zero, then only 32-bits of memory space 306 * are supported. 307 */ 308 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 309 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 310 sc->pmem.valid = 1; 311 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 312 } 313 } else 314 sc->pmem.valid = 1; 315 316 /* Read the existing prefetchable memory window. */ 317 if (sc->pmem.valid) { 318 sc->pmem.reg = PCIR_PMBASEL_1; 319 sc->pmem.step = 20; 320 sc->pmem.mask = WIN_PMEM; 321 sc->pmem.name = "prefetch"; 322 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 323 sc->pmem.base = PCI_PPBMEMBASE( 324 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 325 sc->pmem.limit = PCI_PPBMEMLIMIT( 326 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 327 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 328 max = 0xffffffffffffffff; 329 } else { 330 sc->pmem.base = PCI_PPBMEMBASE(0, val); 331 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 332 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 333 max = 0xffffffff; 334 } 335 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 336 RF_PREFETCHABLE, max); 337 } 338 } 339 340 #else 341 342 /* 343 * Is the prefetch window open (eg, can we allocate memory in it?) 344 */ 345 static int 346 pcib_is_prefetch_open(struct pcib_softc *sc) 347 { 348 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 349 } 350 351 /* 352 * Is the nonprefetch window open (eg, can we allocate memory in it?) 353 */ 354 static int 355 pcib_is_nonprefetch_open(struct pcib_softc *sc) 356 { 357 return (sc->membase > 0 && sc->membase < sc->memlimit); 358 } 359 360 /* 361 * Is the io window open (eg, can we allocate ports in it?) 362 */ 363 static int 364 pcib_is_io_open(struct pcib_softc *sc) 365 { 366 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 367 } 368 369 /* 370 * Get current I/O decode. 371 */ 372 static void 373 pcib_get_io_decode(struct pcib_softc *sc) 374 { 375 device_t dev; 376 uint32_t iolow; 377 378 dev = sc->dev; 379 380 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 381 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 382 sc->iobase = PCI_PPBIOBASE( 383 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 384 else 385 sc->iobase = PCI_PPBIOBASE(0, iolow); 386 387 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 388 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 389 sc->iolimit = PCI_PPBIOLIMIT( 390 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 391 else 392 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 393 } 394 395 /* 396 * Get current memory decode. 397 */ 398 static void 399 pcib_get_mem_decode(struct pcib_softc *sc) 400 { 401 device_t dev; 402 pci_addr_t pmemlow; 403 404 dev = sc->dev; 405 406 sc->membase = PCI_PPBMEMBASE(0, 407 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 408 sc->memlimit = PCI_PPBMEMLIMIT(0, 409 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 410 411 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 412 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 413 sc->pmembase = PCI_PPBMEMBASE( 414 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 415 else 416 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 417 418 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 419 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 420 sc->pmemlimit = PCI_PPBMEMLIMIT( 421 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 422 else 423 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 424 } 425 426 /* 427 * Restore previous I/O decode. 428 */ 429 static void 430 pcib_set_io_decode(struct pcib_softc *sc) 431 { 432 device_t dev; 433 uint32_t iohi; 434 435 dev = sc->dev; 436 437 iohi = sc->iobase >> 16; 438 if (iohi > 0) 439 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 440 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 441 442 iohi = sc->iolimit >> 16; 443 if (iohi > 0) 444 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 445 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 446 } 447 448 /* 449 * Restore previous memory decode. 450 */ 451 static void 452 pcib_set_mem_decode(struct pcib_softc *sc) 453 { 454 device_t dev; 455 pci_addr_t pmemhi; 456 457 dev = sc->dev; 458 459 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 460 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 461 462 pmemhi = sc->pmembase >> 32; 463 if (pmemhi > 0) 464 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 465 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 466 467 pmemhi = sc->pmemlimit >> 32; 468 if (pmemhi > 0) 469 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 470 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 471 } 472 #endif 473 474 /* 475 * Get current bridge configuration. 476 */ 477 static void 478 pcib_cfg_save(struct pcib_softc *sc) 479 { 480 device_t dev; 481 482 dev = sc->dev; 483 484 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 485 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 486 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 487 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 488 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 489 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 490 #ifndef NEW_PCIB 491 if (sc->command & PCIM_CMD_PORTEN) 492 pcib_get_io_decode(sc); 493 if (sc->command & PCIM_CMD_MEMEN) 494 pcib_get_mem_decode(sc); 495 #endif 496 } 497 498 /* 499 * Restore previous bridge configuration. 500 */ 501 static void 502 pcib_cfg_restore(struct pcib_softc *sc) 503 { 504 device_t dev; 505 506 dev = sc->dev; 507 508 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 509 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 510 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 511 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 512 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 513 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 514 #ifdef NEW_PCIB 515 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 516 #else 517 if (sc->command & PCIM_CMD_PORTEN) 518 pcib_set_io_decode(sc); 519 if (sc->command & PCIM_CMD_MEMEN) 520 pcib_set_mem_decode(sc); 521 #endif 522 } 523 524 /* 525 * Generic device interface 526 */ 527 static int 528 pcib_probe(device_t dev) 529 { 530 if ((pci_get_class(dev) == PCIC_BRIDGE) && 531 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 532 device_set_desc(dev, "PCI-PCI bridge"); 533 return(-10000); 534 } 535 return(ENXIO); 536 } 537 538 void 539 pcib_attach_common(device_t dev) 540 { 541 struct pcib_softc *sc; 542 struct sysctl_ctx_list *sctx; 543 struct sysctl_oid *soid; 544 545 sc = device_get_softc(dev); 546 sc->dev = dev; 547 548 /* 549 * Get current bridge configuration. 550 */ 551 sc->domain = pci_get_domain(dev); 552 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 553 pcib_cfg_save(sc); 554 555 /* 556 * Setup sysctl reporting nodes 557 */ 558 sctx = device_get_sysctl_ctx(dev); 559 soid = device_get_sysctl_tree(dev); 560 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 561 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 562 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 563 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 564 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 565 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 566 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 567 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 568 569 /* 570 * Quirk handling. 571 */ 572 switch (pci_get_devid(dev)) { 573 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 574 { 575 uint8_t supbus; 576 577 supbus = pci_read_config(dev, 0x41, 1); 578 if (supbus != 0xff) { 579 sc->secbus = supbus + 1; 580 sc->subbus = supbus + 1; 581 } 582 break; 583 } 584 585 /* 586 * The i82380FB mobile docking controller is a PCI-PCI bridge, 587 * and it is a subtractive bridge. However, the ProgIf is wrong 588 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 589 * happen. There's also a Toshiba bridge that behaves this 590 * way. 591 */ 592 case 0x124b8086: /* Intel 82380FB Mobile */ 593 case 0x060513d7: /* Toshiba ???? */ 594 sc->flags |= PCIB_SUBTRACTIVE; 595 break; 596 597 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 598 case 0x00dd10de: 599 { 600 char *cp; 601 602 if ((cp = getenv("smbios.planar.maker")) == NULL) 603 break; 604 if (strncmp(cp, "Compal", 6) != 0) { 605 freeenv(cp); 606 break; 607 } 608 freeenv(cp); 609 if ((cp = getenv("smbios.planar.product")) == NULL) 610 break; 611 if (strncmp(cp, "08A0", 4) != 0) { 612 freeenv(cp); 613 break; 614 } 615 freeenv(cp); 616 if (sc->subbus < 0xa) { 617 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 618 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 619 } 620 break; 621 } 622 } 623 624 if (pci_msi_device_blacklisted(dev)) 625 sc->flags |= PCIB_DISABLE_MSI; 626 627 /* 628 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 629 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 630 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 631 * This means they act as if they were subtractively decoding 632 * bridges and pass all transactions. Mark them and real ProgIf 1 633 * parts as subtractive. 634 */ 635 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 636 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 637 sc->flags |= PCIB_SUBTRACTIVE; 638 639 #ifdef NEW_PCIB 640 pcib_probe_windows(sc); 641 #endif 642 if (bootverbose) { 643 device_printf(dev, " domain %d\n", sc->domain); 644 device_printf(dev, " secondary bus %d\n", sc->secbus); 645 device_printf(dev, " subordinate bus %d\n", sc->subbus); 646 #ifdef NEW_PCIB 647 if (pcib_is_window_open(&sc->io)) 648 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 649 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 650 if (pcib_is_window_open(&sc->mem)) 651 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 652 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 653 if (pcib_is_window_open(&sc->pmem)) 654 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 655 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 656 #else 657 if (pcib_is_io_open(sc)) 658 device_printf(dev, " I/O decode 0x%x-0x%x\n", 659 sc->iobase, sc->iolimit); 660 if (pcib_is_nonprefetch_open(sc)) 661 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 662 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 663 if (pcib_is_prefetch_open(sc)) 664 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 665 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 666 #endif 667 else 668 device_printf(dev, " no prefetched decode\n"); 669 if (sc->flags & PCIB_SUBTRACTIVE) 670 device_printf(dev, " Subtractively decoded bridge.\n"); 671 } 672 673 /* 674 * XXX If the secondary bus number is zero, we should assign a bus number 675 * since the BIOS hasn't, then initialise the bridge. A simple 676 * bus_alloc_resource with the a couple of busses seems like the right 677 * approach, but we don't know what busses the BIOS might have already 678 * assigned to other bridges on this bus that probe later than we do. 679 * 680 * If the subordinate bus number is less than the secondary bus number, 681 * we should pick a better value. One sensible alternative would be to 682 * pick 255; the only tradeoff here is that configuration transactions 683 * would be more widely routed than absolutely necessary. We could 684 * then do a walk of the tree later and fix it. 685 */ 686 687 /* 688 * Always enable busmastering on bridges so that transactions 689 * initiated on the secondary bus are passed through to the 690 * primary bus. 691 */ 692 pci_enable_busmaster(dev); 693 } 694 695 int 696 pcib_attach(device_t dev) 697 { 698 struct pcib_softc *sc; 699 device_t child; 700 701 pcib_attach_common(dev); 702 sc = device_get_softc(dev); 703 if (sc->secbus != 0) { 704 child = device_add_child(dev, "pci", sc->secbus); 705 if (child != NULL) 706 return(bus_generic_attach(dev)); 707 } 708 709 /* no secondary bus; we should have fixed this */ 710 return(0); 711 } 712 713 int 714 pcib_suspend(device_t dev) 715 { 716 device_t pcib; 717 int dstate, error; 718 719 pcib_cfg_save(device_get_softc(dev)); 720 error = bus_generic_suspend(dev); 721 if (error == 0 && pci_do_power_suspend) { 722 dstate = PCI_POWERSTATE_D3; 723 pcib = device_get_parent(device_get_parent(dev)); 724 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 725 pci_set_powerstate(dev, dstate); 726 } 727 return (error); 728 } 729 730 int 731 pcib_resume(device_t dev) 732 { 733 device_t pcib; 734 735 if (pci_do_power_resume) { 736 pcib = device_get_parent(device_get_parent(dev)); 737 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 738 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 739 } 740 pcib_cfg_restore(device_get_softc(dev)); 741 return (bus_generic_resume(dev)); 742 } 743 744 int 745 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 746 { 747 struct pcib_softc *sc = device_get_softc(dev); 748 749 switch (which) { 750 case PCIB_IVAR_DOMAIN: 751 *result = sc->domain; 752 return(0); 753 case PCIB_IVAR_BUS: 754 *result = sc->secbus; 755 return(0); 756 } 757 return(ENOENT); 758 } 759 760 int 761 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 762 { 763 struct pcib_softc *sc = device_get_softc(dev); 764 765 switch (which) { 766 case PCIB_IVAR_DOMAIN: 767 return(EINVAL); 768 case PCIB_IVAR_BUS: 769 sc->secbus = value; 770 return(0); 771 } 772 return(ENOENT); 773 } 774 775 #ifdef NEW_PCIB 776 /* 777 * Attempt to allocate a resource from the existing resources assigned 778 * to a window. 779 */ 780 static struct resource * 781 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 782 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 783 u_int flags) 784 { 785 struct resource *res; 786 787 if (!pcib_is_window_open(w)) 788 return (NULL); 789 790 res = rman_reserve_resource(&w->rman, start, end, count, 791 flags & ~RF_ACTIVE, child); 792 if (res == NULL) 793 return (NULL); 794 795 if (bootverbose) 796 device_printf(sc->dev, 797 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 798 w->name, rman_get_start(res), rman_get_end(res), *rid, 799 pcib_child_name(child)); 800 rman_set_rid(res, *rid); 801 802 /* 803 * If the resource should be active, pass that request up the 804 * tree. This assumes the parent drivers can handle 805 * activating sub-allocated resources. 806 */ 807 if (flags & RF_ACTIVE) { 808 if (bus_activate_resource(child, type, *rid, res) != 0) { 809 rman_release_resource(res); 810 return (NULL); 811 } 812 } 813 814 return (res); 815 } 816 817 /* 818 * Attempt to grow a window to make room for a given resource request. 819 * The 'step' parameter is log_2 of the desired I/O window's alignment. 820 */ 821 static int 822 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 823 u_long start, u_long end, u_long count, u_int flags) 824 { 825 u_long align, start_free, end_free, front, back, wmask; 826 int error, rid; 827 828 /* 829 * Clamp the desired resource range to the maximum address 830 * this window supports. Reject impossible requests. 831 */ 832 if (!w->valid) 833 return (EINVAL); 834 if (end > w->rman.rm_end) 835 end = w->rman.rm_end; 836 if (start + count - 1 > end || start + count < start) 837 return (EINVAL); 838 wmask = (1ul << w->step) - 1; 839 840 /* 841 * If there is no resource at all, just try to allocate enough 842 * aligned space for this resource. 843 */ 844 if (w->res == NULL) { 845 if (RF_ALIGNMENT(flags) < w->step) { 846 flags &= ~RF_ALIGNMENT_MASK; 847 flags |= RF_ALIGNMENT_LOG2(w->step); 848 } 849 start &= ~wmask; 850 end |= wmask; 851 count = roundup2(count, 1ul << w->step); 852 rid = w->reg; 853 w->res = bus_alloc_resource(sc->dev, type, &rid, start, end, 854 count, flags & ~RF_ACTIVE); 855 if (w->res == NULL) { 856 if (bootverbose) 857 device_printf(sc->dev, 858 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 859 w->name, start, end, count); 860 return (ENXIO); 861 } 862 if (bootverbose) 863 device_printf(sc->dev, 864 "allocated initial %s window of %#lx-%#lx\n", 865 w->name, rman_get_start(w->res), 866 rman_get_end(w->res)); 867 error = rman_manage_region(&w->rman, rman_get_start(w->res), 868 rman_get_end(w->res)); 869 if (error) { 870 if (bootverbose) 871 device_printf(sc->dev, 872 "failed to add initial %s window to rman\n", 873 w->name); 874 bus_release_resource(sc->dev, type, w->reg, w->res); 875 w->res = NULL; 876 return (error); 877 } 878 pcib_activate_window(sc, type); 879 goto updatewin; 880 } 881 882 /* 883 * See if growing the window would help. Compute the minimum 884 * amount of address space needed on both the front and back 885 * ends of the existing window to satisfy the allocation. 886 * 887 * For each end, build a candidate region adjusting for the 888 * required alignment, etc. If there is a free region at the 889 * edge of the window, grow from the inner edge of the free 890 * region. Otherwise grow from the window boundary. 891 * 892 * XXX: Special case: if w->res is completely empty and the 893 * request size is larger than w->res, we should find the 894 * optimal aligned buffer containing w->res and allocate that. 895 */ 896 if (bootverbose) 897 device_printf(sc->dev, 898 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 899 w->name, start, end, count); 900 align = 1ul << RF_ALIGNMENT(flags); 901 if (start < rman_get_start(w->res)) { 902 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 903 0 || start_free != rman_get_start(w->res)) 904 end_free = rman_get_start(w->res); 905 if (end_free > end) 906 end_free = end + 1; 907 908 /* Move end_free down until it is properly aligned. */ 909 end_free &= ~(align - 1); 910 end_free--; 911 front = end_free - (count - 1); 912 913 /* 914 * The resource would now be allocated at (front, 915 * end_free). Ensure that fits in the (start, end) 916 * bounds. end_free is checked above. If 'front' is 917 * ok, ensure it is properly aligned for this window. 918 * Also check for underflow. 919 */ 920 if (front >= start && front <= end_free) { 921 if (bootverbose) 922 printf("\tfront candidate range: %#lx-%#lx\n", 923 front, end_free); 924 front &= ~wmask; 925 front = rman_get_start(w->res) - front; 926 } else 927 front = 0; 928 } else 929 front = 0; 930 if (end > rman_get_end(w->res)) { 931 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 932 0 || end_free != rman_get_end(w->res)) 933 start_free = rman_get_end(w->res) + 1; 934 if (start_free < start) 935 start_free = start; 936 937 /* Move start_free up until it is properly aligned. */ 938 start_free = roundup2(start_free, align); 939 back = start_free + count - 1; 940 941 /* 942 * The resource would now be allocated at (start_free, 943 * back). Ensure that fits in the (start, end) 944 * bounds. start_free is checked above. If 'back' is 945 * ok, ensure it is properly aligned for this window. 946 * Also check for overflow. 947 */ 948 if (back <= end && start_free <= back) { 949 if (bootverbose) 950 printf("\tback candidate range: %#lx-%#lx\n", 951 start_free, back); 952 back |= wmask; 953 back -= rman_get_end(w->res); 954 } else 955 back = 0; 956 } else 957 back = 0; 958 959 /* 960 * Try to allocate the smallest needed region first. 961 * If that fails, fall back to the other region. 962 */ 963 error = ENOSPC; 964 while (front != 0 || back != 0) { 965 if (front != 0 && (front <= back || back == 0)) { 966 error = bus_adjust_resource(sc->dev, type, w->res, 967 rman_get_start(w->res) - front, 968 rman_get_end(w->res)); 969 if (error == 0) 970 break; 971 front = 0; 972 } else { 973 error = bus_adjust_resource(sc->dev, type, w->res, 974 rman_get_start(w->res), 975 rman_get_end(w->res) + back); 976 if (error == 0) 977 break; 978 back = 0; 979 } 980 } 981 982 if (error) 983 return (error); 984 if (bootverbose) 985 device_printf(sc->dev, "grew %s window to %#lx-%#lx\n", 986 w->name, rman_get_start(w->res), rman_get_end(w->res)); 987 988 /* Add the newly allocated region to the resource manager. */ 989 if (w->base != rman_get_start(w->res)) { 990 KASSERT(w->limit == rman_get_end(w->res), ("both ends moved")); 991 error = rman_manage_region(&w->rman, rman_get_start(w->res), 992 w->base - 1); 993 } else { 994 KASSERT(w->limit != rman_get_end(w->res), 995 ("neither end moved")); 996 error = rman_manage_region(&w->rman, w->limit + 1, 997 rman_get_end(w->res)); 998 } 999 if (error) { 1000 if (bootverbose) 1001 device_printf(sc->dev, 1002 "failed to expand %s resource manager\n", w->name); 1003 bus_adjust_resource(sc->dev, type, w->res, w->base, w->limit); 1004 return (error); 1005 } 1006 1007 updatewin: 1008 /* Save the new window. */ 1009 w->base = rman_get_start(w->res); 1010 w->limit = rman_get_end(w->res); 1011 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 1012 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 1013 pcib_write_windows(sc, w->mask); 1014 return (0); 1015 } 1016 1017 /* 1018 * We have to trap resource allocation requests and ensure that the bridge 1019 * is set up to, or capable of handling them. 1020 */ 1021 struct resource * 1022 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1023 u_long start, u_long end, u_long count, u_int flags) 1024 { 1025 struct pcib_softc *sc; 1026 struct resource *r; 1027 1028 sc = device_get_softc(dev); 1029 1030 /* 1031 * VGA resources are decoded iff the VGA enable bit is set in 1032 * the bridge control register. VGA resources do not fall into 1033 * the resource windows and are passed up to the parent. 1034 */ 1035 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1036 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1037 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1038 return (bus_generic_alloc_resource(dev, child, type, 1039 rid, start, end, count, flags)); 1040 else 1041 return (NULL); 1042 } 1043 1044 switch (type) { 1045 case SYS_RES_IOPORT: 1046 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1047 end, count, flags); 1048 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1049 break; 1050 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1051 flags) == 0) 1052 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1053 rid, start, end, count, flags); 1054 break; 1055 case SYS_RES_MEMORY: 1056 /* 1057 * For prefetchable resources, prefer the prefetchable 1058 * memory window, but fall back to the regular memory 1059 * window if that fails. Try both windows before 1060 * attempting to grow a window in case the firmware 1061 * has used a range in the regular memory window to 1062 * map a prefetchable BAR. 1063 */ 1064 if (flags & RF_PREFETCHABLE) { 1065 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1066 rid, start, end, count, flags); 1067 if (r != NULL) 1068 break; 1069 } 1070 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1071 start, end, count, flags); 1072 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1073 break; 1074 if (flags & RF_PREFETCHABLE) { 1075 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1076 count, flags) == 0) { 1077 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1078 type, rid, start, end, count, flags); 1079 if (r != NULL) 1080 break; 1081 } 1082 } 1083 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1084 flags & ~RF_PREFETCHABLE) == 0) 1085 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1086 rid, start, end, count, flags); 1087 break; 1088 default: 1089 return (bus_generic_alloc_resource(dev, child, type, rid, 1090 start, end, count, flags)); 1091 } 1092 1093 /* 1094 * If attempts to suballocate from the window fail but this is a 1095 * subtractive bridge, pass the request up the tree. 1096 */ 1097 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1098 return (bus_generic_alloc_resource(dev, child, type, rid, 1099 start, end, count, flags)); 1100 return (r); 1101 } 1102 1103 int 1104 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1105 u_long start, u_long end) 1106 { 1107 struct pcib_softc *sc; 1108 1109 sc = device_get_softc(bus); 1110 if (pcib_is_resource_managed(sc, type, r)) 1111 return (rman_adjust_resource(r, start, end)); 1112 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1113 } 1114 1115 int 1116 pcib_release_resource(device_t dev, device_t child, int type, int rid, 1117 struct resource *r) 1118 { 1119 struct pcib_softc *sc; 1120 int error; 1121 1122 sc = device_get_softc(dev); 1123 if (pcib_is_resource_managed(sc, type, r)) { 1124 if (rman_get_flags(r) & RF_ACTIVE) { 1125 error = bus_deactivate_resource(child, type, rid, r); 1126 if (error) 1127 return (error); 1128 } 1129 return (rman_release_resource(r)); 1130 } 1131 return (bus_generic_release_resource(dev, child, type, rid, r)); 1132 } 1133 #else 1134 /* 1135 * We have to trap resource allocation requests and ensure that the bridge 1136 * is set up to, or capable of handling them. 1137 */ 1138 struct resource * 1139 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1140 u_long start, u_long end, u_long count, u_int flags) 1141 { 1142 struct pcib_softc *sc = device_get_softc(dev); 1143 const char *name, *suffix; 1144 int ok; 1145 1146 /* 1147 * Fail the allocation for this range if it's not supported. 1148 */ 1149 name = device_get_nameunit(child); 1150 if (name == NULL) { 1151 name = ""; 1152 suffix = ""; 1153 } else 1154 suffix = " "; 1155 switch (type) { 1156 case SYS_RES_IOPORT: 1157 ok = 0; 1158 if (!pcib_is_io_open(sc)) 1159 break; 1160 ok = (start >= sc->iobase && end <= sc->iolimit); 1161 1162 /* 1163 * Make sure we allow access to VGA I/O addresses when the 1164 * bridge has the "VGA Enable" bit set. 1165 */ 1166 if (!ok && pci_is_vga_ioport_range(start, end)) 1167 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1168 1169 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1170 if (!ok) { 1171 if (start < sc->iobase) 1172 start = sc->iobase; 1173 if (end > sc->iolimit) 1174 end = sc->iolimit; 1175 if (start < end) 1176 ok = 1; 1177 } 1178 } else { 1179 ok = 1; 1180 #if 0 1181 /* 1182 * If we overlap with the subtractive range, then 1183 * pick the upper range to use. 1184 */ 1185 if (start < sc->iolimit && end > sc->iobase) 1186 start = sc->iolimit + 1; 1187 #endif 1188 } 1189 if (end < start) { 1190 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1191 end, start); 1192 start = 0; 1193 end = 0; 1194 ok = 0; 1195 } 1196 if (!ok) { 1197 device_printf(dev, "%s%srequested unsupported I/O " 1198 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1199 name, suffix, start, end, sc->iobase, sc->iolimit); 1200 return (NULL); 1201 } 1202 if (bootverbose) 1203 device_printf(dev, 1204 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1205 name, suffix, start, end); 1206 break; 1207 1208 case SYS_RES_MEMORY: 1209 ok = 0; 1210 if (pcib_is_nonprefetch_open(sc)) 1211 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1212 if (pcib_is_prefetch_open(sc)) 1213 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1214 1215 /* 1216 * Make sure we allow access to VGA memory addresses when the 1217 * bridge has the "VGA Enable" bit set. 1218 */ 1219 if (!ok && pci_is_vga_memory_range(start, end)) 1220 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1221 1222 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1223 if (!ok) { 1224 ok = 1; 1225 if (flags & RF_PREFETCHABLE) { 1226 if (pcib_is_prefetch_open(sc)) { 1227 if (start < sc->pmembase) 1228 start = sc->pmembase; 1229 if (end > sc->pmemlimit) 1230 end = sc->pmemlimit; 1231 } else { 1232 ok = 0; 1233 } 1234 } else { /* non-prefetchable */ 1235 if (pcib_is_nonprefetch_open(sc)) { 1236 if (start < sc->membase) 1237 start = sc->membase; 1238 if (end > sc->memlimit) 1239 end = sc->memlimit; 1240 } else { 1241 ok = 0; 1242 } 1243 } 1244 } 1245 } else if (!ok) { 1246 ok = 1; /* subtractive bridge: always ok */ 1247 #if 0 1248 if (pcib_is_nonprefetch_open(sc)) { 1249 if (start < sc->memlimit && end > sc->membase) 1250 start = sc->memlimit + 1; 1251 } 1252 if (pcib_is_prefetch_open(sc)) { 1253 if (start < sc->pmemlimit && end > sc->pmembase) 1254 start = sc->pmemlimit + 1; 1255 } 1256 #endif 1257 } 1258 if (end < start) { 1259 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1260 end, start); 1261 start = 0; 1262 end = 0; 1263 ok = 0; 1264 } 1265 if (!ok && bootverbose) 1266 device_printf(dev, 1267 "%s%srequested unsupported memory range %#lx-%#lx " 1268 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1269 name, suffix, start, end, 1270 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1271 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1272 if (!ok) 1273 return (NULL); 1274 if (bootverbose) 1275 device_printf(dev,"%s%srequested memory range " 1276 "0x%lx-0x%lx: good\n", 1277 name, suffix, start, end); 1278 break; 1279 1280 default: 1281 break; 1282 } 1283 /* 1284 * Bridge is OK decoding this resource, so pass it up. 1285 */ 1286 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1287 count, flags)); 1288 } 1289 #endif 1290 1291 /* 1292 * PCIB interface. 1293 */ 1294 int 1295 pcib_maxslots(device_t dev) 1296 { 1297 return(PCI_SLOTMAX); 1298 } 1299 1300 /* 1301 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1302 */ 1303 uint32_t 1304 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1305 { 1306 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 1307 } 1308 1309 void 1310 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1311 { 1312 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 1313 } 1314 1315 /* 1316 * Route an interrupt across a PCI bridge. 1317 */ 1318 int 1319 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1320 { 1321 device_t bus; 1322 int parent_intpin; 1323 int intnum; 1324 1325 /* 1326 * 1327 * The PCI standard defines a swizzle of the child-side device/intpin to 1328 * the parent-side intpin as follows. 1329 * 1330 * device = device on child bus 1331 * child_intpin = intpin on child bus slot (0-3) 1332 * parent_intpin = intpin on parent bus slot (0-3) 1333 * 1334 * parent_intpin = (device + child_intpin) % 4 1335 */ 1336 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1337 1338 /* 1339 * Our parent is a PCI bus. Its parent must export the pcib interface 1340 * which includes the ability to route interrupts. 1341 */ 1342 bus = device_get_parent(pcib); 1343 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1344 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1345 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1346 pci_get_slot(dev), 'A' + pin - 1, intnum); 1347 } 1348 return(intnum); 1349 } 1350 1351 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1352 int 1353 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1354 { 1355 struct pcib_softc *sc = device_get_softc(pcib); 1356 device_t bus; 1357 1358 if (sc->flags & PCIB_DISABLE_MSI) 1359 return (ENXIO); 1360 bus = device_get_parent(pcib); 1361 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1362 irqs)); 1363 } 1364 1365 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1366 int 1367 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1368 { 1369 device_t bus; 1370 1371 bus = device_get_parent(pcib); 1372 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1373 } 1374 1375 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 1376 int 1377 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1378 { 1379 struct pcib_softc *sc = device_get_softc(pcib); 1380 device_t bus; 1381 1382 if (sc->flags & PCIB_DISABLE_MSI) 1383 return (ENXIO); 1384 bus = device_get_parent(pcib); 1385 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1386 } 1387 1388 /* Pass request to release an MSI-X message up to the parent bridge. */ 1389 int 1390 pcib_release_msix(device_t pcib, device_t dev, int irq) 1391 { 1392 device_t bus; 1393 1394 bus = device_get_parent(pcib); 1395 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1396 } 1397 1398 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 1399 int 1400 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 1401 uint32_t *data) 1402 { 1403 device_t bus; 1404 int error; 1405 1406 bus = device_get_parent(pcib); 1407 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 1408 if (error) 1409 return (error); 1410 1411 pci_ht_map_msi(pcib, *addr); 1412 return (0); 1413 } 1414 1415 /* Pass request for device power state up to parent bridge. */ 1416 int 1417 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 1418 { 1419 device_t bus; 1420 1421 bus = device_get_parent(pcib); 1422 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 1423 } 1424