1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pci_private.h> 50 #include <dev/pci/pcib_private.h> 51 52 #include "pcib_if.h" 53 54 static int pcib_probe(device_t dev); 55 static int pcib_suspend(device_t dev); 56 static int pcib_resume(device_t dev); 57 static int pcib_power_for_sleep(device_t pcib, device_t dev, 58 int *pstate); 59 static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev); 60 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 61 u_int f, u_int reg, int width); 62 static void pcib_write_config(device_t dev, u_int b, u_int s, 63 u_int f, u_int reg, uint32_t val, int width); 64 static int pcib_ari_maxslots(device_t dev); 65 static int pcib_ari_maxfuncs(device_t dev); 66 static int pcib_try_enable_ari(device_t pcib, device_t dev); 67 static int pcib_ari_enabled(device_t pcib); 68 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 69 int *bus, int *slot, int *func); 70 71 static device_method_t pcib_methods[] = { 72 /* Device interface */ 73 DEVMETHOD(device_probe, pcib_probe), 74 DEVMETHOD(device_attach, pcib_attach), 75 DEVMETHOD(device_detach, bus_generic_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 DEVMETHOD(device_suspend, pcib_suspend), 78 DEVMETHOD(device_resume, pcib_resume), 79 80 /* Bus interface */ 81 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 82 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 83 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 84 #ifdef NEW_PCIB 85 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 86 DEVMETHOD(bus_release_resource, pcib_release_resource), 87 #else 88 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 89 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 90 #endif 91 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 92 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 93 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 94 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 95 96 /* pcib interface */ 97 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 98 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 99 DEVMETHOD(pcib_read_config, pcib_read_config), 100 DEVMETHOD(pcib_write_config, pcib_write_config), 101 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 102 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 103 DEVMETHOD(pcib_release_msi, pcib_release_msi), 104 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 105 DEVMETHOD(pcib_release_msix, pcib_release_msix), 106 DEVMETHOD(pcib_map_msi, pcib_map_msi), 107 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 108 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid), 109 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 110 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 111 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 112 113 DEVMETHOD_END 114 }; 115 116 static devclass_t pcib_devclass; 117 118 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 119 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 120 121 #ifdef NEW_PCIB 122 SYSCTL_DECL(_hw_pci); 123 124 static int pci_clear_pcib; 125 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 126 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 127 128 /* 129 * Is a resource from a child device sub-allocated from one of our 130 * resource managers? 131 */ 132 static int 133 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 134 { 135 136 switch (type) { 137 #ifdef PCI_RES_BUS 138 case PCI_RES_BUS: 139 return (rman_is_region_manager(r, &sc->bus.rman)); 140 #endif 141 case SYS_RES_IOPORT: 142 return (rman_is_region_manager(r, &sc->io.rman)); 143 case SYS_RES_MEMORY: 144 /* Prefetchable resources may live in either memory rman. */ 145 if (rman_get_flags(r) & RF_PREFETCHABLE && 146 rman_is_region_manager(r, &sc->pmem.rman)) 147 return (1); 148 return (rman_is_region_manager(r, &sc->mem.rman)); 149 } 150 return (0); 151 } 152 153 static int 154 pcib_is_window_open(struct pcib_window *pw) 155 { 156 157 return (pw->valid && pw->base < pw->limit); 158 } 159 160 /* 161 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 162 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 163 * when allocating the resource windows and rely on the PCI bus driver 164 * to do this for us. 165 */ 166 static void 167 pcib_activate_window(struct pcib_softc *sc, int type) 168 { 169 170 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 171 } 172 173 static void 174 pcib_write_windows(struct pcib_softc *sc, int mask) 175 { 176 device_t dev; 177 uint32_t val; 178 179 dev = sc->dev; 180 if (sc->io.valid && mask & WIN_IO) { 181 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 182 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 183 pci_write_config(dev, PCIR_IOBASEH_1, 184 sc->io.base >> 16, 2); 185 pci_write_config(dev, PCIR_IOLIMITH_1, 186 sc->io.limit >> 16, 2); 187 } 188 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 189 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 190 } 191 192 if (mask & WIN_MEM) { 193 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 194 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 195 } 196 197 if (sc->pmem.valid && mask & WIN_PMEM) { 198 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 199 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 200 pci_write_config(dev, PCIR_PMBASEH_1, 201 sc->pmem.base >> 32, 4); 202 pci_write_config(dev, PCIR_PMLIMITH_1, 203 sc->pmem.limit >> 32, 4); 204 } 205 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 206 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 207 } 208 } 209 210 /* 211 * This is used to reject I/O port allocations that conflict with an 212 * ISA alias range. 213 */ 214 static int 215 pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count) 216 { 217 u_long next_alias; 218 219 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 220 return (0); 221 222 /* Only check fixed ranges for overlap. */ 223 if (start + count - 1 != end) 224 return (0); 225 226 /* ISA aliases are only in the lower 64KB of I/O space. */ 227 if (start >= 65536) 228 return (0); 229 230 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 231 if (start < 0x100) 232 goto alias; 233 234 /* 235 * If the start address is an alias, the range is an alias. 236 * Otherwise, compute the start of the next alias range and 237 * check if it is before the end of the candidate range. 238 */ 239 if ((start & 0x300) != 0) 240 goto alias; 241 next_alias = (start & ~0x3fful) | 0x100; 242 if (next_alias <= end) 243 goto alias; 244 return (0); 245 246 alias: 247 if (bootverbose) 248 device_printf(sc->dev, 249 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start, 250 end); 251 return (1); 252 } 253 254 static void 255 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 256 int count) 257 { 258 struct resource **newarray; 259 int error, i; 260 261 newarray = malloc(sizeof(struct resource *) * (w->count + count), 262 M_DEVBUF, M_WAITOK); 263 if (w->res != NULL) 264 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 265 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 266 free(w->res, M_DEVBUF); 267 w->res = newarray; 268 w->count += count; 269 270 for (i = 0; i < count; i++) { 271 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 272 rman_get_end(res[i])); 273 if (error) 274 panic("Failed to add resource to rman"); 275 } 276 } 277 278 typedef void (nonisa_callback)(u_long start, u_long end, void *arg); 279 280 static void 281 pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb, 282 void *arg) 283 { 284 u_long next_end; 285 286 /* 287 * If start is within an ISA alias range, move up to the start 288 * of the next non-alias range. As a special case, addresses 289 * in the range 0x000 - 0x0ff should also be skipped since 290 * those are used for various system I/O devices in ISA 291 * systems. 292 */ 293 if (start <= 65535) { 294 if (start < 0x100 || (start & 0x300) != 0) { 295 start &= ~0x3ff; 296 start += 0x400; 297 } 298 } 299 300 /* ISA aliases are only in the lower 64KB of I/O space. */ 301 while (start <= MIN(end, 65535)) { 302 next_end = MIN(start | 0xff, end); 303 cb(start, next_end, arg); 304 start += 0x400; 305 } 306 307 if (start <= end) 308 cb(start, end, arg); 309 } 310 311 static void 312 count_ranges(u_long start, u_long end, void *arg) 313 { 314 int *countp; 315 316 countp = arg; 317 (*countp)++; 318 } 319 320 struct alloc_state { 321 struct resource **res; 322 struct pcib_softc *sc; 323 int count, error; 324 }; 325 326 static void 327 alloc_ranges(u_long start, u_long end, void *arg) 328 { 329 struct alloc_state *as; 330 struct pcib_window *w; 331 int rid; 332 333 as = arg; 334 if (as->error != 0) 335 return; 336 337 w = &as->sc->io; 338 rid = w->reg; 339 if (bootverbose) 340 device_printf(as->sc->dev, 341 "allocating non-ISA range %#lx-%#lx\n", start, end); 342 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 343 &rid, start, end, end - start + 1, 0); 344 if (as->res[as->count] == NULL) 345 as->error = ENXIO; 346 else 347 as->count++; 348 } 349 350 static int 351 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end) 352 { 353 struct alloc_state as; 354 int i, new_count; 355 356 /* First, see how many ranges we need. */ 357 new_count = 0; 358 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 359 360 /* Second, allocate the ranges. */ 361 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 362 M_WAITOK); 363 as.sc = sc; 364 as.count = 0; 365 as.error = 0; 366 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 367 if (as.error != 0) { 368 for (i = 0; i < as.count; i++) 369 bus_release_resource(sc->dev, SYS_RES_IOPORT, 370 sc->io.reg, as.res[i]); 371 free(as.res, M_DEVBUF); 372 return (as.error); 373 } 374 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 375 376 /* Third, add the ranges to the window. */ 377 pcib_add_window_resources(&sc->io, as.res, as.count); 378 free(as.res, M_DEVBUF); 379 return (0); 380 } 381 382 static void 383 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 384 int flags, pci_addr_t max_address) 385 { 386 struct resource *res; 387 char buf[64]; 388 int error, rid; 389 390 if (max_address != (u_long)max_address) 391 max_address = ~0ul; 392 w->rman.rm_start = 0; 393 w->rman.rm_end = max_address; 394 w->rman.rm_type = RMAN_ARRAY; 395 snprintf(buf, sizeof(buf), "%s %s window", 396 device_get_nameunit(sc->dev), w->name); 397 w->rman.rm_descr = strdup(buf, M_DEVBUF); 398 error = rman_init(&w->rman); 399 if (error) 400 panic("Failed to initialize %s %s rman", 401 device_get_nameunit(sc->dev), w->name); 402 403 if (!pcib_is_window_open(w)) 404 return; 405 406 if (w->base > max_address || w->limit > max_address) { 407 device_printf(sc->dev, 408 "initial %s window has too many bits, ignoring\n", w->name); 409 return; 410 } 411 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 412 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 413 else { 414 rid = w->reg; 415 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 416 w->limit - w->base + 1, flags); 417 if (res != NULL) 418 pcib_add_window_resources(w, &res, 1); 419 } 420 if (w->res == NULL) { 421 device_printf(sc->dev, 422 "failed to allocate initial %s window: %#jx-%#jx\n", 423 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 424 w->base = max_address; 425 w->limit = 0; 426 pcib_write_windows(sc, w->mask); 427 return; 428 } 429 pcib_activate_window(sc, type); 430 } 431 432 /* 433 * Initialize I/O windows. 434 */ 435 static void 436 pcib_probe_windows(struct pcib_softc *sc) 437 { 438 pci_addr_t max; 439 device_t dev; 440 uint32_t val; 441 442 dev = sc->dev; 443 444 if (pci_clear_pcib) { 445 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 446 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 447 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 448 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 449 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 450 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 451 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 452 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 453 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 454 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 455 } 456 457 /* Determine if the I/O port window is implemented. */ 458 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 459 if (val == 0) { 460 /* 461 * If 'val' is zero, then only 16-bits of I/O space 462 * are supported. 463 */ 464 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 465 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 466 sc->io.valid = 1; 467 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 468 } 469 } else 470 sc->io.valid = 1; 471 472 /* Read the existing I/O port window. */ 473 if (sc->io.valid) { 474 sc->io.reg = PCIR_IOBASEL_1; 475 sc->io.step = 12; 476 sc->io.mask = WIN_IO; 477 sc->io.name = "I/O port"; 478 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 479 sc->io.base = PCI_PPBIOBASE( 480 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 481 sc->io.limit = PCI_PPBIOLIMIT( 482 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 483 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 484 max = 0xffffffff; 485 } else { 486 sc->io.base = PCI_PPBIOBASE(0, val); 487 sc->io.limit = PCI_PPBIOLIMIT(0, 488 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 489 max = 0xffff; 490 } 491 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 492 } 493 494 /* Read the existing memory window. */ 495 sc->mem.valid = 1; 496 sc->mem.reg = PCIR_MEMBASE_1; 497 sc->mem.step = 20; 498 sc->mem.mask = WIN_MEM; 499 sc->mem.name = "memory"; 500 sc->mem.base = PCI_PPBMEMBASE(0, 501 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 502 sc->mem.limit = PCI_PPBMEMLIMIT(0, 503 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 504 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 505 506 /* Determine if the prefetchable memory window is implemented. */ 507 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 508 if (val == 0) { 509 /* 510 * If 'val' is zero, then only 32-bits of memory space 511 * are supported. 512 */ 513 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 514 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 515 sc->pmem.valid = 1; 516 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 517 } 518 } else 519 sc->pmem.valid = 1; 520 521 /* Read the existing prefetchable memory window. */ 522 if (sc->pmem.valid) { 523 sc->pmem.reg = PCIR_PMBASEL_1; 524 sc->pmem.step = 20; 525 sc->pmem.mask = WIN_PMEM; 526 sc->pmem.name = "prefetch"; 527 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 528 sc->pmem.base = PCI_PPBMEMBASE( 529 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 530 sc->pmem.limit = PCI_PPBMEMLIMIT( 531 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 532 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 533 max = 0xffffffffffffffff; 534 } else { 535 sc->pmem.base = PCI_PPBMEMBASE(0, val); 536 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 537 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 538 max = 0xffffffff; 539 } 540 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 541 RF_PREFETCHABLE, max); 542 } 543 } 544 545 #ifdef PCI_RES_BUS 546 /* 547 * Allocate a suitable secondary bus for this bridge if needed and 548 * initialize the resource manager for the secondary bus range. Note 549 * that the minimum count is a desired value and this may allocate a 550 * smaller range. 551 */ 552 void 553 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 554 { 555 char buf[64]; 556 int error, rid, sec_reg; 557 558 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 559 case PCIM_HDRTYPE_BRIDGE: 560 sec_reg = PCIR_SECBUS_1; 561 bus->sub_reg = PCIR_SUBBUS_1; 562 break; 563 case PCIM_HDRTYPE_CARDBUS: 564 sec_reg = PCIR_SECBUS_2; 565 bus->sub_reg = PCIR_SUBBUS_2; 566 break; 567 default: 568 panic("not a PCI bridge"); 569 } 570 bus->sec = pci_read_config(dev, sec_reg, 1); 571 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 572 bus->dev = dev; 573 bus->rman.rm_start = 0; 574 bus->rman.rm_end = PCI_BUSMAX; 575 bus->rman.rm_type = RMAN_ARRAY; 576 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 577 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 578 error = rman_init(&bus->rman); 579 if (error) 580 panic("Failed to initialize %s bus number rman", 581 device_get_nameunit(dev)); 582 583 /* 584 * Allocate a bus range. This will return an existing bus range 585 * if one exists, or a new bus range if one does not. 586 */ 587 rid = 0; 588 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul, 589 min_count, 0); 590 if (bus->res == NULL) { 591 /* 592 * Fall back to just allocating a range of a single bus 593 * number. 594 */ 595 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul, 596 1, 0); 597 } else if (rman_get_size(bus->res) < min_count) 598 /* 599 * Attempt to grow the existing range to satisfy the 600 * minimum desired count. 601 */ 602 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 603 rman_get_start(bus->res), rman_get_start(bus->res) + 604 min_count - 1); 605 606 /* 607 * Add the initial resource to the rman. 608 */ 609 if (bus->res != NULL) { 610 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 611 rman_get_end(bus->res)); 612 if (error) 613 panic("Failed to add resource to rman"); 614 bus->sec = rman_get_start(bus->res); 615 bus->sub = rman_get_end(bus->res); 616 } 617 } 618 619 static struct resource * 620 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 621 u_long start, u_long end, u_long count, u_int flags) 622 { 623 struct resource *res; 624 625 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 626 child); 627 if (res == NULL) 628 return (NULL); 629 630 if (bootverbose) 631 device_printf(bus->dev, 632 "allocated bus range (%lu-%lu) for rid %d of %s\n", 633 rman_get_start(res), rman_get_end(res), *rid, 634 pcib_child_name(child)); 635 rman_set_rid(res, *rid); 636 return (res); 637 } 638 639 /* 640 * Attempt to grow the secondary bus range. This is much simpler than 641 * for I/O windows as the range can only be grown by increasing 642 * subbus. 643 */ 644 static int 645 pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end) 646 { 647 u_long old_end; 648 int error; 649 650 old_end = rman_get_end(bus->res); 651 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 652 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 653 rman_get_start(bus->res), new_end); 654 if (error) 655 return (error); 656 if (bootverbose) 657 device_printf(bus->dev, "grew bus range to %lu-%lu\n", 658 rman_get_start(bus->res), rman_get_end(bus->res)); 659 error = rman_manage_region(&bus->rman, old_end + 1, 660 rman_get_end(bus->res)); 661 if (error) 662 panic("Failed to add resource to rman"); 663 bus->sub = rman_get_end(bus->res); 664 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 665 return (0); 666 } 667 668 struct resource * 669 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 670 u_long start, u_long end, u_long count, u_int flags) 671 { 672 struct resource *res; 673 u_long start_free, end_free, new_end; 674 675 /* 676 * First, see if the request can be satisified by the existing 677 * bus range. 678 */ 679 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 680 if (res != NULL) 681 return (res); 682 683 /* 684 * Figure out a range to grow the bus range. First, find the 685 * first bus number after the last allocated bus in the rman and 686 * enforce that as a minimum starting point for the range. 687 */ 688 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 689 end_free != bus->sub) 690 start_free = bus->sub + 1; 691 if (start_free < start) 692 start_free = start; 693 new_end = start_free + count - 1; 694 695 /* 696 * See if this new range would satisfy the request if it 697 * succeeds. 698 */ 699 if (new_end > end) 700 return (NULL); 701 702 /* Finally, attempt to grow the existing resource. */ 703 if (bootverbose) { 704 device_printf(bus->dev, 705 "attempting to grow bus range for %lu buses\n", count); 706 printf("\tback candidate range: %lu-%lu\n", start_free, 707 new_end); 708 } 709 if (pcib_grow_subbus(bus, new_end) == 0) 710 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 711 flags)); 712 return (NULL); 713 } 714 #endif 715 716 #else 717 718 /* 719 * Is the prefetch window open (eg, can we allocate memory in it?) 720 */ 721 static int 722 pcib_is_prefetch_open(struct pcib_softc *sc) 723 { 724 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 725 } 726 727 /* 728 * Is the nonprefetch window open (eg, can we allocate memory in it?) 729 */ 730 static int 731 pcib_is_nonprefetch_open(struct pcib_softc *sc) 732 { 733 return (sc->membase > 0 && sc->membase < sc->memlimit); 734 } 735 736 /* 737 * Is the io window open (eg, can we allocate ports in it?) 738 */ 739 static int 740 pcib_is_io_open(struct pcib_softc *sc) 741 { 742 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 743 } 744 745 /* 746 * Get current I/O decode. 747 */ 748 static void 749 pcib_get_io_decode(struct pcib_softc *sc) 750 { 751 device_t dev; 752 uint32_t iolow; 753 754 dev = sc->dev; 755 756 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 757 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 758 sc->iobase = PCI_PPBIOBASE( 759 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 760 else 761 sc->iobase = PCI_PPBIOBASE(0, iolow); 762 763 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 764 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 765 sc->iolimit = PCI_PPBIOLIMIT( 766 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 767 else 768 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 769 } 770 771 /* 772 * Get current memory decode. 773 */ 774 static void 775 pcib_get_mem_decode(struct pcib_softc *sc) 776 { 777 device_t dev; 778 pci_addr_t pmemlow; 779 780 dev = sc->dev; 781 782 sc->membase = PCI_PPBMEMBASE(0, 783 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 784 sc->memlimit = PCI_PPBMEMLIMIT(0, 785 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 786 787 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 788 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 789 sc->pmembase = PCI_PPBMEMBASE( 790 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 791 else 792 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 793 794 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 795 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 796 sc->pmemlimit = PCI_PPBMEMLIMIT( 797 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 798 else 799 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 800 } 801 802 /* 803 * Restore previous I/O decode. 804 */ 805 static void 806 pcib_set_io_decode(struct pcib_softc *sc) 807 { 808 device_t dev; 809 uint32_t iohi; 810 811 dev = sc->dev; 812 813 iohi = sc->iobase >> 16; 814 if (iohi > 0) 815 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 816 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 817 818 iohi = sc->iolimit >> 16; 819 if (iohi > 0) 820 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 821 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 822 } 823 824 /* 825 * Restore previous memory decode. 826 */ 827 static void 828 pcib_set_mem_decode(struct pcib_softc *sc) 829 { 830 device_t dev; 831 pci_addr_t pmemhi; 832 833 dev = sc->dev; 834 835 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 836 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 837 838 pmemhi = sc->pmembase >> 32; 839 if (pmemhi > 0) 840 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 841 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 842 843 pmemhi = sc->pmemlimit >> 32; 844 if (pmemhi > 0) 845 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 846 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 847 } 848 #endif 849 850 /* 851 * Get current bridge configuration. 852 */ 853 static void 854 pcib_cfg_save(struct pcib_softc *sc) 855 { 856 #ifndef NEW_PCIB 857 device_t dev; 858 uint16_t command; 859 860 dev = sc->dev; 861 862 command = pci_read_config(dev, PCIR_COMMAND, 2); 863 if (command & PCIM_CMD_PORTEN) 864 pcib_get_io_decode(sc); 865 if (command & PCIM_CMD_MEMEN) 866 pcib_get_mem_decode(sc); 867 #endif 868 } 869 870 /* 871 * Restore previous bridge configuration. 872 */ 873 static void 874 pcib_cfg_restore(struct pcib_softc *sc) 875 { 876 device_t dev; 877 #ifndef NEW_PCIB 878 uint16_t command; 879 #endif 880 dev = sc->dev; 881 882 #ifdef NEW_PCIB 883 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 884 #else 885 command = pci_read_config(dev, PCIR_COMMAND, 2); 886 if (command & PCIM_CMD_PORTEN) 887 pcib_set_io_decode(sc); 888 if (command & PCIM_CMD_MEMEN) 889 pcib_set_mem_decode(sc); 890 #endif 891 } 892 893 /* 894 * Generic device interface 895 */ 896 static int 897 pcib_probe(device_t dev) 898 { 899 if ((pci_get_class(dev) == PCIC_BRIDGE) && 900 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 901 device_set_desc(dev, "PCI-PCI bridge"); 902 return(-10000); 903 } 904 return(ENXIO); 905 } 906 907 void 908 pcib_attach_common(device_t dev) 909 { 910 struct pcib_softc *sc; 911 struct sysctl_ctx_list *sctx; 912 struct sysctl_oid *soid; 913 int comma; 914 915 sc = device_get_softc(dev); 916 sc->dev = dev; 917 918 /* 919 * Get current bridge configuration. 920 */ 921 sc->domain = pci_get_domain(dev); 922 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 923 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 924 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 925 #endif 926 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 927 pcib_cfg_save(sc); 928 929 /* 930 * The primary bus register should always be the bus of the 931 * parent. 932 */ 933 sc->pribus = pci_get_bus(dev); 934 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 935 936 /* 937 * Setup sysctl reporting nodes 938 */ 939 sctx = device_get_sysctl_ctx(dev); 940 soid = device_get_sysctl_tree(dev); 941 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 942 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 943 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 944 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 945 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 946 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 947 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 948 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 949 950 /* 951 * Quirk handling. 952 */ 953 switch (pci_get_devid(dev)) { 954 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 955 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 956 { 957 uint8_t supbus; 958 959 supbus = pci_read_config(dev, 0x41, 1); 960 if (supbus != 0xff) { 961 sc->bus.sec = supbus + 1; 962 sc->bus.sub = supbus + 1; 963 } 964 break; 965 } 966 #endif 967 968 /* 969 * The i82380FB mobile docking controller is a PCI-PCI bridge, 970 * and it is a subtractive bridge. However, the ProgIf is wrong 971 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 972 * happen. There's also a Toshiba bridge that behaves this 973 * way. 974 */ 975 case 0x124b8086: /* Intel 82380FB Mobile */ 976 case 0x060513d7: /* Toshiba ???? */ 977 sc->flags |= PCIB_SUBTRACTIVE; 978 break; 979 980 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 981 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 982 case 0x00dd10de: 983 { 984 char *cp; 985 986 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 987 break; 988 if (strncmp(cp, "Compal", 6) != 0) { 989 freeenv(cp); 990 break; 991 } 992 freeenv(cp); 993 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 994 break; 995 if (strncmp(cp, "08A0", 4) != 0) { 996 freeenv(cp); 997 break; 998 } 999 freeenv(cp); 1000 if (sc->bus.sub < 0xa) { 1001 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1002 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1003 } 1004 break; 1005 } 1006 #endif 1007 } 1008 1009 if (pci_msi_device_blacklisted(dev)) 1010 sc->flags |= PCIB_DISABLE_MSI; 1011 1012 if (pci_msix_device_blacklisted(dev)) 1013 sc->flags |= PCIB_DISABLE_MSIX; 1014 1015 /* 1016 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1017 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1018 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1019 * This means they act as if they were subtractively decoding 1020 * bridges and pass all transactions. Mark them and real ProgIf 1 1021 * parts as subtractive. 1022 */ 1023 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1024 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1025 sc->flags |= PCIB_SUBTRACTIVE; 1026 1027 #ifdef NEW_PCIB 1028 #ifdef PCI_RES_BUS 1029 pcib_setup_secbus(dev, &sc->bus, 1); 1030 #endif 1031 pcib_probe_windows(sc); 1032 #endif 1033 if (bootverbose) { 1034 device_printf(dev, " domain %d\n", sc->domain); 1035 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1036 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1037 #ifdef NEW_PCIB 1038 if (pcib_is_window_open(&sc->io)) 1039 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1040 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1041 if (pcib_is_window_open(&sc->mem)) 1042 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1043 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1044 if (pcib_is_window_open(&sc->pmem)) 1045 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1046 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1047 #else 1048 if (pcib_is_io_open(sc)) 1049 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1050 sc->iobase, sc->iolimit); 1051 if (pcib_is_nonprefetch_open(sc)) 1052 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1053 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1054 if (pcib_is_prefetch_open(sc)) 1055 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1056 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1057 #endif 1058 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1059 sc->flags & PCIB_SUBTRACTIVE) { 1060 device_printf(dev, " special decode "); 1061 comma = 0; 1062 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1063 printf("ISA"); 1064 comma = 1; 1065 } 1066 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1067 printf("%sVGA", comma ? ", " : ""); 1068 comma = 1; 1069 } 1070 if (sc->flags & PCIB_SUBTRACTIVE) 1071 printf("%ssubtractive", comma ? ", " : ""); 1072 printf("\n"); 1073 } 1074 } 1075 1076 /* 1077 * Always enable busmastering on bridges so that transactions 1078 * initiated on the secondary bus are passed through to the 1079 * primary bus. 1080 */ 1081 pci_enable_busmaster(dev); 1082 } 1083 1084 int 1085 pcib_attach(device_t dev) 1086 { 1087 struct pcib_softc *sc; 1088 device_t child; 1089 1090 pcib_attach_common(dev); 1091 sc = device_get_softc(dev); 1092 if (sc->bus.sec != 0) { 1093 child = device_add_child(dev, "pci", sc->bus.sec); 1094 if (child != NULL) 1095 return(bus_generic_attach(dev)); 1096 } 1097 1098 /* no secondary bus; we should have fixed this */ 1099 return(0); 1100 } 1101 1102 int 1103 pcib_suspend(device_t dev) 1104 { 1105 1106 pcib_cfg_save(device_get_softc(dev)); 1107 return (bus_generic_suspend(dev)); 1108 } 1109 1110 int 1111 pcib_resume(device_t dev) 1112 { 1113 1114 pcib_cfg_restore(device_get_softc(dev)); 1115 return (bus_generic_resume(dev)); 1116 } 1117 1118 int 1119 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1120 { 1121 struct pcib_softc *sc = device_get_softc(dev); 1122 1123 switch (which) { 1124 case PCIB_IVAR_DOMAIN: 1125 *result = sc->domain; 1126 return(0); 1127 case PCIB_IVAR_BUS: 1128 *result = sc->bus.sec; 1129 return(0); 1130 } 1131 return(ENOENT); 1132 } 1133 1134 int 1135 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1136 { 1137 1138 switch (which) { 1139 case PCIB_IVAR_DOMAIN: 1140 return(EINVAL); 1141 case PCIB_IVAR_BUS: 1142 return(EINVAL); 1143 } 1144 return(ENOENT); 1145 } 1146 1147 #ifdef NEW_PCIB 1148 /* 1149 * Attempt to allocate a resource from the existing resources assigned 1150 * to a window. 1151 */ 1152 static struct resource * 1153 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1154 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 1155 u_int flags) 1156 { 1157 struct resource *res; 1158 1159 if (!pcib_is_window_open(w)) 1160 return (NULL); 1161 1162 res = rman_reserve_resource(&w->rman, start, end, count, 1163 flags & ~RF_ACTIVE, child); 1164 if (res == NULL) 1165 return (NULL); 1166 1167 if (bootverbose) 1168 device_printf(sc->dev, 1169 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 1170 w->name, rman_get_start(res), rman_get_end(res), *rid, 1171 pcib_child_name(child)); 1172 rman_set_rid(res, *rid); 1173 1174 /* 1175 * If the resource should be active, pass that request up the 1176 * tree. This assumes the parent drivers can handle 1177 * activating sub-allocated resources. 1178 */ 1179 if (flags & RF_ACTIVE) { 1180 if (bus_activate_resource(child, type, *rid, res) != 0) { 1181 rman_release_resource(res); 1182 return (NULL); 1183 } 1184 } 1185 1186 return (res); 1187 } 1188 1189 /* Allocate a fresh resource range for an unconfigured window. */ 1190 static int 1191 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1192 u_long start, u_long end, u_long count, u_int flags) 1193 { 1194 struct resource *res; 1195 u_long base, limit, wmask; 1196 int rid; 1197 1198 /* 1199 * If this is an I/O window on a bridge with ISA enable set 1200 * and the start address is below 64k, then try to allocate an 1201 * initial window of 0x1000 bytes long starting at address 1202 * 0xf000 and walking down. Note that if the original request 1203 * was larger than the non-aliased range size of 0x100 our 1204 * caller would have raised the start address up to 64k 1205 * already. 1206 */ 1207 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1208 start < 65536) { 1209 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1210 limit = base + 0xfff; 1211 1212 /* 1213 * Skip ranges that wouldn't work for the 1214 * original request. Note that the actual 1215 * window that overlaps are the non-alias 1216 * ranges within [base, limit], so this isn't 1217 * quite a simple comparison. 1218 */ 1219 if (start + count > limit - 0x400) 1220 continue; 1221 if (base == 0) { 1222 /* 1223 * The first open region for the window at 1224 * 0 is 0x400-0x4ff. 1225 */ 1226 if (end - count + 1 < 0x400) 1227 continue; 1228 } else { 1229 if (end - count + 1 < base) 1230 continue; 1231 } 1232 1233 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1234 w->base = base; 1235 w->limit = limit; 1236 return (0); 1237 } 1238 } 1239 return (ENOSPC); 1240 } 1241 1242 wmask = (1ul << w->step) - 1; 1243 if (RF_ALIGNMENT(flags) < w->step) { 1244 flags &= ~RF_ALIGNMENT_MASK; 1245 flags |= RF_ALIGNMENT_LOG2(w->step); 1246 } 1247 start &= ~wmask; 1248 end |= wmask; 1249 count = roundup2(count, 1ul << w->step); 1250 rid = w->reg; 1251 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1252 flags & ~RF_ACTIVE); 1253 if (res == NULL) 1254 return (ENOSPC); 1255 pcib_add_window_resources(w, &res, 1); 1256 pcib_activate_window(sc, type); 1257 w->base = rman_get_start(res); 1258 w->limit = rman_get_end(res); 1259 return (0); 1260 } 1261 1262 /* Try to expand an existing window to the requested base and limit. */ 1263 static int 1264 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1265 u_long base, u_long limit) 1266 { 1267 struct resource *res; 1268 int error, i, force_64k_base; 1269 1270 KASSERT(base <= w->base && limit >= w->limit, 1271 ("attempting to shrink window")); 1272 1273 /* 1274 * XXX: pcib_grow_window() doesn't try to do this anyway and 1275 * the error handling for all the edge cases would be tedious. 1276 */ 1277 KASSERT(limit == w->limit || base == w->base, 1278 ("attempting to grow both ends of a window")); 1279 1280 /* 1281 * Yet more special handling for requests to expand an I/O 1282 * window behind an ISA-enabled bridge. Since I/O windows 1283 * have to grow in 0x1000 increments and the end of the 0xffff 1284 * range is an alias, growing a window below 64k will always 1285 * result in allocating new resources and never adjusting an 1286 * existing resource. 1287 */ 1288 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1289 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1290 KASSERT(limit == w->limit || limit <= 65535, 1291 ("attempting to grow both ends across 64k ISA alias")); 1292 1293 if (base != w->base) 1294 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1295 else 1296 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1297 limit); 1298 if (error == 0) { 1299 w->base = base; 1300 w->limit = limit; 1301 } 1302 return (error); 1303 } 1304 1305 /* 1306 * Find the existing resource to adjust. Usually there is only one, 1307 * but for an ISA-enabled bridge we might be growing the I/O window 1308 * above 64k and need to find the existing resource that maps all 1309 * of the area above 64k. 1310 */ 1311 for (i = 0; i < w->count; i++) { 1312 if (rman_get_end(w->res[i]) == w->limit) 1313 break; 1314 } 1315 KASSERT(i != w->count, ("did not find existing resource")); 1316 res = w->res[i]; 1317 1318 /* 1319 * Usually the resource we found should match the window's 1320 * existing range. The one exception is the ISA-enabled case 1321 * mentioned above in which case the resource should start at 1322 * 64k. 1323 */ 1324 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1325 w->base <= 65535) { 1326 KASSERT(rman_get_start(res) == 65536, 1327 ("existing resource mismatch")); 1328 force_64k_base = 1; 1329 } else { 1330 KASSERT(w->base == rman_get_start(res), 1331 ("existing resource mismatch")); 1332 force_64k_base = 0; 1333 } 1334 1335 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1336 rman_get_start(res) : base, limit); 1337 if (error) 1338 return (error); 1339 1340 /* Add the newly allocated region to the resource manager. */ 1341 if (w->base != base) { 1342 error = rman_manage_region(&w->rman, base, w->base - 1); 1343 w->base = base; 1344 } else { 1345 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1346 w->limit = limit; 1347 } 1348 if (error) { 1349 if (bootverbose) 1350 device_printf(sc->dev, 1351 "failed to expand %s resource manager\n", w->name); 1352 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1353 rman_get_start(res) : w->base, w->limit); 1354 } 1355 return (error); 1356 } 1357 1358 /* 1359 * Attempt to grow a window to make room for a given resource request. 1360 */ 1361 static int 1362 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1363 u_long start, u_long end, u_long count, u_int flags) 1364 { 1365 u_long align, start_free, end_free, front, back, wmask; 1366 int error; 1367 1368 /* 1369 * Clamp the desired resource range to the maximum address 1370 * this window supports. Reject impossible requests. 1371 * 1372 * For I/O port requests behind a bridge with the ISA enable 1373 * bit set, force large allocations to start above 64k. 1374 */ 1375 if (!w->valid) 1376 return (EINVAL); 1377 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1378 start < 65536) 1379 start = 65536; 1380 if (end > w->rman.rm_end) 1381 end = w->rman.rm_end; 1382 if (start + count - 1 > end || start + count < start) 1383 return (EINVAL); 1384 wmask = (1ul << w->step) - 1; 1385 1386 /* 1387 * If there is no resource at all, just try to allocate enough 1388 * aligned space for this resource. 1389 */ 1390 if (w->res == NULL) { 1391 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1392 flags); 1393 if (error) { 1394 if (bootverbose) 1395 device_printf(sc->dev, 1396 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 1397 w->name, start, end, count); 1398 return (error); 1399 } 1400 if (bootverbose) 1401 device_printf(sc->dev, 1402 "allocated initial %s window of %#jx-%#jx\n", 1403 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1404 goto updatewin; 1405 } 1406 1407 /* 1408 * See if growing the window would help. Compute the minimum 1409 * amount of address space needed on both the front and back 1410 * ends of the existing window to satisfy the allocation. 1411 * 1412 * For each end, build a candidate region adjusting for the 1413 * required alignment, etc. If there is a free region at the 1414 * edge of the window, grow from the inner edge of the free 1415 * region. Otherwise grow from the window boundary. 1416 * 1417 * Growing an I/O window below 64k for a bridge with the ISA 1418 * enable bit doesn't require any special magic as the step 1419 * size of an I/O window (1k) always includes multiple 1420 * non-alias ranges when it is grown in either direction. 1421 * 1422 * XXX: Special case: if w->res is completely empty and the 1423 * request size is larger than w->res, we should find the 1424 * optimal aligned buffer containing w->res and allocate that. 1425 */ 1426 if (bootverbose) 1427 device_printf(sc->dev, 1428 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 1429 w->name, start, end, count); 1430 align = 1ul << RF_ALIGNMENT(flags); 1431 if (start < w->base) { 1432 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1433 0 || start_free != w->base) 1434 end_free = w->base; 1435 if (end_free > end) 1436 end_free = end + 1; 1437 1438 /* Move end_free down until it is properly aligned. */ 1439 end_free &= ~(align - 1); 1440 end_free--; 1441 front = end_free - (count - 1); 1442 1443 /* 1444 * The resource would now be allocated at (front, 1445 * end_free). Ensure that fits in the (start, end) 1446 * bounds. end_free is checked above. If 'front' is 1447 * ok, ensure it is properly aligned for this window. 1448 * Also check for underflow. 1449 */ 1450 if (front >= start && front <= end_free) { 1451 if (bootverbose) 1452 printf("\tfront candidate range: %#lx-%#lx\n", 1453 front, end_free); 1454 front &= ~wmask; 1455 front = w->base - front; 1456 } else 1457 front = 0; 1458 } else 1459 front = 0; 1460 if (end > w->limit) { 1461 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1462 0 || end_free != w->limit) 1463 start_free = w->limit + 1; 1464 if (start_free < start) 1465 start_free = start; 1466 1467 /* Move start_free up until it is properly aligned. */ 1468 start_free = roundup2(start_free, align); 1469 back = start_free + count - 1; 1470 1471 /* 1472 * The resource would now be allocated at (start_free, 1473 * back). Ensure that fits in the (start, end) 1474 * bounds. start_free is checked above. If 'back' is 1475 * ok, ensure it is properly aligned for this window. 1476 * Also check for overflow. 1477 */ 1478 if (back <= end && start_free <= back) { 1479 if (bootverbose) 1480 printf("\tback candidate range: %#lx-%#lx\n", 1481 start_free, back); 1482 back |= wmask; 1483 back -= w->limit; 1484 } else 1485 back = 0; 1486 } else 1487 back = 0; 1488 1489 /* 1490 * Try to allocate the smallest needed region first. 1491 * If that fails, fall back to the other region. 1492 */ 1493 error = ENOSPC; 1494 while (front != 0 || back != 0) { 1495 if (front != 0 && (front <= back || back == 0)) { 1496 error = pcib_expand_window(sc, w, type, w->base - front, 1497 w->limit); 1498 if (error == 0) 1499 break; 1500 front = 0; 1501 } else { 1502 error = pcib_expand_window(sc, w, type, w->base, 1503 w->limit + back); 1504 if (error == 0) 1505 break; 1506 back = 0; 1507 } 1508 } 1509 1510 if (error) 1511 return (error); 1512 if (bootverbose) 1513 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 1514 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1515 1516 updatewin: 1517 /* Write the new window. */ 1518 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 1519 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 1520 pcib_write_windows(sc, w->mask); 1521 return (0); 1522 } 1523 1524 /* 1525 * We have to trap resource allocation requests and ensure that the bridge 1526 * is set up to, or capable of handling them. 1527 */ 1528 struct resource * 1529 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1530 u_long start, u_long end, u_long count, u_int flags) 1531 { 1532 struct pcib_softc *sc; 1533 struct resource *r; 1534 1535 sc = device_get_softc(dev); 1536 1537 /* 1538 * VGA resources are decoded iff the VGA enable bit is set in 1539 * the bridge control register. VGA resources do not fall into 1540 * the resource windows and are passed up to the parent. 1541 */ 1542 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1543 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1544 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1545 return (bus_generic_alloc_resource(dev, child, type, 1546 rid, start, end, count, flags)); 1547 else 1548 return (NULL); 1549 } 1550 1551 switch (type) { 1552 #ifdef PCI_RES_BUS 1553 case PCI_RES_BUS: 1554 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 1555 count, flags)); 1556 #endif 1557 case SYS_RES_IOPORT: 1558 if (pcib_is_isa_range(sc, start, end, count)) 1559 return (NULL); 1560 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1561 end, count, flags); 1562 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1563 break; 1564 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1565 flags) == 0) 1566 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1567 rid, start, end, count, flags); 1568 break; 1569 case SYS_RES_MEMORY: 1570 /* 1571 * For prefetchable resources, prefer the prefetchable 1572 * memory window, but fall back to the regular memory 1573 * window if that fails. Try both windows before 1574 * attempting to grow a window in case the firmware 1575 * has used a range in the regular memory window to 1576 * map a prefetchable BAR. 1577 */ 1578 if (flags & RF_PREFETCHABLE) { 1579 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1580 rid, start, end, count, flags); 1581 if (r != NULL) 1582 break; 1583 } 1584 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1585 start, end, count, flags); 1586 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1587 break; 1588 if (flags & RF_PREFETCHABLE) { 1589 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1590 count, flags) == 0) { 1591 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1592 type, rid, start, end, count, flags); 1593 if (r != NULL) 1594 break; 1595 } 1596 } 1597 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1598 flags & ~RF_PREFETCHABLE) == 0) 1599 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1600 rid, start, end, count, flags); 1601 break; 1602 default: 1603 return (bus_generic_alloc_resource(dev, child, type, rid, 1604 start, end, count, flags)); 1605 } 1606 1607 /* 1608 * If attempts to suballocate from the window fail but this is a 1609 * subtractive bridge, pass the request up the tree. 1610 */ 1611 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1612 return (bus_generic_alloc_resource(dev, child, type, rid, 1613 start, end, count, flags)); 1614 return (r); 1615 } 1616 1617 int 1618 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1619 u_long start, u_long end) 1620 { 1621 struct pcib_softc *sc; 1622 1623 sc = device_get_softc(bus); 1624 if (pcib_is_resource_managed(sc, type, r)) 1625 return (rman_adjust_resource(r, start, end)); 1626 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1627 } 1628 1629 int 1630 pcib_release_resource(device_t dev, device_t child, int type, int rid, 1631 struct resource *r) 1632 { 1633 struct pcib_softc *sc; 1634 int error; 1635 1636 sc = device_get_softc(dev); 1637 if (pcib_is_resource_managed(sc, type, r)) { 1638 if (rman_get_flags(r) & RF_ACTIVE) { 1639 error = bus_deactivate_resource(child, type, rid, r); 1640 if (error) 1641 return (error); 1642 } 1643 return (rman_release_resource(r)); 1644 } 1645 return (bus_generic_release_resource(dev, child, type, rid, r)); 1646 } 1647 #else 1648 /* 1649 * We have to trap resource allocation requests and ensure that the bridge 1650 * is set up to, or capable of handling them. 1651 */ 1652 struct resource * 1653 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1654 u_long start, u_long end, u_long count, u_int flags) 1655 { 1656 struct pcib_softc *sc = device_get_softc(dev); 1657 const char *name, *suffix; 1658 int ok; 1659 1660 /* 1661 * Fail the allocation for this range if it's not supported. 1662 */ 1663 name = device_get_nameunit(child); 1664 if (name == NULL) { 1665 name = ""; 1666 suffix = ""; 1667 } else 1668 suffix = " "; 1669 switch (type) { 1670 case SYS_RES_IOPORT: 1671 ok = 0; 1672 if (!pcib_is_io_open(sc)) 1673 break; 1674 ok = (start >= sc->iobase && end <= sc->iolimit); 1675 1676 /* 1677 * Make sure we allow access to VGA I/O addresses when the 1678 * bridge has the "VGA Enable" bit set. 1679 */ 1680 if (!ok && pci_is_vga_ioport_range(start, end)) 1681 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1682 1683 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1684 if (!ok) { 1685 if (start < sc->iobase) 1686 start = sc->iobase; 1687 if (end > sc->iolimit) 1688 end = sc->iolimit; 1689 if (start < end) 1690 ok = 1; 1691 } 1692 } else { 1693 ok = 1; 1694 #if 0 1695 /* 1696 * If we overlap with the subtractive range, then 1697 * pick the upper range to use. 1698 */ 1699 if (start < sc->iolimit && end > sc->iobase) 1700 start = sc->iolimit + 1; 1701 #endif 1702 } 1703 if (end < start) { 1704 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1705 end, start); 1706 start = 0; 1707 end = 0; 1708 ok = 0; 1709 } 1710 if (!ok) { 1711 device_printf(dev, "%s%srequested unsupported I/O " 1712 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1713 name, suffix, start, end, sc->iobase, sc->iolimit); 1714 return (NULL); 1715 } 1716 if (bootverbose) 1717 device_printf(dev, 1718 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1719 name, suffix, start, end); 1720 break; 1721 1722 case SYS_RES_MEMORY: 1723 ok = 0; 1724 if (pcib_is_nonprefetch_open(sc)) 1725 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1726 if (pcib_is_prefetch_open(sc)) 1727 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1728 1729 /* 1730 * Make sure we allow access to VGA memory addresses when the 1731 * bridge has the "VGA Enable" bit set. 1732 */ 1733 if (!ok && pci_is_vga_memory_range(start, end)) 1734 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1735 1736 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1737 if (!ok) { 1738 ok = 1; 1739 if (flags & RF_PREFETCHABLE) { 1740 if (pcib_is_prefetch_open(sc)) { 1741 if (start < sc->pmembase) 1742 start = sc->pmembase; 1743 if (end > sc->pmemlimit) 1744 end = sc->pmemlimit; 1745 } else { 1746 ok = 0; 1747 } 1748 } else { /* non-prefetchable */ 1749 if (pcib_is_nonprefetch_open(sc)) { 1750 if (start < sc->membase) 1751 start = sc->membase; 1752 if (end > sc->memlimit) 1753 end = sc->memlimit; 1754 } else { 1755 ok = 0; 1756 } 1757 } 1758 } 1759 } else if (!ok) { 1760 ok = 1; /* subtractive bridge: always ok */ 1761 #if 0 1762 if (pcib_is_nonprefetch_open(sc)) { 1763 if (start < sc->memlimit && end > sc->membase) 1764 start = sc->memlimit + 1; 1765 } 1766 if (pcib_is_prefetch_open(sc)) { 1767 if (start < sc->pmemlimit && end > sc->pmembase) 1768 start = sc->pmemlimit + 1; 1769 } 1770 #endif 1771 } 1772 if (end < start) { 1773 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1774 end, start); 1775 start = 0; 1776 end = 0; 1777 ok = 0; 1778 } 1779 if (!ok && bootverbose) 1780 device_printf(dev, 1781 "%s%srequested unsupported memory range %#lx-%#lx " 1782 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1783 name, suffix, start, end, 1784 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1785 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1786 if (!ok) 1787 return (NULL); 1788 if (bootverbose) 1789 device_printf(dev,"%s%srequested memory range " 1790 "0x%lx-0x%lx: good\n", 1791 name, suffix, start, end); 1792 break; 1793 1794 default: 1795 break; 1796 } 1797 /* 1798 * Bridge is OK decoding this resource, so pass it up. 1799 */ 1800 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1801 count, flags)); 1802 } 1803 #endif 1804 1805 /* 1806 * If ARI is enabled on this downstream port, translate the function number 1807 * to the non-ARI slot/function. The downstream port will convert it back in 1808 * hardware. If ARI is not enabled slot and func are not modified. 1809 */ 1810 static __inline void 1811 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 1812 { 1813 struct pcib_softc *sc; 1814 int ari_func; 1815 1816 sc = device_get_softc(pcib); 1817 ari_func = *func; 1818 1819 if (sc->flags & PCIB_ENABLE_ARI) { 1820 KASSERT(*slot == 0, 1821 ("Non-zero slot number with ARI enabled!")); 1822 *slot = PCIE_ARI_SLOT(ari_func); 1823 *func = PCIE_ARI_FUNC(ari_func); 1824 } 1825 } 1826 1827 1828 static void 1829 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 1830 { 1831 uint32_t ctl2; 1832 1833 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 1834 ctl2 |= PCIEM_CTL2_ARI; 1835 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 1836 1837 sc->flags |= PCIB_ENABLE_ARI; 1838 } 1839 1840 /* 1841 * PCIB interface. 1842 */ 1843 int 1844 pcib_maxslots(device_t dev) 1845 { 1846 return (PCI_SLOTMAX); 1847 } 1848 1849 static int 1850 pcib_ari_maxslots(device_t dev) 1851 { 1852 struct pcib_softc *sc; 1853 1854 sc = device_get_softc(dev); 1855 1856 if (sc->flags & PCIB_ENABLE_ARI) 1857 return (PCIE_ARI_SLOTMAX); 1858 else 1859 return (PCI_SLOTMAX); 1860 } 1861 1862 static int 1863 pcib_ari_maxfuncs(device_t dev) 1864 { 1865 struct pcib_softc *sc; 1866 1867 sc = device_get_softc(dev); 1868 1869 if (sc->flags & PCIB_ENABLE_ARI) 1870 return (PCIE_ARI_FUNCMAX); 1871 else 1872 return (PCI_FUNCMAX); 1873 } 1874 1875 static void 1876 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 1877 int *func) 1878 { 1879 struct pcib_softc *sc; 1880 1881 sc = device_get_softc(pcib); 1882 1883 *bus = PCI_RID2BUS(rid); 1884 if (sc->flags & PCIB_ENABLE_ARI) { 1885 *slot = PCIE_ARI_RID2SLOT(rid); 1886 *func = PCIE_ARI_RID2FUNC(rid); 1887 } else { 1888 *slot = PCI_RID2SLOT(rid); 1889 *func = PCI_RID2FUNC(rid); 1890 } 1891 } 1892 1893 /* 1894 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1895 */ 1896 static uint32_t 1897 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1898 { 1899 1900 pcib_xlate_ari(dev, b, &s, &f); 1901 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 1902 f, reg, width)); 1903 } 1904 1905 static void 1906 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1907 { 1908 1909 pcib_xlate_ari(dev, b, &s, &f); 1910 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 1911 reg, val, width); 1912 } 1913 1914 /* 1915 * Route an interrupt across a PCI bridge. 1916 */ 1917 int 1918 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1919 { 1920 device_t bus; 1921 int parent_intpin; 1922 int intnum; 1923 1924 /* 1925 * 1926 * The PCI standard defines a swizzle of the child-side device/intpin to 1927 * the parent-side intpin as follows. 1928 * 1929 * device = device on child bus 1930 * child_intpin = intpin on child bus slot (0-3) 1931 * parent_intpin = intpin on parent bus slot (0-3) 1932 * 1933 * parent_intpin = (device + child_intpin) % 4 1934 */ 1935 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1936 1937 /* 1938 * Our parent is a PCI bus. Its parent must export the pcib interface 1939 * which includes the ability to route interrupts. 1940 */ 1941 bus = device_get_parent(pcib); 1942 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1943 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1944 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1945 pci_get_slot(dev), 'A' + pin - 1, intnum); 1946 } 1947 return(intnum); 1948 } 1949 1950 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1951 int 1952 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1953 { 1954 struct pcib_softc *sc = device_get_softc(pcib); 1955 device_t bus; 1956 1957 if (sc->flags & PCIB_DISABLE_MSI) 1958 return (ENXIO); 1959 bus = device_get_parent(pcib); 1960 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1961 irqs)); 1962 } 1963 1964 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1965 int 1966 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1967 { 1968 device_t bus; 1969 1970 bus = device_get_parent(pcib); 1971 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1972 } 1973 1974 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 1975 int 1976 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1977 { 1978 struct pcib_softc *sc = device_get_softc(pcib); 1979 device_t bus; 1980 1981 if (sc->flags & PCIB_DISABLE_MSIX) 1982 return (ENXIO); 1983 bus = device_get_parent(pcib); 1984 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1985 } 1986 1987 /* Pass request to release an MSI-X message up to the parent bridge. */ 1988 int 1989 pcib_release_msix(device_t pcib, device_t dev, int irq) 1990 { 1991 device_t bus; 1992 1993 bus = device_get_parent(pcib); 1994 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1995 } 1996 1997 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 1998 int 1999 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2000 uint32_t *data) 2001 { 2002 device_t bus; 2003 int error; 2004 2005 bus = device_get_parent(pcib); 2006 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2007 if (error) 2008 return (error); 2009 2010 pci_ht_map_msi(pcib, *addr); 2011 return (0); 2012 } 2013 2014 /* Pass request for device power state up to parent bridge. */ 2015 int 2016 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2017 { 2018 device_t bus; 2019 2020 bus = device_get_parent(pcib); 2021 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2022 } 2023 2024 static int 2025 pcib_ari_enabled(device_t pcib) 2026 { 2027 struct pcib_softc *sc; 2028 2029 sc = device_get_softc(pcib); 2030 2031 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2032 } 2033 2034 static uint16_t 2035 pcib_ari_get_rid(device_t pcib, device_t dev) 2036 { 2037 struct pcib_softc *sc; 2038 uint8_t bus, slot, func; 2039 2040 sc = device_get_softc(pcib); 2041 2042 if (sc->flags & PCIB_ENABLE_ARI) { 2043 bus = pci_get_bus(dev); 2044 func = pci_get_function(dev); 2045 2046 return (PCI_ARI_RID(bus, func)); 2047 } else { 2048 bus = pci_get_bus(dev); 2049 slot = pci_get_slot(dev); 2050 func = pci_get_function(dev); 2051 2052 return (PCI_RID(bus, slot, func)); 2053 } 2054 } 2055 2056 /* 2057 * Check that the downstream port (pcib) and the endpoint device (dev) both 2058 * support ARI. If so, enable it and return 0, otherwise return an error. 2059 */ 2060 static int 2061 pcib_try_enable_ari(device_t pcib, device_t dev) 2062 { 2063 struct pcib_softc *sc; 2064 int error; 2065 uint32_t cap2; 2066 int ari_cap_off; 2067 uint32_t ari_ver; 2068 uint32_t pcie_pos; 2069 2070 sc = device_get_softc(pcib); 2071 2072 /* 2073 * ARI is controlled in a register in the PCIe capability structure. 2074 * If the downstream port does not have the PCIe capability structure 2075 * then it does not support ARI. 2076 */ 2077 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2078 if (error != 0) 2079 return (ENODEV); 2080 2081 /* Check that the PCIe port advertises ARI support. */ 2082 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2083 if (!(cap2 & PCIEM_CAP2_ARI)) 2084 return (ENODEV); 2085 2086 /* 2087 * Check that the endpoint device advertises ARI support via the ARI 2088 * extended capability structure. 2089 */ 2090 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2091 if (error != 0) 2092 return (ENODEV); 2093 2094 /* 2095 * Finally, check that the endpoint device supports the same version 2096 * of ARI that we do. 2097 */ 2098 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2099 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2100 if (bootverbose) 2101 device_printf(pcib, 2102 "Unsupported version of ARI (%d) detected\n", 2103 PCI_EXTCAP_VER(ari_ver)); 2104 2105 return (ENXIO); 2106 } 2107 2108 pcib_enable_ari(sc, pcie_pos); 2109 2110 return (0); 2111 } 2112 2113