1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/bus.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/resource.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcib_private.h> 51 52 #include "pcib_if.h" 53 54 static int pcib_probe(device_t dev); 55 56 static device_method_t pcib_methods[] = { 57 /* Device interface */ 58 DEVMETHOD(device_probe, pcib_probe), 59 DEVMETHOD(device_attach, pcib_attach), 60 DEVMETHOD(device_shutdown, bus_generic_shutdown), 61 DEVMETHOD(device_suspend, bus_generic_suspend), 62 DEVMETHOD(device_resume, bus_generic_resume), 63 64 /* Bus interface */ 65 DEVMETHOD(bus_print_child, bus_generic_print_child), 66 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 67 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 68 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 69 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 70 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 71 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 72 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 73 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 74 75 /* pcib interface */ 76 DEVMETHOD(pcib_maxslots, pcib_maxslots), 77 DEVMETHOD(pcib_read_config, pcib_read_config), 78 DEVMETHOD(pcib_write_config, pcib_write_config), 79 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 80 81 { 0, 0 } 82 }; 83 84 static driver_t pcib_driver = { 85 "pcib", 86 pcib_methods, 87 sizeof(struct pcib_softc), 88 }; 89 90 devclass_t pcib_devclass; 91 92 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 93 94 /* 95 * sysctl and tunable vars 96 */ 97 static int pci_allow_unsupported_io_range = 0; 98 TUNABLE_INT("hw.pci.allow_unsupported_io_range", 99 (int *)&pci_allow_unsupported_io_range); 100 SYSCTL_DECL(_hw_pci); 101 SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD, 102 &pci_allow_unsupported_io_range, 0, 103 "Allows the PCI Bridge to pass through an unsupported memory range " 104 "assigned by the BIOS."); 105 106 /* 107 * Generic device interface 108 */ 109 static int 110 pcib_probe(device_t dev) 111 { 112 if ((pci_get_class(dev) == PCIC_BRIDGE) && 113 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 114 device_set_desc(dev, "PCI-PCI bridge"); 115 return(-10000); 116 } 117 return(ENXIO); 118 } 119 120 void 121 pcib_attach_common(device_t dev) 122 { 123 struct pcib_softc *sc; 124 uint8_t iolow; 125 126 sc = device_get_softc(dev); 127 sc->dev = dev; 128 129 /* 130 * Get current bridge configuration. 131 */ 132 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 133 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 134 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 135 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 136 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 137 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 138 139 /* 140 * Determine current I/O decode. 141 */ 142 if (sc->command & PCIM_CMD_PORTEN) { 143 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 144 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 145 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 146 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 147 } else { 148 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 149 } 150 151 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 152 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 153 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 154 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 155 } else { 156 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 157 } 158 } 159 160 /* 161 * Determine current memory decode. 162 */ 163 if (sc->command & PCIM_CMD_MEMEN) { 164 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 165 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 166 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 167 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 168 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 169 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 170 } 171 172 /* 173 * Quirk handling. 174 */ 175 switch (pci_get_devid(dev)) { 176 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 177 { 178 uint8_t supbus; 179 180 supbus = pci_read_config(dev, 0x41, 1); 181 if (supbus != 0xff) { 182 sc->secbus = supbus + 1; 183 sc->subbus = supbus + 1; 184 } 185 } 186 break; 187 } 188 189 if (bootverbose) { 190 device_printf(dev, " secondary bus %d\n", sc->secbus); 191 device_printf(dev, " subordinate bus %d\n", sc->subbus); 192 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 193 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 194 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 195 } 196 197 /* 198 * XXX If the secondary bus number is zero, we should assign a bus number 199 * since the BIOS hasn't, then initialise the bridge. 200 */ 201 202 /* 203 * XXX If the subordinate bus number is less than the secondary bus number, 204 * we should pick a better value. One sensible alternative would be to 205 * pick 255; the only tradeoff here is that configuration transactions 206 * would be more widely routed than absolutely necessary. 207 */ 208 } 209 210 int 211 pcib_attach(device_t dev) 212 { 213 struct pcib_softc *sc; 214 device_t child; 215 216 pcib_attach_common(dev); 217 sc = device_get_softc(dev); 218 if (sc->secbus != 0) { 219 child = device_add_child(dev, "pci", sc->secbus); 220 if (child != NULL) 221 return(bus_generic_attach(dev)); 222 } 223 224 /* no secondary bus; we should have fixed this */ 225 return(0); 226 } 227 228 int 229 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 230 { 231 struct pcib_softc *sc = device_get_softc(dev); 232 233 switch (which) { 234 case PCIB_IVAR_BUS: 235 *result = sc->secbus; 236 return(0); 237 } 238 return(ENOENT); 239 } 240 241 int 242 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 243 { 244 struct pcib_softc *sc = device_get_softc(dev); 245 246 switch (which) { 247 case PCIB_IVAR_BUS: 248 sc->secbus = value; 249 break; 250 } 251 return(ENOENT); 252 } 253 254 /* 255 * Is this a decoded ISA I/O port address? Note, we need to do the mask that 256 * we do below because of the ISA alias addresses. I'm not 100% sure that 257 * this is correct. Maybe the bridge needs to be subtractive decode for 258 * this to work? 259 */ 260 static int 261 pcib_is_isa_io(u_long start) 262 { 263 if ((start & 0xfffUL) > 0x3ffUL || start == 0) 264 return (0); 265 return (1); 266 } 267 268 /* 269 * Is this a decoded ISA memory address? 270 */ 271 static int 272 pcib_is_isa_mem(u_long start) 273 { 274 if (start > 0xfffffUL || start == 0) 275 return (0); 276 return (1); 277 } 278 279 /* 280 * Is the prefetch window open (eg, can we allocate memory in it?) 281 */ 282 static int 283 pcib_is_prefetch_open(struct pcib_softc *sc) 284 { 285 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 286 } 287 288 /* 289 * Is the nonprefetch window open (eg, can we allocate memory in it?) 290 */ 291 static int 292 pcib_is_nonprefetch_open(struct pcib_softc *sc) 293 { 294 return (sc->membase > 0 && sc->membase < sc->memlimit); 295 } 296 297 /* 298 * Is the io window open (eg, can we allocate ports in it?) 299 */ 300 static int 301 pcib_is_io_open(struct pcib_softc *sc) 302 { 303 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 304 } 305 306 /* 307 * We have to trap resource allocation requests and ensure that the bridge 308 * is set up to, or capable of handling them. 309 */ 310 struct resource * 311 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 312 u_long start, u_long end, u_long count, u_int flags) 313 { 314 struct pcib_softc *sc = device_get_softc(dev); 315 int ok; 316 317 /* 318 * If this is a "default" allocation against this rid, we can't work 319 * out where it's coming from (we should actually never see these) so we 320 * just have to punt. 321 */ 322 if ((start == 0) && (end == ~0)) { 323 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 324 *rid, device_get_name(child), device_get_unit(child)); 325 } else { 326 /* 327 * Fail the allocation for this range if it's not supported. 328 */ 329 switch (type) { 330 case SYS_RES_IOPORT: 331 ok = 1; 332 if (!pcib_is_isa_io(start)) { 333 ok = 0; 334 if (pcib_is_io_open(sc)) 335 ok = (start >= sc->iobase && end <= sc->iolimit); 336 if (!pci_allow_unsupported_io_range) { 337 if (!ok) { 338 if (start < sc->iobase) 339 start = sc->iobase; 340 if (end > sc->iolimit) 341 end = sc->iolimit; 342 } 343 } else { 344 if (start < sc->iobase) 345 printf("start (%lx) < sc->iobase (%x)\n", start, 346 sc->iobase); 347 if (end > sc->iolimit) 348 printf("end (%lx) > sc->iolimit (%x)\n", 349 end, sc->iolimit); 350 if (end < start) 351 printf("end (%lx) < start (%lx)\n", end, start); 352 } 353 } 354 if (end < start) { 355 start = 0; 356 end = 0; 357 ok = 0; 358 } 359 if (!ok) { 360 device_printf(dev, "device %s%d requested unsupported I/O " 361 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 362 device_get_name(child), device_get_unit(child), start, end, 363 sc->iobase, sc->iolimit); 364 return (NULL); 365 } 366 if (bootverbose) 367 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 368 device_get_name(child), device_get_unit(child), start, end); 369 break; 370 371 case SYS_RES_MEMORY: 372 ok = 1; 373 if (!pcib_is_isa_mem(start)) { 374 ok = 0; 375 if (pcib_is_nonprefetch_open(sc)) 376 ok = ok || (start >= sc->membase && end <= sc->memlimit); 377 if (pcib_is_prefetch_open(sc)) 378 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 379 if (!pci_allow_unsupported_io_range) { 380 if (!ok) { 381 ok = 1; 382 if (flags & RF_PREFETCHABLE) { 383 if (pcib_is_prefetch_open(sc)) { 384 if (start < sc->pmembase) 385 start = sc->pmembase; 386 if (end > sc->pmemlimit) 387 end = sc->pmemlimit; 388 } else { 389 ok = 0; 390 } 391 } else { /* non-prefetchable */ 392 if (pcib_is_nonprefetch_open(sc)) { 393 if (start < sc->membase) 394 start = sc->membase; 395 if (end > sc->memlimit) 396 end = sc->memlimit; 397 } else { 398 ok = 0; 399 } 400 } 401 } 402 } else if (!ok) { 403 ok = 1; /* pci_allow_unsupported_ranges -> always ok */ 404 if (pcib_is_nonprefetch_open(sc)) { 405 if (start < sc->membase) 406 printf("start (%lx) < sc->membase (%x)\n", 407 start, sc->membase); 408 if (end > sc->memlimit) 409 printf("end (%lx) > sc->memlimit (%x)\n", 410 end, sc->memlimit); 411 } 412 if (pcib_is_prefetch_open(sc)) { 413 if (start < sc->pmembase) 414 printf("start (%lx) < sc->pmembase (%x)\n", 415 start, sc->pmembase); 416 if (end > sc->pmemlimit) 417 printf("end (%lx) > sc->pmemlimit (%x)\n", 418 end, sc->memlimit); 419 } 420 if (end < start) 421 printf("end (%lx) < start (%lx)\n", end, start); 422 } 423 } 424 if (end < start) { 425 start = 0; 426 end = 0; 427 ok = 0; 428 } 429 if (!ok && bootverbose) 430 device_printf(dev, 431 "device %s%d requested unsupported memory range " 432 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 433 device_get_name(child), device_get_unit(child), start, 434 end, sc->membase, sc->memlimit, sc->pmembase, 435 sc->pmemlimit); 436 if (!ok) 437 return (NULL); 438 if (bootverbose) 439 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 440 device_get_name(child), device_get_unit(child), start, end); 441 break; 442 443 default: 444 break; 445 } 446 } 447 448 /* 449 * Bridge is OK decoding this resource, so pass it up. 450 */ 451 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 452 } 453 454 /* 455 * PCIB interface. 456 */ 457 int 458 pcib_maxslots(device_t dev) 459 { 460 return(PCI_SLOTMAX); 461 } 462 463 /* 464 * Since we are a child of a PCI bus, its parent must support the pcib interface. 465 */ 466 uint32_t 467 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 468 { 469 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 470 } 471 472 void 473 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 474 { 475 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 476 } 477 478 /* 479 * Route an interrupt across a PCI bridge. 480 */ 481 int 482 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 483 { 484 device_t bus; 485 int parent_intpin; 486 int intnum; 487 488 /* 489 * 490 * The PCI standard defines a swizzle of the child-side device/intpin to 491 * the parent-side intpin as follows. 492 * 493 * device = device on child bus 494 * child_intpin = intpin on child bus slot (0-3) 495 * parent_intpin = intpin on parent bus slot (0-3) 496 * 497 * parent_intpin = (device + child_intpin) % 4 498 */ 499 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 500 501 /* 502 * Our parent is a PCI bus. Its parent must export the pcib interface 503 * which includes the ability to route interrupts. 504 */ 505 bus = device_get_parent(pcib); 506 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 507 if (PCI_INTERRUPT_VALID(intnum)) { 508 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 509 pci_get_slot(dev), 'A' + pin - 1, intnum); 510 } 511 return(intnum); 512 } 513 514 /* 515 * Try to read the bus number of a host-PCI bridge using appropriate config 516 * registers. 517 */ 518 int 519 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 520 uint8_t *busnum) 521 { 522 uint32_t id; 523 524 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 525 if (id == 0xffffffff) 526 return (0); 527 528 switch (id) { 529 case 0x12258086: 530 /* Intel 824?? */ 531 /* XXX This is a guess */ 532 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 533 *busnum = bus; 534 break; 535 case 0x84c48086: 536 /* Intel 82454KX/GX (Orion) */ 537 *busnum = read_config(bus, slot, func, 0x4a, 1); 538 break; 539 case 0x84ca8086: 540 /* 541 * For the 450nx chipset, there is a whole bundle of 542 * things pretending to be host bridges. The MIOC will 543 * be seen first and isn't really a pci bridge (the 544 * actual busses are attached to the PXB's). We need to 545 * read the registers of the MIOC to figure out the 546 * bus numbers for the PXB channels. 547 * 548 * Since the MIOC doesn't have a pci bus attached, we 549 * pretend it wasn't there. 550 */ 551 return (0); 552 case 0x84cb8086: 553 switch (slot) { 554 case 0x12: 555 /* Intel 82454NX PXB#0, Bus#A */ 556 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 557 break; 558 case 0x13: 559 /* Intel 82454NX PXB#0, Bus#B */ 560 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 561 break; 562 case 0x14: 563 /* Intel 82454NX PXB#1, Bus#A */ 564 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 565 break; 566 case 0x15: 567 /* Intel 82454NX PXB#1, Bus#B */ 568 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 569 break; 570 } 571 break; 572 573 /* ServerWorks -- vendor 0x1166 */ 574 case 0x00051166: 575 case 0x00061166: 576 case 0x00081166: 577 case 0x00091166: 578 case 0x00101166: 579 case 0x00111166: 580 case 0x00171166: 581 case 0x01011166: 582 case 0x010f1014: 583 case 0x02011166: 584 case 0x03021014: 585 *busnum = read_config(bus, slot, func, 0x44, 1); 586 break; 587 default: 588 /* Don't know how to read bus number. */ 589 return 0; 590 } 591 592 return 1; 593 } 594