1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/libkern.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pci_private.h> 54 #include <dev/pci/pcib_private.h> 55 56 #include "pcib_if.h" 57 58 static int pcib_probe(device_t dev); 59 static int pcib_suspend(device_t dev); 60 static int pcib_resume(device_t dev); 61 static int pcib_power_for_sleep(device_t pcib, device_t dev, 62 int *pstate); 63 64 static device_method_t pcib_methods[] = { 65 /* Device interface */ 66 DEVMETHOD(device_probe, pcib_probe), 67 DEVMETHOD(device_attach, pcib_attach), 68 DEVMETHOD(device_detach, bus_generic_detach), 69 DEVMETHOD(device_shutdown, bus_generic_shutdown), 70 DEVMETHOD(device_suspend, pcib_suspend), 71 DEVMETHOD(device_resume, pcib_resume), 72 73 /* Bus interface */ 74 DEVMETHOD(bus_print_child, bus_generic_print_child), 75 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 76 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 77 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 78 #ifdef NEW_PCIB 79 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 80 DEVMETHOD(bus_release_resource, pcib_release_resource), 81 #else 82 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 83 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 84 #endif 85 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 86 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 87 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 88 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 89 90 /* pcib interface */ 91 DEVMETHOD(pcib_maxslots, pcib_maxslots), 92 DEVMETHOD(pcib_read_config, pcib_read_config), 93 DEVMETHOD(pcib_write_config, pcib_write_config), 94 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 95 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 96 DEVMETHOD(pcib_release_msi, pcib_release_msi), 97 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 98 DEVMETHOD(pcib_release_msix, pcib_release_msix), 99 DEVMETHOD(pcib_map_msi, pcib_map_msi), 100 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 101 102 { 0, 0 } 103 }; 104 105 static devclass_t pcib_devclass; 106 107 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 108 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 109 110 #ifdef NEW_PCIB 111 /* 112 * XXX Todo: 113 * - properly handle the ISA enable bit. If it is set, we should change 114 * the behavior of the I/O window resource and rman to not allocate the 115 * blocked ranges (upper 768 bytes of each 1K in the first 64k of the 116 * I/O port address space). 117 */ 118 119 /* 120 * Is a resource from a child device sub-allocated from one of our 121 * resource managers? 122 */ 123 static int 124 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 125 { 126 127 switch (type) { 128 case SYS_RES_IOPORT: 129 return (rman_is_region_manager(r, &sc->io.rman)); 130 case SYS_RES_MEMORY: 131 /* Prefetchable resources may live in either memory rman. */ 132 if (rman_get_flags(r) & RF_PREFETCHABLE && 133 rman_is_region_manager(r, &sc->pmem.rman)) 134 return (1); 135 return (rman_is_region_manager(r, &sc->mem.rman)); 136 } 137 return (0); 138 } 139 140 static int 141 pcib_is_window_open(struct pcib_window *pw) 142 { 143 144 return (pw->valid && pw->base < pw->limit); 145 } 146 147 /* 148 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 149 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 150 * when allocating the resource windows and rely on the PCI bus driver 151 * to do this for us. 152 */ 153 static void 154 pcib_activate_window(struct pcib_softc *sc, int type) 155 { 156 157 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 158 } 159 160 static void 161 pcib_write_windows(struct pcib_softc *sc, int mask) 162 { 163 device_t dev; 164 uint32_t val; 165 166 dev = sc->dev; 167 if (sc->io.valid && mask & WIN_IO) { 168 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 169 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 170 pci_write_config(dev, PCIR_IOBASEH_1, 171 sc->io.base >> 16, 2); 172 pci_write_config(dev, PCIR_IOLIMITH_1, 173 sc->io.limit >> 16, 2); 174 } 175 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 176 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 177 } 178 179 if (mask & WIN_MEM) { 180 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 181 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 182 } 183 184 if (sc->pmem.valid && mask & WIN_PMEM) { 185 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 186 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 187 pci_write_config(dev, PCIR_PMBASEH_1, 188 sc->pmem.base >> 32, 4); 189 pci_write_config(dev, PCIR_PMLIMITH_1, 190 sc->pmem.limit >> 32, 4); 191 } 192 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 193 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 194 } 195 } 196 197 static void 198 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 199 int flags, pci_addr_t max_address) 200 { 201 char buf[64]; 202 int error, rid; 203 204 if (max_address != (u_long)max_address) 205 max_address = ~0ul; 206 w->rman.rm_start = 0; 207 w->rman.rm_end = max_address; 208 w->rman.rm_type = RMAN_ARRAY; 209 snprintf(buf, sizeof(buf), "%s %s window", 210 device_get_nameunit(sc->dev), w->name); 211 w->rman.rm_descr = strdup(buf, M_DEVBUF); 212 error = rman_init(&w->rman); 213 if (error) 214 panic("Failed to initialize %s %s rman", 215 device_get_nameunit(sc->dev), w->name); 216 217 if (!pcib_is_window_open(w)) 218 return; 219 220 if (w->base > max_address || w->limit > max_address) { 221 device_printf(sc->dev, 222 "initial %s window has too many bits, ignoring\n", w->name); 223 return; 224 } 225 rid = w->reg; 226 w->res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 227 w->limit - w->base + 1, flags); 228 if (w->res == NULL) { 229 device_printf(sc->dev, 230 "failed to allocate initial %s window: %#jx-%#jx\n", 231 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 232 w->base = max_address; 233 w->limit = 0; 234 pcib_write_windows(sc, w->mask); 235 return; 236 } 237 pcib_activate_window(sc, type); 238 239 error = rman_manage_region(&w->rman, rman_get_start(w->res), 240 rman_get_end(w->res)); 241 if (error) 242 panic("Failed to initialize rman with resource"); 243 } 244 245 /* 246 * Initialize I/O windows. 247 */ 248 static void 249 pcib_probe_windows(struct pcib_softc *sc) 250 { 251 pci_addr_t max; 252 device_t dev; 253 uint32_t val; 254 255 dev = sc->dev; 256 257 /* Determine if the I/O port window is implemented. */ 258 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 259 if (val == 0) { 260 /* 261 * If 'val' is zero, then only 16-bits of I/O space 262 * are supported. 263 */ 264 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 265 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 266 sc->io.valid = 1; 267 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 268 } 269 } else 270 sc->io.valid = 1; 271 272 /* Read the existing I/O port window. */ 273 if (sc->io.valid) { 274 sc->io.reg = PCIR_IOBASEL_1; 275 sc->io.step = 12; 276 sc->io.mask = WIN_IO; 277 sc->io.name = "I/O port"; 278 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 279 sc->io.base = PCI_PPBIOBASE( 280 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 281 sc->io.limit = PCI_PPBIOLIMIT( 282 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 283 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 284 max = 0xffffffff; 285 } else { 286 sc->io.base = PCI_PPBIOBASE(0, val); 287 sc->io.limit = PCI_PPBIOLIMIT(0, 288 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 289 max = 0xffff; 290 } 291 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 292 } 293 294 /* Read the existing memory window. */ 295 sc->mem.valid = 1; 296 sc->mem.reg = PCIR_MEMBASE_1; 297 sc->mem.step = 20; 298 sc->mem.mask = WIN_MEM; 299 sc->mem.name = "memory"; 300 sc->mem.base = PCI_PPBMEMBASE(0, 301 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 302 sc->mem.limit = PCI_PPBMEMLIMIT(0, 303 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 304 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 305 306 /* Determine if the prefetchable memory window is implemented. */ 307 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 308 if (val == 0) { 309 /* 310 * If 'val' is zero, then only 32-bits of memory space 311 * are supported. 312 */ 313 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 314 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 315 sc->pmem.valid = 1; 316 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 317 } 318 } else 319 sc->pmem.valid = 1; 320 321 /* Read the existing prefetchable memory window. */ 322 if (sc->pmem.valid) { 323 sc->pmem.reg = PCIR_PMBASEL_1; 324 sc->pmem.step = 20; 325 sc->pmem.mask = WIN_PMEM; 326 sc->pmem.name = "prefetch"; 327 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 328 sc->pmem.base = PCI_PPBMEMBASE( 329 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 330 sc->pmem.limit = PCI_PPBMEMLIMIT( 331 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 332 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 333 max = 0xffffffffffffffff; 334 } else { 335 sc->pmem.base = PCI_PPBMEMBASE(0, val); 336 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 337 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 338 max = 0xffffffff; 339 } 340 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 341 RF_PREFETCHABLE, max); 342 } 343 } 344 345 #else 346 347 /* 348 * Is the prefetch window open (eg, can we allocate memory in it?) 349 */ 350 static int 351 pcib_is_prefetch_open(struct pcib_softc *sc) 352 { 353 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 354 } 355 356 /* 357 * Is the nonprefetch window open (eg, can we allocate memory in it?) 358 */ 359 static int 360 pcib_is_nonprefetch_open(struct pcib_softc *sc) 361 { 362 return (sc->membase > 0 && sc->membase < sc->memlimit); 363 } 364 365 /* 366 * Is the io window open (eg, can we allocate ports in it?) 367 */ 368 static int 369 pcib_is_io_open(struct pcib_softc *sc) 370 { 371 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 372 } 373 374 /* 375 * Get current I/O decode. 376 */ 377 static void 378 pcib_get_io_decode(struct pcib_softc *sc) 379 { 380 device_t dev; 381 uint32_t iolow; 382 383 dev = sc->dev; 384 385 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 386 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 387 sc->iobase = PCI_PPBIOBASE( 388 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 389 else 390 sc->iobase = PCI_PPBIOBASE(0, iolow); 391 392 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 393 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 394 sc->iolimit = PCI_PPBIOLIMIT( 395 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 396 else 397 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 398 } 399 400 /* 401 * Get current memory decode. 402 */ 403 static void 404 pcib_get_mem_decode(struct pcib_softc *sc) 405 { 406 device_t dev; 407 pci_addr_t pmemlow; 408 409 dev = sc->dev; 410 411 sc->membase = PCI_PPBMEMBASE(0, 412 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 413 sc->memlimit = PCI_PPBMEMLIMIT(0, 414 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 415 416 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 417 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 418 sc->pmembase = PCI_PPBMEMBASE( 419 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 420 else 421 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 422 423 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 424 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 425 sc->pmemlimit = PCI_PPBMEMLIMIT( 426 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 427 else 428 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 429 } 430 431 /* 432 * Restore previous I/O decode. 433 */ 434 static void 435 pcib_set_io_decode(struct pcib_softc *sc) 436 { 437 device_t dev; 438 uint32_t iohi; 439 440 dev = sc->dev; 441 442 iohi = sc->iobase >> 16; 443 if (iohi > 0) 444 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 445 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 446 447 iohi = sc->iolimit >> 16; 448 if (iohi > 0) 449 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 450 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 451 } 452 453 /* 454 * Restore previous memory decode. 455 */ 456 static void 457 pcib_set_mem_decode(struct pcib_softc *sc) 458 { 459 device_t dev; 460 pci_addr_t pmemhi; 461 462 dev = sc->dev; 463 464 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 465 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 466 467 pmemhi = sc->pmembase >> 32; 468 if (pmemhi > 0) 469 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 470 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 471 472 pmemhi = sc->pmemlimit >> 32; 473 if (pmemhi > 0) 474 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 475 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 476 } 477 #endif 478 479 /* 480 * Get current bridge configuration. 481 */ 482 static void 483 pcib_cfg_save(struct pcib_softc *sc) 484 { 485 device_t dev; 486 487 dev = sc->dev; 488 489 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 490 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 491 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 492 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 493 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 494 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 495 #ifndef NEW_PCIB 496 if (sc->command & PCIM_CMD_PORTEN) 497 pcib_get_io_decode(sc); 498 if (sc->command & PCIM_CMD_MEMEN) 499 pcib_get_mem_decode(sc); 500 #endif 501 } 502 503 /* 504 * Restore previous bridge configuration. 505 */ 506 static void 507 pcib_cfg_restore(struct pcib_softc *sc) 508 { 509 device_t dev; 510 511 dev = sc->dev; 512 513 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 514 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 515 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 516 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 517 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 518 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 519 #ifdef NEW_PCIB 520 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 521 #else 522 if (sc->command & PCIM_CMD_PORTEN) 523 pcib_set_io_decode(sc); 524 if (sc->command & PCIM_CMD_MEMEN) 525 pcib_set_mem_decode(sc); 526 #endif 527 } 528 529 /* 530 * Generic device interface 531 */ 532 static int 533 pcib_probe(device_t dev) 534 { 535 if ((pci_get_class(dev) == PCIC_BRIDGE) && 536 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 537 device_set_desc(dev, "PCI-PCI bridge"); 538 return(-10000); 539 } 540 return(ENXIO); 541 } 542 543 void 544 pcib_attach_common(device_t dev) 545 { 546 struct pcib_softc *sc; 547 struct sysctl_ctx_list *sctx; 548 struct sysctl_oid *soid; 549 550 sc = device_get_softc(dev); 551 sc->dev = dev; 552 553 /* 554 * Get current bridge configuration. 555 */ 556 sc->domain = pci_get_domain(dev); 557 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 558 pcib_cfg_save(sc); 559 560 /* 561 * Setup sysctl reporting nodes 562 */ 563 sctx = device_get_sysctl_ctx(dev); 564 soid = device_get_sysctl_tree(dev); 565 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 566 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 567 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 568 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 569 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 570 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 571 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 572 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 573 574 /* 575 * Quirk handling. 576 */ 577 switch (pci_get_devid(dev)) { 578 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 579 { 580 uint8_t supbus; 581 582 supbus = pci_read_config(dev, 0x41, 1); 583 if (supbus != 0xff) { 584 sc->secbus = supbus + 1; 585 sc->subbus = supbus + 1; 586 } 587 break; 588 } 589 590 /* 591 * The i82380FB mobile docking controller is a PCI-PCI bridge, 592 * and it is a subtractive bridge. However, the ProgIf is wrong 593 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 594 * happen. There's also a Toshiba bridge that behaves this 595 * way. 596 */ 597 case 0x124b8086: /* Intel 82380FB Mobile */ 598 case 0x060513d7: /* Toshiba ???? */ 599 sc->flags |= PCIB_SUBTRACTIVE; 600 break; 601 602 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 603 case 0x00dd10de: 604 { 605 char *cp; 606 607 if ((cp = getenv("smbios.planar.maker")) == NULL) 608 break; 609 if (strncmp(cp, "Compal", 6) != 0) { 610 freeenv(cp); 611 break; 612 } 613 freeenv(cp); 614 if ((cp = getenv("smbios.planar.product")) == NULL) 615 break; 616 if (strncmp(cp, "08A0", 4) != 0) { 617 freeenv(cp); 618 break; 619 } 620 freeenv(cp); 621 if (sc->subbus < 0xa) { 622 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 623 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 624 } 625 break; 626 } 627 } 628 629 if (pci_msi_device_blacklisted(dev)) 630 sc->flags |= PCIB_DISABLE_MSI; 631 632 /* 633 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 634 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 635 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 636 * This means they act as if they were subtractively decoding 637 * bridges and pass all transactions. Mark them and real ProgIf 1 638 * parts as subtractive. 639 */ 640 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 641 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 642 sc->flags |= PCIB_SUBTRACTIVE; 643 644 #ifdef NEW_PCIB 645 pcib_probe_windows(sc); 646 #endif 647 if (bootverbose) { 648 device_printf(dev, " domain %d\n", sc->domain); 649 device_printf(dev, " secondary bus %d\n", sc->secbus); 650 device_printf(dev, " subordinate bus %d\n", sc->subbus); 651 #ifdef NEW_PCIB 652 if (pcib_is_window_open(&sc->io)) 653 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 654 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 655 if (pcib_is_window_open(&sc->mem)) 656 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 657 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 658 if (pcib_is_window_open(&sc->pmem)) 659 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 660 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 661 #else 662 if (pcib_is_io_open(sc)) 663 device_printf(dev, " I/O decode 0x%x-0x%x\n", 664 sc->iobase, sc->iolimit); 665 if (pcib_is_nonprefetch_open(sc)) 666 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 667 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 668 if (pcib_is_prefetch_open(sc)) 669 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 670 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 671 #endif 672 else 673 device_printf(dev, " no prefetched decode\n"); 674 if (sc->flags & PCIB_SUBTRACTIVE) 675 device_printf(dev, " Subtractively decoded bridge.\n"); 676 } 677 678 /* 679 * XXX If the secondary bus number is zero, we should assign a bus number 680 * since the BIOS hasn't, then initialise the bridge. A simple 681 * bus_alloc_resource with the a couple of busses seems like the right 682 * approach, but we don't know what busses the BIOS might have already 683 * assigned to other bridges on this bus that probe later than we do. 684 * 685 * If the subordinate bus number is less than the secondary bus number, 686 * we should pick a better value. One sensible alternative would be to 687 * pick 255; the only tradeoff here is that configuration transactions 688 * would be more widely routed than absolutely necessary. We could 689 * then do a walk of the tree later and fix it. 690 */ 691 } 692 693 int 694 pcib_attach(device_t dev) 695 { 696 struct pcib_softc *sc; 697 device_t child; 698 699 pcib_attach_common(dev); 700 sc = device_get_softc(dev); 701 if (sc->secbus != 0) { 702 child = device_add_child(dev, "pci", sc->secbus); 703 if (child != NULL) 704 return(bus_generic_attach(dev)); 705 } 706 707 /* no secondary bus; we should have fixed this */ 708 return(0); 709 } 710 711 int 712 pcib_suspend(device_t dev) 713 { 714 device_t pcib; 715 int dstate, error; 716 717 pcib_cfg_save(device_get_softc(dev)); 718 error = bus_generic_suspend(dev); 719 if (error == 0 && pci_do_power_suspend) { 720 dstate = PCI_POWERSTATE_D3; 721 pcib = device_get_parent(device_get_parent(dev)); 722 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 723 pci_set_powerstate(dev, dstate); 724 } 725 return (error); 726 } 727 728 int 729 pcib_resume(device_t dev) 730 { 731 device_t pcib; 732 733 if (pci_do_power_resume) { 734 pcib = device_get_parent(device_get_parent(dev)); 735 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 736 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 737 } 738 pcib_cfg_restore(device_get_softc(dev)); 739 return (bus_generic_resume(dev)); 740 } 741 742 int 743 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 744 { 745 struct pcib_softc *sc = device_get_softc(dev); 746 747 switch (which) { 748 case PCIB_IVAR_DOMAIN: 749 *result = sc->domain; 750 return(0); 751 case PCIB_IVAR_BUS: 752 *result = sc->secbus; 753 return(0); 754 } 755 return(ENOENT); 756 } 757 758 int 759 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 760 { 761 struct pcib_softc *sc = device_get_softc(dev); 762 763 switch (which) { 764 case PCIB_IVAR_DOMAIN: 765 return(EINVAL); 766 case PCIB_IVAR_BUS: 767 sc->secbus = value; 768 return(0); 769 } 770 return(ENOENT); 771 } 772 773 #ifdef NEW_PCIB 774 static const char * 775 pcib_child_name(device_t child) 776 { 777 static char buf[64]; 778 779 if (device_get_nameunit(child) != NULL) 780 return (device_get_nameunit(child)); 781 snprintf(buf, sizeof(buf), "pci%d:%d:%d:%d", pci_get_domain(child), 782 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 783 return (buf); 784 } 785 786 /* 787 * Attempt to allocate a resource from the existing resources assigned 788 * to a window. 789 */ 790 static struct resource * 791 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 792 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 793 u_int flags) 794 { 795 struct resource *res; 796 797 if (!pcib_is_window_open(w)) 798 return (NULL); 799 800 res = rman_reserve_resource(&w->rman, start, end, count, 801 flags & ~RF_ACTIVE, child); 802 if (res == NULL) 803 return (NULL); 804 805 if (bootverbose) 806 device_printf(sc->dev, 807 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 808 w->name, rman_get_start(res), rman_get_end(res), *rid, 809 pcib_child_name(child)); 810 rman_set_rid(res, *rid); 811 812 /* 813 * If the resource should be active, pass that request up the 814 * tree. This assumes the parent drivers can handle 815 * activating sub-allocated resources. 816 */ 817 if (flags & RF_ACTIVE) { 818 if (bus_activate_resource(child, type, *rid, res) != 0) { 819 rman_release_resource(res); 820 return (NULL); 821 } 822 } 823 824 return (res); 825 } 826 827 /* 828 * Attempt to grow a window to make room for a given resource request. 829 * The 'step' parameter is log_2 of the desired I/O window's alignment. 830 */ 831 static int 832 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 833 u_long start, u_long end, u_long count, u_int flags) 834 { 835 u_long align, start_free, end_free, front, back; 836 int error, rid; 837 838 /* 839 * Clamp the desired resource range to the maximum address 840 * this window supports. Reject impossible requests. 841 */ 842 if (!w->valid) 843 return (EINVAL); 844 if (end > w->rman.rm_end) 845 end = w->rman.rm_end; 846 if (start + count - 1 > end || start + count < start) 847 return (EINVAL); 848 849 /* 850 * If there is no resource at all, just try to allocate enough 851 * aligned space for this resource. 852 */ 853 if (w->res == NULL) { 854 if (RF_ALIGNMENT(flags) < w->step) { 855 flags &= ~RF_ALIGNMENT_MASK; 856 flags |= RF_ALIGNMENT_LOG2(w->step); 857 } 858 start &= ~((1ul << w->step) - 1); 859 end |= ((1ul << w->step) - 1); 860 count = roundup2(count, 1ul << w->step); 861 rid = w->reg; 862 w->res = bus_alloc_resource(sc->dev, type, &rid, start, end, 863 count, flags & ~RF_ACTIVE); 864 if (w->res == NULL) { 865 if (bootverbose) 866 device_printf(sc->dev, 867 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 868 w->name, start, end, count); 869 return (ENXIO); 870 } 871 if (bootverbose) 872 device_printf(sc->dev, 873 "allocated initial %s window of %#lx-%#lx\n", 874 w->name, rman_get_start(w->res), 875 rman_get_end(w->res)); 876 error = rman_manage_region(&w->rman, rman_get_start(w->res), 877 rman_get_end(w->res)); 878 if (error) { 879 if (bootverbose) 880 device_printf(sc->dev, 881 "failed to add initial %s window to rman\n", 882 w->name); 883 bus_release_resource(sc->dev, type, w->reg, w->res); 884 w->res = NULL; 885 return (error); 886 } 887 pcib_activate_window(sc, type); 888 goto updatewin; 889 } 890 891 /* 892 * See if growing the window would help. Compute the minimum 893 * amount of address space needed on both the front and back 894 * ends of the existing window to satisfy the allocation. 895 * 896 * For each end, build a candidate region adjusting for the 897 * required alignment, etc. If there is a free region at the 898 * edge of the window, grow from the inner edge of the free 899 * region. Otherwise grow from the window boundary. 900 * 901 * XXX: Special case: if w->res is completely empty and the 902 * request size is larger than w->res, we should find the 903 * optimal aligned buffer containing w->res and allocate that. 904 */ 905 if (bootverbose) 906 device_printf(sc->dev, 907 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 908 w->name, start, end, count); 909 align = 1ul << RF_ALIGNMENT(flags); 910 if (start < rman_get_start(w->res)) { 911 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 912 0 || start_free != rman_get_start(w->res)) 913 end_free = rman_get_start(w->res) - 1; 914 if (end_free > end) 915 end_free = end; 916 917 /* Move end_free down until it is properly aligned. */ 918 end_free &= ~(align - 1); 919 end_free--; 920 front = end_free - (count - 1); 921 922 /* 923 * The resource would now be allocated at (front, 924 * end_free). Ensure that fits in the (start, end) 925 * bounds. end_free is checked above. If 'front' is 926 * ok, ensure it is properly aligned for this window. 927 * Also check for underflow. 928 */ 929 if (front >= start && front <= end_free) { 930 if (bootverbose) 931 printf("\tfront candidate range: %#lx-%#lx\n", 932 front, end_free); 933 front &= (1ul << w->step) - 1; 934 front = rman_get_start(w->res) - front; 935 } else 936 front = 0; 937 } else 938 front = 0; 939 if (end > rman_get_end(w->res)) { 940 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 941 0 || end_free != rman_get_end(w->res)) 942 start_free = rman_get_end(w->res) + 1; 943 if (start_free < start) 944 start_free = start; 945 946 /* Move start_free up until it is properly aligned. */ 947 start_free = roundup2(start_free, align); 948 back = start_free + count - 1; 949 950 /* 951 * The resource would now be allocated at (start_free, 952 * back). Ensure that fits in the (start, end) 953 * bounds. start_free is checked above. If 'back' is 954 * ok, ensure it is properly aligned for this window. 955 * Also check for overflow. 956 */ 957 if (back <= end && start_free <= back) { 958 if (bootverbose) 959 printf("\tback candidate range: %#lx-%#lx\n", 960 start_free, back); 961 back = roundup2(back + 1, w->step) - 1; 962 back -= rman_get_end(w->res); 963 } else 964 back = 0; 965 } else 966 back = 0; 967 968 /* 969 * Try to allocate the smallest needed region first. 970 * If that fails, fall back to the other region. 971 */ 972 error = ENOSPC; 973 while (front != 0 || back != 0) { 974 if (front != 0 && (front <= back || back == 0)) { 975 error = bus_adjust_resource(sc->dev, type, w->res, 976 rman_get_start(w->res) - front, 977 rman_get_end(w->res)); 978 if (error == 0) 979 break; 980 front = 0; 981 } else { 982 error = bus_adjust_resource(sc->dev, type, w->res, 983 rman_get_start(w->res), 984 rman_get_end(w->res) + back); 985 if (error == 0) 986 break; 987 back = 0; 988 } 989 } 990 991 if (error) 992 return (error); 993 if (bootverbose) 994 device_printf(sc->dev, "grew %s window to %#lx-%#lx\n", 995 w->name, rman_get_start(w->res), rman_get_end(w->res)); 996 997 /* Add the newly allocated region to the resource manager. */ 998 if (w->base != rman_get_start(w->res)) { 999 KASSERT(w->limit == rman_get_end(w->res), ("both ends moved")); 1000 error = rman_manage_region(&w->rman, rman_get_start(w->res), 1001 w->base - 1); 1002 } else { 1003 KASSERT(w->limit != rman_get_end(w->res), 1004 ("neither end moved")); 1005 error = rman_manage_region(&w->rman, w->limit + 1, 1006 rman_get_end(w->res)); 1007 } 1008 if (error) { 1009 if (bootverbose) 1010 device_printf(sc->dev, 1011 "failed to expand %s resource manager\n", w->name); 1012 bus_adjust_resource(sc->dev, type, w->res, w->base, w->limit); 1013 return (error); 1014 } 1015 1016 updatewin: 1017 /* Save the new window. */ 1018 w->base = rman_get_start(w->res); 1019 w->limit = rman_get_end(w->res); 1020 KASSERT((w->base & ((1ul << w->step) - 1)) == 0, 1021 ("start address is not aligned")); 1022 KASSERT((w->limit & ((1ul << w->step) - 1)) == (1ul << w->step) - 1, 1023 ("end address is not aligned")); 1024 pcib_write_windows(sc, w->mask); 1025 return (0); 1026 } 1027 1028 /* 1029 * We have to trap resource allocation requests and ensure that the bridge 1030 * is set up to, or capable of handling them. 1031 */ 1032 struct resource * 1033 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1034 u_long start, u_long end, u_long count, u_int flags) 1035 { 1036 struct pcib_softc *sc; 1037 struct resource *r; 1038 1039 sc = device_get_softc(dev); 1040 1041 /* 1042 * VGA resources are decoded iff the VGA enable bit is set in 1043 * the bridge control register. VGA resources do not fall into 1044 * the resource windows and are passed up to the parent. 1045 */ 1046 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1047 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1048 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1049 return (bus_generic_alloc_resource(dev, child, type, 1050 rid, start, end, count, flags)); 1051 else 1052 return (NULL); 1053 } 1054 1055 switch (type) { 1056 case SYS_RES_IOPORT: 1057 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1058 end, count, flags); 1059 if (r != NULL) 1060 break; 1061 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1062 flags) == 0) 1063 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1064 rid, start, end, count, flags); 1065 break; 1066 case SYS_RES_MEMORY: 1067 /* 1068 * For prefetchable resources, prefer the prefetchable 1069 * memory window, but fall back to the regular memory 1070 * window if that fails. Try both windows before 1071 * attempting to grow a window in case the firmware 1072 * has used a range in the regular memory window to 1073 * map a prefetchable BAR. 1074 */ 1075 if (flags & RF_PREFETCHABLE) { 1076 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1077 rid, start, end, count, flags); 1078 if (r != NULL) 1079 break; 1080 } 1081 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1082 start, end, count, flags); 1083 if (r != NULL) 1084 break; 1085 if (flags & RF_PREFETCHABLE) { 1086 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1087 count, flags) == 0) { 1088 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1089 type, rid, start, end, count, flags); 1090 if (r != NULL) 1091 break; 1092 } 1093 } 1094 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1095 flags & ~RF_PREFETCHABLE) == 0) 1096 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1097 rid, start, end, count, flags); 1098 break; 1099 default: 1100 return (bus_generic_alloc_resource(dev, child, type, rid, 1101 start, end, count, flags)); 1102 } 1103 1104 /* 1105 * If attempts to suballocate from the window fail but this is a 1106 * subtractive bridge, pass the request up the tree. 1107 */ 1108 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1109 return (bus_generic_alloc_resource(dev, child, type, rid, 1110 start, end, count, flags)); 1111 return (r); 1112 } 1113 1114 int 1115 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1116 u_long start, u_long end) 1117 { 1118 struct pcib_softc *sc; 1119 1120 sc = device_get_softc(bus); 1121 if (pcib_is_resource_managed(sc, type, r)) 1122 return (rman_adjust_resource(r, start, end)); 1123 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1124 } 1125 1126 int 1127 pcib_release_resource(device_t dev, device_t child, int type, int rid, 1128 struct resource *r) 1129 { 1130 struct pcib_softc *sc; 1131 int error; 1132 1133 sc = device_get_softc(dev); 1134 if (pcib_is_resource_managed(sc, type, r)) { 1135 if (rman_get_flags(r) & RF_ACTIVE) { 1136 error = bus_deactivate_resource(child, type, rid, r); 1137 if (error) 1138 return (error); 1139 } 1140 return (rman_release_resource(r)); 1141 } 1142 return (bus_generic_release_resource(dev, child, type, rid, r)); 1143 } 1144 #else 1145 /* 1146 * We have to trap resource allocation requests and ensure that the bridge 1147 * is set up to, or capable of handling them. 1148 */ 1149 struct resource * 1150 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1151 u_long start, u_long end, u_long count, u_int flags) 1152 { 1153 struct pcib_softc *sc = device_get_softc(dev); 1154 const char *name, *suffix; 1155 int ok; 1156 1157 /* 1158 * Fail the allocation for this range if it's not supported. 1159 */ 1160 name = device_get_nameunit(child); 1161 if (name == NULL) { 1162 name = ""; 1163 suffix = ""; 1164 } else 1165 suffix = " "; 1166 switch (type) { 1167 case SYS_RES_IOPORT: 1168 ok = 0; 1169 if (!pcib_is_io_open(sc)) 1170 break; 1171 ok = (start >= sc->iobase && end <= sc->iolimit); 1172 1173 /* 1174 * Make sure we allow access to VGA I/O addresses when the 1175 * bridge has the "VGA Enable" bit set. 1176 */ 1177 if (!ok && pci_is_vga_ioport_range(start, end)) 1178 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1179 1180 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1181 if (!ok) { 1182 if (start < sc->iobase) 1183 start = sc->iobase; 1184 if (end > sc->iolimit) 1185 end = sc->iolimit; 1186 if (start < end) 1187 ok = 1; 1188 } 1189 } else { 1190 ok = 1; 1191 #if 0 1192 /* 1193 * If we overlap with the subtractive range, then 1194 * pick the upper range to use. 1195 */ 1196 if (start < sc->iolimit && end > sc->iobase) 1197 start = sc->iolimit + 1; 1198 #endif 1199 } 1200 if (end < start) { 1201 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1202 end, start); 1203 start = 0; 1204 end = 0; 1205 ok = 0; 1206 } 1207 if (!ok) { 1208 device_printf(dev, "%s%srequested unsupported I/O " 1209 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1210 name, suffix, start, end, sc->iobase, sc->iolimit); 1211 return (NULL); 1212 } 1213 if (bootverbose) 1214 device_printf(dev, 1215 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1216 name, suffix, start, end); 1217 break; 1218 1219 case SYS_RES_MEMORY: 1220 ok = 0; 1221 if (pcib_is_nonprefetch_open(sc)) 1222 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1223 if (pcib_is_prefetch_open(sc)) 1224 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1225 1226 /* 1227 * Make sure we allow access to VGA memory addresses when the 1228 * bridge has the "VGA Enable" bit set. 1229 */ 1230 if (!ok && pci_is_vga_memory_range(start, end)) 1231 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1232 1233 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1234 if (!ok) { 1235 ok = 1; 1236 if (flags & RF_PREFETCHABLE) { 1237 if (pcib_is_prefetch_open(sc)) { 1238 if (start < sc->pmembase) 1239 start = sc->pmembase; 1240 if (end > sc->pmemlimit) 1241 end = sc->pmemlimit; 1242 } else { 1243 ok = 0; 1244 } 1245 } else { /* non-prefetchable */ 1246 if (pcib_is_nonprefetch_open(sc)) { 1247 if (start < sc->membase) 1248 start = sc->membase; 1249 if (end > sc->memlimit) 1250 end = sc->memlimit; 1251 } else { 1252 ok = 0; 1253 } 1254 } 1255 } 1256 } else if (!ok) { 1257 ok = 1; /* subtractive bridge: always ok */ 1258 #if 0 1259 if (pcib_is_nonprefetch_open(sc)) { 1260 if (start < sc->memlimit && end > sc->membase) 1261 start = sc->memlimit + 1; 1262 } 1263 if (pcib_is_prefetch_open(sc)) { 1264 if (start < sc->pmemlimit && end > sc->pmembase) 1265 start = sc->pmemlimit + 1; 1266 } 1267 #endif 1268 } 1269 if (end < start) { 1270 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1271 end, start); 1272 start = 0; 1273 end = 0; 1274 ok = 0; 1275 } 1276 if (!ok && bootverbose) 1277 device_printf(dev, 1278 "%s%srequested unsupported memory range %#lx-%#lx " 1279 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1280 name, suffix, start, end, 1281 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1282 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1283 if (!ok) 1284 return (NULL); 1285 if (bootverbose) 1286 device_printf(dev,"%s%srequested memory range " 1287 "0x%lx-0x%lx: good\n", 1288 name, suffix, start, end); 1289 break; 1290 1291 default: 1292 break; 1293 } 1294 /* 1295 * Bridge is OK decoding this resource, so pass it up. 1296 */ 1297 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1298 count, flags)); 1299 } 1300 #endif 1301 1302 /* 1303 * PCIB interface. 1304 */ 1305 int 1306 pcib_maxslots(device_t dev) 1307 { 1308 return(PCI_SLOTMAX); 1309 } 1310 1311 /* 1312 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1313 */ 1314 uint32_t 1315 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1316 { 1317 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 1318 } 1319 1320 void 1321 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1322 { 1323 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 1324 } 1325 1326 /* 1327 * Route an interrupt across a PCI bridge. 1328 */ 1329 int 1330 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1331 { 1332 device_t bus; 1333 int parent_intpin; 1334 int intnum; 1335 1336 /* 1337 * 1338 * The PCI standard defines a swizzle of the child-side device/intpin to 1339 * the parent-side intpin as follows. 1340 * 1341 * device = device on child bus 1342 * child_intpin = intpin on child bus slot (0-3) 1343 * parent_intpin = intpin on parent bus slot (0-3) 1344 * 1345 * parent_intpin = (device + child_intpin) % 4 1346 */ 1347 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1348 1349 /* 1350 * Our parent is a PCI bus. Its parent must export the pcib interface 1351 * which includes the ability to route interrupts. 1352 */ 1353 bus = device_get_parent(pcib); 1354 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1355 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1356 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1357 pci_get_slot(dev), 'A' + pin - 1, intnum); 1358 } 1359 return(intnum); 1360 } 1361 1362 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1363 int 1364 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1365 { 1366 struct pcib_softc *sc = device_get_softc(pcib); 1367 device_t bus; 1368 1369 if (sc->flags & PCIB_DISABLE_MSI) 1370 return (ENXIO); 1371 bus = device_get_parent(pcib); 1372 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1373 irqs)); 1374 } 1375 1376 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1377 int 1378 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1379 { 1380 device_t bus; 1381 1382 bus = device_get_parent(pcib); 1383 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1384 } 1385 1386 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 1387 int 1388 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1389 { 1390 struct pcib_softc *sc = device_get_softc(pcib); 1391 device_t bus; 1392 1393 if (sc->flags & PCIB_DISABLE_MSI) 1394 return (ENXIO); 1395 bus = device_get_parent(pcib); 1396 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1397 } 1398 1399 /* Pass request to release an MSI-X message up to the parent bridge. */ 1400 int 1401 pcib_release_msix(device_t pcib, device_t dev, int irq) 1402 { 1403 device_t bus; 1404 1405 bus = device_get_parent(pcib); 1406 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1407 } 1408 1409 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 1410 int 1411 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 1412 uint32_t *data) 1413 { 1414 device_t bus; 1415 int error; 1416 1417 bus = device_get_parent(pcib); 1418 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 1419 if (error) 1420 return (error); 1421 1422 pci_ht_map_msi(pcib, *addr); 1423 return (0); 1424 } 1425 1426 /* Pass request for device power state up to parent bridge. */ 1427 int 1428 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 1429 { 1430 device_t bus; 1431 1432 bus = device_get_parent(pcib); 1433 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 1434 } 1435 1436 /* 1437 * Try to read the bus number of a host-PCI bridge using appropriate config 1438 * registers. 1439 */ 1440 int 1441 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 1442 uint8_t *busnum) 1443 { 1444 uint32_t id; 1445 1446 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 1447 if (id == 0xffffffff) 1448 return (0); 1449 1450 switch (id) { 1451 case 0x12258086: 1452 /* Intel 824?? */ 1453 /* XXX This is a guess */ 1454 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 1455 *busnum = bus; 1456 break; 1457 case 0x84c48086: 1458 /* Intel 82454KX/GX (Orion) */ 1459 *busnum = read_config(bus, slot, func, 0x4a, 1); 1460 break; 1461 case 0x84ca8086: 1462 /* 1463 * For the 450nx chipset, there is a whole bundle of 1464 * things pretending to be host bridges. The MIOC will 1465 * be seen first and isn't really a pci bridge (the 1466 * actual busses are attached to the PXB's). We need to 1467 * read the registers of the MIOC to figure out the 1468 * bus numbers for the PXB channels. 1469 * 1470 * Since the MIOC doesn't have a pci bus attached, we 1471 * pretend it wasn't there. 1472 */ 1473 return (0); 1474 case 0x84cb8086: 1475 switch (slot) { 1476 case 0x12: 1477 /* Intel 82454NX PXB#0, Bus#A */ 1478 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 1479 break; 1480 case 0x13: 1481 /* Intel 82454NX PXB#0, Bus#B */ 1482 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 1483 break; 1484 case 0x14: 1485 /* Intel 82454NX PXB#1, Bus#A */ 1486 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 1487 break; 1488 case 0x15: 1489 /* Intel 82454NX PXB#1, Bus#B */ 1490 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 1491 break; 1492 } 1493 break; 1494 1495 /* ServerWorks -- vendor 0x1166 */ 1496 case 0x00051166: 1497 case 0x00061166: 1498 case 0x00081166: 1499 case 0x00091166: 1500 case 0x00101166: 1501 case 0x00111166: 1502 case 0x00171166: 1503 case 0x01011166: 1504 case 0x010f1014: 1505 case 0x01101166: 1506 case 0x02011166: 1507 case 0x02251166: 1508 case 0x03021014: 1509 *busnum = read_config(bus, slot, func, 0x44, 1); 1510 break; 1511 1512 /* Compaq/HP -- vendor 0x0e11 */ 1513 case 0x60100e11: 1514 *busnum = read_config(bus, slot, func, 0xc8, 1); 1515 break; 1516 default: 1517 /* Don't know how to read bus number. */ 1518 return 0; 1519 } 1520 1521 return 1; 1522 } 1523