1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <machine/resource.h> 46 47 #include <pci/pcivar.h> 48 #include <pci/pcireg.h> 49 #include <pci/pcib_private.h> 50 51 #include "pcib_if.h" 52 53 static int pcib_probe(device_t dev); 54 55 static device_method_t pcib_methods[] = { 56 /* Device interface */ 57 DEVMETHOD(device_probe, pcib_probe), 58 DEVMETHOD(device_attach, pcib_attach), 59 DEVMETHOD(device_shutdown, bus_generic_shutdown), 60 DEVMETHOD(device_suspend, bus_generic_suspend), 61 DEVMETHOD(device_resume, bus_generic_resume), 62 63 /* Bus interface */ 64 DEVMETHOD(bus_print_child, bus_generic_print_child), 65 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 66 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 68 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 73 74 /* pcib interface */ 75 DEVMETHOD(pcib_maxslots, pcib_maxslots), 76 DEVMETHOD(pcib_read_config, pcib_read_config), 77 DEVMETHOD(pcib_write_config, pcib_write_config), 78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 79 80 { 0, 0 } 81 }; 82 83 static driver_t pcib_driver = { 84 "pcib", 85 pcib_methods, 86 sizeof(struct pcib_softc), 87 }; 88 89 devclass_t pcib_devclass; 90 91 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 92 93 /* 94 * sysctl and tunable vars 95 */ 96 static int pci_allow_unsupported_io_range = 0; 97 TUNABLE_INT("hw.pci.allow_unsupported_io_range", 98 (int *)&pci_allow_unsupported_io_range); 99 SYSCTL_DECL(_hw_pci); 100 SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD, 101 &pci_allow_unsupported_io_range, 0, 102 "Allows the PCI Bridge to pass through an unsupported memory range " 103 "assigned by the BIOS."); 104 105 /* 106 * Generic device interface 107 */ 108 static int 109 pcib_probe(device_t dev) 110 { 111 if ((pci_get_class(dev) == PCIC_BRIDGE) && 112 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 113 device_set_desc(dev, "PCI-PCI bridge"); 114 return(-10000); 115 } 116 return(ENXIO); 117 } 118 119 void 120 pcib_attach_common(device_t dev) 121 { 122 struct pcib_softc *sc; 123 u_int8_t iolow; 124 125 sc = device_get_softc(dev); 126 sc->dev = dev; 127 128 /* 129 * Get current bridge configuration. 130 */ 131 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 132 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 133 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 134 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 135 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 136 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 137 138 /* 139 * Determine current I/O decode. 140 */ 141 if (sc->command & PCIM_CMD_PORTEN) { 142 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 143 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 144 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 145 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 146 } else { 147 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 148 } 149 150 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 151 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 152 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 153 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 154 } else { 155 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 156 } 157 } 158 159 /* 160 * Determine current memory decode. 161 */ 162 if (sc->command & PCIM_CMD_MEMEN) { 163 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 164 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 165 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 166 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 167 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 168 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 169 } 170 171 /* 172 * Quirk handling. 173 */ 174 switch (pci_get_devid(dev)) { 175 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 176 { 177 u_int8_t supbus; 178 179 supbus = pci_read_config(dev, 0x41, 1); 180 if (supbus != 0xff) { 181 sc->secbus = supbus + 1; 182 sc->subbus = supbus + 1; 183 } 184 } 185 break; 186 } 187 188 if (bootverbose) { 189 device_printf(dev, " secondary bus %d\n", sc->secbus); 190 device_printf(dev, " subordinate bus %d\n", sc->subbus); 191 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 192 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 193 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 194 } 195 196 /* 197 * XXX If the secondary bus number is zero, we should assign a bus number 198 * since the BIOS hasn't, then initialise the bridge. 199 */ 200 201 /* 202 * XXX If the subordinate bus number is less than the secondary bus number, 203 * we should pick a better value. One sensible alternative would be to 204 * pick 255; the only tradeoff here is that configuration transactions 205 * would be more widely routed than absolutely necessary. 206 */ 207 } 208 209 int 210 pcib_attach(device_t dev) 211 { 212 struct pcib_softc *sc; 213 device_t child; 214 215 pcib_attach_common(dev); 216 sc = device_get_softc(dev); 217 if (sc->secbus != 0) { 218 child = device_add_child(dev, "pci", sc->secbus); 219 if (child != NULL) 220 return(bus_generic_attach(dev)); 221 } 222 223 /* no secondary bus; we should have fixed this */ 224 return(0); 225 } 226 227 int 228 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 229 { 230 struct pcib_softc *sc = device_get_softc(dev); 231 232 switch (which) { 233 case PCIB_IVAR_BUS: 234 *result = sc->secbus; 235 return(0); 236 } 237 return(ENOENT); 238 } 239 240 int 241 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 242 { 243 struct pcib_softc *sc = device_get_softc(dev); 244 245 switch (which) { 246 case PCIB_IVAR_BUS: 247 sc->secbus = value; 248 break; 249 } 250 return(ENOENT); 251 } 252 253 /* 254 * Is this a decoded ISA I/O port address? Note, we need to do the mask that 255 * we do below because of the ISA alias addresses. I'm not 100% sure that 256 * this is correct. Maybe the bridge needs to be subtractive decode for 257 * this to work? 258 */ 259 static int 260 pcib_is_isa_io(u_long start) 261 { 262 if ((start & 0xfffUL) > 0x3ffUL || start == 0) 263 return (0); 264 return (1); 265 } 266 267 /* 268 * Is this a decoded ISA memory address? 269 */ 270 static int 271 pcib_is_isa_mem(u_long start) 272 { 273 if (start > 0xfffffUL || start == 0) 274 return (0); 275 return (1); 276 } 277 278 /* 279 * Is the prefetch window open (eg, can we allocate memory in it?) 280 */ 281 static int 282 pcib_is_prefetch_open(struct pcib_softc *sc) 283 { 284 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 285 } 286 287 /* 288 * Is the nonprefetch window open (eg, can we allocate memory in it?) 289 */ 290 static int 291 pcib_is_nonprefetch_open(struct pcib_softc *sc) 292 { 293 return (sc->membase > 0 && sc->membase < sc->memlimit); 294 } 295 296 /* 297 * Is the io window open (eg, can we allocate ports in it?) 298 */ 299 static int 300 pcib_is_io_open(struct pcib_softc *sc) 301 { 302 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 303 } 304 305 /* 306 * We have to trap resource allocation requests and ensure that the bridge 307 * is set up to, or capable of handling them. 308 */ 309 struct resource * 310 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 311 u_long start, u_long end, u_long count, u_int flags) 312 { 313 struct pcib_softc *sc = device_get_softc(dev); 314 int ok; 315 316 /* 317 * If this is a "default" allocation against this rid, we can't work 318 * out where it's coming from (we should actually never see these) so we 319 * just have to punt. 320 */ 321 if ((start == 0) && (end == ~0)) { 322 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 323 *rid, device_get_name(child), device_get_unit(child)); 324 } else { 325 /* 326 * Fail the allocation for this range if it's not supported. 327 */ 328 switch (type) { 329 case SYS_RES_IOPORT: 330 ok = 1; 331 if (!pcib_is_isa_io(start)) { 332 ok = 0; 333 if (pcib_is_io_open(sc)) 334 ok = (start >= sc->iobase && end <= sc->iolimit); 335 if (!pci_allow_unsupported_io_range) { 336 if (!ok) { 337 if (start < sc->iobase) 338 start = sc->iobase; 339 if (end > sc->iolimit) 340 end = sc->iolimit; 341 } 342 } else { 343 if (start < sc->iobase) 344 printf("start (%lx) < sc->iobase (%x)\n", start, 345 sc->iobase); 346 if (end > sc->iolimit) 347 printf("end (%lx) > sc->iolimit (%x)\n", 348 end, sc->iolimit); 349 if (end < start) 350 printf("end (%lx) < start (%lx)\n", end, start); 351 } 352 } 353 if (end < start) { 354 start = 0; 355 end = 0; 356 ok = 0; 357 } 358 if (!ok) { 359 device_printf(dev, "device %s%d requested unsupported I/O " 360 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 361 device_get_name(child), device_get_unit(child), start, end, 362 sc->iobase, sc->iolimit); 363 return (NULL); 364 } 365 if (bootverbose) 366 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 367 device_get_name(child), device_get_unit(child), start, end); 368 break; 369 370 case SYS_RES_MEMORY: 371 ok = 1; 372 if (!pcib_is_isa_mem(start)) { 373 ok = 0; 374 if (pcib_is_nonprefetch_open(sc)) 375 ok = ok || (start >= sc->membase && end <= sc->memlimit); 376 if (pcib_is_prefetch_open(sc)) 377 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 378 if (!pci_allow_unsupported_io_range) { 379 if (!ok) { 380 ok = 1; 381 if (flags & RF_PREFETCHABLE) { 382 if (pcib_is_prefetch_open(sc)) { 383 if (start < sc->pmembase) 384 start = sc->pmembase; 385 if (end > sc->pmemlimit) 386 end = sc->pmemlimit; 387 } else { 388 ok = 0; 389 } 390 } else { /* non-prefetchable */ 391 if (pcib_is_nonprefetch_open(sc)) { 392 if (start < sc->membase) 393 start = sc->membase; 394 if (end > sc->memlimit) 395 end = sc->memlimit; 396 } else { 397 ok = 0; 398 } 399 } 400 } 401 } else if (!ok) { 402 ok = 1; /* pci_allow_unsupported_ranges -> always ok */ 403 if (pcib_is_nonprefetch_open(sc)) { 404 if (start < sc->membase) 405 printf("start (%lx) < sc->membase (%x)\n", 406 start, sc->membase); 407 if (end > sc->memlimit) 408 printf("end (%lx) > sc->memlimit (%x)\n", 409 end, sc->memlimit); 410 } 411 if (pcib_is_prefetch_open(sc)) { 412 if (start < sc->pmembase) 413 printf("start (%lx) < sc->pmembase (%x)\n", 414 start, sc->pmembase); 415 if (end > sc->pmemlimit) 416 printf("end (%lx) > sc->pmemlimit (%x)\n", 417 end, sc->memlimit); 418 } 419 if (end < start) 420 printf("end (%lx) < start (%lx)\n", end, start); 421 } 422 } 423 if (end < start) { 424 start = 0; 425 end = 0; 426 ok = 0; 427 } 428 if (!ok && bootverbose) 429 device_printf(dev, 430 "device %s%d requested unsupported memory range " 431 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 432 device_get_name(child), device_get_unit(child), start, 433 end, sc->membase, sc->memlimit, sc->pmembase, 434 sc->pmemlimit); 435 if (!ok) 436 return (NULL); 437 if (bootverbose) 438 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 439 device_get_name(child), device_get_unit(child), start, end); 440 break; 441 442 default: 443 break; 444 } 445 } 446 447 /* 448 * Bridge is OK decoding this resource, so pass it up. 449 */ 450 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 451 } 452 453 /* 454 * PCIB interface. 455 */ 456 int 457 pcib_maxslots(device_t dev) 458 { 459 return(PCI_SLOTMAX); 460 } 461 462 /* 463 * Since we are a child of a PCI bus, its parent must support the pcib interface. 464 */ 465 u_int32_t 466 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 467 { 468 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 469 } 470 471 void 472 pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 473 { 474 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 475 } 476 477 /* 478 * Route an interrupt across a PCI bridge. 479 */ 480 int 481 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 482 { 483 device_t bus; 484 int parent_intpin; 485 int intnum; 486 487 /* 488 * 489 * The PCI standard defines a swizzle of the child-side device/intpin to 490 * the parent-side intpin as follows. 491 * 492 * device = device on child bus 493 * child_intpin = intpin on child bus slot (0-3) 494 * parent_intpin = intpin on parent bus slot (0-3) 495 * 496 * parent_intpin = (device + child_intpin) % 4 497 */ 498 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 499 500 /* 501 * Our parent is a PCI bus. Its parent must export the pcib interface 502 * which includes the ability to route interrupts. 503 */ 504 bus = device_get_parent(pcib); 505 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 506 if (PCI_INTERRUPT_VALID(intnum)) { 507 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 508 pci_get_slot(dev), 'A' + pin - 1, intnum); 509 } 510 return(intnum); 511 } 512 513 /* 514 * Try to read the bus number of a host-PCI bridge using appropriate config 515 * registers. 516 */ 517 int 518 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 519 u_int8_t *busnum) 520 { 521 u_int32_t id; 522 523 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 524 if (id == 0xffffffff) 525 return (0); 526 527 switch (id) { 528 case 0x12258086: 529 /* Intel 824?? */ 530 /* XXX This is a guess */ 531 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 532 *busnum = bus; 533 break; 534 case 0x84c48086: 535 /* Intel 82454KX/GX (Orion) */ 536 *busnum = read_config(bus, slot, func, 0x4a, 1); 537 break; 538 case 0x84ca8086: 539 /* 540 * For the 450nx chipset, there is a whole bundle of 541 * things pretending to be host bridges. The MIOC will 542 * be seen first and isn't really a pci bridge (the 543 * actual busses are attached to the PXB's). We need to 544 * read the registers of the MIOC to figure out the 545 * bus numbers for the PXB channels. 546 * 547 * Since the MIOC doesn't have a pci bus attached, we 548 * pretend it wasn't there. 549 */ 550 return (0); 551 case 0x84cb8086: 552 switch (slot) { 553 case 0x12: 554 /* Intel 82454NX PXB#0, Bus#A */ 555 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 556 break; 557 case 0x13: 558 /* Intel 82454NX PXB#0, Bus#B */ 559 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 560 break; 561 case 0x14: 562 /* Intel 82454NX PXB#1, Bus#A */ 563 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 564 break; 565 case 0x15: 566 /* Intel 82454NX PXB#1, Bus#B */ 567 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 568 break; 569 } 570 break; 571 572 /* ServerWorks -- vendor 0x1166 */ 573 case 0x00051166: 574 case 0x00061166: 575 case 0x00081166: 576 case 0x00091166: 577 case 0x00101166: 578 case 0x00111166: 579 case 0x00171166: 580 case 0x01011166: 581 case 0x010f1014: 582 case 0x02011166: 583 case 0x03021014: 584 *busnum = read_config(bus, slot, func, 0x44, 1); 585 break; 586 default: 587 /* Don't know how to read bus number. */ 588 return 0; 589 } 590 591 return 1; 592 } 593