1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pci_private.h> 50 #include <dev/pci/pcib_private.h> 51 52 #include "pcib_if.h" 53 54 static int pcib_probe(device_t dev); 55 static int pcib_suspend(device_t dev); 56 static int pcib_resume(device_t dev); 57 static int pcib_power_for_sleep(device_t pcib, device_t dev, 58 int *pstate); 59 static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev); 60 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 61 u_int f, u_int reg, int width); 62 static void pcib_write_config(device_t dev, u_int b, u_int s, 63 u_int f, u_int reg, uint32_t val, int width); 64 static int pcib_ari_maxslots(device_t dev); 65 static int pcib_ari_maxfuncs(device_t dev); 66 static int pcib_try_enable_ari(device_t pcib, device_t dev); 67 68 static device_method_t pcib_methods[] = { 69 /* Device interface */ 70 DEVMETHOD(device_probe, pcib_probe), 71 DEVMETHOD(device_attach, pcib_attach), 72 DEVMETHOD(device_detach, bus_generic_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD(device_suspend, pcib_suspend), 75 DEVMETHOD(device_resume, pcib_resume), 76 77 /* Bus interface */ 78 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 79 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 80 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 81 #ifdef NEW_PCIB 82 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 83 DEVMETHOD(bus_release_resource, pcib_release_resource), 84 #else 85 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 86 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 87 #endif 88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 92 93 /* pcib interface */ 94 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 95 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 96 DEVMETHOD(pcib_read_config, pcib_read_config), 97 DEVMETHOD(pcib_write_config, pcib_write_config), 98 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 99 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 100 DEVMETHOD(pcib_release_msi, pcib_release_msi), 101 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 102 DEVMETHOD(pcib_release_msix, pcib_release_msix), 103 DEVMETHOD(pcib_map_msi, pcib_map_msi), 104 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 105 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid), 106 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 107 108 DEVMETHOD_END 109 }; 110 111 static devclass_t pcib_devclass; 112 113 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 114 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 115 116 #ifdef NEW_PCIB 117 SYSCTL_DECL(_hw_pci); 118 119 static int pci_clear_pcib; 120 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 121 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 122 123 /* 124 * Is a resource from a child device sub-allocated from one of our 125 * resource managers? 126 */ 127 static int 128 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 129 { 130 131 switch (type) { 132 #ifdef PCI_RES_BUS 133 case PCI_RES_BUS: 134 return (rman_is_region_manager(r, &sc->bus.rman)); 135 #endif 136 case SYS_RES_IOPORT: 137 return (rman_is_region_manager(r, &sc->io.rman)); 138 case SYS_RES_MEMORY: 139 /* Prefetchable resources may live in either memory rman. */ 140 if (rman_get_flags(r) & RF_PREFETCHABLE && 141 rman_is_region_manager(r, &sc->pmem.rman)) 142 return (1); 143 return (rman_is_region_manager(r, &sc->mem.rman)); 144 } 145 return (0); 146 } 147 148 static int 149 pcib_is_window_open(struct pcib_window *pw) 150 { 151 152 return (pw->valid && pw->base < pw->limit); 153 } 154 155 /* 156 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 157 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 158 * when allocating the resource windows and rely on the PCI bus driver 159 * to do this for us. 160 */ 161 static void 162 pcib_activate_window(struct pcib_softc *sc, int type) 163 { 164 165 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 166 } 167 168 static void 169 pcib_write_windows(struct pcib_softc *sc, int mask) 170 { 171 device_t dev; 172 uint32_t val; 173 174 dev = sc->dev; 175 if (sc->io.valid && mask & WIN_IO) { 176 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 177 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 178 pci_write_config(dev, PCIR_IOBASEH_1, 179 sc->io.base >> 16, 2); 180 pci_write_config(dev, PCIR_IOLIMITH_1, 181 sc->io.limit >> 16, 2); 182 } 183 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 184 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 185 } 186 187 if (mask & WIN_MEM) { 188 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 189 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 190 } 191 192 if (sc->pmem.valid && mask & WIN_PMEM) { 193 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 194 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 195 pci_write_config(dev, PCIR_PMBASEH_1, 196 sc->pmem.base >> 32, 4); 197 pci_write_config(dev, PCIR_PMLIMITH_1, 198 sc->pmem.limit >> 32, 4); 199 } 200 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 201 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 202 } 203 } 204 205 /* 206 * This is used to reject I/O port allocations that conflict with an 207 * ISA alias range. 208 */ 209 static int 210 pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count) 211 { 212 u_long next_alias; 213 214 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 215 return (0); 216 217 /* Only check fixed ranges for overlap. */ 218 if (start + count - 1 != end) 219 return (0); 220 221 /* ISA aliases are only in the lower 64KB of I/O space. */ 222 if (start >= 65536) 223 return (0); 224 225 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 226 if (start < 0x100) 227 goto alias; 228 229 /* 230 * If the start address is an alias, the range is an alias. 231 * Otherwise, compute the start of the next alias range and 232 * check if it is before the end of the candidate range. 233 */ 234 if ((start & 0x300) != 0) 235 goto alias; 236 next_alias = (start & ~0x3fful) | 0x100; 237 if (next_alias <= end) 238 goto alias; 239 return (0); 240 241 alias: 242 if (bootverbose) 243 device_printf(sc->dev, 244 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start, 245 end); 246 return (1); 247 } 248 249 static void 250 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 251 int count) 252 { 253 struct resource **newarray; 254 int error, i; 255 256 newarray = malloc(sizeof(struct resource *) * (w->count + count), 257 M_DEVBUF, M_WAITOK); 258 if (w->res != NULL) 259 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 260 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 261 free(w->res, M_DEVBUF); 262 w->res = newarray; 263 w->count += count; 264 265 for (i = 0; i < count; i++) { 266 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 267 rman_get_end(res[i])); 268 if (error) 269 panic("Failed to add resource to rman"); 270 } 271 } 272 273 typedef void (nonisa_callback)(u_long start, u_long end, void *arg); 274 275 static void 276 pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb, 277 void *arg) 278 { 279 u_long next_end; 280 281 /* 282 * If start is within an ISA alias range, move up to the start 283 * of the next non-alias range. As a special case, addresses 284 * in the range 0x000 - 0x0ff should also be skipped since 285 * those are used for various system I/O devices in ISA 286 * systems. 287 */ 288 if (start <= 65535) { 289 if (start < 0x100 || (start & 0x300) != 0) { 290 start &= ~0x3ff; 291 start += 0x400; 292 } 293 } 294 295 /* ISA aliases are only in the lower 64KB of I/O space. */ 296 while (start <= MIN(end, 65535)) { 297 next_end = MIN(start | 0xff, end); 298 cb(start, next_end, arg); 299 start += 0x400; 300 } 301 302 if (start <= end) 303 cb(start, end, arg); 304 } 305 306 static void 307 count_ranges(u_long start, u_long end, void *arg) 308 { 309 int *countp; 310 311 countp = arg; 312 (*countp)++; 313 } 314 315 struct alloc_state { 316 struct resource **res; 317 struct pcib_softc *sc; 318 int count, error; 319 }; 320 321 static void 322 alloc_ranges(u_long start, u_long end, void *arg) 323 { 324 struct alloc_state *as; 325 struct pcib_window *w; 326 int rid; 327 328 as = arg; 329 if (as->error != 0) 330 return; 331 332 w = &as->sc->io; 333 rid = w->reg; 334 if (bootverbose) 335 device_printf(as->sc->dev, 336 "allocating non-ISA range %#lx-%#lx\n", start, end); 337 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 338 &rid, start, end, end - start + 1, 0); 339 if (as->res[as->count] == NULL) 340 as->error = ENXIO; 341 else 342 as->count++; 343 } 344 345 static int 346 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end) 347 { 348 struct alloc_state as; 349 int i, new_count; 350 351 /* First, see how many ranges we need. */ 352 new_count = 0; 353 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 354 355 /* Second, allocate the ranges. */ 356 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 357 M_WAITOK); 358 as.sc = sc; 359 as.count = 0; 360 as.error = 0; 361 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 362 if (as.error != 0) { 363 for (i = 0; i < as.count; i++) 364 bus_release_resource(sc->dev, SYS_RES_IOPORT, 365 sc->io.reg, as.res[i]); 366 free(as.res, M_DEVBUF); 367 return (as.error); 368 } 369 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 370 371 /* Third, add the ranges to the window. */ 372 pcib_add_window_resources(&sc->io, as.res, as.count); 373 free(as.res, M_DEVBUF); 374 return (0); 375 } 376 377 static void 378 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 379 int flags, pci_addr_t max_address) 380 { 381 struct resource *res; 382 char buf[64]; 383 int error, rid; 384 385 if (max_address != (u_long)max_address) 386 max_address = ~0ul; 387 w->rman.rm_start = 0; 388 w->rman.rm_end = max_address; 389 w->rman.rm_type = RMAN_ARRAY; 390 snprintf(buf, sizeof(buf), "%s %s window", 391 device_get_nameunit(sc->dev), w->name); 392 w->rman.rm_descr = strdup(buf, M_DEVBUF); 393 error = rman_init(&w->rman); 394 if (error) 395 panic("Failed to initialize %s %s rman", 396 device_get_nameunit(sc->dev), w->name); 397 398 if (!pcib_is_window_open(w)) 399 return; 400 401 if (w->base > max_address || w->limit > max_address) { 402 device_printf(sc->dev, 403 "initial %s window has too many bits, ignoring\n", w->name); 404 return; 405 } 406 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 407 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 408 else { 409 rid = w->reg; 410 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 411 w->limit - w->base + 1, flags); 412 if (res != NULL) 413 pcib_add_window_resources(w, &res, 1); 414 } 415 if (w->res == NULL) { 416 device_printf(sc->dev, 417 "failed to allocate initial %s window: %#jx-%#jx\n", 418 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 419 w->base = max_address; 420 w->limit = 0; 421 pcib_write_windows(sc, w->mask); 422 return; 423 } 424 pcib_activate_window(sc, type); 425 } 426 427 /* 428 * Initialize I/O windows. 429 */ 430 static void 431 pcib_probe_windows(struct pcib_softc *sc) 432 { 433 pci_addr_t max; 434 device_t dev; 435 uint32_t val; 436 437 dev = sc->dev; 438 439 if (pci_clear_pcib) { 440 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 441 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 442 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 443 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 444 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 445 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 446 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 447 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 448 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 449 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 450 } 451 452 /* Determine if the I/O port window is implemented. */ 453 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 454 if (val == 0) { 455 /* 456 * If 'val' is zero, then only 16-bits of I/O space 457 * are supported. 458 */ 459 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 460 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 461 sc->io.valid = 1; 462 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 463 } 464 } else 465 sc->io.valid = 1; 466 467 /* Read the existing I/O port window. */ 468 if (sc->io.valid) { 469 sc->io.reg = PCIR_IOBASEL_1; 470 sc->io.step = 12; 471 sc->io.mask = WIN_IO; 472 sc->io.name = "I/O port"; 473 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 474 sc->io.base = PCI_PPBIOBASE( 475 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 476 sc->io.limit = PCI_PPBIOLIMIT( 477 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 478 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 479 max = 0xffffffff; 480 } else { 481 sc->io.base = PCI_PPBIOBASE(0, val); 482 sc->io.limit = PCI_PPBIOLIMIT(0, 483 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 484 max = 0xffff; 485 } 486 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 487 } 488 489 /* Read the existing memory window. */ 490 sc->mem.valid = 1; 491 sc->mem.reg = PCIR_MEMBASE_1; 492 sc->mem.step = 20; 493 sc->mem.mask = WIN_MEM; 494 sc->mem.name = "memory"; 495 sc->mem.base = PCI_PPBMEMBASE(0, 496 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 497 sc->mem.limit = PCI_PPBMEMLIMIT(0, 498 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 499 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 500 501 /* Determine if the prefetchable memory window is implemented. */ 502 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 503 if (val == 0) { 504 /* 505 * If 'val' is zero, then only 32-bits of memory space 506 * are supported. 507 */ 508 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 509 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 510 sc->pmem.valid = 1; 511 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 512 } 513 } else 514 sc->pmem.valid = 1; 515 516 /* Read the existing prefetchable memory window. */ 517 if (sc->pmem.valid) { 518 sc->pmem.reg = PCIR_PMBASEL_1; 519 sc->pmem.step = 20; 520 sc->pmem.mask = WIN_PMEM; 521 sc->pmem.name = "prefetch"; 522 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 523 sc->pmem.base = PCI_PPBMEMBASE( 524 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 525 sc->pmem.limit = PCI_PPBMEMLIMIT( 526 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 527 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 528 max = 0xffffffffffffffff; 529 } else { 530 sc->pmem.base = PCI_PPBMEMBASE(0, val); 531 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 532 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 533 max = 0xffffffff; 534 } 535 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 536 RF_PREFETCHABLE, max); 537 } 538 } 539 540 #ifdef PCI_RES_BUS 541 /* 542 * Allocate a suitable secondary bus for this bridge if needed and 543 * initialize the resource manager for the secondary bus range. Note 544 * that the minimum count is a desired value and this may allocate a 545 * smaller range. 546 */ 547 void 548 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 549 { 550 char buf[64]; 551 int error, rid; 552 553 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 554 case PCIM_HDRTYPE_BRIDGE: 555 bus->sub_reg = PCIR_SUBBUS_1; 556 break; 557 case PCIM_HDRTYPE_CARDBUS: 558 bus->sub_reg = PCIR_SUBBUS_2; 559 break; 560 default: 561 panic("not a PCI bridge"); 562 } 563 bus->dev = dev; 564 bus->rman.rm_start = 0; 565 bus->rman.rm_end = PCI_BUSMAX; 566 bus->rman.rm_type = RMAN_ARRAY; 567 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 568 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 569 error = rman_init(&bus->rman); 570 if (error) 571 panic("Failed to initialize %s bus number rman", 572 device_get_nameunit(dev)); 573 574 /* 575 * Allocate a bus range. This will return an existing bus range 576 * if one exists, or a new bus range if one does not. 577 */ 578 rid = 0; 579 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul, 580 min_count, 0); 581 if (bus->res == NULL) { 582 /* 583 * Fall back to just allocating a range of a single bus 584 * number. 585 */ 586 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul, 587 1, 0); 588 } else if (rman_get_size(bus->res) < min_count) 589 /* 590 * Attempt to grow the existing range to satisfy the 591 * minimum desired count. 592 */ 593 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 594 rman_get_start(bus->res), rman_get_start(bus->res) + 595 min_count - 1); 596 597 /* 598 * Add the initial resource to the rman. 599 */ 600 if (bus->res != NULL) { 601 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 602 rman_get_end(bus->res)); 603 if (error) 604 panic("Failed to add resource to rman"); 605 bus->sec = rman_get_start(bus->res); 606 bus->sub = rman_get_end(bus->res); 607 } 608 } 609 610 static struct resource * 611 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 612 u_long start, u_long end, u_long count, u_int flags) 613 { 614 struct resource *res; 615 616 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 617 child); 618 if (res == NULL) 619 return (NULL); 620 621 if (bootverbose) 622 device_printf(bus->dev, 623 "allocated bus range (%lu-%lu) for rid %d of %s\n", 624 rman_get_start(res), rman_get_end(res), *rid, 625 pcib_child_name(child)); 626 rman_set_rid(res, *rid); 627 return (res); 628 } 629 630 /* 631 * Attempt to grow the secondary bus range. This is much simpler than 632 * for I/O windows as the range can only be grown by increasing 633 * subbus. 634 */ 635 static int 636 pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end) 637 { 638 u_long old_end; 639 int error; 640 641 old_end = rman_get_end(bus->res); 642 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 643 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 644 rman_get_start(bus->res), new_end); 645 if (error) 646 return (error); 647 if (bootverbose) 648 device_printf(bus->dev, "grew bus range to %lu-%lu\n", 649 rman_get_start(bus->res), rman_get_end(bus->res)); 650 error = rman_manage_region(&bus->rman, old_end + 1, 651 rman_get_end(bus->res)); 652 if (error) 653 panic("Failed to add resource to rman"); 654 bus->sub = rman_get_end(bus->res); 655 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 656 return (0); 657 } 658 659 struct resource * 660 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 661 u_long start, u_long end, u_long count, u_int flags) 662 { 663 struct resource *res; 664 u_long start_free, end_free, new_end; 665 666 /* 667 * First, see if the request can be satisified by the existing 668 * bus range. 669 */ 670 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 671 if (res != NULL) 672 return (res); 673 674 /* 675 * Figure out a range to grow the bus range. First, find the 676 * first bus number after the last allocated bus in the rman and 677 * enforce that as a minimum starting point for the range. 678 */ 679 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 680 end_free != bus->sub) 681 start_free = bus->sub + 1; 682 if (start_free < start) 683 start_free = start; 684 new_end = start_free + count - 1; 685 686 /* 687 * See if this new range would satisfy the request if it 688 * succeeds. 689 */ 690 if (new_end > end) 691 return (NULL); 692 693 /* Finally, attempt to grow the existing resource. */ 694 if (bootverbose) { 695 device_printf(bus->dev, 696 "attempting to grow bus range for %lu buses\n", count); 697 printf("\tback candidate range: %lu-%lu\n", start_free, 698 new_end); 699 } 700 if (pcib_grow_subbus(bus, new_end) == 0) 701 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 702 flags)); 703 return (NULL); 704 } 705 #endif 706 707 #else 708 709 /* 710 * Is the prefetch window open (eg, can we allocate memory in it?) 711 */ 712 static int 713 pcib_is_prefetch_open(struct pcib_softc *sc) 714 { 715 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 716 } 717 718 /* 719 * Is the nonprefetch window open (eg, can we allocate memory in it?) 720 */ 721 static int 722 pcib_is_nonprefetch_open(struct pcib_softc *sc) 723 { 724 return (sc->membase > 0 && sc->membase < sc->memlimit); 725 } 726 727 /* 728 * Is the io window open (eg, can we allocate ports in it?) 729 */ 730 static int 731 pcib_is_io_open(struct pcib_softc *sc) 732 { 733 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 734 } 735 736 /* 737 * Get current I/O decode. 738 */ 739 static void 740 pcib_get_io_decode(struct pcib_softc *sc) 741 { 742 device_t dev; 743 uint32_t iolow; 744 745 dev = sc->dev; 746 747 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 748 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 749 sc->iobase = PCI_PPBIOBASE( 750 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 751 else 752 sc->iobase = PCI_PPBIOBASE(0, iolow); 753 754 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 755 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 756 sc->iolimit = PCI_PPBIOLIMIT( 757 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 758 else 759 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 760 } 761 762 /* 763 * Get current memory decode. 764 */ 765 static void 766 pcib_get_mem_decode(struct pcib_softc *sc) 767 { 768 device_t dev; 769 pci_addr_t pmemlow; 770 771 dev = sc->dev; 772 773 sc->membase = PCI_PPBMEMBASE(0, 774 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 775 sc->memlimit = PCI_PPBMEMLIMIT(0, 776 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 777 778 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 779 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 780 sc->pmembase = PCI_PPBMEMBASE( 781 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 782 else 783 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 784 785 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 786 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 787 sc->pmemlimit = PCI_PPBMEMLIMIT( 788 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 789 else 790 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 791 } 792 793 /* 794 * Restore previous I/O decode. 795 */ 796 static void 797 pcib_set_io_decode(struct pcib_softc *sc) 798 { 799 device_t dev; 800 uint32_t iohi; 801 802 dev = sc->dev; 803 804 iohi = sc->iobase >> 16; 805 if (iohi > 0) 806 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 807 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 808 809 iohi = sc->iolimit >> 16; 810 if (iohi > 0) 811 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 812 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 813 } 814 815 /* 816 * Restore previous memory decode. 817 */ 818 static void 819 pcib_set_mem_decode(struct pcib_softc *sc) 820 { 821 device_t dev; 822 pci_addr_t pmemhi; 823 824 dev = sc->dev; 825 826 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 827 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 828 829 pmemhi = sc->pmembase >> 32; 830 if (pmemhi > 0) 831 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 832 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 833 834 pmemhi = sc->pmemlimit >> 32; 835 if (pmemhi > 0) 836 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 837 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 838 } 839 #endif 840 841 /* 842 * Get current bridge configuration. 843 */ 844 static void 845 pcib_cfg_save(struct pcib_softc *sc) 846 { 847 device_t dev; 848 849 dev = sc->dev; 850 851 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 852 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 853 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 854 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 855 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 856 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 857 #ifndef NEW_PCIB 858 if (sc->command & PCIM_CMD_PORTEN) 859 pcib_get_io_decode(sc); 860 if (sc->command & PCIM_CMD_MEMEN) 861 pcib_get_mem_decode(sc); 862 #endif 863 } 864 865 /* 866 * Restore previous bridge configuration. 867 */ 868 static void 869 pcib_cfg_restore(struct pcib_softc *sc) 870 { 871 device_t dev; 872 873 dev = sc->dev; 874 875 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 876 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 877 pci_write_config(dev, PCIR_SECBUS_1, sc->bus.sec, 1); 878 pci_write_config(dev, PCIR_SUBBUS_1, sc->bus.sub, 1); 879 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 880 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 881 #ifdef NEW_PCIB 882 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 883 #else 884 if (sc->command & PCIM_CMD_PORTEN) 885 pcib_set_io_decode(sc); 886 if (sc->command & PCIM_CMD_MEMEN) 887 pcib_set_mem_decode(sc); 888 #endif 889 } 890 891 /* 892 * Generic device interface 893 */ 894 static int 895 pcib_probe(device_t dev) 896 { 897 if ((pci_get_class(dev) == PCIC_BRIDGE) && 898 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 899 device_set_desc(dev, "PCI-PCI bridge"); 900 return(-10000); 901 } 902 return(ENXIO); 903 } 904 905 void 906 pcib_attach_common(device_t dev) 907 { 908 struct pcib_softc *sc; 909 struct sysctl_ctx_list *sctx; 910 struct sysctl_oid *soid; 911 int comma; 912 913 sc = device_get_softc(dev); 914 sc->dev = dev; 915 916 /* 917 * Get current bridge configuration. 918 */ 919 sc->domain = pci_get_domain(dev); 920 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 921 pcib_cfg_save(sc); 922 923 /* 924 * The primary bus register should always be the bus of the 925 * parent. 926 */ 927 sc->pribus = pci_get_bus(dev); 928 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 929 930 /* 931 * Setup sysctl reporting nodes 932 */ 933 sctx = device_get_sysctl_ctx(dev); 934 soid = device_get_sysctl_tree(dev); 935 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 936 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 937 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 938 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 939 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 940 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 941 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 942 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 943 944 /* 945 * Quirk handling. 946 */ 947 switch (pci_get_devid(dev)) { 948 #if !defined(NEW_PCIB) && !defined(PCI_RES_BUS) 949 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 950 { 951 uint8_t supbus; 952 953 supbus = pci_read_config(dev, 0x41, 1); 954 if (supbus != 0xff) { 955 sc->bus.sec = supbus + 1; 956 sc->bus.sub = supbus + 1; 957 } 958 break; 959 } 960 #endif 961 962 /* 963 * The i82380FB mobile docking controller is a PCI-PCI bridge, 964 * and it is a subtractive bridge. However, the ProgIf is wrong 965 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 966 * happen. There's also a Toshiba bridge that behaves this 967 * way. 968 */ 969 case 0x124b8086: /* Intel 82380FB Mobile */ 970 case 0x060513d7: /* Toshiba ???? */ 971 sc->flags |= PCIB_SUBTRACTIVE; 972 break; 973 974 #if !defined(NEW_PCIB) && !defined(PCI_RES_BUS) 975 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 976 case 0x00dd10de: 977 { 978 char *cp; 979 980 if ((cp = getenv("smbios.planar.maker")) == NULL) 981 break; 982 if (strncmp(cp, "Compal", 6) != 0) { 983 freeenv(cp); 984 break; 985 } 986 freeenv(cp); 987 if ((cp = getenv("smbios.planar.product")) == NULL) 988 break; 989 if (strncmp(cp, "08A0", 4) != 0) { 990 freeenv(cp); 991 break; 992 } 993 freeenv(cp); 994 if (sc->bus.sub < 0xa) { 995 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 996 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 997 } 998 break; 999 } 1000 #endif 1001 } 1002 1003 if (pci_msi_device_blacklisted(dev)) 1004 sc->flags |= PCIB_DISABLE_MSI; 1005 1006 if (pci_msix_device_blacklisted(dev)) 1007 sc->flags |= PCIB_DISABLE_MSIX; 1008 1009 /* 1010 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1011 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1012 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1013 * This means they act as if they were subtractively decoding 1014 * bridges and pass all transactions. Mark them and real ProgIf 1 1015 * parts as subtractive. 1016 */ 1017 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1018 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1019 sc->flags |= PCIB_SUBTRACTIVE; 1020 1021 #ifdef NEW_PCIB 1022 #ifdef PCI_RES_BUS 1023 pcib_setup_secbus(dev, &sc->bus, 1); 1024 #endif 1025 pcib_probe_windows(sc); 1026 #endif 1027 if (bootverbose) { 1028 device_printf(dev, " domain %d\n", sc->domain); 1029 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1030 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1031 #ifdef NEW_PCIB 1032 if (pcib_is_window_open(&sc->io)) 1033 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1034 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1035 if (pcib_is_window_open(&sc->mem)) 1036 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1037 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1038 if (pcib_is_window_open(&sc->pmem)) 1039 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1040 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1041 #else 1042 if (pcib_is_io_open(sc)) 1043 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1044 sc->iobase, sc->iolimit); 1045 if (pcib_is_nonprefetch_open(sc)) 1046 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1047 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1048 if (pcib_is_prefetch_open(sc)) 1049 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1050 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1051 #endif 1052 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1053 sc->flags & PCIB_SUBTRACTIVE) { 1054 device_printf(dev, " special decode "); 1055 comma = 0; 1056 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1057 printf("ISA"); 1058 comma = 1; 1059 } 1060 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1061 printf("%sVGA", comma ? ", " : ""); 1062 comma = 1; 1063 } 1064 if (sc->flags & PCIB_SUBTRACTIVE) 1065 printf("%ssubtractive", comma ? ", " : ""); 1066 printf("\n"); 1067 } 1068 } 1069 1070 /* 1071 * Always enable busmastering on bridges so that transactions 1072 * initiated on the secondary bus are passed through to the 1073 * primary bus. 1074 */ 1075 pci_enable_busmaster(dev); 1076 } 1077 1078 int 1079 pcib_attach(device_t dev) 1080 { 1081 struct pcib_softc *sc; 1082 device_t child; 1083 1084 pcib_attach_common(dev); 1085 sc = device_get_softc(dev); 1086 if (sc->bus.sec != 0) { 1087 child = device_add_child(dev, "pci", sc->bus.sec); 1088 if (child != NULL) 1089 return(bus_generic_attach(dev)); 1090 } 1091 1092 /* no secondary bus; we should have fixed this */ 1093 return(0); 1094 } 1095 1096 int 1097 pcib_suspend(device_t dev) 1098 { 1099 device_t pcib; 1100 int dstate, error; 1101 1102 pcib_cfg_save(device_get_softc(dev)); 1103 error = bus_generic_suspend(dev); 1104 if (error == 0 && pci_do_power_suspend) { 1105 dstate = PCI_POWERSTATE_D3; 1106 pcib = device_get_parent(device_get_parent(dev)); 1107 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 1108 pci_set_powerstate(dev, dstate); 1109 } 1110 return (error); 1111 } 1112 1113 int 1114 pcib_resume(device_t dev) 1115 { 1116 device_t pcib; 1117 1118 if (pci_do_power_resume) { 1119 pcib = device_get_parent(device_get_parent(dev)); 1120 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 1121 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1122 } 1123 pcib_cfg_restore(device_get_softc(dev)); 1124 return (bus_generic_resume(dev)); 1125 } 1126 1127 int 1128 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1129 { 1130 struct pcib_softc *sc = device_get_softc(dev); 1131 1132 switch (which) { 1133 case PCIB_IVAR_DOMAIN: 1134 *result = sc->domain; 1135 return(0); 1136 case PCIB_IVAR_BUS: 1137 *result = sc->bus.sec; 1138 return(0); 1139 } 1140 return(ENOENT); 1141 } 1142 1143 int 1144 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1145 { 1146 1147 switch (which) { 1148 case PCIB_IVAR_DOMAIN: 1149 return(EINVAL); 1150 case PCIB_IVAR_BUS: 1151 return(EINVAL); 1152 } 1153 return(ENOENT); 1154 } 1155 1156 #ifdef NEW_PCIB 1157 /* 1158 * Attempt to allocate a resource from the existing resources assigned 1159 * to a window. 1160 */ 1161 static struct resource * 1162 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1163 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 1164 u_int flags) 1165 { 1166 struct resource *res; 1167 1168 if (!pcib_is_window_open(w)) 1169 return (NULL); 1170 1171 res = rman_reserve_resource(&w->rman, start, end, count, 1172 flags & ~RF_ACTIVE, child); 1173 if (res == NULL) 1174 return (NULL); 1175 1176 if (bootverbose) 1177 device_printf(sc->dev, 1178 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 1179 w->name, rman_get_start(res), rman_get_end(res), *rid, 1180 pcib_child_name(child)); 1181 rman_set_rid(res, *rid); 1182 1183 /* 1184 * If the resource should be active, pass that request up the 1185 * tree. This assumes the parent drivers can handle 1186 * activating sub-allocated resources. 1187 */ 1188 if (flags & RF_ACTIVE) { 1189 if (bus_activate_resource(child, type, *rid, res) != 0) { 1190 rman_release_resource(res); 1191 return (NULL); 1192 } 1193 } 1194 1195 return (res); 1196 } 1197 1198 /* Allocate a fresh resource range for an unconfigured window. */ 1199 static int 1200 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1201 u_long start, u_long end, u_long count, u_int flags) 1202 { 1203 struct resource *res; 1204 u_long base, limit, wmask; 1205 int rid; 1206 1207 /* 1208 * If this is an I/O window on a bridge with ISA enable set 1209 * and the start address is below 64k, then try to allocate an 1210 * initial window of 0x1000 bytes long starting at address 1211 * 0xf000 and walking down. Note that if the original request 1212 * was larger than the non-aliased range size of 0x100 our 1213 * caller would have raised the start address up to 64k 1214 * already. 1215 */ 1216 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1217 start < 65536) { 1218 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1219 limit = base + 0xfff; 1220 1221 /* 1222 * Skip ranges that wouldn't work for the 1223 * original request. Note that the actual 1224 * window that overlaps are the non-alias 1225 * ranges within [base, limit], so this isn't 1226 * quite a simple comparison. 1227 */ 1228 if (start + count > limit - 0x400) 1229 continue; 1230 if (base == 0) { 1231 /* 1232 * The first open region for the window at 1233 * 0 is 0x400-0x4ff. 1234 */ 1235 if (end - count + 1 < 0x400) 1236 continue; 1237 } else { 1238 if (end - count + 1 < base) 1239 continue; 1240 } 1241 1242 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1243 w->base = base; 1244 w->limit = limit; 1245 return (0); 1246 } 1247 } 1248 return (ENOSPC); 1249 } 1250 1251 wmask = (1ul << w->step) - 1; 1252 if (RF_ALIGNMENT(flags) < w->step) { 1253 flags &= ~RF_ALIGNMENT_MASK; 1254 flags |= RF_ALIGNMENT_LOG2(w->step); 1255 } 1256 start &= ~wmask; 1257 end |= wmask; 1258 count = roundup2(count, 1ul << w->step); 1259 rid = w->reg; 1260 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1261 flags & ~RF_ACTIVE); 1262 if (res == NULL) 1263 return (ENOSPC); 1264 pcib_add_window_resources(w, &res, 1); 1265 pcib_activate_window(sc, type); 1266 w->base = rman_get_start(res); 1267 w->limit = rman_get_end(res); 1268 return (0); 1269 } 1270 1271 /* Try to expand an existing window to the requested base and limit. */ 1272 static int 1273 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1274 u_long base, u_long limit) 1275 { 1276 struct resource *res; 1277 int error, i, force_64k_base; 1278 1279 KASSERT(base <= w->base && limit >= w->limit, 1280 ("attempting to shrink window")); 1281 1282 /* 1283 * XXX: pcib_grow_window() doesn't try to do this anyway and 1284 * the error handling for all the edge cases would be tedious. 1285 */ 1286 KASSERT(limit == w->limit || base == w->base, 1287 ("attempting to grow both ends of a window")); 1288 1289 /* 1290 * Yet more special handling for requests to expand an I/O 1291 * window behind an ISA-enabled bridge. Since I/O windows 1292 * have to grow in 0x1000 increments and the end of the 0xffff 1293 * range is an alias, growing a window below 64k will always 1294 * result in allocating new resources and never adjusting an 1295 * existing resource. 1296 */ 1297 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1298 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1299 KASSERT(limit == w->limit || limit <= 65535, 1300 ("attempting to grow both ends across 64k ISA alias")); 1301 1302 if (base != w->base) 1303 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1304 else 1305 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1306 limit); 1307 if (error == 0) { 1308 w->base = base; 1309 w->limit = limit; 1310 } 1311 return (error); 1312 } 1313 1314 /* 1315 * Find the existing resource to adjust. Usually there is only one, 1316 * but for an ISA-enabled bridge we might be growing the I/O window 1317 * above 64k and need to find the existing resource that maps all 1318 * of the area above 64k. 1319 */ 1320 for (i = 0; i < w->count; i++) { 1321 if (rman_get_end(w->res[i]) == w->limit) 1322 break; 1323 } 1324 KASSERT(i != w->count, ("did not find existing resource")); 1325 res = w->res[i]; 1326 1327 /* 1328 * Usually the resource we found should match the window's 1329 * existing range. The one exception is the ISA-enabled case 1330 * mentioned above in which case the resource should start at 1331 * 64k. 1332 */ 1333 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1334 w->base <= 65535) { 1335 KASSERT(rman_get_start(res) == 65536, 1336 ("existing resource mismatch")); 1337 force_64k_base = 1; 1338 } else { 1339 KASSERT(w->base == rman_get_start(res), 1340 ("existing resource mismatch")); 1341 force_64k_base = 0; 1342 } 1343 1344 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1345 rman_get_start(res) : base, limit); 1346 if (error) 1347 return (error); 1348 1349 /* Add the newly allocated region to the resource manager. */ 1350 if (w->base != base) { 1351 error = rman_manage_region(&w->rman, base, w->base - 1); 1352 w->base = base; 1353 } else { 1354 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1355 w->limit = limit; 1356 } 1357 if (error) { 1358 if (bootverbose) 1359 device_printf(sc->dev, 1360 "failed to expand %s resource manager\n", w->name); 1361 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1362 rman_get_start(res) : w->base, w->limit); 1363 } 1364 return (error); 1365 } 1366 1367 /* 1368 * Attempt to grow a window to make room for a given resource request. 1369 */ 1370 static int 1371 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1372 u_long start, u_long end, u_long count, u_int flags) 1373 { 1374 u_long align, start_free, end_free, front, back, wmask; 1375 int error; 1376 1377 /* 1378 * Clamp the desired resource range to the maximum address 1379 * this window supports. Reject impossible requests. 1380 * 1381 * For I/O port requests behind a bridge with the ISA enable 1382 * bit set, force large allocations to start above 64k. 1383 */ 1384 if (!w->valid) 1385 return (EINVAL); 1386 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1387 start < 65536) 1388 start = 65536; 1389 if (end > w->rman.rm_end) 1390 end = w->rman.rm_end; 1391 if (start + count - 1 > end || start + count < start) 1392 return (EINVAL); 1393 wmask = (1ul << w->step) - 1; 1394 1395 /* 1396 * If there is no resource at all, just try to allocate enough 1397 * aligned space for this resource. 1398 */ 1399 if (w->res == NULL) { 1400 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1401 flags); 1402 if (error) { 1403 if (bootverbose) 1404 device_printf(sc->dev, 1405 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 1406 w->name, start, end, count); 1407 return (error); 1408 } 1409 if (bootverbose) 1410 device_printf(sc->dev, 1411 "allocated initial %s window of %#jx-%#jx\n", 1412 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1413 goto updatewin; 1414 } 1415 1416 /* 1417 * See if growing the window would help. Compute the minimum 1418 * amount of address space needed on both the front and back 1419 * ends of the existing window to satisfy the allocation. 1420 * 1421 * For each end, build a candidate region adjusting for the 1422 * required alignment, etc. If there is a free region at the 1423 * edge of the window, grow from the inner edge of the free 1424 * region. Otherwise grow from the window boundary. 1425 * 1426 * Growing an I/O window below 64k for a bridge with the ISA 1427 * enable bit doesn't require any special magic as the step 1428 * size of an I/O window (1k) always includes multiple 1429 * non-alias ranges when it is grown in either direction. 1430 * 1431 * XXX: Special case: if w->res is completely empty and the 1432 * request size is larger than w->res, we should find the 1433 * optimal aligned buffer containing w->res and allocate that. 1434 */ 1435 if (bootverbose) 1436 device_printf(sc->dev, 1437 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 1438 w->name, start, end, count); 1439 align = 1ul << RF_ALIGNMENT(flags); 1440 if (start < w->base) { 1441 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1442 0 || start_free != w->base) 1443 end_free = w->base; 1444 if (end_free > end) 1445 end_free = end + 1; 1446 1447 /* Move end_free down until it is properly aligned. */ 1448 end_free &= ~(align - 1); 1449 end_free--; 1450 front = end_free - (count - 1); 1451 1452 /* 1453 * The resource would now be allocated at (front, 1454 * end_free). Ensure that fits in the (start, end) 1455 * bounds. end_free is checked above. If 'front' is 1456 * ok, ensure it is properly aligned for this window. 1457 * Also check for underflow. 1458 */ 1459 if (front >= start && front <= end_free) { 1460 if (bootverbose) 1461 printf("\tfront candidate range: %#lx-%#lx\n", 1462 front, end_free); 1463 front &= ~wmask; 1464 front = w->base - front; 1465 } else 1466 front = 0; 1467 } else 1468 front = 0; 1469 if (end > w->limit) { 1470 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1471 0 || end_free != w->limit) 1472 start_free = w->limit + 1; 1473 if (start_free < start) 1474 start_free = start; 1475 1476 /* Move start_free up until it is properly aligned. */ 1477 start_free = roundup2(start_free, align); 1478 back = start_free + count - 1; 1479 1480 /* 1481 * The resource would now be allocated at (start_free, 1482 * back). Ensure that fits in the (start, end) 1483 * bounds. start_free is checked above. If 'back' is 1484 * ok, ensure it is properly aligned for this window. 1485 * Also check for overflow. 1486 */ 1487 if (back <= end && start_free <= back) { 1488 if (bootverbose) 1489 printf("\tback candidate range: %#lx-%#lx\n", 1490 start_free, back); 1491 back |= wmask; 1492 back -= w->limit; 1493 } else 1494 back = 0; 1495 } else 1496 back = 0; 1497 1498 /* 1499 * Try to allocate the smallest needed region first. 1500 * If that fails, fall back to the other region. 1501 */ 1502 error = ENOSPC; 1503 while (front != 0 || back != 0) { 1504 if (front != 0 && (front <= back || back == 0)) { 1505 error = pcib_expand_window(sc, w, type, w->base - front, 1506 w->limit); 1507 if (error == 0) 1508 break; 1509 front = 0; 1510 } else { 1511 error = pcib_expand_window(sc, w, type, w->base, 1512 w->limit + back); 1513 if (error == 0) 1514 break; 1515 back = 0; 1516 } 1517 } 1518 1519 if (error) 1520 return (error); 1521 if (bootverbose) 1522 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 1523 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1524 1525 updatewin: 1526 /* Write the new window. */ 1527 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 1528 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 1529 pcib_write_windows(sc, w->mask); 1530 return (0); 1531 } 1532 1533 /* 1534 * We have to trap resource allocation requests and ensure that the bridge 1535 * is set up to, or capable of handling them. 1536 */ 1537 struct resource * 1538 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1539 u_long start, u_long end, u_long count, u_int flags) 1540 { 1541 struct pcib_softc *sc; 1542 struct resource *r; 1543 1544 sc = device_get_softc(dev); 1545 1546 /* 1547 * VGA resources are decoded iff the VGA enable bit is set in 1548 * the bridge control register. VGA resources do not fall into 1549 * the resource windows and are passed up to the parent. 1550 */ 1551 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1552 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1553 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1554 return (bus_generic_alloc_resource(dev, child, type, 1555 rid, start, end, count, flags)); 1556 else 1557 return (NULL); 1558 } 1559 1560 switch (type) { 1561 #ifdef PCI_RES_BUS 1562 case PCI_RES_BUS: 1563 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 1564 count, flags)); 1565 #endif 1566 case SYS_RES_IOPORT: 1567 if (pcib_is_isa_range(sc, start, end, count)) 1568 return (NULL); 1569 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1570 end, count, flags); 1571 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1572 break; 1573 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1574 flags) == 0) 1575 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1576 rid, start, end, count, flags); 1577 break; 1578 case SYS_RES_MEMORY: 1579 /* 1580 * For prefetchable resources, prefer the prefetchable 1581 * memory window, but fall back to the regular memory 1582 * window if that fails. Try both windows before 1583 * attempting to grow a window in case the firmware 1584 * has used a range in the regular memory window to 1585 * map a prefetchable BAR. 1586 */ 1587 if (flags & RF_PREFETCHABLE) { 1588 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1589 rid, start, end, count, flags); 1590 if (r != NULL) 1591 break; 1592 } 1593 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1594 start, end, count, flags); 1595 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1596 break; 1597 if (flags & RF_PREFETCHABLE) { 1598 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1599 count, flags) == 0) { 1600 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1601 type, rid, start, end, count, flags); 1602 if (r != NULL) 1603 break; 1604 } 1605 } 1606 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1607 flags & ~RF_PREFETCHABLE) == 0) 1608 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1609 rid, start, end, count, flags); 1610 break; 1611 default: 1612 return (bus_generic_alloc_resource(dev, child, type, rid, 1613 start, end, count, flags)); 1614 } 1615 1616 /* 1617 * If attempts to suballocate from the window fail but this is a 1618 * subtractive bridge, pass the request up the tree. 1619 */ 1620 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1621 return (bus_generic_alloc_resource(dev, child, type, rid, 1622 start, end, count, flags)); 1623 return (r); 1624 } 1625 1626 int 1627 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1628 u_long start, u_long end) 1629 { 1630 struct pcib_softc *sc; 1631 1632 sc = device_get_softc(bus); 1633 if (pcib_is_resource_managed(sc, type, r)) 1634 return (rman_adjust_resource(r, start, end)); 1635 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1636 } 1637 1638 int 1639 pcib_release_resource(device_t dev, device_t child, int type, int rid, 1640 struct resource *r) 1641 { 1642 struct pcib_softc *sc; 1643 int error; 1644 1645 sc = device_get_softc(dev); 1646 if (pcib_is_resource_managed(sc, type, r)) { 1647 if (rman_get_flags(r) & RF_ACTIVE) { 1648 error = bus_deactivate_resource(child, type, rid, r); 1649 if (error) 1650 return (error); 1651 } 1652 return (rman_release_resource(r)); 1653 } 1654 return (bus_generic_release_resource(dev, child, type, rid, r)); 1655 } 1656 #else 1657 /* 1658 * We have to trap resource allocation requests and ensure that the bridge 1659 * is set up to, or capable of handling them. 1660 */ 1661 struct resource * 1662 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1663 u_long start, u_long end, u_long count, u_int flags) 1664 { 1665 struct pcib_softc *sc = device_get_softc(dev); 1666 const char *name, *suffix; 1667 int ok; 1668 1669 /* 1670 * Fail the allocation for this range if it's not supported. 1671 */ 1672 name = device_get_nameunit(child); 1673 if (name == NULL) { 1674 name = ""; 1675 suffix = ""; 1676 } else 1677 suffix = " "; 1678 switch (type) { 1679 case SYS_RES_IOPORT: 1680 ok = 0; 1681 if (!pcib_is_io_open(sc)) 1682 break; 1683 ok = (start >= sc->iobase && end <= sc->iolimit); 1684 1685 /* 1686 * Make sure we allow access to VGA I/O addresses when the 1687 * bridge has the "VGA Enable" bit set. 1688 */ 1689 if (!ok && pci_is_vga_ioport_range(start, end)) 1690 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1691 1692 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1693 if (!ok) { 1694 if (start < sc->iobase) 1695 start = sc->iobase; 1696 if (end > sc->iolimit) 1697 end = sc->iolimit; 1698 if (start < end) 1699 ok = 1; 1700 } 1701 } else { 1702 ok = 1; 1703 #if 0 1704 /* 1705 * If we overlap with the subtractive range, then 1706 * pick the upper range to use. 1707 */ 1708 if (start < sc->iolimit && end > sc->iobase) 1709 start = sc->iolimit + 1; 1710 #endif 1711 } 1712 if (end < start) { 1713 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1714 end, start); 1715 start = 0; 1716 end = 0; 1717 ok = 0; 1718 } 1719 if (!ok) { 1720 device_printf(dev, "%s%srequested unsupported I/O " 1721 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1722 name, suffix, start, end, sc->iobase, sc->iolimit); 1723 return (NULL); 1724 } 1725 if (bootverbose) 1726 device_printf(dev, 1727 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1728 name, suffix, start, end); 1729 break; 1730 1731 case SYS_RES_MEMORY: 1732 ok = 0; 1733 if (pcib_is_nonprefetch_open(sc)) 1734 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1735 if (pcib_is_prefetch_open(sc)) 1736 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1737 1738 /* 1739 * Make sure we allow access to VGA memory addresses when the 1740 * bridge has the "VGA Enable" bit set. 1741 */ 1742 if (!ok && pci_is_vga_memory_range(start, end)) 1743 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1744 1745 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1746 if (!ok) { 1747 ok = 1; 1748 if (flags & RF_PREFETCHABLE) { 1749 if (pcib_is_prefetch_open(sc)) { 1750 if (start < sc->pmembase) 1751 start = sc->pmembase; 1752 if (end > sc->pmemlimit) 1753 end = sc->pmemlimit; 1754 } else { 1755 ok = 0; 1756 } 1757 } else { /* non-prefetchable */ 1758 if (pcib_is_nonprefetch_open(sc)) { 1759 if (start < sc->membase) 1760 start = sc->membase; 1761 if (end > sc->memlimit) 1762 end = sc->memlimit; 1763 } else { 1764 ok = 0; 1765 } 1766 } 1767 } 1768 } else if (!ok) { 1769 ok = 1; /* subtractive bridge: always ok */ 1770 #if 0 1771 if (pcib_is_nonprefetch_open(sc)) { 1772 if (start < sc->memlimit && end > sc->membase) 1773 start = sc->memlimit + 1; 1774 } 1775 if (pcib_is_prefetch_open(sc)) { 1776 if (start < sc->pmemlimit && end > sc->pmembase) 1777 start = sc->pmemlimit + 1; 1778 } 1779 #endif 1780 } 1781 if (end < start) { 1782 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1783 end, start); 1784 start = 0; 1785 end = 0; 1786 ok = 0; 1787 } 1788 if (!ok && bootverbose) 1789 device_printf(dev, 1790 "%s%srequested unsupported memory range %#lx-%#lx " 1791 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1792 name, suffix, start, end, 1793 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1794 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1795 if (!ok) 1796 return (NULL); 1797 if (bootverbose) 1798 device_printf(dev,"%s%srequested memory range " 1799 "0x%lx-0x%lx: good\n", 1800 name, suffix, start, end); 1801 break; 1802 1803 default: 1804 break; 1805 } 1806 /* 1807 * Bridge is OK decoding this resource, so pass it up. 1808 */ 1809 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1810 count, flags)); 1811 } 1812 #endif 1813 1814 /* 1815 * If ARI is enabled on this downstream port, translate the function number 1816 * to the non-ARI slot/function. The downstream port will convert it back in 1817 * hardware. If ARI is not enabled slot and func are not modified. 1818 */ 1819 static __inline void 1820 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 1821 { 1822 struct pcib_softc *sc; 1823 int ari_func; 1824 1825 sc = device_get_softc(pcib); 1826 ari_func = *func; 1827 1828 if (sc->flags & PCIB_ENABLE_ARI) { 1829 KASSERT(*slot == 0, 1830 ("Non-zero slot number with ARI enabled!")); 1831 *slot = PCIE_ARI_SLOT(ari_func); 1832 *func = PCIE_ARI_FUNC(ari_func); 1833 } 1834 } 1835 1836 1837 static void 1838 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 1839 { 1840 uint32_t ctl2; 1841 1842 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 1843 ctl2 |= PCIEM_CTL2_ARI; 1844 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 1845 1846 sc->flags |= PCIB_ENABLE_ARI; 1847 } 1848 1849 /* 1850 * PCIB interface. 1851 */ 1852 int 1853 pcib_maxslots(device_t dev) 1854 { 1855 return (PCI_SLOTMAX); 1856 } 1857 1858 static int 1859 pcib_ari_maxslots(device_t dev) 1860 { 1861 struct pcib_softc *sc; 1862 1863 sc = device_get_softc(dev); 1864 1865 if (sc->flags & PCIB_ENABLE_ARI) 1866 return (PCIE_ARI_SLOTMAX); 1867 else 1868 return (PCI_SLOTMAX); 1869 } 1870 1871 static int 1872 pcib_ari_maxfuncs(device_t dev) 1873 { 1874 struct pcib_softc *sc; 1875 1876 sc = device_get_softc(dev); 1877 1878 if (sc->flags & PCIB_ENABLE_ARI) 1879 return (PCIE_ARI_FUNCMAX); 1880 else 1881 return (PCI_FUNCMAX); 1882 } 1883 1884 /* 1885 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1886 */ 1887 static uint32_t 1888 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1889 { 1890 1891 pcib_xlate_ari(dev, b, &s, &f); 1892 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 1893 f, reg, width)); 1894 } 1895 1896 static void 1897 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1898 { 1899 1900 pcib_xlate_ari(dev, b, &s, &f); 1901 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 1902 reg, val, width); 1903 } 1904 1905 /* 1906 * Route an interrupt across a PCI bridge. 1907 */ 1908 int 1909 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1910 { 1911 device_t bus; 1912 int parent_intpin; 1913 int intnum; 1914 1915 /* 1916 * 1917 * The PCI standard defines a swizzle of the child-side device/intpin to 1918 * the parent-side intpin as follows. 1919 * 1920 * device = device on child bus 1921 * child_intpin = intpin on child bus slot (0-3) 1922 * parent_intpin = intpin on parent bus slot (0-3) 1923 * 1924 * parent_intpin = (device + child_intpin) % 4 1925 */ 1926 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1927 1928 /* 1929 * Our parent is a PCI bus. Its parent must export the pcib interface 1930 * which includes the ability to route interrupts. 1931 */ 1932 bus = device_get_parent(pcib); 1933 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1934 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1935 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1936 pci_get_slot(dev), 'A' + pin - 1, intnum); 1937 } 1938 return(intnum); 1939 } 1940 1941 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1942 int 1943 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1944 { 1945 struct pcib_softc *sc = device_get_softc(pcib); 1946 device_t bus; 1947 1948 if (sc->flags & PCIB_DISABLE_MSI) 1949 return (ENXIO); 1950 bus = device_get_parent(pcib); 1951 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1952 irqs)); 1953 } 1954 1955 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1956 int 1957 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1958 { 1959 device_t bus; 1960 1961 bus = device_get_parent(pcib); 1962 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1963 } 1964 1965 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 1966 int 1967 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1968 { 1969 struct pcib_softc *sc = device_get_softc(pcib); 1970 device_t bus; 1971 1972 if (sc->flags & PCIB_DISABLE_MSIX) 1973 return (ENXIO); 1974 bus = device_get_parent(pcib); 1975 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1976 } 1977 1978 /* Pass request to release an MSI-X message up to the parent bridge. */ 1979 int 1980 pcib_release_msix(device_t pcib, device_t dev, int irq) 1981 { 1982 device_t bus; 1983 1984 bus = device_get_parent(pcib); 1985 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1986 } 1987 1988 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 1989 int 1990 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 1991 uint32_t *data) 1992 { 1993 device_t bus; 1994 int error; 1995 1996 bus = device_get_parent(pcib); 1997 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 1998 if (error) 1999 return (error); 2000 2001 pci_ht_map_msi(pcib, *addr); 2002 return (0); 2003 } 2004 2005 /* Pass request for device power state up to parent bridge. */ 2006 int 2007 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2008 { 2009 device_t bus; 2010 2011 bus = device_get_parent(pcib); 2012 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2013 } 2014 2015 static uint16_t 2016 pcib_ari_get_rid(device_t pcib, device_t dev) 2017 { 2018 struct pcib_softc *sc; 2019 uint8_t bus, slot, func; 2020 2021 sc = device_get_softc(pcib); 2022 2023 if (sc->flags & PCIB_ENABLE_ARI) { 2024 bus = pci_get_bus(dev); 2025 func = pci_get_function(dev); 2026 2027 return (PCI_ARI_RID(bus, func)); 2028 } else { 2029 bus = pci_get_bus(dev); 2030 slot = pci_get_slot(dev); 2031 func = pci_get_function(dev); 2032 2033 return (PCI_RID(bus, slot, func)); 2034 } 2035 } 2036 2037 /* 2038 * Check that the downstream port (pcib) and the endpoint device (dev) both 2039 * support ARI. If so, enable it and return 0, otherwise return an error. 2040 */ 2041 static int 2042 pcib_try_enable_ari(device_t pcib, device_t dev) 2043 { 2044 struct pcib_softc *sc; 2045 int error; 2046 uint32_t cap2; 2047 int ari_cap_off; 2048 uint32_t ari_ver; 2049 uint32_t pcie_pos; 2050 2051 sc = device_get_softc(pcib); 2052 2053 /* 2054 * ARI is controlled in a register in the PCIe capability structure. 2055 * If the downstream port does not have the PCIe capability structure 2056 * then it does not support ARI. 2057 */ 2058 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2059 if (error != 0) 2060 return (ENODEV); 2061 2062 /* Check that the PCIe port advertises ARI support. */ 2063 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2064 if (!(cap2 & PCIEM_CAP2_ARI)) 2065 return (ENODEV); 2066 2067 /* 2068 * Check that the endpoint device advertises ARI support via the ARI 2069 * extended capability structure. 2070 */ 2071 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2072 if (error != 0) 2073 return (ENODEV); 2074 2075 /* 2076 * Finally, check that the endpoint device supports the same version 2077 * of ARI that we do. 2078 */ 2079 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2080 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2081 if (bootverbose) 2082 device_printf(pcib, 2083 "Unsupported version of ARI (%d) detected\n", 2084 PCI_EXTCAP_VER(ari_ver)); 2085 2086 return (ENXIO); 2087 } 2088 2089 pcib_enable_ari(sc, pcie_pos); 2090 2091 return (0); 2092 } 2093 2094