xref: /freebsd/sys/dev/pci/pci_pci.c (revision 5aa839c9e2c373275091b8bf529c1311d0b84d76)
1  /*-
2   * SPDX-License-Identifier: BSD-3-Clause
3   *
4   * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5   * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6   * Copyright (c) 2000 BSDi
7   * All rights reserved.
8   *
9   * Redistribution and use in source and binary forms, with or without
10   * modification, are permitted provided that the following conditions
11   * are met:
12   * 1. Redistributions of source code must retain the above copyright
13   *    notice, this list of conditions and the following disclaimer.
14   * 2. Redistributions in binary form must reproduce the above copyright
15   *    notice, this list of conditions and the following disclaimer in the
16   *    documentation and/or other materials provided with the distribution.
17   * 3. The name of the author may not be used to endorse or promote products
18   *    derived from this software without specific prior written permission.
19   *
20   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30   * SUCH DAMAGE.
31   */
32  
33  #include <sys/cdefs.h>
34  __FBSDID("$FreeBSD$");
35  
36  /*
37   * PCI:PCI bridge support.
38   */
39  
40  #include "opt_pci.h"
41  
42  #include <sys/param.h>
43  #include <sys/bus.h>
44  #include <sys/kernel.h>
45  #include <sys/lock.h>
46  #include <sys/malloc.h>
47  #include <sys/module.h>
48  #include <sys/mutex.h>
49  #include <sys/pciio.h>
50  #include <sys/rman.h>
51  #include <sys/sysctl.h>
52  #include <sys/systm.h>
53  #include <sys/taskqueue.h>
54  
55  #include <dev/pci/pcivar.h>
56  #include <dev/pci/pcireg.h>
57  #include <dev/pci/pci_private.h>
58  #include <dev/pci/pcib_private.h>
59  
60  #include "pcib_if.h"
61  
62  static int		pcib_probe(device_t dev);
63  static int		pcib_suspend(device_t dev);
64  static int		pcib_resume(device_t dev);
65  static int		pcib_power_for_sleep(device_t pcib, device_t dev,
66  			    int *pstate);
67  static int		pcib_ari_get_id(device_t pcib, device_t dev,
68      enum pci_id_type type, uintptr_t *id);
69  static uint32_t		pcib_read_config(device_t dev, u_int b, u_int s,
70      u_int f, u_int reg, int width);
71  static void		pcib_write_config(device_t dev, u_int b, u_int s,
72      u_int f, u_int reg, uint32_t val, int width);
73  static int		pcib_ari_maxslots(device_t dev);
74  static int		pcib_ari_maxfuncs(device_t dev);
75  static int		pcib_try_enable_ari(device_t pcib, device_t dev);
76  static int		pcib_ari_enabled(device_t pcib);
77  static void		pcib_ari_decode_rid(device_t pcib, uint16_t rid,
78  			    int *bus, int *slot, int *func);
79  #ifdef PCI_HP
80  static void		pcib_pcie_ab_timeout(void *arg, int pending);
81  static void		pcib_pcie_cc_timeout(void *arg, int pending);
82  static void		pcib_pcie_dll_timeout(void *arg, int pending);
83  #endif
84  static int		pcib_request_feature_default(device_t pcib, device_t dev,
85  			    enum pci_feature feature);
86  static int		pcib_reset_child(device_t dev, device_t child, int flags);
87  
88  static device_method_t pcib_methods[] = {
89      /* Device interface */
90      DEVMETHOD(device_probe,		pcib_probe),
91      DEVMETHOD(device_attach,		pcib_attach),
92      DEVMETHOD(device_detach,		pcib_detach),
93      DEVMETHOD(device_shutdown,		bus_generic_shutdown),
94      DEVMETHOD(device_suspend,		pcib_suspend),
95      DEVMETHOD(device_resume,		pcib_resume),
96  
97      /* Bus interface */
98      DEVMETHOD(bus_child_present,	pcib_child_present),
99      DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
100      DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
101      DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
102  #ifdef NEW_PCIB
103      DEVMETHOD(bus_adjust_resource,	pcib_adjust_resource),
104      DEVMETHOD(bus_release_resource,	pcib_release_resource),
105  #else
106      DEVMETHOD(bus_adjust_resource,	bus_generic_adjust_resource),
107      DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
108  #endif
109      DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
110      DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
111      DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
112      DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
113      DEVMETHOD(bus_reset_child,		pcib_reset_child),
114  
115      /* pcib interface */
116      DEVMETHOD(pcib_maxslots,		pcib_ari_maxslots),
117      DEVMETHOD(pcib_maxfuncs,		pcib_ari_maxfuncs),
118      DEVMETHOD(pcib_read_config,		pcib_read_config),
119      DEVMETHOD(pcib_write_config,	pcib_write_config),
120      DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
121      DEVMETHOD(pcib_alloc_msi,		pcib_alloc_msi),
122      DEVMETHOD(pcib_release_msi,		pcib_release_msi),
123      DEVMETHOD(pcib_alloc_msix,		pcib_alloc_msix),
124      DEVMETHOD(pcib_release_msix,	pcib_release_msix),
125      DEVMETHOD(pcib_map_msi,		pcib_map_msi),
126      DEVMETHOD(pcib_power_for_sleep,	pcib_power_for_sleep),
127      DEVMETHOD(pcib_get_id,		pcib_ari_get_id),
128      DEVMETHOD(pcib_try_enable_ari,	pcib_try_enable_ari),
129      DEVMETHOD(pcib_ari_enabled,		pcib_ari_enabled),
130      DEVMETHOD(pcib_decode_rid,		pcib_ari_decode_rid),
131      DEVMETHOD(pcib_request_feature,	pcib_request_feature_default),
132  
133      DEVMETHOD_END
134  };
135  
136  static devclass_t pcib_devclass;
137  
138  DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
139  EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL,
140      BUS_PASS_BUS);
141  
142  #if defined(NEW_PCIB) || defined(PCI_HP)
143  SYSCTL_DECL(_hw_pci);
144  #endif
145  
146  #ifdef NEW_PCIB
147  static int pci_clear_pcib;
148  SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
149      "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
150  
151  /*
152   * Get the corresponding window if this resource from a child device was
153   * sub-allocated from one of our window resource managers.
154   */
155  static struct pcib_window *
156  pcib_get_resource_window(struct pcib_softc *sc, int type, struct resource *r)
157  {
158  	switch (type) {
159  	case SYS_RES_IOPORT:
160  		if (rman_is_region_manager(r, &sc->io.rman))
161  			return (&sc->io);
162  		break;
163  	case SYS_RES_MEMORY:
164  		/* Prefetchable resources may live in either memory rman. */
165  		if (rman_get_flags(r) & RF_PREFETCHABLE &&
166  		    rman_is_region_manager(r, &sc->pmem.rman))
167  			return (&sc->pmem);
168  		if (rman_is_region_manager(r, &sc->mem.rman))
169  			return (&sc->mem);
170  		break;
171  	}
172  	return (NULL);
173  }
174  
175  /*
176   * Is a resource from a child device sub-allocated from one of our
177   * resource managers?
178   */
179  static int
180  pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
181  {
182  
183  #ifdef PCI_RES_BUS
184  	if (type == PCI_RES_BUS)
185  		return (rman_is_region_manager(r, &sc->bus.rman));
186  #endif
187  	return (pcib_get_resource_window(sc, type, r) != NULL);
188  }
189  
190  static int
191  pcib_is_window_open(struct pcib_window *pw)
192  {
193  
194  	return (pw->valid && pw->base < pw->limit);
195  }
196  
197  /*
198   * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
199   * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
200   * when allocating the resource windows and rely on the PCI bus driver
201   * to do this for us.
202   */
203  static void
204  pcib_activate_window(struct pcib_softc *sc, int type)
205  {
206  
207  	PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
208  }
209  
210  static void
211  pcib_write_windows(struct pcib_softc *sc, int mask)
212  {
213  	device_t dev;
214  	uint32_t val;
215  
216  	dev = sc->dev;
217  	if (sc->io.valid && mask & WIN_IO) {
218  		val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
219  		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
220  			pci_write_config(dev, PCIR_IOBASEH_1,
221  			    sc->io.base >> 16, 2);
222  			pci_write_config(dev, PCIR_IOLIMITH_1,
223  			    sc->io.limit >> 16, 2);
224  		}
225  		pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
226  		pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
227  	}
228  
229  	if (mask & WIN_MEM) {
230  		pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
231  		pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
232  	}
233  
234  	if (sc->pmem.valid && mask & WIN_PMEM) {
235  		val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
236  		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
237  			pci_write_config(dev, PCIR_PMBASEH_1,
238  			    sc->pmem.base >> 32, 4);
239  			pci_write_config(dev, PCIR_PMLIMITH_1,
240  			    sc->pmem.limit >> 32, 4);
241  		}
242  		pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
243  		pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
244  	}
245  }
246  
247  /*
248   * This is used to reject I/O port allocations that conflict with an
249   * ISA alias range.
250   */
251  static int
252  pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
253      rman_res_t count)
254  {
255  	rman_res_t next_alias;
256  
257  	if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
258  		return (0);
259  
260  	/* Only check fixed ranges for overlap. */
261  	if (start + count - 1 != end)
262  		return (0);
263  
264  	/* ISA aliases are only in the lower 64KB of I/O space. */
265  	if (start >= 65536)
266  		return (0);
267  
268  	/* Check for overlap with 0x000 - 0x0ff as a special case. */
269  	if (start < 0x100)
270  		goto alias;
271  
272  	/*
273  	 * If the start address is an alias, the range is an alias.
274  	 * Otherwise, compute the start of the next alias range and
275  	 * check if it is before the end of the candidate range.
276  	 */
277  	if ((start & 0x300) != 0)
278  		goto alias;
279  	next_alias = (start & ~0x3fful) | 0x100;
280  	if (next_alias <= end)
281  		goto alias;
282  	return (0);
283  
284  alias:
285  	if (bootverbose)
286  		device_printf(sc->dev,
287  		    "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
288  		    end);
289  	return (1);
290  }
291  
292  static void
293  pcib_add_window_resources(struct pcib_window *w, struct resource **res,
294      int count)
295  {
296  	struct resource **newarray;
297  	int error, i;
298  
299  	newarray = malloc(sizeof(struct resource *) * (w->count + count),
300  	    M_DEVBUF, M_WAITOK);
301  	if (w->res != NULL)
302  		bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
303  	bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
304  	free(w->res, M_DEVBUF);
305  	w->res = newarray;
306  	w->count += count;
307  
308  	for (i = 0; i < count; i++) {
309  		error = rman_manage_region(&w->rman, rman_get_start(res[i]),
310  		    rman_get_end(res[i]));
311  		if (error)
312  			panic("Failed to add resource to rman");
313  	}
314  }
315  
316  typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
317  
318  static void
319  pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
320      void *arg)
321  {
322  	rman_res_t next_end;
323  
324  	/*
325  	 * If start is within an ISA alias range, move up to the start
326  	 * of the next non-alias range.  As a special case, addresses
327  	 * in the range 0x000 - 0x0ff should also be skipped since
328  	 * those are used for various system I/O devices in ISA
329  	 * systems.
330  	 */
331  	if (start <= 65535) {
332  		if (start < 0x100 || (start & 0x300) != 0) {
333  			start &= ~0x3ff;
334  			start += 0x400;
335  		}
336  	}
337  
338  	/* ISA aliases are only in the lower 64KB of I/O space. */
339  	while (start <= MIN(end, 65535)) {
340  		next_end = MIN(start | 0xff, end);
341  		cb(start, next_end, arg);
342  		start += 0x400;
343  	}
344  
345  	if (start <= end)
346  		cb(start, end, arg);
347  }
348  
349  static void
350  count_ranges(rman_res_t start, rman_res_t end, void *arg)
351  {
352  	int *countp;
353  
354  	countp = arg;
355  	(*countp)++;
356  }
357  
358  struct alloc_state {
359  	struct resource **res;
360  	struct pcib_softc *sc;
361  	int count, error;
362  };
363  
364  static void
365  alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
366  {
367  	struct alloc_state *as;
368  	struct pcib_window *w;
369  	int rid;
370  
371  	as = arg;
372  	if (as->error != 0)
373  		return;
374  
375  	w = &as->sc->io;
376  	rid = w->reg;
377  	if (bootverbose)
378  		device_printf(as->sc->dev,
379  		    "allocating non-ISA range %#jx-%#jx\n", start, end);
380  	as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
381  	    &rid, start, end, end - start + 1, 0);
382  	if (as->res[as->count] == NULL)
383  		as->error = ENXIO;
384  	else
385  		as->count++;
386  }
387  
388  static int
389  pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
390  {
391  	struct alloc_state as;
392  	int i, new_count;
393  
394  	/* First, see how many ranges we need. */
395  	new_count = 0;
396  	pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
397  
398  	/* Second, allocate the ranges. */
399  	as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
400  	    M_WAITOK);
401  	as.sc = sc;
402  	as.count = 0;
403  	as.error = 0;
404  	pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
405  	if (as.error != 0) {
406  		for (i = 0; i < as.count; i++)
407  			bus_release_resource(sc->dev, SYS_RES_IOPORT,
408  			    sc->io.reg, as.res[i]);
409  		free(as.res, M_DEVBUF);
410  		return (as.error);
411  	}
412  	KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
413  
414  	/* Third, add the ranges to the window. */
415  	pcib_add_window_resources(&sc->io, as.res, as.count);
416  	free(as.res, M_DEVBUF);
417  	return (0);
418  }
419  
420  static void
421  pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
422      int flags, pci_addr_t max_address)
423  {
424  	struct resource *res;
425  	char buf[64];
426  	int error, rid;
427  
428  	if (max_address != (rman_res_t)max_address)
429  		max_address = ~0;
430  	w->rman.rm_start = 0;
431  	w->rman.rm_end = max_address;
432  	w->rman.rm_type = RMAN_ARRAY;
433  	snprintf(buf, sizeof(buf), "%s %s window",
434  	    device_get_nameunit(sc->dev), w->name);
435  	w->rman.rm_descr = strdup(buf, M_DEVBUF);
436  	error = rman_init(&w->rman);
437  	if (error)
438  		panic("Failed to initialize %s %s rman",
439  		    device_get_nameunit(sc->dev), w->name);
440  
441  	if (!pcib_is_window_open(w))
442  		return;
443  
444  	if (w->base > max_address || w->limit > max_address) {
445  		device_printf(sc->dev,
446  		    "initial %s window has too many bits, ignoring\n", w->name);
447  		return;
448  	}
449  	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
450  		(void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
451  	else {
452  		rid = w->reg;
453  		res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
454  		    w->limit - w->base + 1, flags);
455  		if (res != NULL)
456  			pcib_add_window_resources(w, &res, 1);
457  	}
458  	if (w->res == NULL) {
459  		device_printf(sc->dev,
460  		    "failed to allocate initial %s window: %#jx-%#jx\n",
461  		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
462  		w->base = max_address;
463  		w->limit = 0;
464  		pcib_write_windows(sc, w->mask);
465  		return;
466  	}
467  	pcib_activate_window(sc, type);
468  }
469  
470  /*
471   * Initialize I/O windows.
472   */
473  static void
474  pcib_probe_windows(struct pcib_softc *sc)
475  {
476  	pci_addr_t max;
477  	device_t dev;
478  	uint32_t val;
479  
480  	dev = sc->dev;
481  
482  	if (pci_clear_pcib) {
483  		pcib_bridge_init(dev);
484  	}
485  
486  	/* Determine if the I/O port window is implemented. */
487  	val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
488  	if (val == 0) {
489  		/*
490  		 * If 'val' is zero, then only 16-bits of I/O space
491  		 * are supported.
492  		 */
493  		pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
494  		if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
495  			sc->io.valid = 1;
496  			pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
497  		}
498  	} else
499  		sc->io.valid = 1;
500  
501  	/* Read the existing I/O port window. */
502  	if (sc->io.valid) {
503  		sc->io.reg = PCIR_IOBASEL_1;
504  		sc->io.step = 12;
505  		sc->io.mask = WIN_IO;
506  		sc->io.name = "I/O port";
507  		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
508  			sc->io.base = PCI_PPBIOBASE(
509  			    pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
510  			sc->io.limit = PCI_PPBIOLIMIT(
511  			    pci_read_config(dev, PCIR_IOLIMITH_1, 2),
512  			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
513  			max = 0xffffffff;
514  		} else {
515  			sc->io.base = PCI_PPBIOBASE(0, val);
516  			sc->io.limit = PCI_PPBIOLIMIT(0,
517  			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
518  			max = 0xffff;
519  		}
520  		pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
521  	}
522  
523  	/* Read the existing memory window. */
524  	sc->mem.valid = 1;
525  	sc->mem.reg = PCIR_MEMBASE_1;
526  	sc->mem.step = 20;
527  	sc->mem.mask = WIN_MEM;
528  	sc->mem.name = "memory";
529  	sc->mem.base = PCI_PPBMEMBASE(0,
530  	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
531  	sc->mem.limit = PCI_PPBMEMLIMIT(0,
532  	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
533  	pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
534  
535  	/* Determine if the prefetchable memory window is implemented. */
536  	val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
537  	if (val == 0) {
538  		/*
539  		 * If 'val' is zero, then only 32-bits of memory space
540  		 * are supported.
541  		 */
542  		pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
543  		if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
544  			sc->pmem.valid = 1;
545  			pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
546  		}
547  	} else
548  		sc->pmem.valid = 1;
549  
550  	/* Read the existing prefetchable memory window. */
551  	if (sc->pmem.valid) {
552  		sc->pmem.reg = PCIR_PMBASEL_1;
553  		sc->pmem.step = 20;
554  		sc->pmem.mask = WIN_PMEM;
555  		sc->pmem.name = "prefetch";
556  		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
557  			sc->pmem.base = PCI_PPBMEMBASE(
558  			    pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
559  			sc->pmem.limit = PCI_PPBMEMLIMIT(
560  			    pci_read_config(dev, PCIR_PMLIMITH_1, 4),
561  			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
562  			max = 0xffffffffffffffff;
563  		} else {
564  			sc->pmem.base = PCI_PPBMEMBASE(0, val);
565  			sc->pmem.limit = PCI_PPBMEMLIMIT(0,
566  			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
567  			max = 0xffffffff;
568  		}
569  		pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
570  		    RF_PREFETCHABLE, max);
571  	}
572  }
573  
574  static void
575  pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
576  {
577  	device_t dev;
578  	int error, i;
579  
580  	if (!w->valid)
581  		return;
582  
583  	dev = sc->dev;
584  	error = rman_fini(&w->rman);
585  	if (error) {
586  		device_printf(dev, "failed to release %s rman\n", w->name);
587  		return;
588  	}
589  	free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
590  
591  	for (i = 0; i < w->count; i++) {
592  		error = bus_free_resource(dev, type, w->res[i]);
593  		if (error)
594  			device_printf(dev,
595  			    "failed to release %s resource: %d\n", w->name,
596  			    error);
597  	}
598  	free(w->res, M_DEVBUF);
599  }
600  
601  static void
602  pcib_free_windows(struct pcib_softc *sc)
603  {
604  
605  	pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
606  	pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
607  	pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
608  }
609  
610  #ifdef PCI_RES_BUS
611  /*
612   * Allocate a suitable secondary bus for this bridge if needed and
613   * initialize the resource manager for the secondary bus range.  Note
614   * that the minimum count is a desired value and this may allocate a
615   * smaller range.
616   */
617  void
618  pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
619  {
620  	char buf[64];
621  	int error, rid, sec_reg;
622  
623  	switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
624  	case PCIM_HDRTYPE_BRIDGE:
625  		sec_reg = PCIR_SECBUS_1;
626  		bus->sub_reg = PCIR_SUBBUS_1;
627  		break;
628  	case PCIM_HDRTYPE_CARDBUS:
629  		sec_reg = PCIR_SECBUS_2;
630  		bus->sub_reg = PCIR_SUBBUS_2;
631  		break;
632  	default:
633  		panic("not a PCI bridge");
634  	}
635  	bus->sec = pci_read_config(dev, sec_reg, 1);
636  	bus->sub = pci_read_config(dev, bus->sub_reg, 1);
637  	bus->dev = dev;
638  	bus->rman.rm_start = 0;
639  	bus->rman.rm_end = PCI_BUSMAX;
640  	bus->rman.rm_type = RMAN_ARRAY;
641  	snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
642  	bus->rman.rm_descr = strdup(buf, M_DEVBUF);
643  	error = rman_init(&bus->rman);
644  	if (error)
645  		panic("Failed to initialize %s bus number rman",
646  		    device_get_nameunit(dev));
647  
648  	/*
649  	 * Allocate a bus range.  This will return an existing bus range
650  	 * if one exists, or a new bus range if one does not.
651  	 */
652  	rid = 0;
653  	bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
654  	    min_count, 0);
655  	if (bus->res == NULL) {
656  		/*
657  		 * Fall back to just allocating a range of a single bus
658  		 * number.
659  		 */
660  		bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
661  		    1, 0);
662  	} else if (rman_get_size(bus->res) < min_count)
663  		/*
664  		 * Attempt to grow the existing range to satisfy the
665  		 * minimum desired count.
666  		 */
667  		(void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
668  		    rman_get_start(bus->res), rman_get_start(bus->res) +
669  		    min_count - 1);
670  
671  	/*
672  	 * Add the initial resource to the rman.
673  	 */
674  	if (bus->res != NULL) {
675  		error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
676  		    rman_get_end(bus->res));
677  		if (error)
678  			panic("Failed to add resource to rman");
679  		bus->sec = rman_get_start(bus->res);
680  		bus->sub = rman_get_end(bus->res);
681  	}
682  }
683  
684  void
685  pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
686  {
687  	int error;
688  
689  	error = rman_fini(&bus->rman);
690  	if (error) {
691  		device_printf(dev, "failed to release bus number rman\n");
692  		return;
693  	}
694  	free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
695  
696  	error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
697  	if (error)
698  		device_printf(dev,
699  		    "failed to release bus numbers resource: %d\n", error);
700  }
701  
702  static struct resource *
703  pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
704      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
705  {
706  	struct resource *res;
707  
708  	res = rman_reserve_resource(&bus->rman, start, end, count, flags,
709  	    child);
710  	if (res == NULL)
711  		return (NULL);
712  
713  	if (bootverbose)
714  		device_printf(bus->dev,
715  		    "allocated bus range (%ju-%ju) for rid %d of %s\n",
716  		    rman_get_start(res), rman_get_end(res), *rid,
717  		    pcib_child_name(child));
718  	rman_set_rid(res, *rid);
719  	return (res);
720  }
721  
722  /*
723   * Attempt to grow the secondary bus range.  This is much simpler than
724   * for I/O windows as the range can only be grown by increasing
725   * subbus.
726   */
727  static int
728  pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
729  {
730  	rman_res_t old_end;
731  	int error;
732  
733  	old_end = rman_get_end(bus->res);
734  	KASSERT(new_end > old_end, ("attempt to shrink subbus"));
735  	error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
736  	    rman_get_start(bus->res), new_end);
737  	if (error)
738  		return (error);
739  	if (bootverbose)
740  		device_printf(bus->dev, "grew bus range to %ju-%ju\n",
741  		    rman_get_start(bus->res), rman_get_end(bus->res));
742  	error = rman_manage_region(&bus->rman, old_end + 1,
743  	    rman_get_end(bus->res));
744  	if (error)
745  		panic("Failed to add resource to rman");
746  	bus->sub = rman_get_end(bus->res);
747  	pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
748  	return (0);
749  }
750  
751  struct resource *
752  pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
753      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
754  {
755  	struct resource *res;
756  	rman_res_t start_free, end_free, new_end;
757  
758  	/*
759  	 * First, see if the request can be satisified by the existing
760  	 * bus range.
761  	 */
762  	res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
763  	if (res != NULL)
764  		return (res);
765  
766  	/*
767  	 * Figure out a range to grow the bus range.  First, find the
768  	 * first bus number after the last allocated bus in the rman and
769  	 * enforce that as a minimum starting point for the range.
770  	 */
771  	if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
772  	    end_free != bus->sub)
773  		start_free = bus->sub + 1;
774  	if (start_free < start)
775  		start_free = start;
776  	new_end = start_free + count - 1;
777  
778  	/*
779  	 * See if this new range would satisfy the request if it
780  	 * succeeds.
781  	 */
782  	if (new_end > end)
783  		return (NULL);
784  
785  	/* Finally, attempt to grow the existing resource. */
786  	if (bootverbose) {
787  		device_printf(bus->dev,
788  		    "attempting to grow bus range for %ju buses\n", count);
789  		printf("\tback candidate range: %ju-%ju\n", start_free,
790  		    new_end);
791  	}
792  	if (pcib_grow_subbus(bus, new_end) == 0)
793  		return (pcib_suballoc_bus(bus, child, rid, start, end, count,
794  		    flags));
795  	return (NULL);
796  }
797  #endif
798  
799  #else
800  
801  /*
802   * Is the prefetch window open (eg, can we allocate memory in it?)
803   */
804  static int
805  pcib_is_prefetch_open(struct pcib_softc *sc)
806  {
807  	return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
808  }
809  
810  /*
811   * Is the nonprefetch window open (eg, can we allocate memory in it?)
812   */
813  static int
814  pcib_is_nonprefetch_open(struct pcib_softc *sc)
815  {
816  	return (sc->membase > 0 && sc->membase < sc->memlimit);
817  }
818  
819  /*
820   * Is the io window open (eg, can we allocate ports in it?)
821   */
822  static int
823  pcib_is_io_open(struct pcib_softc *sc)
824  {
825  	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
826  }
827  
828  /*
829   * Get current I/O decode.
830   */
831  static void
832  pcib_get_io_decode(struct pcib_softc *sc)
833  {
834  	device_t	dev;
835  	uint32_t	iolow;
836  
837  	dev = sc->dev;
838  
839  	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
840  	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
841  		sc->iobase = PCI_PPBIOBASE(
842  		    pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
843  	else
844  		sc->iobase = PCI_PPBIOBASE(0, iolow);
845  
846  	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
847  	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
848  		sc->iolimit = PCI_PPBIOLIMIT(
849  		    pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
850  	else
851  		sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
852  }
853  
854  /*
855   * Get current memory decode.
856   */
857  static void
858  pcib_get_mem_decode(struct pcib_softc *sc)
859  {
860  	device_t	dev;
861  	pci_addr_t	pmemlow;
862  
863  	dev = sc->dev;
864  
865  	sc->membase = PCI_PPBMEMBASE(0,
866  	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
867  	sc->memlimit = PCI_PPBMEMLIMIT(0,
868  	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
869  
870  	pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
871  	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
872  		sc->pmembase = PCI_PPBMEMBASE(
873  		    pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
874  	else
875  		sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
876  
877  	pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
878  	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
879  		sc->pmemlimit = PCI_PPBMEMLIMIT(
880  		    pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
881  	else
882  		sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
883  }
884  
885  /*
886   * Restore previous I/O decode.
887   */
888  static void
889  pcib_set_io_decode(struct pcib_softc *sc)
890  {
891  	device_t	dev;
892  	uint32_t	iohi;
893  
894  	dev = sc->dev;
895  
896  	iohi = sc->iobase >> 16;
897  	if (iohi > 0)
898  		pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
899  	pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
900  
901  	iohi = sc->iolimit >> 16;
902  	if (iohi > 0)
903  		pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
904  	pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
905  }
906  
907  /*
908   * Restore previous memory decode.
909   */
910  static void
911  pcib_set_mem_decode(struct pcib_softc *sc)
912  {
913  	device_t	dev;
914  	pci_addr_t	pmemhi;
915  
916  	dev = sc->dev;
917  
918  	pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
919  	pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
920  
921  	pmemhi = sc->pmembase >> 32;
922  	if (pmemhi > 0)
923  		pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
924  	pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
925  
926  	pmemhi = sc->pmemlimit >> 32;
927  	if (pmemhi > 0)
928  		pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
929  	pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
930  }
931  #endif
932  
933  #ifdef PCI_HP
934  /*
935   * PCI-express HotPlug support.
936   */
937  static int pci_enable_pcie_hp = 1;
938  SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
939      &pci_enable_pcie_hp, 0,
940      "Enable support for native PCI-express HotPlug.");
941  
942  TASKQUEUE_DEFINE_THREAD(pci_hp);
943  
944  static void
945  pcib_probe_hotplug(struct pcib_softc *sc)
946  {
947  	device_t dev;
948  	uint32_t link_cap;
949  	uint16_t link_sta, slot_sta;
950  
951  	if (!pci_enable_pcie_hp)
952  		return;
953  
954  	dev = sc->dev;
955  	if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
956  		return;
957  
958  	if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
959  		return;
960  
961  	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
962  
963  	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
964  		return;
965  	link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
966  	if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
967  		return;
968  
969  	/*
970  	 * Some devices report that they have an MRL when they actually
971  	 * do not.  Since they always report that the MRL is open, child
972  	 * devices would be ignored.  Try to detect these devices and
973  	 * ignore their claim of HotPlug support.
974  	 *
975  	 * If there is an open MRL but the Data Link Layer is active,
976  	 * the MRL is not real.
977  	 */
978  	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
979  		link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
980  		slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
981  		if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
982  		    (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
983  			return;
984  		}
985  	}
986  
987  	/*
988  	 * Now that we're sure we want to do hot plug, ask the
989  	 * firmware, if any, if that's OK.
990  	 */
991  	if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
992  		if (bootverbose)
993  			device_printf(dev, "Unable to activate hot plug feature.\n");
994  		return;
995  	}
996  
997  	sc->flags |= PCIB_HOTPLUG;
998  }
999  
1000  /*
1001   * Send a HotPlug command to the slot control register.  If this slot
1002   * uses command completion interrupts and a previous command is still
1003   * in progress, then the command is dropped.  Once the previous
1004   * command completes or times out, pcib_pcie_hotplug_update() will be
1005   * invoked to post a new command based on the slot's state at that
1006   * time.
1007   */
1008  static void
1009  pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
1010  {
1011  	device_t dev;
1012  	uint16_t ctl, new;
1013  
1014  	dev = sc->dev;
1015  
1016  	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
1017  		return;
1018  
1019  	ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
1020  	new = (ctl & ~mask) | val;
1021  	if (new == ctl)
1022  		return;
1023  	if (bootverbose)
1024  		device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1025  	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1026  	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1027  	    (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1028  		sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1029  		if (!cold)
1030  			taskqueue_enqueue_timeout(taskqueue_pci_hp,
1031  			    &sc->pcie_cc_task, hz);
1032  	}
1033  }
1034  
1035  static void
1036  pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1037  {
1038  	device_t dev;
1039  
1040  	dev = sc->dev;
1041  
1042  	if (bootverbose)
1043  		device_printf(dev, "Command Completed\n");
1044  	if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1045  		return;
1046  	taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task, NULL);
1047  	sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1048  	wakeup(sc);
1049  }
1050  
1051  /*
1052   * Returns true if a card is fully inserted from the user's
1053   * perspective.  It may not yet be ready for access, but the driver
1054   * can now start enabling access if necessary.
1055   */
1056  static bool
1057  pcib_hotplug_inserted(struct pcib_softc *sc)
1058  {
1059  
1060  	/* Pretend the card isn't present if a detach is forced. */
1061  	if (sc->flags & PCIB_DETACHING)
1062  		return (false);
1063  
1064  	/* Card must be present in the slot. */
1065  	if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1066  		return (false);
1067  
1068  	/* A power fault implicitly turns off power to the slot. */
1069  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1070  		return (false);
1071  
1072  	/* If the MRL is disengaged, the slot is powered off. */
1073  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1074  	    (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1075  		return (false);
1076  
1077  	return (true);
1078  }
1079  
1080  /*
1081   * Returns -1 if the card is fully inserted, powered, and ready for
1082   * access.  Otherwise, returns 0.
1083   */
1084  static int
1085  pcib_hotplug_present(struct pcib_softc *sc)
1086  {
1087  
1088  	/* Card must be inserted. */
1089  	if (!pcib_hotplug_inserted(sc))
1090  		return (0);
1091  
1092  	/* Require the Data Link Layer to be active. */
1093  	if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1094  		return (0);
1095  
1096  	return (-1);
1097  }
1098  
1099  static void
1100  pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1101      bool schedule_task)
1102  {
1103  	bool card_inserted, ei_engaged;
1104  
1105  	/* Clear DETACHING if Presence Detect has cleared. */
1106  	if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1107  	    PCIEM_SLOT_STA_PDC)
1108  		sc->flags &= ~PCIB_DETACHING;
1109  
1110  	card_inserted = pcib_hotplug_inserted(sc);
1111  
1112  	/* Turn the power indicator on if a card is inserted. */
1113  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1114  		mask |= PCIEM_SLOT_CTL_PIC;
1115  		if (card_inserted)
1116  			val |= PCIEM_SLOT_CTL_PI_ON;
1117  		else if (sc->flags & PCIB_DETACH_PENDING)
1118  			val |= PCIEM_SLOT_CTL_PI_BLINK;
1119  		else
1120  			val |= PCIEM_SLOT_CTL_PI_OFF;
1121  	}
1122  
1123  	/* Turn the power on via the Power Controller if a card is inserted. */
1124  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1125  		mask |= PCIEM_SLOT_CTL_PCC;
1126  		if (card_inserted)
1127  			val |= PCIEM_SLOT_CTL_PC_ON;
1128  		else
1129  			val |= PCIEM_SLOT_CTL_PC_OFF;
1130  	}
1131  
1132  	/*
1133  	 * If a card is inserted, enable the Electromechanical
1134  	 * Interlock.  If a card is not inserted (or we are in the
1135  	 * process of detaching), disable the Electromechanical
1136  	 * Interlock.
1137  	 */
1138  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1139  		mask |= PCIEM_SLOT_CTL_EIC;
1140  		ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1141  		if (card_inserted != ei_engaged)
1142  			val |= PCIEM_SLOT_CTL_EIC;
1143  	}
1144  
1145  	/*
1146  	 * Start a timer to see if the Data Link Layer times out.
1147  	 * Note that we only start the timer if Presence Detect or MRL Sensor
1148  	 * changed on this interrupt.  Stop any scheduled timer if
1149  	 * the Data Link Layer is active.
1150  	 */
1151  	if (card_inserted &&
1152  	    !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1153  	    sc->pcie_slot_sta &
1154  	    (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1155  		if (cold)
1156  			device_printf(sc->dev,
1157  			    "Data Link Layer inactive\n");
1158  		else
1159  			taskqueue_enqueue_timeout(taskqueue_pci_hp,
1160  			    &sc->pcie_dll_task, hz);
1161  	} else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1162  		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_dll_task,
1163  		    NULL);
1164  
1165  	pcib_pcie_hotplug_command(sc, val, mask);
1166  
1167  	/*
1168  	 * During attach the child "pci" device is added synchronously;
1169  	 * otherwise, the task is scheduled to manage the child
1170  	 * device.
1171  	 */
1172  	if (schedule_task &&
1173  	    (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1174  		taskqueue_enqueue(taskqueue_pci_hp, &sc->pcie_hp_task);
1175  }
1176  
1177  static void
1178  pcib_pcie_intr_hotplug(void *arg)
1179  {
1180  	struct pcib_softc *sc;
1181  	device_t dev;
1182  	uint16_t old_slot_sta;
1183  
1184  	sc = arg;
1185  	dev = sc->dev;
1186  	PCIB_HP_LOCK(sc);
1187  	old_slot_sta = sc->pcie_slot_sta;
1188  	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1189  
1190  	/* Clear the events just reported. */
1191  	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1192  
1193  	if (bootverbose)
1194  		device_printf(dev, "HotPlug interrupt: %#x\n",
1195  		    sc->pcie_slot_sta);
1196  
1197  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1198  		if (sc->flags & PCIB_DETACH_PENDING) {
1199  			device_printf(dev,
1200  			    "Attention Button Pressed: Detach Cancelled\n");
1201  			sc->flags &= ~PCIB_DETACH_PENDING;
1202  			taskqueue_cancel_timeout(taskqueue_pci_hp,
1203  			    &sc->pcie_ab_task, NULL);
1204  		} else if (old_slot_sta & PCIEM_SLOT_STA_PDS) {
1205  			/* Only initiate detach sequence if device present. */
1206  			device_printf(dev,
1207  		    "Attention Button Pressed: Detaching in 5 seconds\n");
1208  			sc->flags |= PCIB_DETACH_PENDING;
1209  			taskqueue_enqueue_timeout(taskqueue_pci_hp,
1210  			    &sc->pcie_ab_task, 5 * hz);
1211  		}
1212  	}
1213  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1214  		device_printf(dev, "Power Fault Detected\n");
1215  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1216  		device_printf(dev, "MRL Sensor Changed to %s\n",
1217  		    sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1218  		    "closed");
1219  	if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1220  		device_printf(dev, "Presence Detect Changed to %s\n",
1221  		    sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1222  		    "empty");
1223  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1224  		pcib_pcie_hotplug_command_completed(sc);
1225  	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1226  		sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1227  		if (bootverbose)
1228  			device_printf(dev,
1229  			    "Data Link Layer State Changed to %s\n",
1230  			    sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1231  			    "active" : "inactive");
1232  	}
1233  
1234  	pcib_pcie_hotplug_update(sc, 0, 0, true);
1235  	PCIB_HP_UNLOCK(sc);
1236  }
1237  
1238  static void
1239  pcib_pcie_hotplug_task(void *context, int pending)
1240  {
1241  	struct pcib_softc *sc;
1242  	device_t dev;
1243  
1244  	sc = context;
1245  	PCIB_HP_LOCK(sc);
1246  	dev = sc->dev;
1247  	if (pcib_hotplug_present(sc) != 0) {
1248  		if (sc->child == NULL) {
1249  			sc->child = device_add_child(dev, "pci", -1);
1250  			bus_generic_attach(dev);
1251  		}
1252  	} else {
1253  		if (sc->child != NULL) {
1254  			if (device_delete_child(dev, sc->child) == 0)
1255  				sc->child = NULL;
1256  		}
1257  	}
1258  	PCIB_HP_UNLOCK(sc);
1259  }
1260  
1261  static void
1262  pcib_pcie_ab_timeout(void *arg, int pending)
1263  {
1264  	struct pcib_softc *sc = arg;
1265  
1266  	PCIB_HP_LOCK(sc);
1267  	if (sc->flags & PCIB_DETACH_PENDING) {
1268  		sc->flags |= PCIB_DETACHING;
1269  		sc->flags &= ~PCIB_DETACH_PENDING;
1270  		pcib_pcie_hotplug_update(sc, 0, 0, true);
1271  	}
1272  	PCIB_HP_UNLOCK(sc);
1273  }
1274  
1275  static void
1276  pcib_pcie_cc_timeout(void *arg, int pending)
1277  {
1278  	struct pcib_softc *sc = arg;
1279  	device_t dev = sc->dev;
1280  	uint16_t sta;
1281  
1282  	PCIB_HP_LOCK(sc);
1283  	sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1284  	if (!(sta & PCIEM_SLOT_STA_CC)) {
1285  		device_printf(dev, "HotPlug Command Timed Out\n");
1286  		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1287  	} else {
1288  		device_printf(dev,
1289  	    "Missed HotPlug interrupt waiting for Command Completion\n");
1290  		pcib_pcie_intr_hotplug(sc);
1291  	}
1292  	PCIB_HP_UNLOCK(sc);
1293  }
1294  
1295  static void
1296  pcib_pcie_dll_timeout(void *arg, int pending)
1297  {
1298  	struct pcib_softc *sc = arg;
1299  	device_t dev = sc->dev;
1300  	uint16_t sta;
1301  
1302  	PCIB_HP_LOCK(sc);
1303  	sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1304  	if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1305  		device_printf(dev,
1306  		    "Timed out waiting for Data Link Layer Active\n");
1307  		sc->flags |= PCIB_DETACHING;
1308  		pcib_pcie_hotplug_update(sc, 0, 0, true);
1309  	} else if (sta != sc->pcie_link_sta) {
1310  		device_printf(dev,
1311  		    "Missed HotPlug interrupt waiting for DLL Active\n");
1312  		pcib_pcie_intr_hotplug(sc);
1313  	}
1314  	PCIB_HP_UNLOCK(sc);
1315  }
1316  
1317  static int
1318  pcib_alloc_pcie_irq(struct pcib_softc *sc)
1319  {
1320  	device_t dev;
1321  	int count, error, rid;
1322  
1323  	rid = -1;
1324  	dev = sc->dev;
1325  
1326  	/*
1327  	 * For simplicity, only use MSI-X if there is a single message.
1328  	 * To support a device with multiple messages we would have to
1329  	 * use remap intr if the MSI number is not 0.
1330  	 */
1331  	count = pci_msix_count(dev);
1332  	if (count == 1) {
1333  		error = pci_alloc_msix(dev, &count);
1334  		if (error == 0)
1335  			rid = 1;
1336  	}
1337  
1338  	if (rid < 0 && pci_msi_count(dev) > 0) {
1339  		count = 1;
1340  		error = pci_alloc_msi(dev, &count);
1341  		if (error == 0)
1342  			rid = 1;
1343  	}
1344  
1345  	if (rid < 0)
1346  		rid = 0;
1347  
1348  	sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1349  	    RF_ACTIVE | RF_SHAREABLE);
1350  	if (sc->pcie_irq == NULL) {
1351  		device_printf(dev,
1352  		    "Failed to allocate interrupt for PCI-e events\n");
1353  		if (rid > 0)
1354  			pci_release_msi(dev);
1355  		return (ENXIO);
1356  	}
1357  
1358  	error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE,
1359  	    NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1360  	if (error) {
1361  		device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1362  		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1363  		if (rid > 0)
1364  			pci_release_msi(dev);
1365  		return (error);
1366  	}
1367  	return (0);
1368  }
1369  
1370  static int
1371  pcib_release_pcie_irq(struct pcib_softc *sc)
1372  {
1373  	device_t dev;
1374  	int error;
1375  
1376  	dev = sc->dev;
1377  	error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1378  	if (error)
1379  		return (error);
1380  	error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1381  	if (error)
1382  		return (error);
1383  	return (pci_release_msi(dev));
1384  }
1385  
1386  static void
1387  pcib_setup_hotplug(struct pcib_softc *sc)
1388  {
1389  	device_t dev;
1390  	uint16_t mask, val;
1391  
1392  	dev = sc->dev;
1393  	TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1394  	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_ab_task, 0,
1395  	    pcib_pcie_ab_timeout, sc);
1396  	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_cc_task, 0,
1397  	    pcib_pcie_cc_timeout, sc);
1398  	TIMEOUT_TASK_INIT(taskqueue_pci_hp, &sc->pcie_dll_task, 0,
1399  	    pcib_pcie_dll_timeout, sc);
1400  	sc->pcie_hp_lock = bus_topo_mtx();
1401  
1402  	/* Allocate IRQ. */
1403  	if (pcib_alloc_pcie_irq(sc) != 0)
1404  		return;
1405  
1406  	sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1407  	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1408  
1409  	/* Clear any events previously pending. */
1410  	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1411  
1412  	/* Enable HotPlug events. */
1413  	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1414  	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1415  	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1416  	val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1417  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1418  		val |= PCIEM_SLOT_CTL_ABPE;
1419  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1420  		val |= PCIEM_SLOT_CTL_PFDE;
1421  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1422  		val |= PCIEM_SLOT_CTL_MRLSCE;
1423  	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1424  		val |= PCIEM_SLOT_CTL_CCIE;
1425  
1426  	/* Turn the attention indicator off. */
1427  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1428  		mask |= PCIEM_SLOT_CTL_AIC;
1429  		val |= PCIEM_SLOT_CTL_AI_OFF;
1430  	}
1431  
1432  	pcib_pcie_hotplug_update(sc, val, mask, false);
1433  }
1434  
1435  static int
1436  pcib_detach_hotplug(struct pcib_softc *sc)
1437  {
1438  	uint16_t mask, val;
1439  	int error;
1440  
1441  	/* Disable the card in the slot and force it to detach. */
1442  	if (sc->flags & PCIB_DETACH_PENDING) {
1443  		sc->flags &= ~PCIB_DETACH_PENDING;
1444  		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_ab_task,
1445  		    NULL);
1446  	}
1447  	sc->flags |= PCIB_DETACHING;
1448  
1449  	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1450  		taskqueue_cancel_timeout(taskqueue_pci_hp, &sc->pcie_cc_task,
1451  		    NULL);
1452  		tsleep(sc, 0, "hpcmd", hz);
1453  		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1454  	}
1455  
1456  	/* Disable HotPlug events. */
1457  	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1458  	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1459  	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1460  	val = 0;
1461  
1462  	/* Turn the attention indicator off. */
1463  	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1464  		mask |= PCIEM_SLOT_CTL_AIC;
1465  		val |= PCIEM_SLOT_CTL_AI_OFF;
1466  	}
1467  
1468  	pcib_pcie_hotplug_update(sc, val, mask, false);
1469  
1470  	error = pcib_release_pcie_irq(sc);
1471  	if (error)
1472  		return (error);
1473  	taskqueue_drain(taskqueue_pci_hp, &sc->pcie_hp_task);
1474  	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_ab_task);
1475  	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_cc_task);
1476  	taskqueue_drain_timeout(taskqueue_pci_hp, &sc->pcie_dll_task);
1477  	return (0);
1478  }
1479  #endif
1480  
1481  /*
1482   * Get current bridge configuration.
1483   */
1484  static void
1485  pcib_cfg_save(struct pcib_softc *sc)
1486  {
1487  #ifndef NEW_PCIB
1488  	device_t	dev;
1489  	uint16_t command;
1490  
1491  	dev = sc->dev;
1492  
1493  	command = pci_read_config(dev, PCIR_COMMAND, 2);
1494  	if (command & PCIM_CMD_PORTEN)
1495  		pcib_get_io_decode(sc);
1496  	if (command & PCIM_CMD_MEMEN)
1497  		pcib_get_mem_decode(sc);
1498  #endif
1499  }
1500  
1501  /*
1502   * Restore previous bridge configuration.
1503   */
1504  static void
1505  pcib_cfg_restore(struct pcib_softc *sc)
1506  {
1507  #ifndef NEW_PCIB
1508  	uint16_t command;
1509  #endif
1510  
1511  #ifdef NEW_PCIB
1512  	pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1513  #else
1514  	command = pci_read_config(sc->dev, PCIR_COMMAND, 2);
1515  	if (command & PCIM_CMD_PORTEN)
1516  		pcib_set_io_decode(sc);
1517  	if (command & PCIM_CMD_MEMEN)
1518  		pcib_set_mem_decode(sc);
1519  #endif
1520  }
1521  
1522  /*
1523   * Generic device interface
1524   */
1525  static int
1526  pcib_probe(device_t dev)
1527  {
1528      if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1529  	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1530  	device_set_desc(dev, "PCI-PCI bridge");
1531  	return(-10000);
1532      }
1533      return(ENXIO);
1534  }
1535  
1536  void
1537  pcib_attach_common(device_t dev)
1538  {
1539      struct pcib_softc	*sc;
1540      struct sysctl_ctx_list *sctx;
1541      struct sysctl_oid	*soid;
1542      int comma;
1543  
1544      sc = device_get_softc(dev);
1545      sc->dev = dev;
1546  
1547      /*
1548       * Get current bridge configuration.
1549       */
1550      sc->domain = pci_get_domain(dev);
1551  #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1552      sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1553      sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1554  #endif
1555      sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1556      pcib_cfg_save(sc);
1557  
1558      /*
1559       * The primary bus register should always be the bus of the
1560       * parent.
1561       */
1562      sc->pribus = pci_get_bus(dev);
1563      pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1564  
1565      /*
1566       * Setup sysctl reporting nodes
1567       */
1568      sctx = device_get_sysctl_ctx(dev);
1569      soid = device_get_sysctl_tree(dev);
1570      SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1571        CTLFLAG_RD, &sc->domain, 0, "Domain number");
1572      SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1573        CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1574      SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1575        CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1576      SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1577        CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1578  
1579      /*
1580       * Quirk handling.
1581       */
1582      switch (pci_get_devid(dev)) {
1583  #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1584      case 0x12258086:		/* Intel 82454KX/GX (Orion) */
1585  	{
1586  	    uint8_t	supbus;
1587  
1588  	    supbus = pci_read_config(dev, 0x41, 1);
1589  	    if (supbus != 0xff) {
1590  		sc->bus.sec = supbus + 1;
1591  		sc->bus.sub = supbus + 1;
1592  	    }
1593  	    break;
1594  	}
1595  #endif
1596  
1597      /*
1598       * The i82380FB mobile docking controller is a PCI-PCI bridge,
1599       * and it is a subtractive bridge.  However, the ProgIf is wrong
1600       * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1601       * happen.  There are also Toshiba and Cavium ThunderX bridges
1602       * that behave this way.
1603       */
1604      case 0xa002177d:		/* Cavium ThunderX */
1605      case 0x124b8086:		/* Intel 82380FB Mobile */
1606      case 0x060513d7:		/* Toshiba ???? */
1607  	sc->flags |= PCIB_SUBTRACTIVE;
1608  	break;
1609  
1610  #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1611      /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1612      case 0x00dd10de:
1613  	{
1614  	    char *cp;
1615  
1616  	    if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1617  		break;
1618  	    if (strncmp(cp, "Compal", 6) != 0) {
1619  		freeenv(cp);
1620  		break;
1621  	    }
1622  	    freeenv(cp);
1623  	    if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1624  		break;
1625  	    if (strncmp(cp, "08A0", 4) != 0) {
1626  		freeenv(cp);
1627  		break;
1628  	    }
1629  	    freeenv(cp);
1630  	    if (sc->bus.sub < 0xa) {
1631  		pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1632  		sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1633  	    }
1634  	    break;
1635  	}
1636  #endif
1637      }
1638  
1639      if (pci_msi_device_blacklisted(dev))
1640  	sc->flags |= PCIB_DISABLE_MSI;
1641  
1642      if (pci_msix_device_blacklisted(dev))
1643  	sc->flags |= PCIB_DISABLE_MSIX;
1644  
1645      /*
1646       * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1647       * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
1648       * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1649       * This means they act as if they were subtractively decoding
1650       * bridges and pass all transactions.  Mark them and real ProgIf 1
1651       * parts as subtractive.
1652       */
1653      if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1654        pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1655  	sc->flags |= PCIB_SUBTRACTIVE;
1656  
1657  #ifdef PCI_HP
1658      pcib_probe_hotplug(sc);
1659  #endif
1660  #ifdef NEW_PCIB
1661  #ifdef PCI_RES_BUS
1662      pcib_setup_secbus(dev, &sc->bus, 1);
1663  #endif
1664      pcib_probe_windows(sc);
1665  #endif
1666  #ifdef PCI_HP
1667      if (sc->flags & PCIB_HOTPLUG)
1668  	    pcib_setup_hotplug(sc);
1669  #endif
1670      if (bootverbose) {
1671  	device_printf(dev, "  domain            %d\n", sc->domain);
1672  	device_printf(dev, "  secondary bus     %d\n", sc->bus.sec);
1673  	device_printf(dev, "  subordinate bus   %d\n", sc->bus.sub);
1674  #ifdef NEW_PCIB
1675  	if (pcib_is_window_open(&sc->io))
1676  	    device_printf(dev, "  I/O decode        0x%jx-0x%jx\n",
1677  	      (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1678  	if (pcib_is_window_open(&sc->mem))
1679  	    device_printf(dev, "  memory decode     0x%jx-0x%jx\n",
1680  	      (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1681  	if (pcib_is_window_open(&sc->pmem))
1682  	    device_printf(dev, "  prefetched decode 0x%jx-0x%jx\n",
1683  	      (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1684  #else
1685  	if (pcib_is_io_open(sc))
1686  	    device_printf(dev, "  I/O decode        0x%x-0x%x\n",
1687  	      sc->iobase, sc->iolimit);
1688  	if (pcib_is_nonprefetch_open(sc))
1689  	    device_printf(dev, "  memory decode     0x%jx-0x%jx\n",
1690  	      (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1691  	if (pcib_is_prefetch_open(sc))
1692  	    device_printf(dev, "  prefetched decode 0x%jx-0x%jx\n",
1693  	      (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1694  #endif
1695  	if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1696  	    sc->flags & PCIB_SUBTRACTIVE) {
1697  		device_printf(dev, "  special decode    ");
1698  		comma = 0;
1699  		if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1700  			printf("ISA");
1701  			comma = 1;
1702  		}
1703  		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1704  			printf("%sVGA", comma ? ", " : "");
1705  			comma = 1;
1706  		}
1707  		if (sc->flags & PCIB_SUBTRACTIVE)
1708  			printf("%ssubtractive", comma ? ", " : "");
1709  		printf("\n");
1710  	}
1711      }
1712  
1713      /*
1714       * Always enable busmastering on bridges so that transactions
1715       * initiated on the secondary bus are passed through to the
1716       * primary bus.
1717       */
1718      pci_enable_busmaster(dev);
1719  }
1720  
1721  #ifdef PCI_HP
1722  static int
1723  pcib_present(struct pcib_softc *sc)
1724  {
1725  
1726  	if (sc->flags & PCIB_HOTPLUG)
1727  		return (pcib_hotplug_present(sc) != 0);
1728  	return (1);
1729  }
1730  #endif
1731  
1732  int
1733  pcib_attach_child(device_t dev)
1734  {
1735  	struct pcib_softc *sc;
1736  
1737  	sc = device_get_softc(dev);
1738  	if (sc->bus.sec == 0) {
1739  		/* no secondary bus; we should have fixed this */
1740  		return(0);
1741  	}
1742  
1743  #ifdef PCI_HP
1744  	if (!pcib_present(sc)) {
1745  		/* An empty HotPlug slot, so don't add a PCI bus yet. */
1746  		return (0);
1747  	}
1748  #endif
1749  
1750  	sc->child = device_add_child(dev, "pci", -1);
1751  	return (bus_generic_attach(dev));
1752  }
1753  
1754  int
1755  pcib_attach(device_t dev)
1756  {
1757  
1758      pcib_attach_common(dev);
1759      return (pcib_attach_child(dev));
1760  }
1761  
1762  int
1763  pcib_detach(device_t dev)
1764  {
1765  #if defined(PCI_HP) || defined(NEW_PCIB)
1766  	struct pcib_softc *sc;
1767  #endif
1768  	int error;
1769  
1770  #if defined(PCI_HP) || defined(NEW_PCIB)
1771  	sc = device_get_softc(dev);
1772  #endif
1773  	error = bus_generic_detach(dev);
1774  	if (error)
1775  		return (error);
1776  #ifdef PCI_HP
1777  	if (sc->flags & PCIB_HOTPLUG) {
1778  		error = pcib_detach_hotplug(sc);
1779  		if (error)
1780  			return (error);
1781  	}
1782  #endif
1783  	error = device_delete_children(dev);
1784  	if (error)
1785  		return (error);
1786  #ifdef NEW_PCIB
1787  	pcib_free_windows(sc);
1788  #ifdef PCI_RES_BUS
1789  	pcib_free_secbus(dev, &sc->bus);
1790  #endif
1791  #endif
1792  	return (0);
1793  }
1794  
1795  int
1796  pcib_suspend(device_t dev)
1797  {
1798  
1799  	pcib_cfg_save(device_get_softc(dev));
1800  	return (bus_generic_suspend(dev));
1801  }
1802  
1803  int
1804  pcib_resume(device_t dev)
1805  {
1806  
1807  	pcib_cfg_restore(device_get_softc(dev));
1808  
1809  	/*
1810  	 * Restore the Command register only after restoring the windows.
1811  	 * The bridge should not be claiming random windows.
1812  	 */
1813  	pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2);
1814  	return (bus_generic_resume(dev));
1815  }
1816  
1817  void
1818  pcib_bridge_init(device_t dev)
1819  {
1820  	pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1821  	pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1822  	pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1823  	pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1824  	pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1825  	pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1826  	pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1827  	pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1828  	pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1829  	pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1830  }
1831  
1832  int
1833  pcib_child_present(device_t dev, device_t child)
1834  {
1835  #ifdef PCI_HP
1836  	struct pcib_softc *sc = device_get_softc(dev);
1837  	int retval;
1838  
1839  	retval = bus_child_present(dev);
1840  	if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1841  		retval = pcib_hotplug_present(sc);
1842  	return (retval);
1843  #else
1844  	return (bus_child_present(dev));
1845  #endif
1846  }
1847  
1848  int
1849  pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1850  {
1851      struct pcib_softc	*sc = device_get_softc(dev);
1852  
1853      switch (which) {
1854      case PCIB_IVAR_DOMAIN:
1855  	*result = sc->domain;
1856  	return(0);
1857      case PCIB_IVAR_BUS:
1858  	*result = sc->bus.sec;
1859  	return(0);
1860      }
1861      return(ENOENT);
1862  }
1863  
1864  int
1865  pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1866  {
1867  
1868      switch (which) {
1869      case PCIB_IVAR_DOMAIN:
1870  	return(EINVAL);
1871      case PCIB_IVAR_BUS:
1872  	return(EINVAL);
1873      }
1874      return(ENOENT);
1875  }
1876  
1877  #ifdef NEW_PCIB
1878  /*
1879   * Attempt to allocate a resource from the existing resources assigned
1880   * to a window.
1881   */
1882  static struct resource *
1883  pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1884      device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1885      rman_res_t count, u_int flags)
1886  {
1887  	struct resource *res;
1888  
1889  	if (!pcib_is_window_open(w))
1890  		return (NULL);
1891  
1892  	res = rman_reserve_resource(&w->rman, start, end, count,
1893  	    flags & ~RF_ACTIVE, child);
1894  	if (res == NULL)
1895  		return (NULL);
1896  
1897  	if (bootverbose)
1898  		device_printf(sc->dev,
1899  		    "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1900  		    w->name, rman_get_start(res), rman_get_end(res), *rid,
1901  		    pcib_child_name(child));
1902  	rman_set_rid(res, *rid);
1903  
1904  	/*
1905  	 * If the resource should be active, pass that request up the
1906  	 * tree.  This assumes the parent drivers can handle
1907  	 * activating sub-allocated resources.
1908  	 */
1909  	if (flags & RF_ACTIVE) {
1910  		if (bus_activate_resource(child, type, *rid, res) != 0) {
1911  			rman_release_resource(res);
1912  			return (NULL);
1913  		}
1914  	}
1915  
1916  	return (res);
1917  }
1918  
1919  /* Allocate a fresh resource range for an unconfigured window. */
1920  static int
1921  pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1922      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1923  {
1924  	struct resource *res;
1925  	rman_res_t base, limit, wmask;
1926  	int rid;
1927  
1928  	/*
1929  	 * If this is an I/O window on a bridge with ISA enable set
1930  	 * and the start address is below 64k, then try to allocate an
1931  	 * initial window of 0x1000 bytes long starting at address
1932  	 * 0xf000 and walking down.  Note that if the original request
1933  	 * was larger than the non-aliased range size of 0x100 our
1934  	 * caller would have raised the start address up to 64k
1935  	 * already.
1936  	 */
1937  	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1938  	    start < 65536) {
1939  		for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1940  			limit = base + 0xfff;
1941  
1942  			/*
1943  			 * Skip ranges that wouldn't work for the
1944  			 * original request.  Note that the actual
1945  			 * window that overlaps are the non-alias
1946  			 * ranges within [base, limit], so this isn't
1947  			 * quite a simple comparison.
1948  			 */
1949  			if (start + count > limit - 0x400)
1950  				continue;
1951  			if (base == 0) {
1952  				/*
1953  				 * The first open region for the window at
1954  				 * 0 is 0x400-0x4ff.
1955  				 */
1956  				if (end - count + 1 < 0x400)
1957  					continue;
1958  			} else {
1959  				if (end - count + 1 < base)
1960  					continue;
1961  			}
1962  
1963  			if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1964  				w->base = base;
1965  				w->limit = limit;
1966  				return (0);
1967  			}
1968  		}
1969  		return (ENOSPC);
1970  	}
1971  
1972  	wmask = ((rman_res_t)1 << w->step) - 1;
1973  	if (RF_ALIGNMENT(flags) < w->step) {
1974  		flags &= ~RF_ALIGNMENT_MASK;
1975  		flags |= RF_ALIGNMENT_LOG2(w->step);
1976  	}
1977  	start &= ~wmask;
1978  	end |= wmask;
1979  	count = roundup2(count, (rman_res_t)1 << w->step);
1980  	rid = w->reg;
1981  	res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1982  	    flags & ~RF_ACTIVE);
1983  	if (res == NULL)
1984  		return (ENOSPC);
1985  	pcib_add_window_resources(w, &res, 1);
1986  	pcib_activate_window(sc, type);
1987  	w->base = rman_get_start(res);
1988  	w->limit = rman_get_end(res);
1989  	return (0);
1990  }
1991  
1992  /* Try to expand an existing window to the requested base and limit. */
1993  static int
1994  pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1995      rman_res_t base, rman_res_t limit)
1996  {
1997  	struct resource *res;
1998  	int error, i, force_64k_base;
1999  
2000  	KASSERT(base <= w->base && limit >= w->limit,
2001  	    ("attempting to shrink window"));
2002  
2003  	/*
2004  	 * XXX: pcib_grow_window() doesn't try to do this anyway and
2005  	 * the error handling for all the edge cases would be tedious.
2006  	 */
2007  	KASSERT(limit == w->limit || base == w->base,
2008  	    ("attempting to grow both ends of a window"));
2009  
2010  	/*
2011  	 * Yet more special handling for requests to expand an I/O
2012  	 * window behind an ISA-enabled bridge.  Since I/O windows
2013  	 * have to grow in 0x1000 increments and the end of the 0xffff
2014  	 * range is an alias, growing a window below 64k will always
2015  	 * result in allocating new resources and never adjusting an
2016  	 * existing resource.
2017  	 */
2018  	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2019  	    (limit <= 65535 || (base <= 65535 && base != w->base))) {
2020  		KASSERT(limit == w->limit || limit <= 65535,
2021  		    ("attempting to grow both ends across 64k ISA alias"));
2022  
2023  		if (base != w->base)
2024  			error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
2025  		else
2026  			error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2027  			    limit);
2028  		if (error == 0) {
2029  			w->base = base;
2030  			w->limit = limit;
2031  		}
2032  		return (error);
2033  	}
2034  
2035  	/*
2036  	 * Find the existing resource to adjust.  Usually there is only one,
2037  	 * but for an ISA-enabled bridge we might be growing the I/O window
2038  	 * above 64k and need to find the existing resource that maps all
2039  	 * of the area above 64k.
2040  	 */
2041  	for (i = 0; i < w->count; i++) {
2042  		if (rman_get_end(w->res[i]) == w->limit)
2043  			break;
2044  	}
2045  	KASSERT(i != w->count, ("did not find existing resource"));
2046  	res = w->res[i];
2047  
2048  	/*
2049  	 * Usually the resource we found should match the window's
2050  	 * existing range.  The one exception is the ISA-enabled case
2051  	 * mentioned above in which case the resource should start at
2052  	 * 64k.
2053  	 */
2054  	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2055  	    w->base <= 65535) {
2056  		KASSERT(rman_get_start(res) == 65536,
2057  		    ("existing resource mismatch"));
2058  		force_64k_base = 1;
2059  	} else {
2060  		KASSERT(w->base == rman_get_start(res),
2061  		    ("existing resource mismatch"));
2062  		force_64k_base = 0;
2063  	}
2064  
2065  	error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2066  	    rman_get_start(res) : base, limit);
2067  	if (error)
2068  		return (error);
2069  
2070  	/* Add the newly allocated region to the resource manager. */
2071  	if (w->base != base) {
2072  		error = rman_manage_region(&w->rman, base, w->base - 1);
2073  		w->base = base;
2074  	} else {
2075  		error = rman_manage_region(&w->rman, w->limit + 1, limit);
2076  		w->limit = limit;
2077  	}
2078  	if (error) {
2079  		if (bootverbose)
2080  			device_printf(sc->dev,
2081  			    "failed to expand %s resource manager\n", w->name);
2082  		(void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2083  		    rman_get_start(res) : w->base, w->limit);
2084  	}
2085  	return (error);
2086  }
2087  
2088  /*
2089   * Attempt to grow a window to make room for a given resource request.
2090   */
2091  static int
2092  pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2093      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2094  {
2095  	rman_res_t align, start_free, end_free, front, back, wmask;
2096  	int error;
2097  
2098  	/*
2099  	 * Clamp the desired resource range to the maximum address
2100  	 * this window supports.  Reject impossible requests.
2101  	 *
2102  	 * For I/O port requests behind a bridge with the ISA enable
2103  	 * bit set, force large allocations to start above 64k.
2104  	 */
2105  	if (!w->valid)
2106  		return (EINVAL);
2107  	if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2108  	    start < 65536)
2109  		start = 65536;
2110  	if (end > w->rman.rm_end)
2111  		end = w->rman.rm_end;
2112  	if (start + count - 1 > end || start + count < start)
2113  		return (EINVAL);
2114  	wmask = ((rman_res_t)1 << w->step) - 1;
2115  
2116  	/*
2117  	 * If there is no resource at all, just try to allocate enough
2118  	 * aligned space for this resource.
2119  	 */
2120  	if (w->res == NULL) {
2121  		error = pcib_alloc_new_window(sc, w, type, start, end, count,
2122  		    flags);
2123  		if (error) {
2124  			if (bootverbose)
2125  				device_printf(sc->dev,
2126  		    "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2127  				    w->name, start, end, count);
2128  			return (error);
2129  		}
2130  		if (bootverbose)
2131  			device_printf(sc->dev,
2132  			    "allocated initial %s window of %#jx-%#jx\n",
2133  			    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2134  		goto updatewin;
2135  	}
2136  
2137  	/*
2138  	 * See if growing the window would help.  Compute the minimum
2139  	 * amount of address space needed on both the front and back
2140  	 * ends of the existing window to satisfy the allocation.
2141  	 *
2142  	 * For each end, build a candidate region adjusting for the
2143  	 * required alignment, etc.  If there is a free region at the
2144  	 * edge of the window, grow from the inner edge of the free
2145  	 * region.  Otherwise grow from the window boundary.
2146  	 *
2147  	 * Growing an I/O window below 64k for a bridge with the ISA
2148  	 * enable bit doesn't require any special magic as the step
2149  	 * size of an I/O window (1k) always includes multiple
2150  	 * non-alias ranges when it is grown in either direction.
2151  	 *
2152  	 * XXX: Special case: if w->res is completely empty and the
2153  	 * request size is larger than w->res, we should find the
2154  	 * optimal aligned buffer containing w->res and allocate that.
2155  	 */
2156  	if (bootverbose)
2157  		device_printf(sc->dev,
2158  		    "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2159  		    w->name, start, end, count);
2160  	align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2161  	if (start < w->base) {
2162  		if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2163  		    0 || start_free != w->base)
2164  			end_free = w->base;
2165  		if (end_free > end)
2166  			end_free = end + 1;
2167  
2168  		/* Move end_free down until it is properly aligned. */
2169  		end_free &= ~(align - 1);
2170  		end_free--;
2171  		front = end_free - (count - 1);
2172  
2173  		/*
2174  		 * The resource would now be allocated at (front,
2175  		 * end_free).  Ensure that fits in the (start, end)
2176  		 * bounds.  end_free is checked above.  If 'front' is
2177  		 * ok, ensure it is properly aligned for this window.
2178  		 * Also check for underflow.
2179  		 */
2180  		if (front >= start && front <= end_free) {
2181  			if (bootverbose)
2182  				printf("\tfront candidate range: %#jx-%#jx\n",
2183  				    front, end_free);
2184  			front &= ~wmask;
2185  			front = w->base - front;
2186  		} else
2187  			front = 0;
2188  	} else
2189  		front = 0;
2190  	if (end > w->limit) {
2191  		if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2192  		    0 || end_free != w->limit)
2193  			start_free = w->limit + 1;
2194  		if (start_free < start)
2195  			start_free = start;
2196  
2197  		/* Move start_free up until it is properly aligned. */
2198  		start_free = roundup2(start_free, align);
2199  		back = start_free + count - 1;
2200  
2201  		/*
2202  		 * The resource would now be allocated at (start_free,
2203  		 * back).  Ensure that fits in the (start, end)
2204  		 * bounds.  start_free is checked above.  If 'back' is
2205  		 * ok, ensure it is properly aligned for this window.
2206  		 * Also check for overflow.
2207  		 */
2208  		if (back <= end && start_free <= back) {
2209  			if (bootverbose)
2210  				printf("\tback candidate range: %#jx-%#jx\n",
2211  				    start_free, back);
2212  			back |= wmask;
2213  			back -= w->limit;
2214  		} else
2215  			back = 0;
2216  	} else
2217  		back = 0;
2218  
2219  	/*
2220  	 * Try to allocate the smallest needed region first.
2221  	 * If that fails, fall back to the other region.
2222  	 */
2223  	error = ENOSPC;
2224  	while (front != 0 || back != 0) {
2225  		if (front != 0 && (front <= back || back == 0)) {
2226  			error = pcib_expand_window(sc, w, type, w->base - front,
2227  			    w->limit);
2228  			if (error == 0)
2229  				break;
2230  			front = 0;
2231  		} else {
2232  			error = pcib_expand_window(sc, w, type, w->base,
2233  			    w->limit + back);
2234  			if (error == 0)
2235  				break;
2236  			back = 0;
2237  		}
2238  	}
2239  
2240  	if (error)
2241  		return (error);
2242  	if (bootverbose)
2243  		device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2244  		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2245  
2246  updatewin:
2247  	/* Write the new window. */
2248  	KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2249  	KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2250  	pcib_write_windows(sc, w->mask);
2251  	return (0);
2252  }
2253  
2254  /*
2255   * We have to trap resource allocation requests and ensure that the bridge
2256   * is set up to, or capable of handling them.
2257   */
2258  struct resource *
2259  pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2260      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2261  {
2262  	struct pcib_softc *sc;
2263  	struct resource *r;
2264  
2265  	sc = device_get_softc(dev);
2266  
2267  	/*
2268  	 * VGA resources are decoded iff the VGA enable bit is set in
2269  	 * the bridge control register.  VGA resources do not fall into
2270  	 * the resource windows and are passed up to the parent.
2271  	 */
2272  	if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2273  	    (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2274  		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2275  			return (bus_generic_alloc_resource(dev, child, type,
2276  			    rid, start, end, count, flags));
2277  		else
2278  			return (NULL);
2279  	}
2280  
2281  	switch (type) {
2282  #ifdef PCI_RES_BUS
2283  	case PCI_RES_BUS:
2284  		return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2285  		    count, flags));
2286  #endif
2287  	case SYS_RES_IOPORT:
2288  		if (pcib_is_isa_range(sc, start, end, count))
2289  			return (NULL);
2290  		r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2291  		    end, count, flags);
2292  		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2293  			break;
2294  		if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2295  		    flags) == 0)
2296  			r = pcib_suballoc_resource(sc, &sc->io, child, type,
2297  			    rid, start, end, count, flags);
2298  		break;
2299  	case SYS_RES_MEMORY:
2300  		/*
2301  		 * For prefetchable resources, prefer the prefetchable
2302  		 * memory window, but fall back to the regular memory
2303  		 * window if that fails.  Try both windows before
2304  		 * attempting to grow a window in case the firmware
2305  		 * has used a range in the regular memory window to
2306  		 * map a prefetchable BAR.
2307  		 */
2308  		if (flags & RF_PREFETCHABLE) {
2309  			r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2310  			    rid, start, end, count, flags);
2311  			if (r != NULL)
2312  				break;
2313  		}
2314  		r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2315  		    start, end, count, flags);
2316  		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2317  			break;
2318  		if (flags & RF_PREFETCHABLE) {
2319  			if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2320  			    count, flags) == 0) {
2321  				r = pcib_suballoc_resource(sc, &sc->pmem, child,
2322  				    type, rid, start, end, count, flags);
2323  				if (r != NULL)
2324  					break;
2325  			}
2326  		}
2327  		if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2328  		    flags & ~RF_PREFETCHABLE) == 0)
2329  			r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2330  			    rid, start, end, count, flags);
2331  		break;
2332  	default:
2333  		return (bus_generic_alloc_resource(dev, child, type, rid,
2334  		    start, end, count, flags));
2335  	}
2336  
2337  	/*
2338  	 * If attempts to suballocate from the window fail but this is a
2339  	 * subtractive bridge, pass the request up the tree.
2340  	 */
2341  	if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2342  		return (bus_generic_alloc_resource(dev, child, type, rid,
2343  		    start, end, count, flags));
2344  	return (r);
2345  }
2346  
2347  int
2348  pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2349      rman_res_t start, rman_res_t end)
2350  {
2351  	struct pcib_softc *sc;
2352  	struct pcib_window *w;
2353  	rman_res_t wmask;
2354  	int error;
2355  
2356  	sc = device_get_softc(bus);
2357  
2358  	/*
2359  	 * If the resource wasn't sub-allocated from one of our region
2360  	 * managers then just pass the request up.
2361  	 */
2362  	if (!pcib_is_resource_managed(sc, type, r))
2363  		return (bus_generic_adjust_resource(bus, child, type, r,
2364  		    start, end));
2365  
2366  #ifdef PCI_RES_BUS
2367  	if (type == PCI_RES_BUS) {
2368  		/*
2369  		 * If our bus range isn't big enough to grow the sub-allocation
2370  		 * then we need to grow our bus range. Any request that would
2371  		 * require us to decrease the start of our own bus range is
2372  		 * invalid, we can only extend the end; ignore such requests
2373  		 * and let rman_adjust_resource fail below.
2374  		 */
2375  		if (start >= sc->bus.sec && end > sc->bus.sub) {
2376  			error = pcib_grow_subbus(&sc->bus, end);
2377  			if (error != 0)
2378  				return (error);
2379  		}
2380  	} else
2381  #endif
2382  	{
2383  		/*
2384  		 * Resource is managed and not a secondary bus number, must
2385  		 * be from one of our windows.
2386  		 */
2387  		w = pcib_get_resource_window(sc, type, r);
2388  		KASSERT(w != NULL,
2389  		    ("%s: no window for resource (%#jx-%#jx) type %d",
2390  		    __func__, rman_get_start(r), rman_get_end(r), type));
2391  
2392  		/*
2393  		 * If our window isn't big enough to grow the sub-allocation
2394  		 * then we need to expand the window.
2395  		 */
2396  		if (start < w->base || end > w->limit) {
2397  			wmask = ((rman_res_t)1 << w->step) - 1;
2398  			error = pcib_expand_window(sc, w, type,
2399  			    MIN(start & ~wmask, w->base),
2400  			    MAX(end | wmask, w->limit));
2401  			if (error != 0)
2402  				return (error);
2403  			if (bootverbose)
2404  				device_printf(sc->dev,
2405  				    "grew %s window to %#jx-%#jx\n",
2406  				    w->name, (uintmax_t)w->base,
2407  				    (uintmax_t)w->limit);
2408  			pcib_write_windows(sc, w->mask);
2409  		}
2410  	}
2411  
2412  	return (rman_adjust_resource(r, start, end));
2413  }
2414  
2415  int
2416  pcib_release_resource(device_t dev, device_t child, int type, int rid,
2417      struct resource *r)
2418  {
2419  	struct pcib_softc *sc;
2420  	int error;
2421  
2422  	sc = device_get_softc(dev);
2423  	if (pcib_is_resource_managed(sc, type, r)) {
2424  		if (rman_get_flags(r) & RF_ACTIVE) {
2425  			error = bus_deactivate_resource(child, type, rid, r);
2426  			if (error)
2427  				return (error);
2428  		}
2429  		return (rman_release_resource(r));
2430  	}
2431  	return (bus_generic_release_resource(dev, child, type, rid, r));
2432  }
2433  #else
2434  /*
2435   * We have to trap resource allocation requests and ensure that the bridge
2436   * is set up to, or capable of handling them.
2437   */
2438  struct resource *
2439  pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2440      rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2441  {
2442  	struct pcib_softc	*sc = device_get_softc(dev);
2443  	const char *name, *suffix;
2444  	int ok;
2445  
2446  	/*
2447  	 * Fail the allocation for this range if it's not supported.
2448  	 */
2449  	name = device_get_nameunit(child);
2450  	if (name == NULL) {
2451  		name = "";
2452  		suffix = "";
2453  	} else
2454  		suffix = " ";
2455  	switch (type) {
2456  	case SYS_RES_IOPORT:
2457  		ok = 0;
2458  		if (!pcib_is_io_open(sc))
2459  			break;
2460  		ok = (start >= sc->iobase && end <= sc->iolimit);
2461  
2462  		/*
2463  		 * Make sure we allow access to VGA I/O addresses when the
2464  		 * bridge has the "VGA Enable" bit set.
2465  		 */
2466  		if (!ok && pci_is_vga_ioport_range(start, end))
2467  			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2468  
2469  		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2470  			if (!ok) {
2471  				if (start < sc->iobase)
2472  					start = sc->iobase;
2473  				if (end > sc->iolimit)
2474  					end = sc->iolimit;
2475  				if (start < end)
2476  					ok = 1;
2477  			}
2478  		} else {
2479  			ok = 1;
2480  #if 0
2481  			/*
2482  			 * If we overlap with the subtractive range, then
2483  			 * pick the upper range to use.
2484  			 */
2485  			if (start < sc->iolimit && end > sc->iobase)
2486  				start = sc->iolimit + 1;
2487  #endif
2488  		}
2489  		if (end < start) {
2490  			device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2491  			    end, start);
2492  			start = 0;
2493  			end = 0;
2494  			ok = 0;
2495  		}
2496  		if (!ok) {
2497  			device_printf(dev, "%s%srequested unsupported I/O "
2498  			    "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2499  			    name, suffix, start, end, sc->iobase, sc->iolimit);
2500  			return (NULL);
2501  		}
2502  		if (bootverbose)
2503  			device_printf(dev,
2504  			    "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2505  			    name, suffix, start, end);
2506  		break;
2507  
2508  	case SYS_RES_MEMORY:
2509  		ok = 0;
2510  		if (pcib_is_nonprefetch_open(sc))
2511  			ok = ok || (start >= sc->membase && end <= sc->memlimit);
2512  		if (pcib_is_prefetch_open(sc))
2513  			ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2514  
2515  		/*
2516  		 * Make sure we allow access to VGA memory addresses when the
2517  		 * bridge has the "VGA Enable" bit set.
2518  		 */
2519  		if (!ok && pci_is_vga_memory_range(start, end))
2520  			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2521  
2522  		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2523  			if (!ok) {
2524  				ok = 1;
2525  				if (flags & RF_PREFETCHABLE) {
2526  					if (pcib_is_prefetch_open(sc)) {
2527  						if (start < sc->pmembase)
2528  							start = sc->pmembase;
2529  						if (end > sc->pmemlimit)
2530  							end = sc->pmemlimit;
2531  					} else {
2532  						ok = 0;
2533  					}
2534  				} else {	/* non-prefetchable */
2535  					if (pcib_is_nonprefetch_open(sc)) {
2536  						if (start < sc->membase)
2537  							start = sc->membase;
2538  						if (end > sc->memlimit)
2539  							end = sc->memlimit;
2540  					} else {
2541  						ok = 0;
2542  					}
2543  				}
2544  			}
2545  		} else if (!ok) {
2546  			ok = 1;	/* subtractive bridge: always ok */
2547  #if 0
2548  			if (pcib_is_nonprefetch_open(sc)) {
2549  				if (start < sc->memlimit && end > sc->membase)
2550  					start = sc->memlimit + 1;
2551  			}
2552  			if (pcib_is_prefetch_open(sc)) {
2553  				if (start < sc->pmemlimit && end > sc->pmembase)
2554  					start = sc->pmemlimit + 1;
2555  			}
2556  #endif
2557  		}
2558  		if (end < start) {
2559  			device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2560  			    end, start);
2561  			start = 0;
2562  			end = 0;
2563  			ok = 0;
2564  		}
2565  		if (!ok && bootverbose)
2566  			device_printf(dev,
2567  			    "%s%srequested unsupported memory range %#jx-%#jx "
2568  			    "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2569  			    name, suffix, start, end,
2570  			    (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2571  			    (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2572  		if (!ok)
2573  			return (NULL);
2574  		if (bootverbose)
2575  			device_printf(dev,"%s%srequested memory range "
2576  			    "0x%jx-0x%jx: good\n",
2577  			    name, suffix, start, end);
2578  		break;
2579  
2580  	default:
2581  		break;
2582  	}
2583  	/*
2584  	 * Bridge is OK decoding this resource, so pass it up.
2585  	 */
2586  	return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2587  	    count, flags));
2588  }
2589  #endif
2590  
2591  /*
2592   * If ARI is enabled on this downstream port, translate the function number
2593   * to the non-ARI slot/function.  The downstream port will convert it back in
2594   * hardware.  If ARI is not enabled slot and func are not modified.
2595   */
2596  static __inline void
2597  pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2598  {
2599  	struct pcib_softc *sc;
2600  	int ari_func;
2601  
2602  	sc = device_get_softc(pcib);
2603  	ari_func = *func;
2604  
2605  	if (sc->flags & PCIB_ENABLE_ARI) {
2606  		KASSERT(*slot == 0,
2607  		    ("Non-zero slot number with ARI enabled!"));
2608  		*slot = PCIE_ARI_SLOT(ari_func);
2609  		*func = PCIE_ARI_FUNC(ari_func);
2610  	}
2611  }
2612  
2613  static void
2614  pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2615  {
2616  	uint32_t ctl2;
2617  
2618  	ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2619  	ctl2 |= PCIEM_CTL2_ARI;
2620  	pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2621  
2622  	sc->flags |= PCIB_ENABLE_ARI;
2623  }
2624  
2625  /*
2626   * PCIB interface.
2627   */
2628  int
2629  pcib_maxslots(device_t dev)
2630  {
2631  #if !defined(__amd64__) && !defined(__i386__)
2632  	uint32_t pcie_pos;
2633  	uint16_t val;
2634  
2635  	/*
2636  	 * If this is a PCIe rootport or downstream switch port, there's only
2637  	 * one slot permitted.
2638  	 */
2639  	if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2640  		val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2641  		val &= PCIEM_FLAGS_TYPE;
2642  		if (val == PCIEM_TYPE_ROOT_PORT ||
2643  		    val == PCIEM_TYPE_DOWNSTREAM_PORT)
2644  			return (0);
2645  	}
2646  #endif
2647  	return (PCI_SLOTMAX);
2648  }
2649  
2650  static int
2651  pcib_ari_maxslots(device_t dev)
2652  {
2653  	struct pcib_softc *sc;
2654  
2655  	sc = device_get_softc(dev);
2656  
2657  	if (sc->flags & PCIB_ENABLE_ARI)
2658  		return (PCIE_ARI_SLOTMAX);
2659  	else
2660  		return (pcib_maxslots(dev));
2661  }
2662  
2663  static int
2664  pcib_ari_maxfuncs(device_t dev)
2665  {
2666  	struct pcib_softc *sc;
2667  
2668  	sc = device_get_softc(dev);
2669  
2670  	if (sc->flags & PCIB_ENABLE_ARI)
2671  		return (PCIE_ARI_FUNCMAX);
2672  	else
2673  		return (PCI_FUNCMAX);
2674  }
2675  
2676  static void
2677  pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2678      int *func)
2679  {
2680  	struct pcib_softc *sc;
2681  
2682  	sc = device_get_softc(pcib);
2683  
2684  	*bus = PCI_RID2BUS(rid);
2685  	if (sc->flags & PCIB_ENABLE_ARI) {
2686  		*slot = PCIE_ARI_RID2SLOT(rid);
2687  		*func = PCIE_ARI_RID2FUNC(rid);
2688  	} else {
2689  		*slot = PCI_RID2SLOT(rid);
2690  		*func = PCI_RID2FUNC(rid);
2691  	}
2692  }
2693  
2694  /*
2695   * Since we are a child of a PCI bus, its parent must support the pcib interface.
2696   */
2697  static uint32_t
2698  pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2699  {
2700  #ifdef PCI_HP
2701  	struct pcib_softc *sc;
2702  
2703  	sc = device_get_softc(dev);
2704  	if (!pcib_present(sc)) {
2705  		switch (width) {
2706  		case 2:
2707  			return (0xffff);
2708  		case 1:
2709  			return (0xff);
2710  		default:
2711  			return (0xffffffff);
2712  		}
2713  	}
2714  #endif
2715  	pcib_xlate_ari(dev, b, &s, &f);
2716  	return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2717  	    f, reg, width));
2718  }
2719  
2720  static void
2721  pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2722  {
2723  #ifdef PCI_HP
2724  	struct pcib_softc *sc;
2725  
2726  	sc = device_get_softc(dev);
2727  	if (!pcib_present(sc))
2728  		return;
2729  #endif
2730  	pcib_xlate_ari(dev, b, &s, &f);
2731  	PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2732  	    reg, val, width);
2733  }
2734  
2735  /*
2736   * Route an interrupt across a PCI bridge.
2737   */
2738  int
2739  pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2740  {
2741      device_t	bus;
2742      int		parent_intpin;
2743      int		intnum;
2744  
2745      /*
2746       *
2747       * The PCI standard defines a swizzle of the child-side device/intpin to
2748       * the parent-side intpin as follows.
2749       *
2750       * device = device on child bus
2751       * child_intpin = intpin on child bus slot (0-3)
2752       * parent_intpin = intpin on parent bus slot (0-3)
2753       *
2754       * parent_intpin = (device + child_intpin) % 4
2755       */
2756      parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2757  
2758      /*
2759       * Our parent is a PCI bus.  Its parent must export the pcib interface
2760       * which includes the ability to route interrupts.
2761       */
2762      bus = device_get_parent(pcib);
2763      intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2764      if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2765  	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2766  	    pci_get_slot(dev), 'A' + pin - 1, intnum);
2767      }
2768      return(intnum);
2769  }
2770  
2771  /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2772  int
2773  pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2774  {
2775  	struct pcib_softc *sc = device_get_softc(pcib);
2776  	device_t bus;
2777  
2778  	if (sc->flags & PCIB_DISABLE_MSI)
2779  		return (ENXIO);
2780  	bus = device_get_parent(pcib);
2781  	return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2782  	    irqs));
2783  }
2784  
2785  /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2786  int
2787  pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2788  {
2789  	device_t bus;
2790  
2791  	bus = device_get_parent(pcib);
2792  	return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2793  }
2794  
2795  /* Pass request to alloc an MSI-X message up to the parent bridge. */
2796  int
2797  pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2798  {
2799  	struct pcib_softc *sc = device_get_softc(pcib);
2800  	device_t bus;
2801  
2802  	if (sc->flags & PCIB_DISABLE_MSIX)
2803  		return (ENXIO);
2804  	bus = device_get_parent(pcib);
2805  	return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2806  }
2807  
2808  /* Pass request to release an MSI-X message up to the parent bridge. */
2809  int
2810  pcib_release_msix(device_t pcib, device_t dev, int irq)
2811  {
2812  	device_t bus;
2813  
2814  	bus = device_get_parent(pcib);
2815  	return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2816  }
2817  
2818  /* Pass request to map MSI/MSI-X message up to parent bridge. */
2819  int
2820  pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2821      uint32_t *data)
2822  {
2823  	device_t bus;
2824  	int error;
2825  
2826  	bus = device_get_parent(pcib);
2827  	error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2828  	if (error)
2829  		return (error);
2830  
2831  	pci_ht_map_msi(pcib, *addr);
2832  	return (0);
2833  }
2834  
2835  /* Pass request for device power state up to parent bridge. */
2836  int
2837  pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2838  {
2839  	device_t bus;
2840  
2841  	bus = device_get_parent(pcib);
2842  	return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2843  }
2844  
2845  static int
2846  pcib_ari_enabled(device_t pcib)
2847  {
2848  	struct pcib_softc *sc;
2849  
2850  	sc = device_get_softc(pcib);
2851  
2852  	return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2853  }
2854  
2855  static int
2856  pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2857      uintptr_t *id)
2858  {
2859  	struct pcib_softc *sc;
2860  	device_t bus_dev;
2861  	uint8_t bus, slot, func;
2862  
2863  	if (type != PCI_ID_RID) {
2864  		bus_dev = device_get_parent(pcib);
2865  		return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2866  	}
2867  
2868  	sc = device_get_softc(pcib);
2869  
2870  	if (sc->flags & PCIB_ENABLE_ARI) {
2871  		bus = pci_get_bus(dev);
2872  		func = pci_get_function(dev);
2873  
2874  		*id = (PCI_ARI_RID(bus, func));
2875  	} else {
2876  		bus = pci_get_bus(dev);
2877  		slot = pci_get_slot(dev);
2878  		func = pci_get_function(dev);
2879  
2880  		*id = (PCI_RID(bus, slot, func));
2881  	}
2882  
2883  	return (0);
2884  }
2885  
2886  /*
2887   * Check that the downstream port (pcib) and the endpoint device (dev) both
2888   * support ARI.  If so, enable it and return 0, otherwise return an error.
2889   */
2890  static int
2891  pcib_try_enable_ari(device_t pcib, device_t dev)
2892  {
2893  	struct pcib_softc *sc;
2894  	int error;
2895  	uint32_t cap2;
2896  	int ari_cap_off;
2897  	uint32_t ari_ver;
2898  	uint32_t pcie_pos;
2899  
2900  	sc = device_get_softc(pcib);
2901  
2902  	/*
2903  	 * ARI is controlled in a register in the PCIe capability structure.
2904  	 * If the downstream port does not have the PCIe capability structure
2905  	 * then it does not support ARI.
2906  	 */
2907  	error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2908  	if (error != 0)
2909  		return (ENODEV);
2910  
2911  	/* Check that the PCIe port advertises ARI support. */
2912  	cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2913  	if (!(cap2 & PCIEM_CAP2_ARI))
2914  		return (ENODEV);
2915  
2916  	/*
2917  	 * Check that the endpoint device advertises ARI support via the ARI
2918  	 * extended capability structure.
2919  	 */
2920  	error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2921  	if (error != 0)
2922  		return (ENODEV);
2923  
2924  	/*
2925  	 * Finally, check that the endpoint device supports the same version
2926  	 * of ARI that we do.
2927  	 */
2928  	ari_ver = pci_read_config(dev, ari_cap_off, 4);
2929  	if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2930  		if (bootverbose)
2931  			device_printf(pcib,
2932  			    "Unsupported version of ARI (%d) detected\n",
2933  			    PCI_EXTCAP_VER(ari_ver));
2934  
2935  		return (ENXIO);
2936  	}
2937  
2938  	pcib_enable_ari(sc, pcie_pos);
2939  
2940  	return (0);
2941  }
2942  
2943  int
2944  pcib_request_feature_allow(device_t pcib, device_t dev,
2945      enum pci_feature feature)
2946  {
2947  	/*
2948  	 * No host firmware we have to negotiate with, so we allow
2949  	 * every valid feature requested.
2950  	 */
2951  	switch (feature) {
2952  	case PCI_FEATURE_AER:
2953  	case PCI_FEATURE_HP:
2954  		break;
2955  	default:
2956  		return (EINVAL);
2957  	}
2958  
2959  	return (0);
2960  }
2961  
2962  int
2963  pcib_request_feature(device_t dev, enum pci_feature feature)
2964  {
2965  
2966  	/*
2967  	 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2968  	 * the firmware overrides the method of PCI-PCI bridges.
2969  	 */
2970  	return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2971  }
2972  
2973  /*
2974   * Pass the request to use this PCI feature up the tree. Either there's a
2975   * firmware like ACPI that's using this feature that will approve (or deny) the
2976   * request to take it over, or the platform has no such firmware, in which case
2977   * the request will be approved. If the request is approved, the OS is expected
2978   * to make use of the feature or render it harmless.
2979   */
2980  static int
2981  pcib_request_feature_default(device_t pcib, device_t dev,
2982      enum pci_feature feature)
2983  {
2984  	device_t bus;
2985  
2986  	/*
2987  	 * Our parent is necessarily a pci bus. Its parent will either be
2988  	 * another pci bridge (which passes it up) or a host bridge that can
2989  	 * approve or reject the request.
2990  	 */
2991  	bus = device_get_parent(pcib);
2992  	return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
2993  }
2994  
2995  static int
2996  pcib_reset_child(device_t dev, device_t child, int flags)
2997  {
2998  	struct pci_devinfo *pdinfo;
2999  	int error;
3000  
3001  	error = 0;
3002  	if (dev == NULL || device_get_parent(child) != dev)
3003  		goto out;
3004  	error = ENXIO;
3005  	if (device_get_devclass(child) != devclass_find("pci"))
3006  		goto out;
3007  	pdinfo = device_get_ivars(dev);
3008  	if (pdinfo->cfg.pcie.pcie_location != 0 &&
3009  	    (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
3010  	    pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
3011  		error = bus_helper_reset_prepare(child, flags);
3012  		if (error == 0) {
3013  			error = pcie_link_reset(dev,
3014  			    pdinfo->cfg.pcie.pcie_location);
3015  			/* XXXKIB call _post even if error != 0 ? */
3016  			bus_helper_reset_post(child, flags);
3017  		}
3018  	}
3019  out:
3020  	return (error);
3021  }
3022