1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/sysctl.h> 42 43 #include <machine/resource.h> 44 45 #include <pci/pcivar.h> 46 #include <pci/pcireg.h> 47 #include <pci/pcib_private.h> 48 49 #include "pcib_if.h" 50 51 static int pcib_probe(device_t dev); 52 static int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 53 54 static device_method_t pcib_methods[] = { 55 /* Device interface */ 56 DEVMETHOD(device_probe, pcib_probe), 57 DEVMETHOD(device_attach, pcib_attach), 58 DEVMETHOD(device_shutdown, bus_generic_shutdown), 59 DEVMETHOD(device_suspend, bus_generic_suspend), 60 DEVMETHOD(device_resume, bus_generic_resume), 61 62 /* Bus interface */ 63 DEVMETHOD(bus_print_child, bus_generic_print_child), 64 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 65 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 66 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 67 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 68 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 69 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 70 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 71 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 72 73 /* pcib interface */ 74 DEVMETHOD(pcib_maxslots, pcib_maxslots), 75 DEVMETHOD(pcib_read_config, pcib_read_config), 76 DEVMETHOD(pcib_write_config, pcib_write_config), 77 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 78 79 { 0, 0 } 80 }; 81 82 static driver_t pcib_driver = { 83 "pcib", 84 pcib_methods, 85 sizeof(struct pcib_softc), 86 }; 87 88 devclass_t pcib_devclass; 89 90 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 91 92 /* 93 * sysctl and tunable vars 94 */ 95 static int pci_allow_unsupported_io_range = 0; 96 TUNABLE_INT("hw.pci.allow_unsupported_io_range", 97 (int *)&pci_allow_unsupported_io_range); 98 SYSCTL_DECL(_hw_pci); 99 SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD, 100 &pci_allow_unsupported_io_range, 0, 101 "Allows the PCI Bridge to pass through an unsupported memory range " 102 "assigned by the BIOS."); 103 104 /* 105 * Generic device interface 106 */ 107 static int 108 pcib_probe(device_t dev) 109 { 110 if ((pci_get_class(dev) == PCIC_BRIDGE) && 111 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 112 device_set_desc(dev, "PCI-PCI bridge"); 113 return(-10000); 114 } 115 return(ENXIO); 116 } 117 118 void 119 pcib_attach_common(device_t dev) 120 { 121 struct pcib_softc *sc; 122 u_int8_t iolow; 123 124 sc = device_get_softc(dev); 125 sc->dev = dev; 126 127 /* 128 * Get current bridge configuration. 129 */ 130 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 131 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 132 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 133 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 134 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 135 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 136 137 /* 138 * Determine current I/O decode. 139 */ 140 if (sc->command & PCIM_CMD_PORTEN) { 141 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 142 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 143 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 144 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 145 } else { 146 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 147 } 148 149 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 150 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 151 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 152 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 153 } else { 154 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 155 } 156 } 157 158 /* 159 * Determine current memory decode. 160 */ 161 if (sc->command & PCIM_CMD_MEMEN) { 162 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 163 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 164 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 165 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 166 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 167 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 168 } 169 170 /* 171 * Quirk handling. 172 */ 173 switch (pci_get_devid(dev)) { 174 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 175 { 176 u_int8_t supbus; 177 178 supbus = pci_read_config(dev, 0x41, 1); 179 if (supbus != 0xff) { 180 sc->secbus = supbus + 1; 181 sc->subbus = supbus + 1; 182 } 183 } 184 break; 185 } 186 187 if (bootverbose) { 188 device_printf(dev, " secondary bus %d\n", sc->secbus); 189 device_printf(dev, " subordinate bus %d\n", sc->subbus); 190 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 191 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 192 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 193 } 194 195 /* 196 * XXX If the secondary bus number is zero, we should assign a bus number 197 * since the BIOS hasn't, then initialise the bridge. 198 */ 199 200 /* 201 * XXX If the subordinate bus number is less than the secondary bus number, 202 * we should pick a better value. One sensible alternative would be to 203 * pick 255; the only tradeoff here is that configuration transactions 204 * would be more widely routed than absolutely necessary. 205 */ 206 } 207 208 int 209 pcib_attach(device_t dev) 210 { 211 struct pcib_softc *sc; 212 device_t child; 213 214 pcib_attach_common(dev); 215 sc = device_get_softc(dev); 216 if (sc->secbus != 0) { 217 child = device_add_child(dev, "pci", sc->secbus); 218 if (child != NULL) 219 return(bus_generic_attach(dev)); 220 } 221 222 /* no secondary bus; we should have fixed this */ 223 return(0); 224 } 225 226 int 227 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 228 { 229 struct pcib_softc *sc = device_get_softc(dev); 230 231 switch (which) { 232 case PCIB_IVAR_BUS: 233 *result = sc->secbus; 234 return(0); 235 } 236 return(ENOENT); 237 } 238 239 int 240 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 241 { 242 struct pcib_softc *sc = device_get_softc(dev); 243 244 switch (which) { 245 case PCIB_IVAR_BUS: 246 sc->secbus = value; 247 break; 248 } 249 return(ENOENT); 250 } 251 252 /* 253 * Is this a decoded ISA I/O port address? Note, we need to do the mask that 254 * we do below because of the ISA alias addresses. I'm not 100% sure that 255 * this is correct. 256 */ 257 static int 258 pcib_is_isa_io(u_long start) 259 { 260 if ((start & 0xfffUL) > 0x3ffUL || start == 0) 261 return (0); 262 return (1); 263 } 264 265 /* 266 * Is this a decoded ISA memory address? 267 */ 268 static int 269 pcib_is_isa_mem(u_long start) 270 { 271 if (start > 0xfffffUL || start == 0) 272 return (0); 273 return (1); 274 } 275 276 /* 277 * We have to trap resource allocation requests and ensure that the bridge 278 * is set up to, or capable of handling them. 279 */ 280 struct resource * 281 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 282 u_long start, u_long end, u_long count, u_int flags) 283 { 284 struct pcib_softc *sc = device_get_softc(dev); 285 286 /* 287 * If this is a "default" allocation against this rid, we can't work 288 * out where it's coming from (we should actually never see these) so we 289 * just have to punt. 290 */ 291 if ((start == 0) && (end == ~0)) { 292 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 293 *rid, device_get_name(child), device_get_unit(child)); 294 } else { 295 /* 296 * Fail the allocation for this range if it's not supported. 297 * 298 * XXX we should probably just fix up the bridge decode and soldier on. 299 */ 300 switch (type) { 301 case SYS_RES_IOPORT: 302 if (!pcib_is_isa_io(start)) { 303 if (!pci_allow_unsupported_io_range) { 304 if (start < sc->iobase) 305 start = sc->iobase; 306 if (end > sc->iolimit) 307 end = sc->iolimit; 308 if (end < start) 309 start = 0; 310 } else { 311 if (start < sc->iobase) 312 printf("start (%lx) < sc->iobase (%x)\n", start, 313 sc->iobase); 314 if (end > sc->iolimit) 315 printf("end (%lx) > sc->iolimit (%x)\n", 316 end, sc->iolimit); 317 if (end < start) 318 printf("end (%lx) < start (%lx)\n", end, start); 319 } 320 } 321 if (!pcib_is_isa_io(start) && 322 ((start < sc->iobase) || (end > sc->iolimit))) { 323 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 324 " (decoding 0x%x-0x%x)\n", 325 device_get_name(child), device_get_unit(child), start, end, 326 sc->iobase, sc->iolimit); 327 return (NULL); 328 } 329 if (bootverbose) 330 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 331 device_get_name(child), device_get_unit(child), start, end); 332 break; 333 334 /* 335 * XXX will have to decide whether the device making the request is asking 336 * for prefetchable memory or not. If it's coming from another bridge 337 * down the line, do we assume not, or ask the bridge to pass in another 338 * flag as the request bubbles up? 339 */ 340 case SYS_RES_MEMORY: 341 if (!pcib_is_isa_mem(start)) { 342 if (!pci_allow_unsupported_io_range) { 343 if (start < sc->membase && end >= sc->membase) 344 start = sc->membase; 345 if (end > sc->memlimit) 346 end = sc->memlimit; 347 if (end < start) 348 start = 0; 349 } else { 350 if (start < sc->membase && end > sc->membase) 351 printf("start (%lx) < sc->membase (%x)\n", 352 start, sc->membase); 353 if (end > sc->memlimit) 354 printf("end (%lx) > sc->memlimit (%x)\n", 355 end, sc->memlimit); 356 if (end < start) 357 printf("end (%lx) < start (%lx)\n", end, start); 358 } 359 } 360 if (!pcib_is_isa_mem(start) && 361 (((start < sc->membase) || (end > sc->memlimit)) && 362 ((start < sc->pmembase) || (end > sc->pmemlimit)))) { 363 if (bootverbose) 364 device_printf(dev, 365 "device %s%d requested unsupported memory range " 366 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 367 device_get_name(child), device_get_unit(child), start, 368 end, sc->membase, sc->memlimit, sc->pmembase, 369 sc->pmemlimit); 370 if (!pci_allow_unsupported_io_range) 371 return (NULL); 372 } 373 if (bootverbose) 374 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 375 device_get_name(child), device_get_unit(child), start, end); 376 break; 377 378 default: 379 break; 380 } 381 } 382 383 /* 384 * Bridge is OK decoding this resource, so pass it up. 385 */ 386 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 387 } 388 389 /* 390 * PCIB interface. 391 */ 392 int 393 pcib_maxslots(device_t dev) 394 { 395 return(PCI_SLOTMAX); 396 } 397 398 /* 399 * Since we are a child of a PCI bus, its parent must support the pcib interface. 400 */ 401 u_int32_t 402 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 403 { 404 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 405 } 406 407 void 408 pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 409 { 410 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 411 } 412 413 /* 414 * Route an interrupt across a PCI bridge. 415 */ 416 static int 417 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 418 { 419 device_t bus; 420 int parent_intpin; 421 int intnum; 422 423 /* 424 * 425 * The PCI standard defines a swizzle of the child-side device/intpin to 426 * the parent-side intpin as follows. 427 * 428 * device = device on child bus 429 * child_intpin = intpin on child bus slot (0-3) 430 * parent_intpin = intpin on parent bus slot (0-3) 431 * 432 * parent_intpin = (device + child_intpin) % 4 433 */ 434 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 435 436 /* 437 * Our parent is a PCI bus. Its parent must export the pcib interface 438 * which includes the ability to route interrupts. 439 */ 440 bus = device_get_parent(pcib); 441 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 442 if (PCI_INTERRUPT_VALID(intnum)) { 443 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 444 pci_get_slot(dev), 'A' + pin - 1, intnum); 445 } 446 return(intnum); 447 } 448 449 /* 450 * Try to read the bus number of a host-PCI bridge using appropriate config 451 * registers. 452 */ 453 int 454 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 455 u_int8_t *busnum) 456 { 457 u_int32_t id; 458 459 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 460 if (id == 0xffffffff) 461 return (0); 462 463 switch (id) { 464 case 0x12258086: 465 /* Intel 824?? */ 466 /* XXX This is a guess */ 467 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 468 *busnum = bus; 469 break; 470 case 0x84c48086: 471 /* Intel 82454KX/GX (Orion) */ 472 *busnum = read_config(bus, slot, func, 0x4a, 1); 473 break; 474 case 0x84ca8086: 475 /* 476 * For the 450nx chipset, there is a whole bundle of 477 * things pretending to be host bridges. The MIOC will 478 * be seen first and isn't really a pci bridge (the 479 * actual busses are attached to the PXB's). We need to 480 * read the registers of the MIOC to figure out the 481 * bus numbers for the PXB channels. 482 * 483 * Since the MIOC doesn't have a pci bus attached, we 484 * pretend it wasn't there. 485 */ 486 return (0); 487 case 0x84cb8086: 488 switch (slot) { 489 case 0x12: 490 /* Intel 82454NX PXB#0, Bus#A */ 491 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 492 break; 493 case 0x13: 494 /* Intel 82454NX PXB#0, Bus#B */ 495 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 496 break; 497 case 0x14: 498 /* Intel 82454NX PXB#1, Bus#A */ 499 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 500 break; 501 case 0x15: 502 /* Intel 82454NX PXB#1, Bus#B */ 503 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 504 break; 505 } 506 break; 507 508 /* ServerWorks -- vendor 0x1166 */ 509 case 0x00051166: 510 case 0x00061166: 511 case 0x00081166: 512 case 0x00091166: 513 case 0x00101166: 514 case 0x00111166: 515 case 0x00171166: 516 case 0x01011166: 517 case 0x010f1014: 518 case 0x02011166: 519 case 0x03021014: 520 *busnum = read_config(bus, slot, func, 0x44, 1); 521 break; 522 default: 523 /* Don't know how to read bus number. */ 524 return 0; 525 } 526 527 return 1; 528 } 529