1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 42 #include <machine/resource.h> 43 44 #include <pci/pcivar.h> 45 #include <pci/pcireg.h> 46 47 #include "pcib_if.h" 48 49 /* 50 * Bridge-specific data. 51 */ 52 struct pcib_softc 53 { 54 device_t dev; 55 u_int16_t command; /* command register */ 56 u_int8_t secbus; /* secondary bus number */ 57 u_int8_t subbus; /* subordinate bus number */ 58 pci_addr_t pmembase; /* base address of prefetchable memory */ 59 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 60 pci_addr_t membase; /* base address of memory window */ 61 pci_addr_t memlimit; /* topmost address of memory window */ 62 u_int32_t iobase; /* base address of port window */ 63 u_int32_t iolimit; /* topmost address of port window */ 64 u_int16_t secstat; /* secondary bus status register */ 65 u_int16_t bridgectl; /* bridge control register */ 66 u_int8_t seclat; /* secondary bus latency timer */ 67 }; 68 69 static int pcib_probe(device_t dev); 70 static int pcib_attach(device_t dev); 71 static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 72 static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 73 static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 74 u_long start, u_long end, u_long count, u_int flags); 75 static int pcib_maxslots(device_t dev); 76 static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); 77 static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); 78 static int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 79 80 static device_method_t pcib_methods[] = { 81 /* Device interface */ 82 DEVMETHOD(device_probe, pcib_probe), 83 DEVMETHOD(device_attach, pcib_attach), 84 DEVMETHOD(device_shutdown, bus_generic_shutdown), 85 DEVMETHOD(device_suspend, bus_generic_suspend), 86 DEVMETHOD(device_resume, bus_generic_resume), 87 88 /* Bus interface */ 89 DEVMETHOD(bus_print_child, bus_generic_print_child), 90 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 91 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 92 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 93 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 94 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 95 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 96 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 97 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 98 99 /* pcib interface */ 100 DEVMETHOD(pcib_maxslots, pcib_maxslots), 101 DEVMETHOD(pcib_read_config, pcib_read_config), 102 DEVMETHOD(pcib_write_config, pcib_write_config), 103 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 104 105 { 0, 0 } 106 }; 107 108 static driver_t pcib_driver = { 109 "pcib", 110 pcib_methods, 111 sizeof(struct pcib_softc), 112 }; 113 114 static devclass_t pcib_devclass; 115 116 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 117 118 /* 119 * Generic device interface 120 */ 121 static int 122 pcib_probe(device_t dev) 123 { 124 if ((pci_get_class(dev) == PCIC_BRIDGE) && 125 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 126 device_set_desc(dev, "PCI-PCI bridge"); 127 return(-10000); 128 } 129 return(ENXIO); 130 } 131 132 static int 133 pcib_attach(device_t dev) 134 { 135 struct pcib_softc *sc; 136 device_t child; 137 u_int8_t iolow; 138 139 sc = device_get_softc(dev); 140 sc->dev = dev; 141 142 /* 143 * Get current bridge configuration. 144 */ 145 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 146 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 147 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 148 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 149 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 150 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 151 152 /* 153 * Determine current I/O decode. 154 */ 155 if (sc->command & PCIM_CMD_PORTEN) { 156 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 157 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 158 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 159 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 160 } else { 161 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 162 } 163 164 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 165 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 166 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 167 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 168 } else { 169 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 170 } 171 } 172 173 /* 174 * Determine current memory decode. 175 */ 176 if (sc->command & PCIM_CMD_MEMEN) { 177 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 178 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 179 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 180 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 181 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 182 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 183 } 184 185 /* 186 * Quirk handling. 187 */ 188 switch (pci_get_devid(dev)) { 189 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 190 { 191 u_int8_t supbus; 192 193 supbus = pci_read_config(dev, 0x41, 1); 194 if (supbus != 0xff) { 195 sc->secbus = supbus + 1; 196 sc->subbus = supbus + 1; 197 } 198 } 199 break; 200 } 201 202 if (bootverbose) { 203 device_printf(dev, " secondary bus %d\n", sc->secbus); 204 device_printf(dev, " subordinate bus %d\n", sc->subbus); 205 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 206 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 207 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 208 } 209 210 /* 211 * XXX If the secondary bus number is zero, we should assign a bus number 212 * since the BIOS hasn't, then initialise the bridge. 213 */ 214 215 /* 216 * XXX If the subordinate bus number is less than the secondary bus number, 217 * we should pick a better value. One sensible alternative would be to 218 * pick 255; the only tradeoff here is that configuration transactions 219 * would be more widely routed than absolutely necessary. 220 */ 221 222 if (sc->secbus != 0) { 223 child = device_add_child(dev, "pci", -1); 224 if (child != NULL) 225 return(bus_generic_attach(dev)); 226 } 227 228 /* no secondary bus; we should have fixed this */ 229 return(0); 230 } 231 232 static int 233 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 234 { 235 struct pcib_softc *sc = device_get_softc(dev); 236 237 switch (which) { 238 case PCIB_IVAR_BUS: 239 *result = sc->secbus; 240 return(0); 241 } 242 return(ENOENT); 243 } 244 245 static int 246 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 247 { 248 struct pcib_softc *sc = device_get_softc(dev); 249 250 switch (which) { 251 case PCIB_IVAR_BUS: 252 sc->secbus = value; 253 break; 254 } 255 return(ENOENT); 256 } 257 258 /* 259 * We have to trap resource allocation requests and ensure that the bridge 260 * is set up to, or capable of handling them. 261 */ 262 static struct resource * 263 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 264 u_long start, u_long end, u_long count, u_int flags) 265 { 266 struct pcib_softc *sc = device_get_softc(dev); 267 268 /* 269 * If this is a "default" allocation against this rid, we can't work 270 * out where it's coming from (we should actually never see these) so we 271 * just have to punt. 272 */ 273 if ((start == 0) && (end == ~0)) { 274 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 275 *rid, device_get_name(child), device_get_unit(child)); 276 } else { 277 /* 278 * Fail the allocation for this range if it's not supported. 279 * 280 * XXX we should probably just fix up the bridge decode and soldier on. 281 */ 282 switch (type) { 283 case SYS_RES_IOPORT: 284 if ((start < sc->iobase) || (end > sc->iolimit)) { 285 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 286 " (decoding 0x%x-0x%x)\n", 287 device_get_name(child), device_get_unit(child), start, end, 288 sc->iobase, sc->iolimit); 289 return(NULL); 290 } 291 if (bootverbose) 292 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 293 device_get_name(child), device_get_unit(child), start, end); 294 break; 295 296 /* 297 * XXX will have to decide whether the device making the request is asking 298 * for prefetchable memory or not. If it's coming from another bridge 299 * down the line, do we assume not, or ask the bridge to pass in another 300 * flag as the request bubbles up? 301 */ 302 case SYS_RES_MEMORY: 303 if (((start < sc->membase) || (end > sc->memlimit)) && 304 ((start < sc->pmembase) || (end > sc->pmemlimit))) { 305 device_printf(dev, "device %s%d requested unsupported memory range 0x%lx-0x%lx" 306 " (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 307 device_get_name(child), device_get_unit(child), start, end, 308 sc->membase, sc->memlimit, sc->pmembase, sc->pmemlimit); 309 return(NULL); 310 } 311 if (bootverbose) 312 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 313 device_get_name(child), device_get_unit(child), start, end); 314 break; 315 316 default: 317 break; 318 } 319 } 320 321 /* 322 * Bridge is OK decoding this resource, so pass it up. 323 */ 324 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 325 } 326 327 /* 328 * PCIB interface. 329 */ 330 static int 331 pcib_maxslots(device_t dev) 332 { 333 return(PCI_SLOTMAX); 334 } 335 336 /* 337 * Since we are a child of a PCI bus, its parent must support the pcib interface. 338 */ 339 static u_int32_t 340 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 341 { 342 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 343 } 344 345 static void 346 pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 347 { 348 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 349 } 350 351 /* 352 * Route an interrupt across a PCI bridge. 353 */ 354 static int 355 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 356 { 357 device_t bus; 358 int parent_intpin; 359 int intnum; 360 361 /* 362 * 363 * The PCI standard defines a swizzle of the child-side device/intpin to 364 * the parent-side intpin as follows. 365 * 366 * device = device on child bus 367 * child_intpin = intpin on child bus slot (0-3) 368 * parent_intpin = intpin on parent bus slot (0-3) 369 * 370 * parent_intpin = (device + child_intpin) % 4 371 */ 372 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 373 374 /* 375 * Our parent is a PCI bus. Its parent must export the pcib interface 376 * which includes the ability to route interrupts. 377 */ 378 bus = device_get_parent(pcib); 379 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 380 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev), 381 'A' + pin - 1, intnum); 382 return(intnum); 383 } 384