xref: /freebsd/sys/dev/pci/pci_pci.c (revision 20bd59416dcacbd2b776fe49dfa193900f303287)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5  * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6  * Copyright (c) 2000 BSDi
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. The name of the author may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * PCI:PCI bridge support.
38  */
39 
40 #include "opt_pci.h"
41 
42 #include <sys/param.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
49 #include <sys/pciio.h>
50 #include <sys/rman.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pci_private.h>
58 #include <dev/pci/pcib_private.h>
59 
60 #include "pcib_if.h"
61 
62 static int		pcib_probe(device_t dev);
63 static int		pcib_suspend(device_t dev);
64 static int		pcib_resume(device_t dev);
65 static int		pcib_power_for_sleep(device_t pcib, device_t dev,
66 			    int *pstate);
67 static int		pcib_ari_get_id(device_t pcib, device_t dev,
68     enum pci_id_type type, uintptr_t *id);
69 static uint32_t		pcib_read_config(device_t dev, u_int b, u_int s,
70     u_int f, u_int reg, int width);
71 static void		pcib_write_config(device_t dev, u_int b, u_int s,
72     u_int f, u_int reg, uint32_t val, int width);
73 static int		pcib_ari_maxslots(device_t dev);
74 static int		pcib_ari_maxfuncs(device_t dev);
75 static int		pcib_try_enable_ari(device_t pcib, device_t dev);
76 static int		pcib_ari_enabled(device_t pcib);
77 static void		pcib_ari_decode_rid(device_t pcib, uint16_t rid,
78 			    int *bus, int *slot, int *func);
79 #ifdef PCI_HP
80 static void		pcib_pcie_ab_timeout(void *arg);
81 static void		pcib_pcie_cc_timeout(void *arg);
82 static void		pcib_pcie_dll_timeout(void *arg);
83 #endif
84 static int		pcib_request_feature_default(device_t pcib, device_t dev,
85 			    enum pci_feature feature);
86 static int		pcib_reset_child(device_t dev, device_t child, int flags);
87 
88 static device_method_t pcib_methods[] = {
89     /* Device interface */
90     DEVMETHOD(device_probe,		pcib_probe),
91     DEVMETHOD(device_attach,		pcib_attach),
92     DEVMETHOD(device_detach,		pcib_detach),
93     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
94     DEVMETHOD(device_suspend,		pcib_suspend),
95     DEVMETHOD(device_resume,		pcib_resume),
96 
97     /* Bus interface */
98     DEVMETHOD(bus_child_present,	pcib_child_present),
99     DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
100     DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
101     DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
102 #ifdef NEW_PCIB
103     DEVMETHOD(bus_adjust_resource,	pcib_adjust_resource),
104     DEVMETHOD(bus_release_resource,	pcib_release_resource),
105 #else
106     DEVMETHOD(bus_adjust_resource,	bus_generic_adjust_resource),
107     DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
108 #endif
109     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
110     DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
111     DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
112     DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
113     DEVMETHOD(bus_reset_child,		pcib_reset_child),
114 
115     /* pcib interface */
116     DEVMETHOD(pcib_maxslots,		pcib_ari_maxslots),
117     DEVMETHOD(pcib_maxfuncs,		pcib_ari_maxfuncs),
118     DEVMETHOD(pcib_read_config,		pcib_read_config),
119     DEVMETHOD(pcib_write_config,	pcib_write_config),
120     DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
121     DEVMETHOD(pcib_alloc_msi,		pcib_alloc_msi),
122     DEVMETHOD(pcib_release_msi,		pcib_release_msi),
123     DEVMETHOD(pcib_alloc_msix,		pcib_alloc_msix),
124     DEVMETHOD(pcib_release_msix,	pcib_release_msix),
125     DEVMETHOD(pcib_map_msi,		pcib_map_msi),
126     DEVMETHOD(pcib_power_for_sleep,	pcib_power_for_sleep),
127     DEVMETHOD(pcib_get_id,		pcib_ari_get_id),
128     DEVMETHOD(pcib_try_enable_ari,	pcib_try_enable_ari),
129     DEVMETHOD(pcib_ari_enabled,		pcib_ari_enabled),
130     DEVMETHOD(pcib_decode_rid,		pcib_ari_decode_rid),
131     DEVMETHOD(pcib_request_feature,	pcib_request_feature_default),
132 
133     DEVMETHOD_END
134 };
135 
136 static devclass_t pcib_devclass;
137 
138 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
139 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL,
140     BUS_PASS_BUS);
141 
142 #if defined(NEW_PCIB) || defined(PCI_HP)
143 SYSCTL_DECL(_hw_pci);
144 #endif
145 
146 #ifdef NEW_PCIB
147 static int pci_clear_pcib;
148 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
149     "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
150 
151 /*
152  * Is a resource from a child device sub-allocated from one of our
153  * resource managers?
154  */
155 static int
156 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
157 {
158 
159 	switch (type) {
160 #ifdef PCI_RES_BUS
161 	case PCI_RES_BUS:
162 		return (rman_is_region_manager(r, &sc->bus.rman));
163 #endif
164 	case SYS_RES_IOPORT:
165 		return (rman_is_region_manager(r, &sc->io.rman));
166 	case SYS_RES_MEMORY:
167 		/* Prefetchable resources may live in either memory rman. */
168 		if (rman_get_flags(r) & RF_PREFETCHABLE &&
169 		    rman_is_region_manager(r, &sc->pmem.rman))
170 			return (1);
171 		return (rman_is_region_manager(r, &sc->mem.rman));
172 	}
173 	return (0);
174 }
175 
176 static int
177 pcib_is_window_open(struct pcib_window *pw)
178 {
179 
180 	return (pw->valid && pw->base < pw->limit);
181 }
182 
183 /*
184  * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
185  * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
186  * when allocating the resource windows and rely on the PCI bus driver
187  * to do this for us.
188  */
189 static void
190 pcib_activate_window(struct pcib_softc *sc, int type)
191 {
192 
193 	PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
194 }
195 
196 static void
197 pcib_write_windows(struct pcib_softc *sc, int mask)
198 {
199 	device_t dev;
200 	uint32_t val;
201 
202 	dev = sc->dev;
203 	if (sc->io.valid && mask & WIN_IO) {
204 		val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
205 		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
206 			pci_write_config(dev, PCIR_IOBASEH_1,
207 			    sc->io.base >> 16, 2);
208 			pci_write_config(dev, PCIR_IOLIMITH_1,
209 			    sc->io.limit >> 16, 2);
210 		}
211 		pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
212 		pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
213 	}
214 
215 	if (mask & WIN_MEM) {
216 		pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
217 		pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
218 	}
219 
220 	if (sc->pmem.valid && mask & WIN_PMEM) {
221 		val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
222 		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
223 			pci_write_config(dev, PCIR_PMBASEH_1,
224 			    sc->pmem.base >> 32, 4);
225 			pci_write_config(dev, PCIR_PMLIMITH_1,
226 			    sc->pmem.limit >> 32, 4);
227 		}
228 		pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
229 		pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
230 	}
231 }
232 
233 /*
234  * This is used to reject I/O port allocations that conflict with an
235  * ISA alias range.
236  */
237 static int
238 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
239     rman_res_t count)
240 {
241 	rman_res_t next_alias;
242 
243 	if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
244 		return (0);
245 
246 	/* Only check fixed ranges for overlap. */
247 	if (start + count - 1 != end)
248 		return (0);
249 
250 	/* ISA aliases are only in the lower 64KB of I/O space. */
251 	if (start >= 65536)
252 		return (0);
253 
254 	/* Check for overlap with 0x000 - 0x0ff as a special case. */
255 	if (start < 0x100)
256 		goto alias;
257 
258 	/*
259 	 * If the start address is an alias, the range is an alias.
260 	 * Otherwise, compute the start of the next alias range and
261 	 * check if it is before the end of the candidate range.
262 	 */
263 	if ((start & 0x300) != 0)
264 		goto alias;
265 	next_alias = (start & ~0x3fful) | 0x100;
266 	if (next_alias <= end)
267 		goto alias;
268 	return (0);
269 
270 alias:
271 	if (bootverbose)
272 		device_printf(sc->dev,
273 		    "I/O range %#jx-%#jx overlaps with an ISA alias\n", start,
274 		    end);
275 	return (1);
276 }
277 
278 static void
279 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
280     int count)
281 {
282 	struct resource **newarray;
283 	int error, i;
284 
285 	newarray = malloc(sizeof(struct resource *) * (w->count + count),
286 	    M_DEVBUF, M_WAITOK);
287 	if (w->res != NULL)
288 		bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
289 	bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
290 	free(w->res, M_DEVBUF);
291 	w->res = newarray;
292 	w->count += count;
293 
294 	for (i = 0; i < count; i++) {
295 		error = rman_manage_region(&w->rman, rman_get_start(res[i]),
296 		    rman_get_end(res[i]));
297 		if (error)
298 			panic("Failed to add resource to rman");
299 	}
300 }
301 
302 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
303 
304 static void
305 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
306     void *arg)
307 {
308 	rman_res_t next_end;
309 
310 	/*
311 	 * If start is within an ISA alias range, move up to the start
312 	 * of the next non-alias range.  As a special case, addresses
313 	 * in the range 0x000 - 0x0ff should also be skipped since
314 	 * those are used for various system I/O devices in ISA
315 	 * systems.
316 	 */
317 	if (start <= 65535) {
318 		if (start < 0x100 || (start & 0x300) != 0) {
319 			start &= ~0x3ff;
320 			start += 0x400;
321 		}
322 	}
323 
324 	/* ISA aliases are only in the lower 64KB of I/O space. */
325 	while (start <= MIN(end, 65535)) {
326 		next_end = MIN(start | 0xff, end);
327 		cb(start, next_end, arg);
328 		start += 0x400;
329 	}
330 
331 	if (start <= end)
332 		cb(start, end, arg);
333 }
334 
335 static void
336 count_ranges(rman_res_t start, rman_res_t end, void *arg)
337 {
338 	int *countp;
339 
340 	countp = arg;
341 	(*countp)++;
342 }
343 
344 struct alloc_state {
345 	struct resource **res;
346 	struct pcib_softc *sc;
347 	int count, error;
348 };
349 
350 static void
351 alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
352 {
353 	struct alloc_state *as;
354 	struct pcib_window *w;
355 	int rid;
356 
357 	as = arg;
358 	if (as->error != 0)
359 		return;
360 
361 	w = &as->sc->io;
362 	rid = w->reg;
363 	if (bootverbose)
364 		device_printf(as->sc->dev,
365 		    "allocating non-ISA range %#jx-%#jx\n", start, end);
366 	as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
367 	    &rid, start, end, end - start + 1, 0);
368 	if (as->res[as->count] == NULL)
369 		as->error = ENXIO;
370 	else
371 		as->count++;
372 }
373 
374 static int
375 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
376 {
377 	struct alloc_state as;
378 	int i, new_count;
379 
380 	/* First, see how many ranges we need. */
381 	new_count = 0;
382 	pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
383 
384 	/* Second, allocate the ranges. */
385 	as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
386 	    M_WAITOK);
387 	as.sc = sc;
388 	as.count = 0;
389 	as.error = 0;
390 	pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
391 	if (as.error != 0) {
392 		for (i = 0; i < as.count; i++)
393 			bus_release_resource(sc->dev, SYS_RES_IOPORT,
394 			    sc->io.reg, as.res[i]);
395 		free(as.res, M_DEVBUF);
396 		return (as.error);
397 	}
398 	KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
399 
400 	/* Third, add the ranges to the window. */
401 	pcib_add_window_resources(&sc->io, as.res, as.count);
402 	free(as.res, M_DEVBUF);
403 	return (0);
404 }
405 
406 static void
407 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
408     int flags, pci_addr_t max_address)
409 {
410 	struct resource *res;
411 	char buf[64];
412 	int error, rid;
413 
414 	if (max_address != (rman_res_t)max_address)
415 		max_address = ~0;
416 	w->rman.rm_start = 0;
417 	w->rman.rm_end = max_address;
418 	w->rman.rm_type = RMAN_ARRAY;
419 	snprintf(buf, sizeof(buf), "%s %s window",
420 	    device_get_nameunit(sc->dev), w->name);
421 	w->rman.rm_descr = strdup(buf, M_DEVBUF);
422 	error = rman_init(&w->rman);
423 	if (error)
424 		panic("Failed to initialize %s %s rman",
425 		    device_get_nameunit(sc->dev), w->name);
426 
427 	if (!pcib_is_window_open(w))
428 		return;
429 
430 	if (w->base > max_address || w->limit > max_address) {
431 		device_printf(sc->dev,
432 		    "initial %s window has too many bits, ignoring\n", w->name);
433 		return;
434 	}
435 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
436 		(void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
437 	else {
438 		rid = w->reg;
439 		res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
440 		    w->limit - w->base + 1, flags);
441 		if (res != NULL)
442 			pcib_add_window_resources(w, &res, 1);
443 	}
444 	if (w->res == NULL) {
445 		device_printf(sc->dev,
446 		    "failed to allocate initial %s window: %#jx-%#jx\n",
447 		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
448 		w->base = max_address;
449 		w->limit = 0;
450 		pcib_write_windows(sc, w->mask);
451 		return;
452 	}
453 	pcib_activate_window(sc, type);
454 }
455 
456 /*
457  * Initialize I/O windows.
458  */
459 static void
460 pcib_probe_windows(struct pcib_softc *sc)
461 {
462 	pci_addr_t max;
463 	device_t dev;
464 	uint32_t val;
465 
466 	dev = sc->dev;
467 
468 	if (pci_clear_pcib) {
469 		pcib_bridge_init(dev);
470 	}
471 
472 	/* Determine if the I/O port window is implemented. */
473 	val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
474 	if (val == 0) {
475 		/*
476 		 * If 'val' is zero, then only 16-bits of I/O space
477 		 * are supported.
478 		 */
479 		pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
480 		if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
481 			sc->io.valid = 1;
482 			pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
483 		}
484 	} else
485 		sc->io.valid = 1;
486 
487 	/* Read the existing I/O port window. */
488 	if (sc->io.valid) {
489 		sc->io.reg = PCIR_IOBASEL_1;
490 		sc->io.step = 12;
491 		sc->io.mask = WIN_IO;
492 		sc->io.name = "I/O port";
493 		if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
494 			sc->io.base = PCI_PPBIOBASE(
495 			    pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
496 			sc->io.limit = PCI_PPBIOLIMIT(
497 			    pci_read_config(dev, PCIR_IOLIMITH_1, 2),
498 			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
499 			max = 0xffffffff;
500 		} else {
501 			sc->io.base = PCI_PPBIOBASE(0, val);
502 			sc->io.limit = PCI_PPBIOLIMIT(0,
503 			    pci_read_config(dev, PCIR_IOLIMITL_1, 1));
504 			max = 0xffff;
505 		}
506 		pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
507 	}
508 
509 	/* Read the existing memory window. */
510 	sc->mem.valid = 1;
511 	sc->mem.reg = PCIR_MEMBASE_1;
512 	sc->mem.step = 20;
513 	sc->mem.mask = WIN_MEM;
514 	sc->mem.name = "memory";
515 	sc->mem.base = PCI_PPBMEMBASE(0,
516 	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
517 	sc->mem.limit = PCI_PPBMEMLIMIT(0,
518 	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
519 	pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
520 
521 	/* Determine if the prefetchable memory window is implemented. */
522 	val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
523 	if (val == 0) {
524 		/*
525 		 * If 'val' is zero, then only 32-bits of memory space
526 		 * are supported.
527 		 */
528 		pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
529 		if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
530 			sc->pmem.valid = 1;
531 			pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
532 		}
533 	} else
534 		sc->pmem.valid = 1;
535 
536 	/* Read the existing prefetchable memory window. */
537 	if (sc->pmem.valid) {
538 		sc->pmem.reg = PCIR_PMBASEL_1;
539 		sc->pmem.step = 20;
540 		sc->pmem.mask = WIN_PMEM;
541 		sc->pmem.name = "prefetch";
542 		if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
543 			sc->pmem.base = PCI_PPBMEMBASE(
544 			    pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
545 			sc->pmem.limit = PCI_PPBMEMLIMIT(
546 			    pci_read_config(dev, PCIR_PMLIMITH_1, 4),
547 			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
548 			max = 0xffffffffffffffff;
549 		} else {
550 			sc->pmem.base = PCI_PPBMEMBASE(0, val);
551 			sc->pmem.limit = PCI_PPBMEMLIMIT(0,
552 			    pci_read_config(dev, PCIR_PMLIMITL_1, 2));
553 			max = 0xffffffff;
554 		}
555 		pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
556 		    RF_PREFETCHABLE, max);
557 	}
558 }
559 
560 static void
561 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type)
562 {
563 	device_t dev;
564 	int error, i;
565 
566 	if (!w->valid)
567 		return;
568 
569 	dev = sc->dev;
570 	error = rman_fini(&w->rman);
571 	if (error) {
572 		device_printf(dev, "failed to release %s rman\n", w->name);
573 		return;
574 	}
575 	free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF);
576 
577 	for (i = 0; i < w->count; i++) {
578 		error = bus_free_resource(dev, type, w->res[i]);
579 		if (error)
580 			device_printf(dev,
581 			    "failed to release %s resource: %d\n", w->name,
582 			    error);
583 	}
584 	free(w->res, M_DEVBUF);
585 }
586 
587 static void
588 pcib_free_windows(struct pcib_softc *sc)
589 {
590 
591 	pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY);
592 	pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY);
593 	pcib_release_window(sc, &sc->io, SYS_RES_IOPORT);
594 }
595 
596 #ifdef PCI_RES_BUS
597 /*
598  * Allocate a suitable secondary bus for this bridge if needed and
599  * initialize the resource manager for the secondary bus range.  Note
600  * that the minimum count is a desired value and this may allocate a
601  * smaller range.
602  */
603 void
604 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
605 {
606 	char buf[64];
607 	int error, rid, sec_reg;
608 
609 	switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
610 	case PCIM_HDRTYPE_BRIDGE:
611 		sec_reg = PCIR_SECBUS_1;
612 		bus->sub_reg = PCIR_SUBBUS_1;
613 		break;
614 	case PCIM_HDRTYPE_CARDBUS:
615 		sec_reg = PCIR_SECBUS_2;
616 		bus->sub_reg = PCIR_SUBBUS_2;
617 		break;
618 	default:
619 		panic("not a PCI bridge");
620 	}
621 	bus->sec = pci_read_config(dev, sec_reg, 1);
622 	bus->sub = pci_read_config(dev, bus->sub_reg, 1);
623 	bus->dev = dev;
624 	bus->rman.rm_start = 0;
625 	bus->rman.rm_end = PCI_BUSMAX;
626 	bus->rman.rm_type = RMAN_ARRAY;
627 	snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
628 	bus->rman.rm_descr = strdup(buf, M_DEVBUF);
629 	error = rman_init(&bus->rman);
630 	if (error)
631 		panic("Failed to initialize %s bus number rman",
632 		    device_get_nameunit(dev));
633 
634 	/*
635 	 * Allocate a bus range.  This will return an existing bus range
636 	 * if one exists, or a new bus range if one does not.
637 	 */
638 	rid = 0;
639 	bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
640 	    min_count, 0);
641 	if (bus->res == NULL) {
642 		/*
643 		 * Fall back to just allocating a range of a single bus
644 		 * number.
645 		 */
646 		bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid,
647 		    1, 0);
648 	} else if (rman_get_size(bus->res) < min_count)
649 		/*
650 		 * Attempt to grow the existing range to satisfy the
651 		 * minimum desired count.
652 		 */
653 		(void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
654 		    rman_get_start(bus->res), rman_get_start(bus->res) +
655 		    min_count - 1);
656 
657 	/*
658 	 * Add the initial resource to the rman.
659 	 */
660 	if (bus->res != NULL) {
661 		error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
662 		    rman_get_end(bus->res));
663 		if (error)
664 			panic("Failed to add resource to rman");
665 		bus->sec = rman_get_start(bus->res);
666 		bus->sub = rman_get_end(bus->res);
667 	}
668 }
669 
670 void
671 pcib_free_secbus(device_t dev, struct pcib_secbus *bus)
672 {
673 	int error;
674 
675 	error = rman_fini(&bus->rman);
676 	if (error) {
677 		device_printf(dev, "failed to release bus number rman\n");
678 		return;
679 	}
680 	free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF);
681 
682 	error = bus_free_resource(dev, PCI_RES_BUS, bus->res);
683 	if (error)
684 		device_printf(dev,
685 		    "failed to release bus numbers resource: %d\n", error);
686 }
687 
688 static struct resource *
689 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
690     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
691 {
692 	struct resource *res;
693 
694 	res = rman_reserve_resource(&bus->rman, start, end, count, flags,
695 	    child);
696 	if (res == NULL)
697 		return (NULL);
698 
699 	if (bootverbose)
700 		device_printf(bus->dev,
701 		    "allocated bus range (%ju-%ju) for rid %d of %s\n",
702 		    rman_get_start(res), rman_get_end(res), *rid,
703 		    pcib_child_name(child));
704 	rman_set_rid(res, *rid);
705 	return (res);
706 }
707 
708 /*
709  * Attempt to grow the secondary bus range.  This is much simpler than
710  * for I/O windows as the range can only be grown by increasing
711  * subbus.
712  */
713 static int
714 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
715 {
716 	rman_res_t old_end;
717 	int error;
718 
719 	old_end = rman_get_end(bus->res);
720 	KASSERT(new_end > old_end, ("attempt to shrink subbus"));
721 	error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
722 	    rman_get_start(bus->res), new_end);
723 	if (error)
724 		return (error);
725 	if (bootverbose)
726 		device_printf(bus->dev, "grew bus range to %ju-%ju\n",
727 		    rman_get_start(bus->res), rman_get_end(bus->res));
728 	error = rman_manage_region(&bus->rman, old_end + 1,
729 	    rman_get_end(bus->res));
730 	if (error)
731 		panic("Failed to add resource to rman");
732 	bus->sub = rman_get_end(bus->res);
733 	pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
734 	return (0);
735 }
736 
737 struct resource *
738 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
739     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
740 {
741 	struct resource *res;
742 	rman_res_t start_free, end_free, new_end;
743 
744 	/*
745 	 * First, see if the request can be satisified by the existing
746 	 * bus range.
747 	 */
748 	res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
749 	if (res != NULL)
750 		return (res);
751 
752 	/*
753 	 * Figure out a range to grow the bus range.  First, find the
754 	 * first bus number after the last allocated bus in the rman and
755 	 * enforce that as a minimum starting point for the range.
756 	 */
757 	if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
758 	    end_free != bus->sub)
759 		start_free = bus->sub + 1;
760 	if (start_free < start)
761 		start_free = start;
762 	new_end = start_free + count - 1;
763 
764 	/*
765 	 * See if this new range would satisfy the request if it
766 	 * succeeds.
767 	 */
768 	if (new_end > end)
769 		return (NULL);
770 
771 	/* Finally, attempt to grow the existing resource. */
772 	if (bootverbose) {
773 		device_printf(bus->dev,
774 		    "attempting to grow bus range for %ju buses\n", count);
775 		printf("\tback candidate range: %ju-%ju\n", start_free,
776 		    new_end);
777 	}
778 	if (pcib_grow_subbus(bus, new_end) == 0)
779 		return (pcib_suballoc_bus(bus, child, rid, start, end, count,
780 		    flags));
781 	return (NULL);
782 }
783 #endif
784 
785 #else
786 
787 /*
788  * Is the prefetch window open (eg, can we allocate memory in it?)
789  */
790 static int
791 pcib_is_prefetch_open(struct pcib_softc *sc)
792 {
793 	return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
794 }
795 
796 /*
797  * Is the nonprefetch window open (eg, can we allocate memory in it?)
798  */
799 static int
800 pcib_is_nonprefetch_open(struct pcib_softc *sc)
801 {
802 	return (sc->membase > 0 && sc->membase < sc->memlimit);
803 }
804 
805 /*
806  * Is the io window open (eg, can we allocate ports in it?)
807  */
808 static int
809 pcib_is_io_open(struct pcib_softc *sc)
810 {
811 	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
812 }
813 
814 /*
815  * Get current I/O decode.
816  */
817 static void
818 pcib_get_io_decode(struct pcib_softc *sc)
819 {
820 	device_t	dev;
821 	uint32_t	iolow;
822 
823 	dev = sc->dev;
824 
825 	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
826 	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
827 		sc->iobase = PCI_PPBIOBASE(
828 		    pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
829 	else
830 		sc->iobase = PCI_PPBIOBASE(0, iolow);
831 
832 	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
833 	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
834 		sc->iolimit = PCI_PPBIOLIMIT(
835 		    pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
836 	else
837 		sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
838 }
839 
840 /*
841  * Get current memory decode.
842  */
843 static void
844 pcib_get_mem_decode(struct pcib_softc *sc)
845 {
846 	device_t	dev;
847 	pci_addr_t	pmemlow;
848 
849 	dev = sc->dev;
850 
851 	sc->membase = PCI_PPBMEMBASE(0,
852 	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
853 	sc->memlimit = PCI_PPBMEMLIMIT(0,
854 	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
855 
856 	pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
857 	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
858 		sc->pmembase = PCI_PPBMEMBASE(
859 		    pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
860 	else
861 		sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
862 
863 	pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
864 	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
865 		sc->pmemlimit = PCI_PPBMEMLIMIT(
866 		    pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
867 	else
868 		sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
869 }
870 
871 /*
872  * Restore previous I/O decode.
873  */
874 static void
875 pcib_set_io_decode(struct pcib_softc *sc)
876 {
877 	device_t	dev;
878 	uint32_t	iohi;
879 
880 	dev = sc->dev;
881 
882 	iohi = sc->iobase >> 16;
883 	if (iohi > 0)
884 		pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
885 	pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
886 
887 	iohi = sc->iolimit >> 16;
888 	if (iohi > 0)
889 		pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
890 	pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
891 }
892 
893 /*
894  * Restore previous memory decode.
895  */
896 static void
897 pcib_set_mem_decode(struct pcib_softc *sc)
898 {
899 	device_t	dev;
900 	pci_addr_t	pmemhi;
901 
902 	dev = sc->dev;
903 
904 	pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
905 	pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
906 
907 	pmemhi = sc->pmembase >> 32;
908 	if (pmemhi > 0)
909 		pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
910 	pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
911 
912 	pmemhi = sc->pmemlimit >> 32;
913 	if (pmemhi > 0)
914 		pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
915 	pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
916 }
917 #endif
918 
919 #ifdef PCI_HP
920 /*
921  * PCI-express HotPlug support.
922  */
923 static int pci_enable_pcie_hp = 1;
924 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN,
925     &pci_enable_pcie_hp, 0,
926     "Enable support for native PCI-express HotPlug.");
927 
928 static void
929 pcib_probe_hotplug(struct pcib_softc *sc)
930 {
931 	device_t dev;
932 	uint32_t link_cap;
933 	uint16_t link_sta, slot_sta;
934 
935 	if (!pci_enable_pcie_hp)
936 		return;
937 
938 	dev = sc->dev;
939 	if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0)
940 		return;
941 
942 	if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT))
943 		return;
944 
945 	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
946 
947 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
948 		return;
949 	link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
950 	if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0)
951 		return;
952 
953 	/*
954 	 * Some devices report that they have an MRL when they actually
955 	 * do not.  Since they always report that the MRL is open, child
956 	 * devices would be ignored.  Try to detect these devices and
957 	 * ignore their claim of HotPlug support.
958 	 *
959 	 * If there is an open MRL but the Data Link Layer is active,
960 	 * the MRL is not real.
961 	 */
962 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) {
963 		link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
964 		slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
965 		if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 &&
966 		    (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) {
967 			return;
968 		}
969 	}
970 
971 	/*
972 	 * Now that we're sure we want to do hot plug, ask the
973 	 * firmware, if any, if that's OK.
974 	 */
975 	if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) {
976 		if (bootverbose)
977 			device_printf(dev, "Unable to activate hot plug feature.\n");
978 		return;
979 	}
980 
981 	sc->flags |= PCIB_HOTPLUG;
982 }
983 
984 /*
985  * Send a HotPlug command to the slot control register.  If this slot
986  * uses command completion interrupts and a previous command is still
987  * in progress, then the command is dropped.  Once the previous
988  * command completes or times out, pcib_pcie_hotplug_update() will be
989  * invoked to post a new command based on the slot's state at that
990  * time.
991  */
992 static void
993 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
994 {
995 	device_t dev;
996 	uint16_t ctl, new;
997 
998 	dev = sc->dev;
999 
1000 	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
1001 		return;
1002 
1003 	ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
1004 	new = (ctl & ~mask) | val;
1005 	if (new == ctl)
1006 		return;
1007 	if (bootverbose)
1008 		device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
1009 	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
1010 	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
1011 	    (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
1012 		sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
1013 		if (!cold)
1014 			callout_reset(&sc->pcie_cc_timer, hz,
1015 			    pcib_pcie_cc_timeout, sc);
1016 	}
1017 }
1018 
1019 static void
1020 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
1021 {
1022 	device_t dev;
1023 
1024 	dev = sc->dev;
1025 
1026 	if (bootverbose)
1027 		device_printf(dev, "Command Completed\n");
1028 	if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
1029 		return;
1030 	callout_stop(&sc->pcie_cc_timer);
1031 	sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1032 	wakeup(sc);
1033 }
1034 
1035 /*
1036  * Returns true if a card is fully inserted from the user's
1037  * perspective.  It may not yet be ready for access, but the driver
1038  * can now start enabling access if necessary.
1039  */
1040 static bool
1041 pcib_hotplug_inserted(struct pcib_softc *sc)
1042 {
1043 
1044 	/* Pretend the card isn't present if a detach is forced. */
1045 	if (sc->flags & PCIB_DETACHING)
1046 		return (false);
1047 
1048 	/* Card must be present in the slot. */
1049 	if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0)
1050 		return (false);
1051 
1052 	/* A power fault implicitly turns off power to the slot. */
1053 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1054 		return (false);
1055 
1056 	/* If the MRL is disengaged, the slot is powered off. */
1057 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP &&
1058 	    (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0)
1059 		return (false);
1060 
1061 	return (true);
1062 }
1063 
1064 /*
1065  * Returns -1 if the card is fully inserted, powered, and ready for
1066  * access.  Otherwise, returns 0.
1067  */
1068 static int
1069 pcib_hotplug_present(struct pcib_softc *sc)
1070 {
1071 
1072 	/* Card must be inserted. */
1073 	if (!pcib_hotplug_inserted(sc))
1074 		return (0);
1075 
1076 	/*
1077 	 * Require the Electromechanical Interlock to be engaged if
1078 	 * present.
1079 	 */
1080 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP &&
1081 	    (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0)
1082 		return (0);
1083 
1084 	/* Require the Data Link Layer to be active. */
1085 	if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE))
1086 		return (0);
1087 
1088 	return (-1);
1089 }
1090 
1091 static void
1092 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
1093     bool schedule_task)
1094 {
1095 	bool card_inserted, ei_engaged;
1096 
1097 	/* Clear DETACHING if Presence Detect has cleared. */
1098 	if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) ==
1099 	    PCIEM_SLOT_STA_PDC)
1100 		sc->flags &= ~PCIB_DETACHING;
1101 
1102 	card_inserted = pcib_hotplug_inserted(sc);
1103 
1104 	/* Turn the power indicator on if a card is inserted. */
1105 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) {
1106 		mask |= PCIEM_SLOT_CTL_PIC;
1107 		if (card_inserted)
1108 			val |= PCIEM_SLOT_CTL_PI_ON;
1109 		else if (sc->flags & PCIB_DETACH_PENDING)
1110 			val |= PCIEM_SLOT_CTL_PI_BLINK;
1111 		else
1112 			val |= PCIEM_SLOT_CTL_PI_OFF;
1113 	}
1114 
1115 	/* Turn the power on via the Power Controller if a card is inserted. */
1116 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) {
1117 		mask |= PCIEM_SLOT_CTL_PCC;
1118 		if (card_inserted)
1119 			val |= PCIEM_SLOT_CTL_PC_ON;
1120 		else
1121 			val |= PCIEM_SLOT_CTL_PC_OFF;
1122 	}
1123 
1124 	/*
1125 	 * If a card is inserted, enable the Electromechanical
1126 	 * Interlock.  If a card is not inserted (or we are in the
1127 	 * process of detaching), disable the Electromechanical
1128 	 * Interlock.
1129 	 */
1130 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
1131 		mask |= PCIEM_SLOT_CTL_EIC;
1132 		ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0;
1133 		if (card_inserted != ei_engaged)
1134 			val |= PCIEM_SLOT_CTL_EIC;
1135 	}
1136 
1137 	/*
1138 	 * Start a timer to see if the Data Link Layer times out.
1139 	 * Note that we only start the timer if Presence Detect or MRL Sensor
1140 	 * changed on this interrupt.  Stop any scheduled timer if
1141 	 * the Data Link Layer is active.
1142 	 */
1143 	if (card_inserted &&
1144 	    !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) &&
1145 	    sc->pcie_slot_sta &
1146 	    (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) {
1147 		if (cold)
1148 			device_printf(sc->dev,
1149 			    "Data Link Layer inactive\n");
1150 		else
1151 			callout_reset(&sc->pcie_dll_timer, hz,
1152 			    pcib_pcie_dll_timeout, sc);
1153 	} else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)
1154 		callout_stop(&sc->pcie_dll_timer);
1155 
1156 	pcib_pcie_hotplug_command(sc, val, mask);
1157 
1158 	/*
1159 	 * During attach the child "pci" device is added synchronously;
1160 	 * otherwise, the task is scheduled to manage the child
1161 	 * device.
1162 	 */
1163 	if (schedule_task &&
1164 	    (pcib_hotplug_present(sc) != 0) != (sc->child != NULL))
1165 		taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task);
1166 }
1167 
1168 static void
1169 pcib_pcie_intr_hotplug(void *arg)
1170 {
1171 	struct pcib_softc *sc;
1172 	device_t dev;
1173 	uint16_t old_slot_sta;
1174 
1175 	sc = arg;
1176 	dev = sc->dev;
1177 	old_slot_sta = sc->pcie_slot_sta;
1178 	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1179 
1180 	/* Clear the events just reported. */
1181 	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1182 
1183 	if (bootverbose)
1184 		device_printf(dev, "HotPlug interrupt: %#x\n",
1185 		    sc->pcie_slot_sta);
1186 
1187 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) {
1188 		if (sc->flags & PCIB_DETACH_PENDING) {
1189 			device_printf(dev,
1190 			    "Attention Button Pressed: Detach Cancelled\n");
1191 			sc->flags &= ~PCIB_DETACH_PENDING;
1192 			callout_stop(&sc->pcie_ab_timer);
1193 		} else if (old_slot_sta & PCIEM_SLOT_STA_PDS) {
1194 			/* Only initiate detach sequence if device present. */
1195 			device_printf(dev,
1196 		    "Attention Button Pressed: Detaching in 5 seconds\n");
1197 			sc->flags |= PCIB_DETACH_PENDING;
1198 			callout_reset(&sc->pcie_ab_timer, 5 * hz,
1199 			    pcib_pcie_ab_timeout, sc);
1200 		}
1201 	}
1202 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD)
1203 		device_printf(dev, "Power Fault Detected\n");
1204 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC)
1205 		device_printf(dev, "MRL Sensor Changed to %s\n",
1206 		    sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" :
1207 		    "closed");
1208 	if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC)
1209 		device_printf(dev, "Presence Detect Changed to %s\n",
1210 		    sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" :
1211 		    "empty");
1212 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC)
1213 		pcib_pcie_hotplug_command_completed(sc);
1214 	if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) {
1215 		sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1216 		if (bootverbose)
1217 			device_printf(dev,
1218 			    "Data Link Layer State Changed to %s\n",
1219 			    sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ?
1220 			    "active" : "inactive");
1221 	}
1222 
1223 	pcib_pcie_hotplug_update(sc, 0, 0, true);
1224 }
1225 
1226 static void
1227 pcib_pcie_hotplug_task(void *context, int pending)
1228 {
1229 	struct pcib_softc *sc;
1230 	device_t dev;
1231 
1232 	sc = context;
1233 	mtx_lock(&Giant);
1234 	dev = sc->dev;
1235 	if (pcib_hotplug_present(sc) != 0) {
1236 		if (sc->child == NULL) {
1237 			sc->child = device_add_child(dev, "pci", -1);
1238 			bus_generic_attach(dev);
1239 		}
1240 	} else {
1241 		if (sc->child != NULL) {
1242 			if (device_delete_child(dev, sc->child) == 0)
1243 				sc->child = NULL;
1244 		}
1245 	}
1246 	mtx_unlock(&Giant);
1247 }
1248 
1249 static void
1250 pcib_pcie_ab_timeout(void *arg)
1251 {
1252 	struct pcib_softc *sc;
1253 
1254 	sc = arg;
1255 	mtx_assert(&Giant, MA_OWNED);
1256 	if (sc->flags & PCIB_DETACH_PENDING) {
1257 		sc->flags |= PCIB_DETACHING;
1258 		sc->flags &= ~PCIB_DETACH_PENDING;
1259 		pcib_pcie_hotplug_update(sc, 0, 0, true);
1260 	}
1261 }
1262 
1263 static void
1264 pcib_pcie_cc_timeout(void *arg)
1265 {
1266 	struct pcib_softc *sc;
1267 	device_t dev;
1268 	uint16_t sta;
1269 
1270 	sc = arg;
1271 	dev = sc->dev;
1272 	mtx_assert(&Giant, MA_OWNED);
1273 	sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1274 	if (!(sta & PCIEM_SLOT_STA_CC)) {
1275 		device_printf(dev, "HotPlug Command Timed Out\n");
1276 		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1277 	} else {
1278 		device_printf(dev,
1279 	    "Missed HotPlug interrupt waiting for Command Completion\n");
1280 		pcib_pcie_intr_hotplug(sc);
1281 	}
1282 }
1283 
1284 static void
1285 pcib_pcie_dll_timeout(void *arg)
1286 {
1287 	struct pcib_softc *sc;
1288 	device_t dev;
1289 	uint16_t sta;
1290 
1291 	sc = arg;
1292 	dev = sc->dev;
1293 	mtx_assert(&Giant, MA_OWNED);
1294 	sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1295 	if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) {
1296 		device_printf(dev,
1297 		    "Timed out waiting for Data Link Layer Active\n");
1298 		sc->flags |= PCIB_DETACHING;
1299 		pcib_pcie_hotplug_update(sc, 0, 0, true);
1300 	} else if (sta != sc->pcie_link_sta) {
1301 		device_printf(dev,
1302 		    "Missed HotPlug interrupt waiting for DLL Active\n");
1303 		pcib_pcie_intr_hotplug(sc);
1304 	}
1305 }
1306 
1307 static int
1308 pcib_alloc_pcie_irq(struct pcib_softc *sc)
1309 {
1310 	device_t dev;
1311 	int count, error, rid;
1312 
1313 	rid = -1;
1314 	dev = sc->dev;
1315 
1316 	/*
1317 	 * For simplicity, only use MSI-X if there is a single message.
1318 	 * To support a device with multiple messages we would have to
1319 	 * use remap intr if the MSI number is not 0.
1320 	 */
1321 	count = pci_msix_count(dev);
1322 	if (count == 1) {
1323 		error = pci_alloc_msix(dev, &count);
1324 		if (error == 0)
1325 			rid = 1;
1326 	}
1327 
1328 	if (rid < 0 && pci_msi_count(dev) > 0) {
1329 		count = 1;
1330 		error = pci_alloc_msi(dev, &count);
1331 		if (error == 0)
1332 			rid = 1;
1333 	}
1334 
1335 	if (rid < 0)
1336 		rid = 0;
1337 
1338 	sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1339 	    RF_ACTIVE);
1340 	if (sc->pcie_irq == NULL) {
1341 		device_printf(dev,
1342 		    "Failed to allocate interrupt for PCI-e events\n");
1343 		if (rid > 0)
1344 			pci_release_msi(dev);
1345 		return (ENXIO);
1346 	}
1347 
1348 	error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC,
1349 	    NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand);
1350 	if (error) {
1351 		device_printf(dev, "Failed to setup PCI-e interrupt handler\n");
1352 		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq);
1353 		if (rid > 0)
1354 			pci_release_msi(dev);
1355 		return (error);
1356 	}
1357 	return (0);
1358 }
1359 
1360 static int
1361 pcib_release_pcie_irq(struct pcib_softc *sc)
1362 {
1363 	device_t dev;
1364 	int error;
1365 
1366 	dev = sc->dev;
1367 	error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand);
1368 	if (error)
1369 		return (error);
1370 	error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq);
1371 	if (error)
1372 		return (error);
1373 	return (pci_release_msi(dev));
1374 }
1375 
1376 static void
1377 pcib_setup_hotplug(struct pcib_softc *sc)
1378 {
1379 	device_t dev;
1380 	uint16_t mask, val;
1381 
1382 	dev = sc->dev;
1383 	callout_init(&sc->pcie_ab_timer, 0);
1384 	callout_init(&sc->pcie_cc_timer, 0);
1385 	callout_init(&sc->pcie_dll_timer, 0);
1386 	TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc);
1387 
1388 	/* Allocate IRQ. */
1389 	if (pcib_alloc_pcie_irq(sc) != 0)
1390 		return;
1391 
1392 	sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2);
1393 	sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2);
1394 
1395 	/* Clear any events previously pending. */
1396 	pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2);
1397 
1398 	/* Enable HotPlug events. */
1399 	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1400 	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1401 	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1402 	val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE;
1403 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB)
1404 		val |= PCIEM_SLOT_CTL_ABPE;
1405 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP)
1406 		val |= PCIEM_SLOT_CTL_PFDE;
1407 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP)
1408 		val |= PCIEM_SLOT_CTL_MRLSCE;
1409 	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS))
1410 		val |= PCIEM_SLOT_CTL_CCIE;
1411 
1412 	/* Turn the attention indicator off. */
1413 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1414 		mask |= PCIEM_SLOT_CTL_AIC;
1415 		val |= PCIEM_SLOT_CTL_AI_OFF;
1416 	}
1417 
1418 	pcib_pcie_hotplug_update(sc, val, mask, false);
1419 }
1420 
1421 static int
1422 pcib_detach_hotplug(struct pcib_softc *sc)
1423 {
1424 	uint16_t mask, val;
1425 	int error;
1426 
1427 	/* Disable the card in the slot and force it to detach. */
1428 	if (sc->flags & PCIB_DETACH_PENDING) {
1429 		sc->flags &= ~PCIB_DETACH_PENDING;
1430 		callout_stop(&sc->pcie_ab_timer);
1431 	}
1432 	sc->flags |= PCIB_DETACHING;
1433 
1434 	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
1435 		callout_stop(&sc->pcie_cc_timer);
1436 		tsleep(sc, 0, "hpcmd", hz);
1437 		sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
1438 	}
1439 
1440 	/* Disable HotPlug events. */
1441 	mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE |
1442 	    PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE |
1443 	    PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE;
1444 	val = 0;
1445 
1446 	/* Turn the attention indicator off. */
1447 	if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) {
1448 		mask |= PCIEM_SLOT_CTL_AIC;
1449 		val |= PCIEM_SLOT_CTL_AI_OFF;
1450 	}
1451 
1452 	pcib_pcie_hotplug_update(sc, val, mask, false);
1453 
1454 	error = pcib_release_pcie_irq(sc);
1455 	if (error)
1456 		return (error);
1457 	taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task);
1458 	callout_drain(&sc->pcie_ab_timer);
1459 	callout_drain(&sc->pcie_cc_timer);
1460 	callout_drain(&sc->pcie_dll_timer);
1461 	return (0);
1462 }
1463 #endif
1464 
1465 /*
1466  * Get current bridge configuration.
1467  */
1468 static void
1469 pcib_cfg_save(struct pcib_softc *sc)
1470 {
1471 #ifndef NEW_PCIB
1472 	device_t	dev;
1473 	uint16_t command;
1474 
1475 	dev = sc->dev;
1476 
1477 	command = pci_read_config(dev, PCIR_COMMAND, 2);
1478 	if (command & PCIM_CMD_PORTEN)
1479 		pcib_get_io_decode(sc);
1480 	if (command & PCIM_CMD_MEMEN)
1481 		pcib_get_mem_decode(sc);
1482 #endif
1483 }
1484 
1485 /*
1486  * Restore previous bridge configuration.
1487  */
1488 static void
1489 pcib_cfg_restore(struct pcib_softc *sc)
1490 {
1491 #ifndef NEW_PCIB
1492 	uint16_t command;
1493 #endif
1494 
1495 #ifdef NEW_PCIB
1496 	pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
1497 #else
1498 	command = pci_read_config(sc->dev, PCIR_COMMAND, 2);
1499 	if (command & PCIM_CMD_PORTEN)
1500 		pcib_set_io_decode(sc);
1501 	if (command & PCIM_CMD_MEMEN)
1502 		pcib_set_mem_decode(sc);
1503 #endif
1504 }
1505 
1506 /*
1507  * Generic device interface
1508  */
1509 static int
1510 pcib_probe(device_t dev)
1511 {
1512     if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1513 	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1514 	device_set_desc(dev, "PCI-PCI bridge");
1515 	return(-10000);
1516     }
1517     return(ENXIO);
1518 }
1519 
1520 void
1521 pcib_attach_common(device_t dev)
1522 {
1523     struct pcib_softc	*sc;
1524     struct sysctl_ctx_list *sctx;
1525     struct sysctl_oid	*soid;
1526     int comma;
1527 
1528     sc = device_get_softc(dev);
1529     sc->dev = dev;
1530 
1531     /*
1532      * Get current bridge configuration.
1533      */
1534     sc->domain = pci_get_domain(dev);
1535 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1536     sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
1537     sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1538 #endif
1539     sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1540     pcib_cfg_save(sc);
1541 
1542     /*
1543      * The primary bus register should always be the bus of the
1544      * parent.
1545      */
1546     sc->pribus = pci_get_bus(dev);
1547     pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
1548 
1549     /*
1550      * Setup sysctl reporting nodes
1551      */
1552     sctx = device_get_sysctl_ctx(dev);
1553     soid = device_get_sysctl_tree(dev);
1554     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
1555       CTLFLAG_RD, &sc->domain, 0, "Domain number");
1556     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
1557       CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
1558     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
1559       CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
1560     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
1561       CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
1562 
1563     /*
1564      * Quirk handling.
1565      */
1566     switch (pci_get_devid(dev)) {
1567 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1568     case 0x12258086:		/* Intel 82454KX/GX (Orion) */
1569 	{
1570 	    uint8_t	supbus;
1571 
1572 	    supbus = pci_read_config(dev, 0x41, 1);
1573 	    if (supbus != 0xff) {
1574 		sc->bus.sec = supbus + 1;
1575 		sc->bus.sub = supbus + 1;
1576 	    }
1577 	    break;
1578 	}
1579 #endif
1580 
1581     /*
1582      * The i82380FB mobile docking controller is a PCI-PCI bridge,
1583      * and it is a subtractive bridge.  However, the ProgIf is wrong
1584      * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
1585      * happen.  There are also Toshiba and Cavium ThunderX bridges
1586      * that behave this way.
1587      */
1588     case 0xa002177d:		/* Cavium ThunderX */
1589     case 0x124b8086:		/* Intel 82380FB Mobile */
1590     case 0x060513d7:		/* Toshiba ???? */
1591 	sc->flags |= PCIB_SUBTRACTIVE;
1592 	break;
1593 
1594 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
1595     /* Compaq R3000 BIOS sets wrong subordinate bus number. */
1596     case 0x00dd10de:
1597 	{
1598 	    char *cp;
1599 
1600 	    if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
1601 		break;
1602 	    if (strncmp(cp, "Compal", 6) != 0) {
1603 		freeenv(cp);
1604 		break;
1605 	    }
1606 	    freeenv(cp);
1607 	    if ((cp = kern_getenv("smbios.planar.product")) == NULL)
1608 		break;
1609 	    if (strncmp(cp, "08A0", 4) != 0) {
1610 		freeenv(cp);
1611 		break;
1612 	    }
1613 	    freeenv(cp);
1614 	    if (sc->bus.sub < 0xa) {
1615 		pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
1616 		sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1617 	    }
1618 	    break;
1619 	}
1620 #endif
1621     }
1622 
1623     if (pci_msi_device_blacklisted(dev))
1624 	sc->flags |= PCIB_DISABLE_MSI;
1625 
1626     if (pci_msix_device_blacklisted(dev))
1627 	sc->flags |= PCIB_DISABLE_MSIX;
1628 
1629     /*
1630      * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1631      * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
1632      * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1633      * This means they act as if they were subtractively decoding
1634      * bridges and pass all transactions.  Mark them and real ProgIf 1
1635      * parts as subtractive.
1636      */
1637     if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1638       pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1639 	sc->flags |= PCIB_SUBTRACTIVE;
1640 
1641 #ifdef PCI_HP
1642     pcib_probe_hotplug(sc);
1643 #endif
1644 #ifdef NEW_PCIB
1645 #ifdef PCI_RES_BUS
1646     pcib_setup_secbus(dev, &sc->bus, 1);
1647 #endif
1648     pcib_probe_windows(sc);
1649 #endif
1650 #ifdef PCI_HP
1651     if (sc->flags & PCIB_HOTPLUG)
1652 	    pcib_setup_hotplug(sc);
1653 #endif
1654     if (bootverbose) {
1655 	device_printf(dev, "  domain            %d\n", sc->domain);
1656 	device_printf(dev, "  secondary bus     %d\n", sc->bus.sec);
1657 	device_printf(dev, "  subordinate bus   %d\n", sc->bus.sub);
1658 #ifdef NEW_PCIB
1659 	if (pcib_is_window_open(&sc->io))
1660 	    device_printf(dev, "  I/O decode        0x%jx-0x%jx\n",
1661 	      (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1662 	if (pcib_is_window_open(&sc->mem))
1663 	    device_printf(dev, "  memory decode     0x%jx-0x%jx\n",
1664 	      (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1665 	if (pcib_is_window_open(&sc->pmem))
1666 	    device_printf(dev, "  prefetched decode 0x%jx-0x%jx\n",
1667 	      (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1668 #else
1669 	if (pcib_is_io_open(sc))
1670 	    device_printf(dev, "  I/O decode        0x%x-0x%x\n",
1671 	      sc->iobase, sc->iolimit);
1672 	if (pcib_is_nonprefetch_open(sc))
1673 	    device_printf(dev, "  memory decode     0x%jx-0x%jx\n",
1674 	      (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1675 	if (pcib_is_prefetch_open(sc))
1676 	    device_printf(dev, "  prefetched decode 0x%jx-0x%jx\n",
1677 	      (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1678 #endif
1679 	if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1680 	    sc->flags & PCIB_SUBTRACTIVE) {
1681 		device_printf(dev, "  special decode    ");
1682 		comma = 0;
1683 		if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1684 			printf("ISA");
1685 			comma = 1;
1686 		}
1687 		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1688 			printf("%sVGA", comma ? ", " : "");
1689 			comma = 1;
1690 		}
1691 		if (sc->flags & PCIB_SUBTRACTIVE)
1692 			printf("%ssubtractive", comma ? ", " : "");
1693 		printf("\n");
1694 	}
1695     }
1696 
1697     /*
1698      * Always enable busmastering on bridges so that transactions
1699      * initiated on the secondary bus are passed through to the
1700      * primary bus.
1701      */
1702     pci_enable_busmaster(dev);
1703 }
1704 
1705 #ifdef PCI_HP
1706 static int
1707 pcib_present(struct pcib_softc *sc)
1708 {
1709 
1710 	if (sc->flags & PCIB_HOTPLUG)
1711 		return (pcib_hotplug_present(sc) != 0);
1712 	return (1);
1713 }
1714 #endif
1715 
1716 int
1717 pcib_attach_child(device_t dev)
1718 {
1719 	struct pcib_softc *sc;
1720 
1721 	sc = device_get_softc(dev);
1722 	if (sc->bus.sec == 0) {
1723 		/* no secondary bus; we should have fixed this */
1724 		return(0);
1725 	}
1726 
1727 #ifdef PCI_HP
1728 	if (!pcib_present(sc)) {
1729 		/* An empty HotPlug slot, so don't add a PCI bus yet. */
1730 		return (0);
1731 	}
1732 #endif
1733 
1734 	sc->child = device_add_child(dev, "pci", -1);
1735 	return (bus_generic_attach(dev));
1736 }
1737 
1738 int
1739 pcib_attach(device_t dev)
1740 {
1741 
1742     pcib_attach_common(dev);
1743     return (pcib_attach_child(dev));
1744 }
1745 
1746 int
1747 pcib_detach(device_t dev)
1748 {
1749 #if defined(PCI_HP) || defined(NEW_PCIB)
1750 	struct pcib_softc *sc;
1751 #endif
1752 	int error;
1753 
1754 #if defined(PCI_HP) || defined(NEW_PCIB)
1755 	sc = device_get_softc(dev);
1756 #endif
1757 	error = bus_generic_detach(dev);
1758 	if (error)
1759 		return (error);
1760 #ifdef PCI_HP
1761 	if (sc->flags & PCIB_HOTPLUG) {
1762 		error = pcib_detach_hotplug(sc);
1763 		if (error)
1764 			return (error);
1765 	}
1766 #endif
1767 	error = device_delete_children(dev);
1768 	if (error)
1769 		return (error);
1770 #ifdef NEW_PCIB
1771 	pcib_free_windows(sc);
1772 #ifdef PCI_RES_BUS
1773 	pcib_free_secbus(dev, &sc->bus);
1774 #endif
1775 #endif
1776 	return (0);
1777 }
1778 
1779 int
1780 pcib_suspend(device_t dev)
1781 {
1782 
1783 	pcib_cfg_save(device_get_softc(dev));
1784 	return (bus_generic_suspend(dev));
1785 }
1786 
1787 int
1788 pcib_resume(device_t dev)
1789 {
1790 
1791 	pcib_cfg_restore(device_get_softc(dev));
1792 	return (bus_generic_resume(dev));
1793 }
1794 
1795 void
1796 pcib_bridge_init(device_t dev)
1797 {
1798 	pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
1799 	pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
1800 	pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
1801 	pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
1802 	pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
1803 	pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
1804 	pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
1805 	pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
1806 	pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
1807 	pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
1808 }
1809 
1810 int
1811 pcib_child_present(device_t dev, device_t child)
1812 {
1813 #ifdef PCI_HP
1814 	struct pcib_softc *sc = device_get_softc(dev);
1815 	int retval;
1816 
1817 	retval = bus_child_present(dev);
1818 	if (retval != 0 && sc->flags & PCIB_HOTPLUG)
1819 		retval = pcib_hotplug_present(sc);
1820 	return (retval);
1821 #else
1822 	return (bus_child_present(dev));
1823 #endif
1824 }
1825 
1826 int
1827 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1828 {
1829     struct pcib_softc	*sc = device_get_softc(dev);
1830 
1831     switch (which) {
1832     case PCIB_IVAR_DOMAIN:
1833 	*result = sc->domain;
1834 	return(0);
1835     case PCIB_IVAR_BUS:
1836 	*result = sc->bus.sec;
1837 	return(0);
1838     }
1839     return(ENOENT);
1840 }
1841 
1842 int
1843 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1844 {
1845 
1846     switch (which) {
1847     case PCIB_IVAR_DOMAIN:
1848 	return(EINVAL);
1849     case PCIB_IVAR_BUS:
1850 	return(EINVAL);
1851     }
1852     return(ENOENT);
1853 }
1854 
1855 #ifdef NEW_PCIB
1856 /*
1857  * Attempt to allocate a resource from the existing resources assigned
1858  * to a window.
1859  */
1860 static struct resource *
1861 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1862     device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
1863     rman_res_t count, u_int flags)
1864 {
1865 	struct resource *res;
1866 
1867 	if (!pcib_is_window_open(w))
1868 		return (NULL);
1869 
1870 	res = rman_reserve_resource(&w->rman, start, end, count,
1871 	    flags & ~RF_ACTIVE, child);
1872 	if (res == NULL)
1873 		return (NULL);
1874 
1875 	if (bootverbose)
1876 		device_printf(sc->dev,
1877 		    "allocated %s range (%#jx-%#jx) for rid %x of %s\n",
1878 		    w->name, rman_get_start(res), rman_get_end(res), *rid,
1879 		    pcib_child_name(child));
1880 	rman_set_rid(res, *rid);
1881 
1882 	/*
1883 	 * If the resource should be active, pass that request up the
1884 	 * tree.  This assumes the parent drivers can handle
1885 	 * activating sub-allocated resources.
1886 	 */
1887 	if (flags & RF_ACTIVE) {
1888 		if (bus_activate_resource(child, type, *rid, res) != 0) {
1889 			rman_release_resource(res);
1890 			return (NULL);
1891 		}
1892 	}
1893 
1894 	return (res);
1895 }
1896 
1897 /* Allocate a fresh resource range for an unconfigured window. */
1898 static int
1899 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1900     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1901 {
1902 	struct resource *res;
1903 	rman_res_t base, limit, wmask;
1904 	int rid;
1905 
1906 	/*
1907 	 * If this is an I/O window on a bridge with ISA enable set
1908 	 * and the start address is below 64k, then try to allocate an
1909 	 * initial window of 0x1000 bytes long starting at address
1910 	 * 0xf000 and walking down.  Note that if the original request
1911 	 * was larger than the non-aliased range size of 0x100 our
1912 	 * caller would have raised the start address up to 64k
1913 	 * already.
1914 	 */
1915 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1916 	    start < 65536) {
1917 		for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1918 			limit = base + 0xfff;
1919 
1920 			/*
1921 			 * Skip ranges that wouldn't work for the
1922 			 * original request.  Note that the actual
1923 			 * window that overlaps are the non-alias
1924 			 * ranges within [base, limit], so this isn't
1925 			 * quite a simple comparison.
1926 			 */
1927 			if (start + count > limit - 0x400)
1928 				continue;
1929 			if (base == 0) {
1930 				/*
1931 				 * The first open region for the window at
1932 				 * 0 is 0x400-0x4ff.
1933 				 */
1934 				if (end - count + 1 < 0x400)
1935 					continue;
1936 			} else {
1937 				if (end - count + 1 < base)
1938 					continue;
1939 			}
1940 
1941 			if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1942 				w->base = base;
1943 				w->limit = limit;
1944 				return (0);
1945 			}
1946 		}
1947 		return (ENOSPC);
1948 	}
1949 
1950 	wmask = ((rman_res_t)1 << w->step) - 1;
1951 	if (RF_ALIGNMENT(flags) < w->step) {
1952 		flags &= ~RF_ALIGNMENT_MASK;
1953 		flags |= RF_ALIGNMENT_LOG2(w->step);
1954 	}
1955 	start &= ~wmask;
1956 	end |= wmask;
1957 	count = roundup2(count, (rman_res_t)1 << w->step);
1958 	rid = w->reg;
1959 	res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1960 	    flags & ~RF_ACTIVE);
1961 	if (res == NULL)
1962 		return (ENOSPC);
1963 	pcib_add_window_resources(w, &res, 1);
1964 	pcib_activate_window(sc, type);
1965 	w->base = rman_get_start(res);
1966 	w->limit = rman_get_end(res);
1967 	return (0);
1968 }
1969 
1970 /* Try to expand an existing window to the requested base and limit. */
1971 static int
1972 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1973     rman_res_t base, rman_res_t limit)
1974 {
1975 	struct resource *res;
1976 	int error, i, force_64k_base;
1977 
1978 	KASSERT(base <= w->base && limit >= w->limit,
1979 	    ("attempting to shrink window"));
1980 
1981 	/*
1982 	 * XXX: pcib_grow_window() doesn't try to do this anyway and
1983 	 * the error handling for all the edge cases would be tedious.
1984 	 */
1985 	KASSERT(limit == w->limit || base == w->base,
1986 	    ("attempting to grow both ends of a window"));
1987 
1988 	/*
1989 	 * Yet more special handling for requests to expand an I/O
1990 	 * window behind an ISA-enabled bridge.  Since I/O windows
1991 	 * have to grow in 0x1000 increments and the end of the 0xffff
1992 	 * range is an alias, growing a window below 64k will always
1993 	 * result in allocating new resources and never adjusting an
1994 	 * existing resource.
1995 	 */
1996 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1997 	    (limit <= 65535 || (base <= 65535 && base != w->base))) {
1998 		KASSERT(limit == w->limit || limit <= 65535,
1999 		    ("attempting to grow both ends across 64k ISA alias"));
2000 
2001 		if (base != w->base)
2002 			error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
2003 		else
2004 			error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
2005 			    limit);
2006 		if (error == 0) {
2007 			w->base = base;
2008 			w->limit = limit;
2009 		}
2010 		return (error);
2011 	}
2012 
2013 	/*
2014 	 * Find the existing resource to adjust.  Usually there is only one,
2015 	 * but for an ISA-enabled bridge we might be growing the I/O window
2016 	 * above 64k and need to find the existing resource that maps all
2017 	 * of the area above 64k.
2018 	 */
2019 	for (i = 0; i < w->count; i++) {
2020 		if (rman_get_end(w->res[i]) == w->limit)
2021 			break;
2022 	}
2023 	KASSERT(i != w->count, ("did not find existing resource"));
2024 	res = w->res[i];
2025 
2026 	/*
2027 	 * Usually the resource we found should match the window's
2028 	 * existing range.  The one exception is the ISA-enabled case
2029 	 * mentioned above in which case the resource should start at
2030 	 * 64k.
2031 	 */
2032 	if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
2033 	    w->base <= 65535) {
2034 		KASSERT(rman_get_start(res) == 65536,
2035 		    ("existing resource mismatch"));
2036 		force_64k_base = 1;
2037 	} else {
2038 		KASSERT(w->base == rman_get_start(res),
2039 		    ("existing resource mismatch"));
2040 		force_64k_base = 0;
2041 	}
2042 
2043 	error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2044 	    rman_get_start(res) : base, limit);
2045 	if (error)
2046 		return (error);
2047 
2048 	/* Add the newly allocated region to the resource manager. */
2049 	if (w->base != base) {
2050 		error = rman_manage_region(&w->rman, base, w->base - 1);
2051 		w->base = base;
2052 	} else {
2053 		error = rman_manage_region(&w->rman, w->limit + 1, limit);
2054 		w->limit = limit;
2055 	}
2056 	if (error) {
2057 		if (bootverbose)
2058 			device_printf(sc->dev,
2059 			    "failed to expand %s resource manager\n", w->name);
2060 		(void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
2061 		    rman_get_start(res) : w->base, w->limit);
2062 	}
2063 	return (error);
2064 }
2065 
2066 /*
2067  * Attempt to grow a window to make room for a given resource request.
2068  */
2069 static int
2070 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
2071     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2072 {
2073 	rman_res_t align, start_free, end_free, front, back, wmask;
2074 	int error;
2075 
2076 	/*
2077 	 * Clamp the desired resource range to the maximum address
2078 	 * this window supports.  Reject impossible requests.
2079 	 *
2080 	 * For I/O port requests behind a bridge with the ISA enable
2081 	 * bit set, force large allocations to start above 64k.
2082 	 */
2083 	if (!w->valid)
2084 		return (EINVAL);
2085 	if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
2086 	    start < 65536)
2087 		start = 65536;
2088 	if (end > w->rman.rm_end)
2089 		end = w->rman.rm_end;
2090 	if (start + count - 1 > end || start + count < start)
2091 		return (EINVAL);
2092 	wmask = ((rman_res_t)1 << w->step) - 1;
2093 
2094 	/*
2095 	 * If there is no resource at all, just try to allocate enough
2096 	 * aligned space for this resource.
2097 	 */
2098 	if (w->res == NULL) {
2099 		error = pcib_alloc_new_window(sc, w, type, start, end, count,
2100 		    flags);
2101 		if (error) {
2102 			if (bootverbose)
2103 				device_printf(sc->dev,
2104 		    "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n",
2105 				    w->name, start, end, count);
2106 			return (error);
2107 		}
2108 		if (bootverbose)
2109 			device_printf(sc->dev,
2110 			    "allocated initial %s window of %#jx-%#jx\n",
2111 			    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2112 		goto updatewin;
2113 	}
2114 
2115 	/*
2116 	 * See if growing the window would help.  Compute the minimum
2117 	 * amount of address space needed on both the front and back
2118 	 * ends of the existing window to satisfy the allocation.
2119 	 *
2120 	 * For each end, build a candidate region adjusting for the
2121 	 * required alignment, etc.  If there is a free region at the
2122 	 * edge of the window, grow from the inner edge of the free
2123 	 * region.  Otherwise grow from the window boundary.
2124 	 *
2125 	 * Growing an I/O window below 64k for a bridge with the ISA
2126 	 * enable bit doesn't require any special magic as the step
2127 	 * size of an I/O window (1k) always includes multiple
2128 	 * non-alias ranges when it is grown in either direction.
2129 	 *
2130 	 * XXX: Special case: if w->res is completely empty and the
2131 	 * request size is larger than w->res, we should find the
2132 	 * optimal aligned buffer containing w->res and allocate that.
2133 	 */
2134 	if (bootverbose)
2135 		device_printf(sc->dev,
2136 		    "attempting to grow %s window for (%#jx-%#jx,%#jx)\n",
2137 		    w->name, start, end, count);
2138 	align = (rman_res_t)1 << RF_ALIGNMENT(flags);
2139 	if (start < w->base) {
2140 		if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
2141 		    0 || start_free != w->base)
2142 			end_free = w->base;
2143 		if (end_free > end)
2144 			end_free = end + 1;
2145 
2146 		/* Move end_free down until it is properly aligned. */
2147 		end_free &= ~(align - 1);
2148 		end_free--;
2149 		front = end_free - (count - 1);
2150 
2151 		/*
2152 		 * The resource would now be allocated at (front,
2153 		 * end_free).  Ensure that fits in the (start, end)
2154 		 * bounds.  end_free is checked above.  If 'front' is
2155 		 * ok, ensure it is properly aligned for this window.
2156 		 * Also check for underflow.
2157 		 */
2158 		if (front >= start && front <= end_free) {
2159 			if (bootverbose)
2160 				printf("\tfront candidate range: %#jx-%#jx\n",
2161 				    front, end_free);
2162 			front &= ~wmask;
2163 			front = w->base - front;
2164 		} else
2165 			front = 0;
2166 	} else
2167 		front = 0;
2168 	if (end > w->limit) {
2169 		if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
2170 		    0 || end_free != w->limit)
2171 			start_free = w->limit + 1;
2172 		if (start_free < start)
2173 			start_free = start;
2174 
2175 		/* Move start_free up until it is properly aligned. */
2176 		start_free = roundup2(start_free, align);
2177 		back = start_free + count - 1;
2178 
2179 		/*
2180 		 * The resource would now be allocated at (start_free,
2181 		 * back).  Ensure that fits in the (start, end)
2182 		 * bounds.  start_free is checked above.  If 'back' is
2183 		 * ok, ensure it is properly aligned for this window.
2184 		 * Also check for overflow.
2185 		 */
2186 		if (back <= end && start_free <= back) {
2187 			if (bootverbose)
2188 				printf("\tback candidate range: %#jx-%#jx\n",
2189 				    start_free, back);
2190 			back |= wmask;
2191 			back -= w->limit;
2192 		} else
2193 			back = 0;
2194 	} else
2195 		back = 0;
2196 
2197 	/*
2198 	 * Try to allocate the smallest needed region first.
2199 	 * If that fails, fall back to the other region.
2200 	 */
2201 	error = ENOSPC;
2202 	while (front != 0 || back != 0) {
2203 		if (front != 0 && (front <= back || back == 0)) {
2204 			error = pcib_expand_window(sc, w, type, w->base - front,
2205 			    w->limit);
2206 			if (error == 0)
2207 				break;
2208 			front = 0;
2209 		} else {
2210 			error = pcib_expand_window(sc, w, type, w->base,
2211 			    w->limit + back);
2212 			if (error == 0)
2213 				break;
2214 			back = 0;
2215 		}
2216 	}
2217 
2218 	if (error)
2219 		return (error);
2220 	if (bootverbose)
2221 		device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
2222 		    w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
2223 
2224 updatewin:
2225 	/* Write the new window. */
2226 	KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
2227 	KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
2228 	pcib_write_windows(sc, w->mask);
2229 	return (0);
2230 }
2231 
2232 /*
2233  * We have to trap resource allocation requests and ensure that the bridge
2234  * is set up to, or capable of handling them.
2235  */
2236 struct resource *
2237 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2238     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2239 {
2240 	struct pcib_softc *sc;
2241 	struct resource *r;
2242 
2243 	sc = device_get_softc(dev);
2244 
2245 	/*
2246 	 * VGA resources are decoded iff the VGA enable bit is set in
2247 	 * the bridge control register.  VGA resources do not fall into
2248 	 * the resource windows and are passed up to the parent.
2249 	 */
2250 	if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
2251 	    (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
2252 		if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
2253 			return (bus_generic_alloc_resource(dev, child, type,
2254 			    rid, start, end, count, flags));
2255 		else
2256 			return (NULL);
2257 	}
2258 
2259 	switch (type) {
2260 #ifdef PCI_RES_BUS
2261 	case PCI_RES_BUS:
2262 		return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
2263 		    count, flags));
2264 #endif
2265 	case SYS_RES_IOPORT:
2266 		if (pcib_is_isa_range(sc, start, end, count))
2267 			return (NULL);
2268 		r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
2269 		    end, count, flags);
2270 		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2271 			break;
2272 		if (pcib_grow_window(sc, &sc->io, type, start, end, count,
2273 		    flags) == 0)
2274 			r = pcib_suballoc_resource(sc, &sc->io, child, type,
2275 			    rid, start, end, count, flags);
2276 		break;
2277 	case SYS_RES_MEMORY:
2278 		/*
2279 		 * For prefetchable resources, prefer the prefetchable
2280 		 * memory window, but fall back to the regular memory
2281 		 * window if that fails.  Try both windows before
2282 		 * attempting to grow a window in case the firmware
2283 		 * has used a range in the regular memory window to
2284 		 * map a prefetchable BAR.
2285 		 */
2286 		if (flags & RF_PREFETCHABLE) {
2287 			r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
2288 			    rid, start, end, count, flags);
2289 			if (r != NULL)
2290 				break;
2291 		}
2292 		r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
2293 		    start, end, count, flags);
2294 		if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
2295 			break;
2296 		if (flags & RF_PREFETCHABLE) {
2297 			if (pcib_grow_window(sc, &sc->pmem, type, start, end,
2298 			    count, flags) == 0) {
2299 				r = pcib_suballoc_resource(sc, &sc->pmem, child,
2300 				    type, rid, start, end, count, flags);
2301 				if (r != NULL)
2302 					break;
2303 			}
2304 		}
2305 		if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
2306 		    flags & ~RF_PREFETCHABLE) == 0)
2307 			r = pcib_suballoc_resource(sc, &sc->mem, child, type,
2308 			    rid, start, end, count, flags);
2309 		break;
2310 	default:
2311 		return (bus_generic_alloc_resource(dev, child, type, rid,
2312 		    start, end, count, flags));
2313 	}
2314 
2315 	/*
2316 	 * If attempts to suballocate from the window fail but this is a
2317 	 * subtractive bridge, pass the request up the tree.
2318 	 */
2319 	if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
2320 		return (bus_generic_alloc_resource(dev, child, type, rid,
2321 		    start, end, count, flags));
2322 	return (r);
2323 }
2324 
2325 int
2326 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
2327     rman_res_t start, rman_res_t end)
2328 {
2329 	struct pcib_softc *sc;
2330 
2331 	sc = device_get_softc(bus);
2332 	if (pcib_is_resource_managed(sc, type, r))
2333 		return (rman_adjust_resource(r, start, end));
2334 	return (bus_generic_adjust_resource(bus, child, type, r, start, end));
2335 }
2336 
2337 int
2338 pcib_release_resource(device_t dev, device_t child, int type, int rid,
2339     struct resource *r)
2340 {
2341 	struct pcib_softc *sc;
2342 	int error;
2343 
2344 	sc = device_get_softc(dev);
2345 	if (pcib_is_resource_managed(sc, type, r)) {
2346 		if (rman_get_flags(r) & RF_ACTIVE) {
2347 			error = bus_deactivate_resource(child, type, rid, r);
2348 			if (error)
2349 				return (error);
2350 		}
2351 		return (rman_release_resource(r));
2352 	}
2353 	return (bus_generic_release_resource(dev, child, type, rid, r));
2354 }
2355 #else
2356 /*
2357  * We have to trap resource allocation requests and ensure that the bridge
2358  * is set up to, or capable of handling them.
2359  */
2360 struct resource *
2361 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
2362     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
2363 {
2364 	struct pcib_softc	*sc = device_get_softc(dev);
2365 	const char *name, *suffix;
2366 	int ok;
2367 
2368 	/*
2369 	 * Fail the allocation for this range if it's not supported.
2370 	 */
2371 	name = device_get_nameunit(child);
2372 	if (name == NULL) {
2373 		name = "";
2374 		suffix = "";
2375 	} else
2376 		suffix = " ";
2377 	switch (type) {
2378 	case SYS_RES_IOPORT:
2379 		ok = 0;
2380 		if (!pcib_is_io_open(sc))
2381 			break;
2382 		ok = (start >= sc->iobase && end <= sc->iolimit);
2383 
2384 		/*
2385 		 * Make sure we allow access to VGA I/O addresses when the
2386 		 * bridge has the "VGA Enable" bit set.
2387 		 */
2388 		if (!ok && pci_is_vga_ioport_range(start, end))
2389 			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2390 
2391 		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2392 			if (!ok) {
2393 				if (start < sc->iobase)
2394 					start = sc->iobase;
2395 				if (end > sc->iolimit)
2396 					end = sc->iolimit;
2397 				if (start < end)
2398 					ok = 1;
2399 			}
2400 		} else {
2401 			ok = 1;
2402 #if 0
2403 			/*
2404 			 * If we overlap with the subtractive range, then
2405 			 * pick the upper range to use.
2406 			 */
2407 			if (start < sc->iolimit && end > sc->iobase)
2408 				start = sc->iolimit + 1;
2409 #endif
2410 		}
2411 		if (end < start) {
2412 			device_printf(dev, "ioport: end (%jx) < start (%jx)\n",
2413 			    end, start);
2414 			start = 0;
2415 			end = 0;
2416 			ok = 0;
2417 		}
2418 		if (!ok) {
2419 			device_printf(dev, "%s%srequested unsupported I/O "
2420 			    "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n",
2421 			    name, suffix, start, end, sc->iobase, sc->iolimit);
2422 			return (NULL);
2423 		}
2424 		if (bootverbose)
2425 			device_printf(dev,
2426 			    "%s%srequested I/O range 0x%jx-0x%jx: in range\n",
2427 			    name, suffix, start, end);
2428 		break;
2429 
2430 	case SYS_RES_MEMORY:
2431 		ok = 0;
2432 		if (pcib_is_nonprefetch_open(sc))
2433 			ok = ok || (start >= sc->membase && end <= sc->memlimit);
2434 		if (pcib_is_prefetch_open(sc))
2435 			ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
2436 
2437 		/*
2438 		 * Make sure we allow access to VGA memory addresses when the
2439 		 * bridge has the "VGA Enable" bit set.
2440 		 */
2441 		if (!ok && pci_is_vga_memory_range(start, end))
2442 			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
2443 
2444 		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
2445 			if (!ok) {
2446 				ok = 1;
2447 				if (flags & RF_PREFETCHABLE) {
2448 					if (pcib_is_prefetch_open(sc)) {
2449 						if (start < sc->pmembase)
2450 							start = sc->pmembase;
2451 						if (end > sc->pmemlimit)
2452 							end = sc->pmemlimit;
2453 					} else {
2454 						ok = 0;
2455 					}
2456 				} else {	/* non-prefetchable */
2457 					if (pcib_is_nonprefetch_open(sc)) {
2458 						if (start < sc->membase)
2459 							start = sc->membase;
2460 						if (end > sc->memlimit)
2461 							end = sc->memlimit;
2462 					} else {
2463 						ok = 0;
2464 					}
2465 				}
2466 			}
2467 		} else if (!ok) {
2468 			ok = 1;	/* subtractive bridge: always ok */
2469 #if 0
2470 			if (pcib_is_nonprefetch_open(sc)) {
2471 				if (start < sc->memlimit && end > sc->membase)
2472 					start = sc->memlimit + 1;
2473 			}
2474 			if (pcib_is_prefetch_open(sc)) {
2475 				if (start < sc->pmemlimit && end > sc->pmembase)
2476 					start = sc->pmemlimit + 1;
2477 			}
2478 #endif
2479 		}
2480 		if (end < start) {
2481 			device_printf(dev, "memory: end (%jx) < start (%jx)\n",
2482 			    end, start);
2483 			start = 0;
2484 			end = 0;
2485 			ok = 0;
2486 		}
2487 		if (!ok && bootverbose)
2488 			device_printf(dev,
2489 			    "%s%srequested unsupported memory range %#jx-%#jx "
2490 			    "(decoding %#jx-%#jx, %#jx-%#jx)\n",
2491 			    name, suffix, start, end,
2492 			    (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
2493 			    (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2494 		if (!ok)
2495 			return (NULL);
2496 		if (bootverbose)
2497 			device_printf(dev,"%s%srequested memory range "
2498 			    "0x%jx-0x%jx: good\n",
2499 			    name, suffix, start, end);
2500 		break;
2501 
2502 	default:
2503 		break;
2504 	}
2505 	/*
2506 	 * Bridge is OK decoding this resource, so pass it up.
2507 	 */
2508 	return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
2509 	    count, flags));
2510 }
2511 #endif
2512 
2513 /*
2514  * If ARI is enabled on this downstream port, translate the function number
2515  * to the non-ARI slot/function.  The downstream port will convert it back in
2516  * hardware.  If ARI is not enabled slot and func are not modified.
2517  */
2518 static __inline void
2519 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
2520 {
2521 	struct pcib_softc *sc;
2522 	int ari_func;
2523 
2524 	sc = device_get_softc(pcib);
2525 	ari_func = *func;
2526 
2527 	if (sc->flags & PCIB_ENABLE_ARI) {
2528 		KASSERT(*slot == 0,
2529 		    ("Non-zero slot number with ARI enabled!"));
2530 		*slot = PCIE_ARI_SLOT(ari_func);
2531 		*func = PCIE_ARI_FUNC(ari_func);
2532 	}
2533 }
2534 
2535 
2536 static void
2537 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
2538 {
2539 	uint32_t ctl2;
2540 
2541 	ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
2542 	ctl2 |= PCIEM_CTL2_ARI;
2543 	pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
2544 
2545 	sc->flags |= PCIB_ENABLE_ARI;
2546 }
2547 
2548 /*
2549  * PCIB interface.
2550  */
2551 int
2552 pcib_maxslots(device_t dev)
2553 {
2554 #if !defined(__amd64__) && !defined(__i386__)
2555 	uint32_t pcie_pos;
2556 	uint16_t val;
2557 
2558 	/*
2559 	 * If this is a PCIe rootport or downstream switch port, there's only
2560 	 * one slot permitted.
2561 	 */
2562 	if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) {
2563 		val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2);
2564 		val &= PCIEM_FLAGS_TYPE;
2565 		if (val == PCIEM_TYPE_ROOT_PORT ||
2566 		    val == PCIEM_TYPE_DOWNSTREAM_PORT)
2567 			return (0);
2568 	}
2569 #endif
2570 	return (PCI_SLOTMAX);
2571 }
2572 
2573 static int
2574 pcib_ari_maxslots(device_t dev)
2575 {
2576 	struct pcib_softc *sc;
2577 
2578 	sc = device_get_softc(dev);
2579 
2580 	if (sc->flags & PCIB_ENABLE_ARI)
2581 		return (PCIE_ARI_SLOTMAX);
2582 	else
2583 		return (pcib_maxslots(dev));
2584 }
2585 
2586 static int
2587 pcib_ari_maxfuncs(device_t dev)
2588 {
2589 	struct pcib_softc *sc;
2590 
2591 	sc = device_get_softc(dev);
2592 
2593 	if (sc->flags & PCIB_ENABLE_ARI)
2594 		return (PCIE_ARI_FUNCMAX);
2595 	else
2596 		return (PCI_FUNCMAX);
2597 }
2598 
2599 static void
2600 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
2601     int *func)
2602 {
2603 	struct pcib_softc *sc;
2604 
2605 	sc = device_get_softc(pcib);
2606 
2607 	*bus = PCI_RID2BUS(rid);
2608 	if (sc->flags & PCIB_ENABLE_ARI) {
2609 		*slot = PCIE_ARI_RID2SLOT(rid);
2610 		*func = PCIE_ARI_RID2FUNC(rid);
2611 	} else {
2612 		*slot = PCI_RID2SLOT(rid);
2613 		*func = PCI_RID2FUNC(rid);
2614 	}
2615 }
2616 
2617 /*
2618  * Since we are a child of a PCI bus, its parent must support the pcib interface.
2619  */
2620 static uint32_t
2621 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
2622 {
2623 #ifdef PCI_HP
2624 	struct pcib_softc *sc;
2625 
2626 	sc = device_get_softc(dev);
2627 	if (!pcib_present(sc)) {
2628 		switch (width) {
2629 		case 2:
2630 			return (0xffff);
2631 		case 1:
2632 			return (0xff);
2633 		default:
2634 			return (0xffffffff);
2635 		}
2636 	}
2637 #endif
2638 	pcib_xlate_ari(dev, b, &s, &f);
2639 	return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
2640 	    f, reg, width));
2641 }
2642 
2643 static void
2644 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
2645 {
2646 #ifdef PCI_HP
2647 	struct pcib_softc *sc;
2648 
2649 	sc = device_get_softc(dev);
2650 	if (!pcib_present(sc))
2651 		return;
2652 #endif
2653 	pcib_xlate_ari(dev, b, &s, &f);
2654 	PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
2655 	    reg, val, width);
2656 }
2657 
2658 /*
2659  * Route an interrupt across a PCI bridge.
2660  */
2661 int
2662 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
2663 {
2664     device_t	bus;
2665     int		parent_intpin;
2666     int		intnum;
2667 
2668     /*
2669      *
2670      * The PCI standard defines a swizzle of the child-side device/intpin to
2671      * the parent-side intpin as follows.
2672      *
2673      * device = device on child bus
2674      * child_intpin = intpin on child bus slot (0-3)
2675      * parent_intpin = intpin on parent bus slot (0-3)
2676      *
2677      * parent_intpin = (device + child_intpin) % 4
2678      */
2679     parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
2680 
2681     /*
2682      * Our parent is a PCI bus.  Its parent must export the pcib interface
2683      * which includes the ability to route interrupts.
2684      */
2685     bus = device_get_parent(pcib);
2686     intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
2687     if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
2688 	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
2689 	    pci_get_slot(dev), 'A' + pin - 1, intnum);
2690     }
2691     return(intnum);
2692 }
2693 
2694 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
2695 int
2696 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
2697 {
2698 	struct pcib_softc *sc = device_get_softc(pcib);
2699 	device_t bus;
2700 
2701 	if (sc->flags & PCIB_DISABLE_MSI)
2702 		return (ENXIO);
2703 	bus = device_get_parent(pcib);
2704 	return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
2705 	    irqs));
2706 }
2707 
2708 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
2709 int
2710 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
2711 {
2712 	device_t bus;
2713 
2714 	bus = device_get_parent(pcib);
2715 	return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
2716 }
2717 
2718 /* Pass request to alloc an MSI-X message up to the parent bridge. */
2719 int
2720 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
2721 {
2722 	struct pcib_softc *sc = device_get_softc(pcib);
2723 	device_t bus;
2724 
2725 	if (sc->flags & PCIB_DISABLE_MSIX)
2726 		return (ENXIO);
2727 	bus = device_get_parent(pcib);
2728 	return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
2729 }
2730 
2731 /* Pass request to release an MSI-X message up to the parent bridge. */
2732 int
2733 pcib_release_msix(device_t pcib, device_t dev, int irq)
2734 {
2735 	device_t bus;
2736 
2737 	bus = device_get_parent(pcib);
2738 	return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
2739 }
2740 
2741 /* Pass request to map MSI/MSI-X message up to parent bridge. */
2742 int
2743 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
2744     uint32_t *data)
2745 {
2746 	device_t bus;
2747 	int error;
2748 
2749 	bus = device_get_parent(pcib);
2750 	error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2751 	if (error)
2752 		return (error);
2753 
2754 	pci_ht_map_msi(pcib, *addr);
2755 	return (0);
2756 }
2757 
2758 /* Pass request for device power state up to parent bridge. */
2759 int
2760 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2761 {
2762 	device_t bus;
2763 
2764 	bus = device_get_parent(pcib);
2765 	return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2766 }
2767 
2768 static int
2769 pcib_ari_enabled(device_t pcib)
2770 {
2771 	struct pcib_softc *sc;
2772 
2773 	sc = device_get_softc(pcib);
2774 
2775 	return ((sc->flags & PCIB_ENABLE_ARI) != 0);
2776 }
2777 
2778 static int
2779 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type,
2780     uintptr_t *id)
2781 {
2782 	struct pcib_softc *sc;
2783 	device_t bus_dev;
2784 	uint8_t bus, slot, func;
2785 
2786 	if (type != PCI_ID_RID) {
2787 		bus_dev = device_get_parent(pcib);
2788 		return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id));
2789 	}
2790 
2791 	sc = device_get_softc(pcib);
2792 
2793 	if (sc->flags & PCIB_ENABLE_ARI) {
2794 		bus = pci_get_bus(dev);
2795 		func = pci_get_function(dev);
2796 
2797 		*id = (PCI_ARI_RID(bus, func));
2798 	} else {
2799 		bus = pci_get_bus(dev);
2800 		slot = pci_get_slot(dev);
2801 		func = pci_get_function(dev);
2802 
2803 		*id = (PCI_RID(bus, slot, func));
2804 	}
2805 
2806 	return (0);
2807 }
2808 
2809 /*
2810  * Check that the downstream port (pcib) and the endpoint device (dev) both
2811  * support ARI.  If so, enable it and return 0, otherwise return an error.
2812  */
2813 static int
2814 pcib_try_enable_ari(device_t pcib, device_t dev)
2815 {
2816 	struct pcib_softc *sc;
2817 	int error;
2818 	uint32_t cap2;
2819 	int ari_cap_off;
2820 	uint32_t ari_ver;
2821 	uint32_t pcie_pos;
2822 
2823 	sc = device_get_softc(pcib);
2824 
2825 	/*
2826 	 * ARI is controlled in a register in the PCIe capability structure.
2827 	 * If the downstream port does not have the PCIe capability structure
2828 	 * then it does not support ARI.
2829 	 */
2830 	error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2831 	if (error != 0)
2832 		return (ENODEV);
2833 
2834 	/* Check that the PCIe port advertises ARI support. */
2835 	cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2836 	if (!(cap2 & PCIEM_CAP2_ARI))
2837 		return (ENODEV);
2838 
2839 	/*
2840 	 * Check that the endpoint device advertises ARI support via the ARI
2841 	 * extended capability structure.
2842 	 */
2843 	error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2844 	if (error != 0)
2845 		return (ENODEV);
2846 
2847 	/*
2848 	 * Finally, check that the endpoint device supports the same version
2849 	 * of ARI that we do.
2850 	 */
2851 	ari_ver = pci_read_config(dev, ari_cap_off, 4);
2852 	if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2853 		if (bootverbose)
2854 			device_printf(pcib,
2855 			    "Unsupported version of ARI (%d) detected\n",
2856 			    PCI_EXTCAP_VER(ari_ver));
2857 
2858 		return (ENXIO);
2859 	}
2860 
2861 	pcib_enable_ari(sc, pcie_pos);
2862 
2863 	return (0);
2864 }
2865 
2866 int
2867 pcib_request_feature_allow(device_t pcib, device_t dev,
2868     enum pci_feature feature)
2869 {
2870 	/*
2871 	 * No host firmware we have to negotiate with, so we allow
2872 	 * every valid feature requested.
2873 	 */
2874 	switch (feature) {
2875 	case PCI_FEATURE_AER:
2876 	case PCI_FEATURE_HP:
2877 		break;
2878 	default:
2879 		return (EINVAL);
2880 	}
2881 
2882 	return (0);
2883 }
2884 
2885 int
2886 pcib_request_feature(device_t dev, enum pci_feature feature)
2887 {
2888 
2889 	/*
2890 	 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case
2891 	 * the firmware overrides the method of PCI-PCI bridges.
2892 	 */
2893 	return (PCIB_REQUEST_FEATURE(dev, dev, feature));
2894 }
2895 
2896 /*
2897  * Pass the request to use this PCI feature up the tree. Either there's a
2898  * firmware like ACPI that's using this feature that will approve (or deny) the
2899  * request to take it over, or the platform has no such firmware, in which case
2900  * the request will be approved. If the request is approved, the OS is expected
2901  * to make use of the feature or render it harmless.
2902  */
2903 static int
2904 pcib_request_feature_default(device_t pcib, device_t dev,
2905     enum pci_feature feature)
2906 {
2907 	device_t bus;
2908 
2909 	/*
2910 	 * Our parent is necessarily a pci bus. Its parent will either be
2911 	 * another pci bridge (which passes it up) or a host bridge that can
2912 	 * approve or reject the request.
2913 	 */
2914 	bus = device_get_parent(pcib);
2915 	return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
2916 }
2917 
2918 static int
2919 pcib_reset_child(device_t dev, device_t child, int flags)
2920 {
2921 	struct pci_devinfo *pdinfo;
2922 	int error;
2923 
2924 	error = 0;
2925 	if (dev == NULL || device_get_parent(child) != dev)
2926 		goto out;
2927 	error = ENXIO;
2928 	if (device_get_devclass(child) != devclass_find("pci"))
2929 		goto out;
2930 	pdinfo = device_get_ivars(dev);
2931 	if (pdinfo->cfg.pcie.pcie_location != 0 &&
2932 	    (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
2933 	    pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
2934 		error = bus_helper_reset_prepare(child, flags);
2935 		if (error == 0) {
2936 			error = pcie_link_reset(dev,
2937 			    pdinfo->cfg.pcie.pcie_location);
2938 			/* XXXKIB call _post even if error != 0 ? */
2939 			bus_helper_reset_post(child, flags);
2940 		}
2941 	}
2942 out:
2943 	return (error);
2944 }
2945