1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/pciio.h> 48 #include <sys/rman.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_private.h> 56 #include <dev/pci/pcib_private.h> 57 58 #include "pcib_if.h" 59 60 static int pcib_probe(device_t dev); 61 static int pcib_resume(device_t dev); 62 63 static bus_child_present_t pcib_child_present; 64 static bus_alloc_resource_t pcib_alloc_resource; 65 static bus_adjust_resource_t pcib_adjust_resource; 66 static bus_release_resource_t pcib_release_resource; 67 static bus_activate_resource_t pcib_activate_resource; 68 static bus_deactivate_resource_t pcib_deactivate_resource; 69 static bus_map_resource_t pcib_map_resource; 70 static bus_unmap_resource_t pcib_unmap_resource; 71 static int pcib_reset_child(device_t dev, device_t child, int flags); 72 73 static int pcib_power_for_sleep(device_t pcib, device_t dev, 74 int *pstate); 75 static int pcib_ari_get_id(device_t pcib, device_t dev, 76 enum pci_id_type type, uintptr_t *id); 77 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 78 u_int f, u_int reg, int width); 79 static void pcib_write_config(device_t dev, u_int b, u_int s, 80 u_int f, u_int reg, uint32_t val, int width); 81 static int pcib_ari_maxslots(device_t dev); 82 static int pcib_ari_maxfuncs(device_t dev); 83 static int pcib_try_enable_ari(device_t pcib, device_t dev); 84 static int pcib_ari_enabled(device_t pcib); 85 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 86 int *bus, int *slot, int *func); 87 #ifdef PCI_HP 88 static void pcib_pcie_ab_timeout(void *arg, int pending); 89 static void pcib_pcie_cc_timeout(void *arg, int pending); 90 static void pcib_pcie_dll_timeout(void *arg, int pending); 91 #endif 92 static int pcib_request_feature_default(device_t pcib, device_t dev, 93 enum pci_feature feature); 94 95 static device_method_t pcib_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pcib_probe), 98 DEVMETHOD(device_attach, pcib_attach), 99 DEVMETHOD(device_detach, pcib_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, bus_generic_suspend), 102 DEVMETHOD(device_resume, pcib_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_child_present, pcib_child_present), 106 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 107 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 108 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 109 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 110 DEVMETHOD(bus_release_resource, pcib_release_resource), 111 DEVMETHOD(bus_activate_resource, pcib_activate_resource), 112 DEVMETHOD(bus_deactivate_resource, pcib_deactivate_resource), 113 DEVMETHOD(bus_map_resource, pcib_map_resource), 114 DEVMETHOD(bus_unmap_resource, pcib_unmap_resource), 115 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 116 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 117 DEVMETHOD(bus_reset_child, pcib_reset_child), 118 119 /* pcib interface */ 120 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 121 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 122 DEVMETHOD(pcib_read_config, pcib_read_config), 123 DEVMETHOD(pcib_write_config, pcib_write_config), 124 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 125 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 126 DEVMETHOD(pcib_release_msi, pcib_release_msi), 127 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 128 DEVMETHOD(pcib_release_msix, pcib_release_msix), 129 DEVMETHOD(pcib_map_msi, pcib_map_msi), 130 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 131 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 132 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 133 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 134 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 135 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 136 137 DEVMETHOD_END 138 }; 139 140 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 141 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, NULL, NULL, BUS_PASS_BUS); 142 143 SYSCTL_DECL(_hw_pci); 144 145 static int pci_clear_pcib; 146 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 147 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 148 149 /* 150 * Get the corresponding window if this resource from a child device was 151 * sub-allocated from one of our window resource managers. 152 */ 153 static struct pcib_window * 154 pcib_get_resource_window(struct pcib_softc *sc, struct resource *r) 155 { 156 switch (rman_get_type(r)) { 157 case SYS_RES_IOPORT: 158 if (rman_is_region_manager(r, &sc->io.rman)) 159 return (&sc->io); 160 break; 161 case SYS_RES_MEMORY: 162 /* Prefetchable resources may live in either memory rman. */ 163 if (rman_get_flags(r) & RF_PREFETCHABLE && 164 rman_is_region_manager(r, &sc->pmem.rman)) 165 return (&sc->pmem); 166 if (rman_is_region_manager(r, &sc->mem.rman)) 167 return (&sc->mem); 168 break; 169 } 170 return (NULL); 171 } 172 173 /* 174 * Is a resource from a child device sub-allocated from one of our 175 * resource managers? 176 */ 177 static int 178 pcib_is_resource_managed(struct pcib_softc *sc, struct resource *r) 179 { 180 181 if (rman_get_type(r) == PCI_RES_BUS) 182 return (rman_is_region_manager(r, &sc->bus.rman)); 183 return (pcib_get_resource_window(sc, r) != NULL); 184 } 185 186 static int 187 pcib_is_window_open(struct pcib_window *pw) 188 { 189 190 return (pw->valid && pw->base < pw->limit); 191 } 192 193 /* 194 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 195 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 196 * when allocating the resource windows and rely on the PCI bus driver 197 * to do this for us. 198 */ 199 static void 200 pcib_activate_window(struct pcib_softc *sc, int type) 201 { 202 203 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 204 } 205 206 static void 207 pcib_write_windows(struct pcib_softc *sc, int mask) 208 { 209 device_t dev; 210 uint32_t val; 211 212 dev = sc->dev; 213 if (sc->io.valid && mask & WIN_IO) { 214 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 215 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 216 pci_write_config(dev, PCIR_IOBASEH_1, 217 sc->io.base >> 16, 2); 218 pci_write_config(dev, PCIR_IOLIMITH_1, 219 sc->io.limit >> 16, 2); 220 } 221 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 222 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 223 } 224 225 if (mask & WIN_MEM) { 226 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 227 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 228 } 229 230 if (sc->pmem.valid && mask & WIN_PMEM) { 231 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 232 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 233 pci_write_config(dev, PCIR_PMBASEH_1, 234 sc->pmem.base >> 32, 4); 235 pci_write_config(dev, PCIR_PMLIMITH_1, 236 sc->pmem.limit >> 32, 4); 237 } 238 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 239 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 240 } 241 } 242 243 /* 244 * This is used to reject I/O port allocations that conflict with an 245 * ISA alias range. 246 */ 247 static int 248 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 249 rman_res_t count) 250 { 251 rman_res_t next_alias; 252 253 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 254 return (0); 255 256 /* Only check fixed ranges for overlap. */ 257 if (start + count - 1 != end) 258 return (0); 259 260 /* ISA aliases are only in the lower 64KB of I/O space. */ 261 if (start >= 65536) 262 return (0); 263 264 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 265 if (start < 0x100) 266 goto alias; 267 268 /* 269 * If the start address is an alias, the range is an alias. 270 * Otherwise, compute the start of the next alias range and 271 * check if it is before the end of the candidate range. 272 */ 273 if ((start & 0x300) != 0) 274 goto alias; 275 next_alias = (start & ~0x3fful) | 0x100; 276 if (next_alias <= end) 277 goto alias; 278 return (0); 279 280 alias: 281 if (bootverbose) 282 device_printf(sc->dev, 283 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 284 end); 285 return (1); 286 } 287 288 static void 289 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 290 int count) 291 { 292 struct resource **newarray; 293 int error, i; 294 295 newarray = malloc(sizeof(struct resource *) * (w->count + count), 296 M_DEVBUF, M_WAITOK); 297 if (w->res != NULL) 298 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 299 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 300 free(w->res, M_DEVBUF); 301 w->res = newarray; 302 w->count += count; 303 304 for (i = 0; i < count; i++) { 305 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 306 rman_get_end(res[i])); 307 if (error) 308 panic("Failed to add resource to rman"); 309 } 310 } 311 312 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 313 314 static void 315 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 316 void *arg) 317 { 318 rman_res_t next_end; 319 320 /* 321 * If start is within an ISA alias range, move up to the start 322 * of the next non-alias range. As a special case, addresses 323 * in the range 0x000 - 0x0ff should also be skipped since 324 * those are used for various system I/O devices in ISA 325 * systems. 326 */ 327 if (start <= 65535) { 328 if (start < 0x100 || (start & 0x300) != 0) { 329 start &= ~0x3ff; 330 start += 0x400; 331 } 332 } 333 334 /* ISA aliases are only in the lower 64KB of I/O space. */ 335 while (start <= MIN(end, 65535)) { 336 next_end = MIN(start | 0xff, end); 337 cb(start, next_end, arg); 338 start += 0x400; 339 } 340 341 if (start <= end) 342 cb(start, end, arg); 343 } 344 345 static void 346 count_ranges(rman_res_t start, rman_res_t end, void *arg) 347 { 348 int *countp; 349 350 countp = arg; 351 (*countp)++; 352 } 353 354 struct alloc_state { 355 struct resource **res; 356 struct pcib_softc *sc; 357 int count, error; 358 }; 359 360 static void 361 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 362 { 363 struct alloc_state *as; 364 struct pcib_window *w; 365 int rid; 366 367 as = arg; 368 if (as->error != 0) 369 return; 370 371 w = &as->sc->io; 372 rid = w->reg; 373 if (bootverbose) 374 device_printf(as->sc->dev, 375 "allocating non-ISA range %#jx-%#jx\n", start, end); 376 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 377 &rid, start, end, end - start + 1, RF_ACTIVE | RF_UNMAPPED); 378 if (as->res[as->count] == NULL) 379 as->error = ENXIO; 380 else 381 as->count++; 382 } 383 384 static int 385 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 386 { 387 struct alloc_state as; 388 int i, new_count; 389 390 /* First, see how many ranges we need. */ 391 new_count = 0; 392 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 393 394 /* Second, allocate the ranges. */ 395 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 396 M_WAITOK); 397 as.sc = sc; 398 as.count = 0; 399 as.error = 0; 400 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 401 if (as.error != 0) { 402 for (i = 0; i < as.count; i++) 403 bus_release_resource(sc->dev, SYS_RES_IOPORT, 404 sc->io.reg, as.res[i]); 405 free(as.res, M_DEVBUF); 406 return (as.error); 407 } 408 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 409 410 /* Third, add the ranges to the window. */ 411 pcib_add_window_resources(&sc->io, as.res, as.count); 412 free(as.res, M_DEVBUF); 413 return (0); 414 } 415 416 static void 417 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 418 int flags, pci_addr_t max_address) 419 { 420 struct resource *res; 421 char buf[64]; 422 int error, rid; 423 424 if (max_address != (rman_res_t)max_address) 425 max_address = ~0; 426 w->rman.rm_start = 0; 427 w->rman.rm_end = max_address; 428 w->rman.rm_type = RMAN_ARRAY; 429 snprintf(buf, sizeof(buf), "%s %s window", 430 device_get_nameunit(sc->dev), w->name); 431 w->rman.rm_descr = strdup(buf, M_DEVBUF); 432 error = rman_init(&w->rman); 433 if (error) 434 panic("Failed to initialize %s %s rman", 435 device_get_nameunit(sc->dev), w->name); 436 437 if (!pcib_is_window_open(w)) 438 return; 439 440 /* 441 * Assume that a window where both the base and limit read as 442 * zero is not really open, or at least not assigned a valid 443 * range by the firmware. This can happen if a bridge device 444 * is never initialized by firmware, or if a platform driver 445 * resets the bridge. 446 * 447 * If devices behind this bridge have firmware-assigned 448 * resources in this range then the window will be reallocated 449 * on-demand. 450 */ 451 if (w->base == 0 && w->limit == ((pci_addr_t)1 << w->step) - 1) { 452 w->base = max_address; 453 w->limit = 0; 454 pcib_write_windows(sc, w->mask); 455 return; 456 } 457 458 if (w->base > max_address || w->limit > max_address) { 459 device_printf(sc->dev, 460 "initial %s window has too many bits, ignoring\n", w->name); 461 return; 462 } 463 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 464 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 465 else { 466 rid = w->reg; 467 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 468 w->limit - w->base + 1, flags | RF_ACTIVE | RF_UNMAPPED); 469 if (res != NULL) 470 pcib_add_window_resources(w, &res, 1); 471 } 472 if (w->res == NULL) { 473 device_printf(sc->dev, 474 "failed to allocate initial %s window: %#jx-%#jx\n", 475 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 476 w->base = max_address; 477 w->limit = 0; 478 pcib_write_windows(sc, w->mask); 479 return; 480 } 481 pcib_activate_window(sc, type); 482 } 483 484 /* 485 * Initialize I/O windows. 486 */ 487 static void 488 pcib_probe_windows(struct pcib_softc *sc) 489 { 490 pci_addr_t max; 491 device_t dev; 492 uint32_t val; 493 494 dev = sc->dev; 495 496 if (pci_clear_pcib) { 497 pcib_bridge_init(dev); 498 } 499 500 /* Determine if the I/O port window is implemented. */ 501 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 502 if (val == 0) { 503 /* 504 * If 'val' is zero, then only 16-bits of I/O space 505 * are supported. 506 */ 507 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 508 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 509 sc->io.valid = 1; 510 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 511 } 512 } else 513 sc->io.valid = 1; 514 515 /* Read the existing I/O port window. */ 516 if (sc->io.valid) { 517 sc->io.reg = PCIR_IOBASEL_1; 518 sc->io.step = 12; 519 sc->io.mask = WIN_IO; 520 sc->io.name = "I/O port"; 521 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 522 sc->io.base = PCI_PPBIOBASE( 523 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 524 sc->io.limit = PCI_PPBIOLIMIT( 525 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 526 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 527 max = 0xffffffff; 528 } else { 529 sc->io.base = PCI_PPBIOBASE(0, val); 530 sc->io.limit = PCI_PPBIOLIMIT(0, 531 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 532 max = 0xffff; 533 } 534 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 535 } 536 537 /* Read the existing memory window. */ 538 sc->mem.valid = 1; 539 sc->mem.reg = PCIR_MEMBASE_1; 540 sc->mem.step = 20; 541 sc->mem.mask = WIN_MEM; 542 sc->mem.name = "memory"; 543 sc->mem.base = PCI_PPBMEMBASE(0, 544 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 545 sc->mem.limit = PCI_PPBMEMLIMIT(0, 546 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 547 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 548 549 /* Determine if the prefetchable memory window is implemented. */ 550 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 551 if (val == 0) { 552 /* 553 * If 'val' is zero, then only 32-bits of memory space 554 * are supported. 555 */ 556 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 557 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 558 sc->pmem.valid = 1; 559 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 560 } 561 } else 562 sc->pmem.valid = 1; 563 564 /* Read the existing prefetchable memory window. */ 565 if (sc->pmem.valid) { 566 sc->pmem.reg = PCIR_PMBASEL_1; 567 sc->pmem.step = 20; 568 sc->pmem.mask = WIN_PMEM; 569 sc->pmem.name = "prefetch"; 570 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 571 sc->pmem.base = PCI_PPBMEMBASE( 572 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 573 sc->pmem.limit = PCI_PPBMEMLIMIT( 574 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 575 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 576 max = 0xffffffffffffffff; 577 } else { 578 sc->pmem.base = PCI_PPBMEMBASE(0, val); 579 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 580 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 581 max = 0xffffffff; 582 } 583 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 584 RF_PREFETCHABLE, max); 585 } 586 } 587 588 static void 589 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 590 { 591 device_t dev; 592 int error, i; 593 594 if (!w->valid) 595 return; 596 597 dev = sc->dev; 598 error = rman_fini(&w->rman); 599 if (error) { 600 device_printf(dev, "failed to release %s rman\n", w->name); 601 return; 602 } 603 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 604 605 for (i = 0; i < w->count; i++) { 606 error = bus_free_resource(dev, type, w->res[i]); 607 if (error) 608 device_printf(dev, 609 "failed to release %s resource: %d\n", w->name, 610 error); 611 } 612 free(w->res, M_DEVBUF); 613 } 614 615 static void 616 pcib_free_windows(struct pcib_softc *sc) 617 { 618 619 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 620 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 621 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 622 } 623 624 /* 625 * Allocate a suitable secondary bus for this bridge if needed and 626 * initialize the resource manager for the secondary bus range. Note 627 * that the minimum count is a desired value and this may allocate a 628 * smaller range. 629 */ 630 void 631 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 632 { 633 char buf[64]; 634 int error, rid, sec_reg; 635 636 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 637 case PCIM_HDRTYPE_BRIDGE: 638 sec_reg = PCIR_SECBUS_1; 639 bus->sub_reg = PCIR_SUBBUS_1; 640 break; 641 case PCIM_HDRTYPE_CARDBUS: 642 sec_reg = PCIR_SECBUS_2; 643 bus->sub_reg = PCIR_SUBBUS_2; 644 break; 645 default: 646 panic("not a PCI bridge"); 647 } 648 bus->sec = pci_read_config(dev, sec_reg, 1); 649 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 650 bus->dev = dev; 651 bus->rman.rm_start = 0; 652 bus->rman.rm_end = PCI_BUSMAX; 653 bus->rman.rm_type = RMAN_ARRAY; 654 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 655 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 656 error = rman_init(&bus->rman); 657 if (error) 658 panic("Failed to initialize %s bus number rman", 659 device_get_nameunit(dev)); 660 661 /* 662 * Allocate a bus range. This will return an existing bus range 663 * if one exists, or a new bus range if one does not. 664 */ 665 rid = 0; 666 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 667 min_count, RF_ACTIVE); 668 if (bus->res == NULL) { 669 /* 670 * Fall back to just allocating a range of a single bus 671 * number. 672 */ 673 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 674 1, RF_ACTIVE); 675 } else if (rman_get_size(bus->res) < min_count) 676 /* 677 * Attempt to grow the existing range to satisfy the 678 * minimum desired count. 679 */ 680 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 681 rman_get_start(bus->res), rman_get_start(bus->res) + 682 min_count - 1); 683 684 /* 685 * Add the initial resource to the rman. 686 */ 687 if (bus->res != NULL) { 688 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 689 rman_get_end(bus->res)); 690 if (error) 691 panic("Failed to add resource to rman"); 692 bus->sec = rman_get_start(bus->res); 693 bus->sub = rman_get_end(bus->res); 694 } 695 } 696 697 void 698 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 699 { 700 int error; 701 702 error = rman_fini(&bus->rman); 703 if (error) { 704 device_printf(dev, "failed to release bus number rman\n"); 705 return; 706 } 707 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 708 709 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 710 if (error) 711 device_printf(dev, 712 "failed to release bus numbers resource: %d\n", error); 713 } 714 715 static struct resource * 716 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int rid, 717 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 718 { 719 struct resource *res; 720 721 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 722 child); 723 if (res == NULL) 724 return (NULL); 725 726 if (bootverbose) 727 device_printf(bus->dev, 728 "allocated bus range (%ju-%ju) for rid %d of %s\n", 729 rman_get_start(res), rman_get_end(res), rid, 730 pcib_child_name(child)); 731 rman_set_rid(res, rid); 732 rman_set_type(res, PCI_RES_BUS); 733 return (res); 734 } 735 736 /* 737 * Attempt to grow the secondary bus range. This is much simpler than 738 * for I/O windows as the range can only be grown by increasing 739 * subbus. 740 */ 741 static int 742 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 743 { 744 rman_res_t old_end; 745 int error; 746 747 old_end = rman_get_end(bus->res); 748 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 749 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 750 rman_get_start(bus->res), new_end); 751 if (error) 752 return (error); 753 if (bootverbose) 754 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 755 rman_get_start(bus->res), rman_get_end(bus->res)); 756 error = rman_manage_region(&bus->rman, old_end + 1, 757 rman_get_end(bus->res)); 758 if (error) 759 panic("Failed to add resource to rman"); 760 bus->sub = rman_get_end(bus->res); 761 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 762 return (0); 763 } 764 765 struct resource * 766 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int rid, 767 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 768 { 769 struct resource *res; 770 rman_res_t start_free, end_free, new_end; 771 772 /* 773 * First, see if the request can be satisified by the existing 774 * bus range. 775 */ 776 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 777 if (res != NULL) 778 return (res); 779 780 /* 781 * Figure out a range to grow the bus range. First, find the 782 * first bus number after the last allocated bus in the rman and 783 * enforce that as a minimum starting point for the range. 784 */ 785 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 786 end_free != bus->sub) 787 start_free = bus->sub + 1; 788 if (start_free < start) 789 start_free = start; 790 new_end = start_free + count - 1; 791 792 /* 793 * See if this new range would satisfy the request if it 794 * succeeds. 795 */ 796 if (new_end > end) 797 return (NULL); 798 799 /* Finally, attempt to grow the existing resource. */ 800 if (bootverbose) { 801 device_printf(bus->dev, 802 "attempting to grow bus range for %ju buses\n", count); 803 printf("\tback candidate range: %ju-%ju\n", start_free, 804 new_end); 805 } 806 if (pcib_grow_subbus(bus, new_end) == 0) 807 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 808 flags)); 809 return (NULL); 810 } 811 812 #ifdef PCI_HP 813 /* 814 * PCI-express HotPlug support. 815 */ 816 static int pci_enable_pcie_hp = 1; 817 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 818 &pci_enable_pcie_hp, 0, 819 "Enable support for native PCI-express HotPlug."); 820 821 static sbintime_t pcie_hp_detach_timeout = 5 * SBT_1S; 822 SYSCTL_SBINTIME_MSEC(_hw_pci, OID_AUTO, pcie_hp_detach_timeout, CTLFLAG_RWTUN, 823 &pcie_hp_detach_timeout, 824 "Attention Button delay for PCI-express Eject."); 825 826 static void 827 pcib_probe_hotplug(struct pcib_softc *sc) 828 { 829 device_t dev; 830 uint32_t link_cap; 831 uint16_t link_sta, slot_sta; 832 833 if (!pci_enable_pcie_hp) 834 return; 835 836 dev = sc->dev; 837 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 838 return; 839 840 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 841 return; 842 843 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 844 845 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 846 return; 847 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 848 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 849 return; 850 851 /* 852 * Some devices report that they have an MRL when they actually 853 * do not. Since they always report that the MRL is open, child 854 * devices would be ignored. Try to detect these devices and 855 * ignore their claim of HotPlug support. 856 * 857 * If there is an open MRL but the Data Link Layer is active, 858 * the MRL is not real. 859 */ 860 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 861 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 862 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 863 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 864 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 865 return; 866 } 867 } 868 869 /* 870 * Now that we're sure we want to do hot plug, ask the 871 * firmware, if any, if that's OK. 872 */ 873 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 874 if (bootverbose) 875 device_printf(dev, "Unable to activate hot plug feature.\n"); 876 return; 877 } 878 879 sc->flags |= PCIB_HOTPLUG; 880 } 881 882 /* 883 * Send a HotPlug command to the slot control register. If this slot 884 * uses command completion interrupts and a previous command is still 885 * in progress, then the command is dropped. Once the previous 886 * command completes or times out, pcib_pcie_hotplug_update() will be 887 * invoked to post a new command based on the slot's state at that 888 * time. 889 */ 890 static void 891 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 892 { 893 device_t dev; 894 uint16_t ctl, new; 895 896 dev = sc->dev; 897 898 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 899 return; 900 901 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 902 new = (ctl & ~mask) | val; 903 if (new == ctl) 904 return; 905 if (bootverbose) 906 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 907 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 908 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 909 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 910 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 911 if (!cold) 912 taskqueue_enqueue_timeout(taskqueue_bus, 913 &sc->pcie_cc_task, hz); 914 } 915 } 916 917 static void 918 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 919 { 920 device_t dev; 921 922 dev = sc->dev; 923 924 if (bootverbose) 925 device_printf(dev, "Command Completed\n"); 926 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 927 return; 928 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, NULL); 929 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 930 wakeup(sc); 931 } 932 933 /* 934 * Returns true if a card is fully inserted from the user's 935 * perspective. It may not yet be ready for access, but the driver 936 * can now start enabling access if necessary. 937 */ 938 static bool 939 pcib_hotplug_inserted(struct pcib_softc *sc) 940 { 941 942 /* Pretend the card isn't present if a detach is forced. */ 943 if (sc->flags & PCIB_DETACHING) 944 return (false); 945 946 /* Card must be present in the slot. */ 947 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 948 return (false); 949 950 /* A power fault implicitly turns off power to the slot. */ 951 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP && 952 sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 953 return (false); 954 955 /* If the MRL is disengaged, the slot is powered off. */ 956 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 957 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 958 return (false); 959 960 return (true); 961 } 962 963 /* 964 * Returns -1 if the card is fully inserted, powered, and ready for 965 * access. Otherwise, returns 0. 966 */ 967 static int 968 pcib_hotplug_present(struct pcib_softc *sc) 969 { 970 971 /* Card must be inserted. */ 972 if (!pcib_hotplug_inserted(sc)) 973 return (0); 974 975 /* Require the Data Link Layer to be active. */ 976 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 977 return (0); 978 979 return (-1); 980 } 981 982 static int pci_enable_pcie_ei = 0; 983 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_ei, CTLFLAG_RWTUN, 984 &pci_enable_pcie_ei, 0, 985 "Enable support for PCI-express Electromechanical Interlock."); 986 987 static void 988 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 989 bool schedule_task) 990 { 991 bool card_inserted, ei_engaged; 992 993 /* Clear DETACHING if Presence Detect has cleared. */ 994 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 995 PCIEM_SLOT_STA_PDC) 996 sc->flags &= ~PCIB_DETACHING; 997 998 card_inserted = pcib_hotplug_inserted(sc); 999 1000 /* Turn the power indicator on if a card is inserted. */ 1001 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1002 mask |= PCIEM_SLOT_CTL_PIC; 1003 if (card_inserted) 1004 val |= PCIEM_SLOT_CTL_PI_ON; 1005 else if (sc->flags & PCIB_DETACH_PENDING) 1006 val |= PCIEM_SLOT_CTL_PI_BLINK; 1007 else 1008 val |= PCIEM_SLOT_CTL_PI_OFF; 1009 } 1010 1011 /* Turn the power on via the Power Controller if a card is inserted. */ 1012 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1013 mask |= PCIEM_SLOT_CTL_PCC; 1014 if (card_inserted) 1015 val |= PCIEM_SLOT_CTL_PC_ON; 1016 else 1017 val |= PCIEM_SLOT_CTL_PC_OFF; 1018 } 1019 1020 /* 1021 * If a card is inserted, enable the Electromechanical 1022 * Interlock. If a card is not inserted (or we are in the 1023 * process of detaching), disable the Electromechanical 1024 * Interlock. 1025 */ 1026 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) && 1027 pci_enable_pcie_ei) { 1028 mask |= PCIEM_SLOT_CTL_EIC; 1029 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1030 if (card_inserted != ei_engaged) 1031 val |= PCIEM_SLOT_CTL_EIC; 1032 } 1033 1034 /* 1035 * Start a timer to see if the Data Link Layer times out. 1036 * Note that we only start the timer if Presence Detect or MRL Sensor 1037 * changed on this interrupt. Stop any scheduled timer if 1038 * the Data Link Layer is active. 1039 */ 1040 if (card_inserted && 1041 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1042 sc->pcie_slot_sta & 1043 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1044 if (cold) 1045 device_printf(sc->dev, 1046 "Data Link Layer inactive\n"); 1047 else 1048 taskqueue_enqueue_timeout(taskqueue_bus, 1049 &sc->pcie_dll_task, hz); 1050 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1051 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_dll_task, 1052 NULL); 1053 1054 pcib_pcie_hotplug_command(sc, val, mask); 1055 1056 /* 1057 * During attach the child "pci" device is added synchronously; 1058 * otherwise, the task is scheduled to manage the child 1059 * device. 1060 */ 1061 if (schedule_task && 1062 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1063 taskqueue_enqueue(taskqueue_bus, &sc->pcie_hp_task); 1064 } 1065 1066 static void 1067 pcib_pcie_intr_hotplug(void *arg) 1068 { 1069 struct pcib_softc *sc; 1070 device_t dev; 1071 uint16_t old_slot_sta; 1072 1073 sc = arg; 1074 dev = sc->dev; 1075 PCIB_HP_LOCK(sc); 1076 old_slot_sta = sc->pcie_slot_sta; 1077 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1078 1079 /* Clear the events just reported. */ 1080 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1081 1082 if (bootverbose) 1083 device_printf(dev, "HotPlug interrupt: %#x\n", 1084 sc->pcie_slot_sta); 1085 1086 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1087 if (sc->flags & PCIB_DETACH_PENDING) { 1088 device_printf(dev, 1089 "Attention Button Pressed: Detach Cancelled\n"); 1090 sc->flags &= ~PCIB_DETACH_PENDING; 1091 taskqueue_cancel_timeout(taskqueue_bus, 1092 &sc->pcie_ab_task, NULL); 1093 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) { 1094 /* Only initiate detach sequence if device present. */ 1095 if (pcie_hp_detach_timeout != 0) { 1096 device_printf(dev, 1097 "Attention Button Pressed: Detaching in %ld ms\n", 1098 (long)(pcie_hp_detach_timeout / SBT_1MS)); 1099 sc->flags |= PCIB_DETACH_PENDING; 1100 taskqueue_enqueue_timeout_sbt(taskqueue_bus, 1101 &sc->pcie_ab_task, pcie_hp_detach_timeout, 1102 SBT_1S, 0); 1103 } else { 1104 sc->flags |= PCIB_DETACHING; 1105 } 1106 } 1107 } 1108 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1109 device_printf(dev, "Power Fault Detected\n"); 1110 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1111 device_printf(dev, "MRL Sensor Changed to %s\n", 1112 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1113 "closed"); 1114 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1115 device_printf(dev, "Presence Detect Changed to %s\n", 1116 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1117 "empty"); 1118 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1119 pcib_pcie_hotplug_command_completed(sc); 1120 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1121 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1122 if (bootverbose) 1123 device_printf(dev, 1124 "Data Link Layer State Changed to %s\n", 1125 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1126 "active" : "inactive"); 1127 } 1128 1129 pcib_pcie_hotplug_update(sc, 0, 0, true); 1130 PCIB_HP_UNLOCK(sc); 1131 } 1132 1133 static void 1134 pcib_pcie_hotplug_task(void *context, int pending) 1135 { 1136 struct pcib_softc *sc; 1137 device_t dev; 1138 1139 sc = context; 1140 PCIB_HP_LOCK(sc); 1141 dev = sc->dev; 1142 if (pcib_hotplug_present(sc) != 0) { 1143 if (sc->child == NULL) { 1144 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1145 bus_attach_children(dev); 1146 } 1147 } else { 1148 if (sc->child != NULL) { 1149 if (device_delete_child(dev, sc->child) == 0) 1150 sc->child = NULL; 1151 } 1152 } 1153 PCIB_HP_UNLOCK(sc); 1154 } 1155 1156 static void 1157 pcib_pcie_ab_timeout(void *arg, int pending) 1158 { 1159 struct pcib_softc *sc = arg; 1160 1161 PCIB_HP_LOCK(sc); 1162 if (sc->flags & PCIB_DETACH_PENDING) { 1163 sc->flags |= PCIB_DETACHING; 1164 sc->flags &= ~PCIB_DETACH_PENDING; 1165 pcib_pcie_hotplug_update(sc, 0, 0, true); 1166 } 1167 PCIB_HP_UNLOCK(sc); 1168 } 1169 1170 static void 1171 pcib_pcie_cc_timeout(void *arg, int pending) 1172 { 1173 struct pcib_softc *sc = arg; 1174 device_t dev = sc->dev; 1175 uint16_t sta; 1176 1177 PCIB_HP_LOCK(sc); 1178 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1179 if (!(sta & PCIEM_SLOT_STA_CC)) { 1180 device_printf(dev, "HotPlug Command Timed Out\n"); 1181 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1182 } else { 1183 device_printf(dev, 1184 "Missed HotPlug interrupt waiting for Command Completion\n"); 1185 pcib_pcie_intr_hotplug(sc); 1186 } 1187 PCIB_HP_UNLOCK(sc); 1188 } 1189 1190 static void 1191 pcib_pcie_dll_timeout(void *arg, int pending) 1192 { 1193 struct pcib_softc *sc = arg; 1194 device_t dev = sc->dev; 1195 uint16_t sta; 1196 1197 PCIB_HP_LOCK(sc); 1198 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1199 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1200 device_printf(dev, 1201 "Timed out waiting for Data Link Layer Active\n"); 1202 sc->flags |= PCIB_DETACHING; 1203 pcib_pcie_hotplug_update(sc, 0, 0, true); 1204 } else if (sta != sc->pcie_link_sta) { 1205 device_printf(dev, 1206 "Missed HotPlug interrupt waiting for DLL Active\n"); 1207 pcib_pcie_intr_hotplug(sc); 1208 } 1209 PCIB_HP_UNLOCK(sc); 1210 } 1211 1212 static int 1213 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1214 { 1215 device_t dev; 1216 int count, error, mem_rid, rid; 1217 1218 rid = -1; 1219 dev = sc->dev; 1220 1221 /* 1222 * For simplicity, only use MSI-X if there is a single message. 1223 * To support a device with multiple messages we would have to 1224 * use remap intr if the MSI number is not 0. 1225 */ 1226 count = pci_msix_count(dev); 1227 if (count == 1) { 1228 mem_rid = pci_msix_table_bar(dev); 1229 sc->pcie_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1230 &mem_rid, RF_ACTIVE); 1231 if (sc->pcie_mem == NULL) { 1232 device_printf(dev, 1233 "Failed to allocate BAR for MSI-X table\n"); 1234 } else { 1235 error = pci_alloc_msix(dev, &count); 1236 if (error == 0) 1237 rid = 1; 1238 } 1239 } 1240 1241 if (rid < 0 && pci_msi_count(dev) > 0) { 1242 count = 1; 1243 error = pci_alloc_msi(dev, &count); 1244 if (error == 0) 1245 rid = 1; 1246 } 1247 1248 if (rid < 0) 1249 rid = 0; 1250 1251 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1252 RF_ACTIVE | RF_SHAREABLE); 1253 if (sc->pcie_irq == NULL) { 1254 device_printf(dev, 1255 "Failed to allocate interrupt for PCI-e events\n"); 1256 if (rid > 0) 1257 pci_release_msi(dev); 1258 return (ENXIO); 1259 } 1260 1261 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE, 1262 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1263 if (error) { 1264 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1265 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1266 if (rid > 0) 1267 pci_release_msi(dev); 1268 return (error); 1269 } 1270 return (0); 1271 } 1272 1273 static int 1274 pcib_release_pcie_irq(struct pcib_softc *sc) 1275 { 1276 device_t dev; 1277 int error; 1278 1279 dev = sc->dev; 1280 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1281 if (error) 1282 return (error); 1283 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1284 if (error) 1285 return (error); 1286 error = pci_release_msi(dev); 1287 if (error) 1288 return (error); 1289 if (sc->pcie_mem != NULL) 1290 error = bus_free_resource(dev, SYS_RES_MEMORY, sc->pcie_mem); 1291 return (error); 1292 } 1293 1294 static void 1295 pcib_setup_hotplug(struct pcib_softc *sc) 1296 { 1297 device_t dev; 1298 uint16_t mask, val; 1299 1300 dev = sc->dev; 1301 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1302 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_ab_task, 0, 1303 pcib_pcie_ab_timeout, sc); 1304 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_cc_task, 0, 1305 pcib_pcie_cc_timeout, sc); 1306 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_dll_task, 0, 1307 pcib_pcie_dll_timeout, sc); 1308 sc->pcie_hp_lock = bus_topo_mtx(); 1309 1310 /* Allocate IRQ. */ 1311 if (pcib_alloc_pcie_irq(sc) != 0) 1312 return; 1313 1314 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1315 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1316 1317 /* Clear any events previously pending. */ 1318 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1319 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1320 1321 /* Enable HotPlug events. */ 1322 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1323 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1324 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1325 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1326 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1327 val |= PCIEM_SLOT_CTL_ABPE; 1328 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1329 val |= PCIEM_SLOT_CTL_PFDE; 1330 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1331 val |= PCIEM_SLOT_CTL_MRLSCE; 1332 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1333 val |= PCIEM_SLOT_CTL_CCIE; 1334 1335 /* Turn the attention indicator off. */ 1336 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1337 mask |= PCIEM_SLOT_CTL_AIC; 1338 val |= PCIEM_SLOT_CTL_AI_OFF; 1339 } 1340 1341 pcib_pcie_hotplug_update(sc, val, mask, false); 1342 } 1343 1344 static int 1345 pcib_detach_hotplug(struct pcib_softc *sc) 1346 { 1347 uint16_t mask, val; 1348 int error; 1349 1350 /* Disable the card in the slot and force it to detach. */ 1351 if (sc->flags & PCIB_DETACH_PENDING) { 1352 sc->flags &= ~PCIB_DETACH_PENDING; 1353 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_ab_task, 1354 NULL); 1355 } 1356 sc->flags |= PCIB_DETACHING; 1357 1358 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1359 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, 1360 NULL); 1361 tsleep(sc, 0, "hpcmd", hz); 1362 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1363 } 1364 1365 /* Disable HotPlug events. */ 1366 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1367 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1368 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1369 val = 0; 1370 1371 /* Turn the attention indicator off. */ 1372 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1373 mask |= PCIEM_SLOT_CTL_AIC; 1374 val |= PCIEM_SLOT_CTL_AI_OFF; 1375 } 1376 1377 pcib_pcie_hotplug_update(sc, val, mask, false); 1378 1379 error = pcib_release_pcie_irq(sc); 1380 if (error) 1381 return (error); 1382 taskqueue_drain(taskqueue_bus, &sc->pcie_hp_task); 1383 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_ab_task); 1384 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_cc_task); 1385 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_dll_task); 1386 return (0); 1387 } 1388 #endif 1389 1390 /* 1391 * Restore previous bridge configuration. 1392 */ 1393 static void 1394 pcib_cfg_restore(struct pcib_softc *sc) 1395 { 1396 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1397 } 1398 1399 /* 1400 * Generic device interface 1401 */ 1402 static int 1403 pcib_probe(device_t dev) 1404 { 1405 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1406 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1407 device_set_desc(dev, "PCI-PCI bridge"); 1408 return(-10000); 1409 } 1410 return(ENXIO); 1411 } 1412 1413 void 1414 pcib_attach_common(device_t dev) 1415 { 1416 struct pcib_softc *sc; 1417 struct sysctl_ctx_list *sctx; 1418 struct sysctl_oid *soid; 1419 int comma; 1420 1421 sc = device_get_softc(dev); 1422 sc->dev = dev; 1423 1424 /* 1425 * Get current bridge configuration. 1426 */ 1427 sc->domain = pci_get_domain(dev); 1428 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1429 1430 /* 1431 * The primary bus register should always be the bus of the 1432 * parent. 1433 */ 1434 sc->pribus = pci_get_bus(dev); 1435 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1436 1437 /* 1438 * Setup sysctl reporting nodes 1439 */ 1440 sctx = device_get_sysctl_ctx(dev); 1441 soid = device_get_sysctl_tree(dev); 1442 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1443 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1444 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1445 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1446 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1447 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1448 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1449 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1450 1451 /* 1452 * Quirk handling. 1453 */ 1454 switch (pci_get_devid(dev)) { 1455 /* 1456 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1457 * and it is a subtractive bridge. However, the ProgIf is wrong 1458 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1459 * happen. There are also Toshiba and Cavium ThunderX bridges 1460 * that behave this way. 1461 */ 1462 case 0xa002177d: /* Cavium ThunderX */ 1463 case 0x124b8086: /* Intel 82380FB Mobile */ 1464 case 0x060513d7: /* Toshiba ???? */ 1465 sc->flags |= PCIB_SUBTRACTIVE; 1466 break; 1467 } 1468 1469 if (pci_msi_device_blacklisted(dev)) 1470 sc->flags |= PCIB_DISABLE_MSI; 1471 1472 if (pci_msix_device_blacklisted(dev)) 1473 sc->flags |= PCIB_DISABLE_MSIX; 1474 1475 /* 1476 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1477 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1478 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1479 * This means they act as if they were subtractively decoding 1480 * bridges and pass all transactions. Mark them and real ProgIf 1 1481 * parts as subtractive. 1482 */ 1483 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1484 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1485 sc->flags |= PCIB_SUBTRACTIVE; 1486 1487 #ifdef PCI_HP 1488 pcib_probe_hotplug(sc); 1489 #endif 1490 pcib_setup_secbus(dev, &sc->bus, 1); 1491 pcib_probe_windows(sc); 1492 #ifdef PCI_HP 1493 if (sc->flags & PCIB_HOTPLUG) 1494 pcib_setup_hotplug(sc); 1495 #endif 1496 if (bootverbose) { 1497 device_printf(dev, " domain %d\n", sc->domain); 1498 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1499 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1500 if (pcib_is_window_open(&sc->io)) 1501 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1502 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1503 if (pcib_is_window_open(&sc->mem)) 1504 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1505 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1506 if (pcib_is_window_open(&sc->pmem)) 1507 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1508 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1509 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1510 sc->flags & PCIB_SUBTRACTIVE) { 1511 device_printf(dev, " special decode "); 1512 comma = 0; 1513 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1514 printf("ISA"); 1515 comma = 1; 1516 } 1517 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1518 printf("%sVGA", comma ? ", " : ""); 1519 comma = 1; 1520 } 1521 if (sc->flags & PCIB_SUBTRACTIVE) 1522 printf("%ssubtractive", comma ? ", " : ""); 1523 printf("\n"); 1524 } 1525 } 1526 1527 /* 1528 * Always enable busmastering on bridges so that transactions 1529 * initiated on the secondary bus are passed through to the 1530 * primary bus. 1531 */ 1532 pci_enable_busmaster(dev); 1533 } 1534 1535 #ifdef PCI_HP 1536 static int 1537 pcib_present(struct pcib_softc *sc) 1538 { 1539 1540 if (sc->flags & PCIB_HOTPLUG) 1541 return (pcib_hotplug_present(sc) != 0); 1542 return (1); 1543 } 1544 #endif 1545 1546 int 1547 pcib_attach_child(device_t dev) 1548 { 1549 struct pcib_softc *sc; 1550 1551 sc = device_get_softc(dev); 1552 if (sc->bus.sec == 0) { 1553 /* no secondary bus; we should have fixed this */ 1554 return(0); 1555 } 1556 1557 #ifdef PCI_HP 1558 if (!pcib_present(sc)) { 1559 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1560 return (0); 1561 } 1562 #endif 1563 1564 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1565 bus_attach_children(dev); 1566 return (0); 1567 } 1568 1569 int 1570 pcib_attach(device_t dev) 1571 { 1572 1573 pcib_attach_common(dev); 1574 return (pcib_attach_child(dev)); 1575 } 1576 1577 int 1578 pcib_detach(device_t dev) 1579 { 1580 struct pcib_softc *sc; 1581 int error; 1582 1583 sc = device_get_softc(dev); 1584 error = bus_detach_children(dev); 1585 if (error) 1586 return (error); 1587 #ifdef PCI_HP 1588 if (sc->flags & PCIB_HOTPLUG) { 1589 error = pcib_detach_hotplug(sc); 1590 if (error) 1591 return (error); 1592 } 1593 #endif 1594 error = device_delete_children(dev); 1595 if (error) 1596 return (error); 1597 pcib_free_windows(sc); 1598 pcib_free_secbus(dev, &sc->bus); 1599 return (0); 1600 } 1601 1602 int 1603 pcib_resume(device_t dev) 1604 { 1605 1606 pcib_cfg_restore(device_get_softc(dev)); 1607 1608 /* 1609 * Restore the Command register only after restoring the windows. 1610 * The bridge should not be claiming random windows. 1611 */ 1612 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2); 1613 return (bus_generic_resume(dev)); 1614 } 1615 1616 void 1617 pcib_bridge_init(device_t dev) 1618 { 1619 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1620 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1621 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1622 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1623 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1624 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1625 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1626 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1627 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1628 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1629 } 1630 1631 int 1632 pcib_child_present(device_t dev, device_t child) 1633 { 1634 #ifdef PCI_HP 1635 struct pcib_softc *sc = device_get_softc(dev); 1636 int retval; 1637 1638 retval = bus_child_present(dev); 1639 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1640 retval = pcib_hotplug_present(sc); 1641 return (retval); 1642 #else 1643 return (bus_child_present(dev)); 1644 #endif 1645 } 1646 1647 int 1648 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1649 { 1650 struct pcib_softc *sc = device_get_softc(dev); 1651 1652 switch (which) { 1653 case PCIB_IVAR_DOMAIN: 1654 *result = sc->domain; 1655 return(0); 1656 case PCIB_IVAR_BUS: 1657 *result = sc->bus.sec; 1658 return(0); 1659 } 1660 return(ENOENT); 1661 } 1662 1663 int 1664 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1665 { 1666 1667 switch (which) { 1668 case PCIB_IVAR_DOMAIN: 1669 return(EINVAL); 1670 case PCIB_IVAR_BUS: 1671 return(EINVAL); 1672 } 1673 return(ENOENT); 1674 } 1675 1676 /* 1677 * Attempt to allocate a resource from the existing resources assigned 1678 * to a window. 1679 */ 1680 static struct resource * 1681 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1682 device_t child, int type, int rid, rman_res_t start, rman_res_t end, 1683 rman_res_t count, u_int flags) 1684 { 1685 struct resource *res; 1686 1687 if (!pcib_is_window_open(w)) 1688 return (NULL); 1689 1690 res = rman_reserve_resource(&w->rman, start, end, count, 1691 flags & ~RF_ACTIVE, child); 1692 if (res == NULL) 1693 return (NULL); 1694 1695 if (bootverbose) 1696 device_printf(sc->dev, 1697 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1698 w->name, rman_get_start(res), rman_get_end(res), rid, 1699 pcib_child_name(child)); 1700 rman_set_rid(res, rid); 1701 rman_set_type(res, type); 1702 1703 if (flags & RF_ACTIVE) { 1704 if (bus_activate_resource(child, type, rid, res) != 0) { 1705 rman_release_resource(res); 1706 return (NULL); 1707 } 1708 } 1709 1710 return (res); 1711 } 1712 1713 /* Allocate a fresh resource range for an unconfigured window. */ 1714 static int 1715 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1716 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1717 { 1718 struct resource *res; 1719 rman_res_t base, limit, wmask; 1720 int rid; 1721 1722 /* 1723 * If this is an I/O window on a bridge with ISA enable set 1724 * and the start address is below 64k, then try to allocate an 1725 * initial window of 0x1000 bytes long starting at address 1726 * 0xf000 and walking down. Note that if the original request 1727 * was larger than the non-aliased range size of 0x100 our 1728 * caller would have raised the start address up to 64k 1729 * already. 1730 */ 1731 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1732 start < 65536) { 1733 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1734 limit = base + 0xfff; 1735 1736 /* 1737 * Skip ranges that wouldn't work for the 1738 * original request. Note that the actual 1739 * window that overlaps are the non-alias 1740 * ranges within [base, limit], so this isn't 1741 * quite a simple comparison. 1742 */ 1743 if (start + count > limit - 0x400) 1744 continue; 1745 if (base == 0) { 1746 /* 1747 * The first open region for the window at 1748 * 0 is 0x400-0x4ff. 1749 */ 1750 if (end - count + 1 < 0x400) 1751 continue; 1752 } else { 1753 if (end - count + 1 < base) 1754 continue; 1755 } 1756 1757 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1758 w->base = base; 1759 w->limit = limit; 1760 return (0); 1761 } 1762 } 1763 return (ENOSPC); 1764 } 1765 1766 wmask = ((rman_res_t)1 << w->step) - 1; 1767 if (RF_ALIGNMENT(flags) < w->step) { 1768 flags &= ~RF_ALIGNMENT_MASK; 1769 flags |= RF_ALIGNMENT_LOG2(w->step); 1770 } 1771 start &= ~wmask; 1772 end |= wmask; 1773 count = roundup2(count, (rman_res_t)1 << w->step); 1774 rid = w->reg; 1775 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1776 flags | RF_ACTIVE | RF_UNMAPPED); 1777 if (res == NULL) 1778 return (ENOSPC); 1779 pcib_add_window_resources(w, &res, 1); 1780 pcib_activate_window(sc, type); 1781 w->base = rman_get_start(res); 1782 w->limit = rman_get_end(res); 1783 return (0); 1784 } 1785 1786 /* Try to expand an existing window to the requested base and limit. */ 1787 static int 1788 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1789 rman_res_t base, rman_res_t limit) 1790 { 1791 struct resource *res; 1792 int error, i, force_64k_base; 1793 1794 KASSERT(base <= w->base && limit >= w->limit, 1795 ("attempting to shrink window")); 1796 1797 /* 1798 * XXX: pcib_grow_window() doesn't try to do this anyway and 1799 * the error handling for all the edge cases would be tedious. 1800 */ 1801 KASSERT(limit == w->limit || base == w->base, 1802 ("attempting to grow both ends of a window")); 1803 1804 /* 1805 * Yet more special handling for requests to expand an I/O 1806 * window behind an ISA-enabled bridge. Since I/O windows 1807 * have to grow in 0x1000 increments and the end of the 0xffff 1808 * range is an alias, growing a window below 64k will always 1809 * result in allocating new resources and never adjusting an 1810 * existing resource. 1811 */ 1812 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1813 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1814 KASSERT(limit == w->limit || limit <= 65535, 1815 ("attempting to grow both ends across 64k ISA alias")); 1816 1817 if (base != w->base) 1818 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1819 else 1820 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1821 limit); 1822 if (error == 0) { 1823 w->base = base; 1824 w->limit = limit; 1825 } 1826 return (error); 1827 } 1828 1829 /* 1830 * Find the existing resource to adjust. Usually there is only one, 1831 * but for an ISA-enabled bridge we might be growing the I/O window 1832 * above 64k and need to find the existing resource that maps all 1833 * of the area above 64k. 1834 */ 1835 for (i = 0; i < w->count; i++) { 1836 if (rman_get_end(w->res[i]) == w->limit) 1837 break; 1838 } 1839 KASSERT(i != w->count, ("did not find existing resource")); 1840 res = w->res[i]; 1841 1842 /* 1843 * Usually the resource we found should match the window's 1844 * existing range. The one exception is the ISA-enabled case 1845 * mentioned above in which case the resource should start at 1846 * 64k. 1847 */ 1848 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1849 w->base <= 65535) { 1850 KASSERT(rman_get_start(res) == 65536, 1851 ("existing resource mismatch")); 1852 force_64k_base = 1; 1853 } else { 1854 KASSERT(w->base == rman_get_start(res), 1855 ("existing resource mismatch")); 1856 force_64k_base = 0; 1857 } 1858 1859 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1860 rman_get_start(res) : base, limit); 1861 if (error) 1862 return (error); 1863 1864 /* Add the newly allocated region to the resource manager. */ 1865 if (w->base != base) { 1866 error = rman_manage_region(&w->rman, base, w->base - 1); 1867 w->base = base; 1868 } else { 1869 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1870 w->limit = limit; 1871 } 1872 if (error) { 1873 if (bootverbose) 1874 device_printf(sc->dev, 1875 "failed to expand %s resource manager\n", w->name); 1876 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1877 rman_get_start(res) : w->base, w->limit); 1878 } 1879 return (error); 1880 } 1881 1882 /* 1883 * Attempt to grow a window to make room for a given resource request. 1884 */ 1885 static int 1886 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1887 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1888 { 1889 rman_res_t align, start_free, end_free, front, back, wmask; 1890 int error; 1891 1892 /* 1893 * Clamp the desired resource range to the maximum address 1894 * this window supports. Reject impossible requests. 1895 * 1896 * For I/O port requests behind a bridge with the ISA enable 1897 * bit set, force large allocations to start above 64k. 1898 */ 1899 if (!w->valid) 1900 return (EINVAL); 1901 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1902 start < 65536) 1903 start = 65536; 1904 if (end > w->rman.rm_end) 1905 end = w->rman.rm_end; 1906 if (start + count - 1 > end || start + count < start) 1907 return (EINVAL); 1908 wmask = ((rman_res_t)1 << w->step) - 1; 1909 1910 /* 1911 * If there is no resource at all, just try to allocate enough 1912 * aligned space for this resource. 1913 */ 1914 if (w->res == NULL) { 1915 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1916 flags); 1917 if (error) { 1918 if (bootverbose) 1919 device_printf(sc->dev, 1920 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 1921 w->name, start, end, count); 1922 return (error); 1923 } 1924 if (bootverbose) 1925 device_printf(sc->dev, 1926 "allocated initial %s window of %#jx-%#jx\n", 1927 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1928 goto updatewin; 1929 } 1930 1931 /* 1932 * See if growing the window would help. Compute the minimum 1933 * amount of address space needed on both the front and back 1934 * ends of the existing window to satisfy the allocation. 1935 * 1936 * For each end, build a candidate region adjusting for the 1937 * required alignment, etc. If there is a free region at the 1938 * edge of the window, grow from the inner edge of the free 1939 * region. Otherwise grow from the window boundary. 1940 * 1941 * Growing an I/O window below 64k for a bridge with the ISA 1942 * enable bit doesn't require any special magic as the step 1943 * size of an I/O window (1k) always includes multiple 1944 * non-alias ranges when it is grown in either direction. 1945 * 1946 * XXX: Special case: if w->res is completely empty and the 1947 * request size is larger than w->res, we should find the 1948 * optimal aligned buffer containing w->res and allocate that. 1949 */ 1950 if (bootverbose) 1951 device_printf(sc->dev, 1952 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 1953 w->name, start, end, count); 1954 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 1955 if (start < w->base) { 1956 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1957 0 || start_free != w->base) 1958 end_free = w->base; 1959 if (end_free > end) 1960 end_free = end + 1; 1961 1962 /* Move end_free down until it is properly aligned. */ 1963 end_free &= ~(align - 1); 1964 end_free--; 1965 front = end_free - (count - 1); 1966 1967 /* 1968 * The resource would now be allocated at (front, 1969 * end_free). Ensure that fits in the (start, end) 1970 * bounds. end_free is checked above. If 'front' is 1971 * ok, ensure it is properly aligned for this window. 1972 * Also check for underflow. 1973 */ 1974 if (front >= start && front <= end_free) { 1975 if (bootverbose) 1976 printf("\tfront candidate range: %#jx-%#jx\n", 1977 front, end_free); 1978 front &= ~wmask; 1979 front = w->base - front; 1980 } else 1981 front = 0; 1982 } else 1983 front = 0; 1984 if (end > w->limit) { 1985 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1986 0 || end_free != w->limit) 1987 start_free = w->limit + 1; 1988 if (start_free < start) 1989 start_free = start; 1990 1991 /* Move start_free up until it is properly aligned. */ 1992 start_free = roundup2(start_free, align); 1993 back = start_free + count - 1; 1994 1995 /* 1996 * The resource would now be allocated at (start_free, 1997 * back). Ensure that fits in the (start, end) 1998 * bounds. start_free is checked above. If 'back' is 1999 * ok, ensure it is properly aligned for this window. 2000 * Also check for overflow. 2001 */ 2002 if (back <= end && start_free <= back) { 2003 if (bootverbose) 2004 printf("\tback candidate range: %#jx-%#jx\n", 2005 start_free, back); 2006 back |= wmask; 2007 back -= w->limit; 2008 } else 2009 back = 0; 2010 } else 2011 back = 0; 2012 2013 /* 2014 * Try to allocate the smallest needed region first. 2015 * If that fails, fall back to the other region. 2016 */ 2017 error = ENOSPC; 2018 while (front != 0 || back != 0) { 2019 if (front != 0 && (front <= back || back == 0)) { 2020 error = pcib_expand_window(sc, w, type, w->base - front, 2021 w->limit); 2022 if (error == 0) 2023 break; 2024 front = 0; 2025 } else { 2026 error = pcib_expand_window(sc, w, type, w->base, 2027 w->limit + back); 2028 if (error == 0) 2029 break; 2030 back = 0; 2031 } 2032 } 2033 2034 if (error) 2035 return (error); 2036 if (bootverbose) 2037 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2038 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2039 2040 updatewin: 2041 /* Write the new window. */ 2042 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2043 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2044 pcib_write_windows(sc, w->mask); 2045 return (0); 2046 } 2047 2048 /* 2049 * We have to trap resource allocation requests and ensure that the bridge 2050 * is set up to, or capable of handling them. 2051 */ 2052 static struct resource * 2053 pcib_alloc_resource(device_t dev, device_t child, int type, int rid, 2054 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2055 { 2056 struct pcib_softc *sc; 2057 struct resource *r; 2058 2059 sc = device_get_softc(dev); 2060 2061 /* 2062 * VGA resources are decoded iff the VGA enable bit is set in 2063 * the bridge control register. VGA resources do not fall into 2064 * the resource windows and are passed up to the parent. 2065 */ 2066 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2067 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2068 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2069 return (bus_generic_alloc_resource(dev, child, type, 2070 rid, start, end, count, flags)); 2071 else 2072 return (NULL); 2073 } 2074 2075 switch (type) { 2076 case PCI_RES_BUS: 2077 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2078 count, flags)); 2079 case SYS_RES_IOPORT: 2080 if (pcib_is_isa_range(sc, start, end, count)) 2081 return (NULL); 2082 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2083 end, count, flags); 2084 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2085 break; 2086 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2087 flags) == 0) 2088 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2089 rid, start, end, count, flags); 2090 break; 2091 case SYS_RES_MEMORY: 2092 /* 2093 * For prefetchable resources, prefer the prefetchable 2094 * memory window, but fall back to the regular memory 2095 * window if that fails. Try both windows before 2096 * attempting to grow a window in case the firmware 2097 * has used a range in the regular memory window to 2098 * map a prefetchable BAR. 2099 */ 2100 if (flags & RF_PREFETCHABLE) { 2101 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2102 rid, start, end, count, flags); 2103 if (r != NULL) 2104 break; 2105 } 2106 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2107 start, end, count, flags); 2108 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2109 break; 2110 if (flags & RF_PREFETCHABLE) { 2111 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2112 count, flags) == 0) { 2113 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2114 type, rid, start, end, count, flags); 2115 if (r != NULL) 2116 break; 2117 } 2118 } 2119 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2120 flags & ~RF_PREFETCHABLE) == 0) 2121 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2122 rid, start, end, count, flags); 2123 break; 2124 default: 2125 return (bus_generic_alloc_resource(dev, child, type, rid, 2126 start, end, count, flags)); 2127 } 2128 2129 /* 2130 * If attempts to suballocate from the window fail but this is a 2131 * subtractive bridge, pass the request up the tree. 2132 */ 2133 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2134 return (bus_generic_alloc_resource(dev, child, type, rid, 2135 start, end, count, flags)); 2136 return (r); 2137 } 2138 2139 static int 2140 pcib_adjust_resource(device_t bus, device_t child, struct resource *r, 2141 rman_res_t start, rman_res_t end) 2142 { 2143 struct pcib_softc *sc; 2144 struct pcib_window *w; 2145 rman_res_t wmask; 2146 int error, type; 2147 2148 sc = device_get_softc(bus); 2149 type = rman_get_type(r); 2150 2151 /* 2152 * If the resource wasn't sub-allocated from one of our region 2153 * managers then just pass the request up. 2154 */ 2155 if (!pcib_is_resource_managed(sc, r)) 2156 return (bus_generic_adjust_resource(bus, child, r, start, end)); 2157 2158 if (type == PCI_RES_BUS) { 2159 /* 2160 * If our bus range isn't big enough to grow the sub-allocation 2161 * then we need to grow our bus range. Any request that would 2162 * require us to decrease the start of our own bus range is 2163 * invalid, we can only extend the end; ignore such requests 2164 * and let rman_adjust_resource fail below. 2165 */ 2166 if (start >= sc->bus.sec && end > sc->bus.sub) { 2167 error = pcib_grow_subbus(&sc->bus, end); 2168 if (error != 0) 2169 return (error); 2170 } 2171 } else { 2172 /* 2173 * Resource is managed and not a secondary bus number, must 2174 * be from one of our windows. 2175 */ 2176 w = pcib_get_resource_window(sc, r); 2177 KASSERT(w != NULL, 2178 ("%s: no window for resource (%#jx-%#jx) type %d", 2179 __func__, rman_get_start(r), rman_get_end(r), type)); 2180 2181 /* 2182 * If our window isn't big enough to grow the sub-allocation 2183 * then we need to expand the window. 2184 */ 2185 if (start < w->base || end > w->limit) { 2186 wmask = ((rman_res_t)1 << w->step) - 1; 2187 error = pcib_expand_window(sc, w, type, 2188 MIN(start & ~wmask, w->base), 2189 MAX(end | wmask, w->limit)); 2190 if (error != 0) 2191 return (error); 2192 if (bootverbose) 2193 device_printf(sc->dev, 2194 "grew %s window to %#jx-%#jx\n", 2195 w->name, (uintmax_t)w->base, 2196 (uintmax_t)w->limit); 2197 pcib_write_windows(sc, w->mask); 2198 } 2199 } 2200 2201 return (rman_adjust_resource(r, start, end)); 2202 } 2203 2204 static int 2205 pcib_release_resource(device_t dev, device_t child, struct resource *r) 2206 { 2207 struct pcib_softc *sc; 2208 int error; 2209 2210 sc = device_get_softc(dev); 2211 if (pcib_is_resource_managed(sc, r)) { 2212 if (rman_get_flags(r) & RF_ACTIVE) { 2213 error = bus_deactivate_resource(child, r); 2214 if (error) 2215 return (error); 2216 } 2217 return (rman_release_resource(r)); 2218 } 2219 return (bus_generic_release_resource(dev, child, r)); 2220 } 2221 2222 static int 2223 pcib_activate_resource(device_t dev, device_t child, struct resource *r) 2224 { 2225 struct pcib_softc *sc = device_get_softc(dev); 2226 struct resource_map map; 2227 int error, type; 2228 2229 if (!pcib_is_resource_managed(sc, r)) 2230 return (bus_generic_activate_resource(dev, child, r)); 2231 2232 error = rman_activate_resource(r); 2233 if (error != 0) 2234 return (error); 2235 2236 type = rman_get_type(r); 2237 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2238 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2239 error = BUS_MAP_RESOURCE(dev, child, r, NULL, &map); 2240 if (error != 0) { 2241 rman_deactivate_resource(r); 2242 return (error); 2243 } 2244 2245 rman_set_mapping(r, &map); 2246 } 2247 return (0); 2248 } 2249 2250 static int 2251 pcib_deactivate_resource(device_t dev, device_t child, struct resource *r) 2252 { 2253 struct pcib_softc *sc = device_get_softc(dev); 2254 struct resource_map map; 2255 int error, type; 2256 2257 if (!pcib_is_resource_managed(sc, r)) 2258 return (bus_generic_deactivate_resource(dev, child, r)); 2259 2260 error = rman_deactivate_resource(r); 2261 if (error != 0) 2262 return (error); 2263 2264 type = rman_get_type(r); 2265 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2266 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2267 rman_get_mapping(r, &map); 2268 BUS_UNMAP_RESOURCE(dev, child, r, &map); 2269 } 2270 return (0); 2271 } 2272 2273 static struct resource * 2274 pcib_find_parent_resource(struct pcib_window *w, struct resource *r) 2275 { 2276 for (int i = 0; i < w->count; i++) { 2277 if (rman_get_start(w->res[i]) <= rman_get_start(r) && 2278 rman_get_end(w->res[i]) >= rman_get_end(r)) 2279 return (w->res[i]); 2280 } 2281 return (NULL); 2282 } 2283 2284 static int 2285 pcib_map_resource(device_t dev, device_t child, struct resource *r, 2286 struct resource_map_request *argsp, struct resource_map *map) 2287 { 2288 struct pcib_softc *sc = device_get_softc(dev); 2289 struct resource_map_request args; 2290 struct pcib_window *w; 2291 struct resource *pres; 2292 rman_res_t length, start; 2293 int error; 2294 2295 w = pcib_get_resource_window(sc, r); 2296 if (w == NULL) 2297 return (bus_generic_map_resource(dev, child, r, argsp, map)); 2298 2299 /* Resources must be active to be mapped. */ 2300 if (!(rman_get_flags(r) & RF_ACTIVE)) 2301 return (ENXIO); 2302 2303 resource_init_map_request(&args); 2304 error = resource_validate_map_request(r, argsp, &args, &start, &length); 2305 if (error) 2306 return (error); 2307 2308 pres = pcib_find_parent_resource(w, r); 2309 if (pres == NULL) 2310 return (ENOENT); 2311 2312 args.offset = start - rman_get_start(pres); 2313 args.length = length; 2314 return (bus_map_resource(dev, pres, &args, map)); 2315 } 2316 2317 static int 2318 pcib_unmap_resource(device_t dev, device_t child, struct resource *r, 2319 struct resource_map *map) 2320 { 2321 struct pcib_softc *sc = device_get_softc(dev); 2322 struct pcib_window *w; 2323 struct resource *pres; 2324 2325 w = pcib_get_resource_window(sc, r); 2326 if (w == NULL) 2327 return (bus_generic_unmap_resource(dev, child, r, map)); 2328 2329 pres = pcib_find_parent_resource(w, r); 2330 if (pres == NULL) 2331 return (ENOENT); 2332 return (bus_unmap_resource(dev, pres, map)); 2333 } 2334 2335 /* 2336 * If ARI is enabled on this downstream port, translate the function number 2337 * to the non-ARI slot/function. The downstream port will convert it back in 2338 * hardware. If ARI is not enabled slot and func are not modified. 2339 */ 2340 static __inline void 2341 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2342 { 2343 struct pcib_softc *sc; 2344 int ari_func; 2345 2346 sc = device_get_softc(pcib); 2347 ari_func = *func; 2348 2349 if (sc->flags & PCIB_ENABLE_ARI) { 2350 KASSERT(*slot == 0, 2351 ("Non-zero slot number with ARI enabled!")); 2352 *slot = PCIE_ARI_SLOT(ari_func); 2353 *func = PCIE_ARI_FUNC(ari_func); 2354 } 2355 } 2356 2357 static void 2358 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2359 { 2360 uint32_t ctl2; 2361 2362 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2363 ctl2 |= PCIEM_CTL2_ARI; 2364 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2365 2366 sc->flags |= PCIB_ENABLE_ARI; 2367 } 2368 2369 /* 2370 * PCIB interface. 2371 */ 2372 int 2373 pcib_maxslots(device_t dev) 2374 { 2375 #if !defined(__amd64__) && !defined(__i386__) 2376 uint32_t pcie_pos; 2377 uint16_t val; 2378 2379 /* 2380 * If this is a PCIe rootport or downstream switch port, there's only 2381 * one slot permitted. 2382 */ 2383 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) { 2384 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2); 2385 val &= PCIEM_FLAGS_TYPE; 2386 if (val == PCIEM_TYPE_ROOT_PORT || 2387 val == PCIEM_TYPE_DOWNSTREAM_PORT) 2388 return (0); 2389 } 2390 #endif 2391 return (PCI_SLOTMAX); 2392 } 2393 2394 static int 2395 pcib_ari_maxslots(device_t dev) 2396 { 2397 struct pcib_softc *sc; 2398 2399 sc = device_get_softc(dev); 2400 2401 if (sc->flags & PCIB_ENABLE_ARI) 2402 return (PCIE_ARI_SLOTMAX); 2403 else 2404 return (pcib_maxslots(dev)); 2405 } 2406 2407 static int 2408 pcib_ari_maxfuncs(device_t dev) 2409 { 2410 struct pcib_softc *sc; 2411 2412 sc = device_get_softc(dev); 2413 2414 if (sc->flags & PCIB_ENABLE_ARI) 2415 return (PCIE_ARI_FUNCMAX); 2416 else 2417 return (PCI_FUNCMAX); 2418 } 2419 2420 static void 2421 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2422 int *func) 2423 { 2424 struct pcib_softc *sc; 2425 2426 sc = device_get_softc(pcib); 2427 2428 *bus = PCI_RID2BUS(rid); 2429 if (sc->flags & PCIB_ENABLE_ARI) { 2430 *slot = PCIE_ARI_RID2SLOT(rid); 2431 *func = PCIE_ARI_RID2FUNC(rid); 2432 } else { 2433 *slot = PCI_RID2SLOT(rid); 2434 *func = PCI_RID2FUNC(rid); 2435 } 2436 } 2437 2438 /* 2439 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2440 */ 2441 static uint32_t 2442 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2443 { 2444 #ifdef PCI_HP 2445 struct pcib_softc *sc; 2446 2447 sc = device_get_softc(dev); 2448 if (!pcib_present(sc)) { 2449 switch (width) { 2450 case 2: 2451 return (0xffff); 2452 case 1: 2453 return (0xff); 2454 default: 2455 return (0xffffffff); 2456 } 2457 } 2458 #endif 2459 pcib_xlate_ari(dev, b, &s, &f); 2460 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2461 f, reg, width)); 2462 } 2463 2464 static void 2465 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2466 { 2467 #ifdef PCI_HP 2468 struct pcib_softc *sc; 2469 2470 sc = device_get_softc(dev); 2471 if (!pcib_present(sc)) 2472 return; 2473 #endif 2474 pcib_xlate_ari(dev, b, &s, &f); 2475 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2476 reg, val, width); 2477 } 2478 2479 /* 2480 * Route an interrupt across a PCI bridge. 2481 */ 2482 int 2483 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2484 { 2485 device_t bus; 2486 int parent_intpin; 2487 int intnum; 2488 2489 /* 2490 * 2491 * The PCI standard defines a swizzle of the child-side device/intpin to 2492 * the parent-side intpin as follows. 2493 * 2494 * device = device on child bus 2495 * child_intpin = intpin on child bus slot (0-3) 2496 * parent_intpin = intpin on parent bus slot (0-3) 2497 * 2498 * parent_intpin = (device + child_intpin) % 4 2499 */ 2500 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2501 2502 /* 2503 * Our parent is a PCI bus. Its parent must export the pcib interface 2504 * which includes the ability to route interrupts. 2505 */ 2506 bus = device_get_parent(pcib); 2507 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2508 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2509 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2510 pci_get_slot(dev), 'A' + pin - 1, intnum); 2511 } 2512 return(intnum); 2513 } 2514 2515 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2516 int 2517 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2518 { 2519 struct pcib_softc *sc = device_get_softc(pcib); 2520 device_t bus; 2521 2522 if (sc->flags & PCIB_DISABLE_MSI) 2523 return (ENXIO); 2524 bus = device_get_parent(pcib); 2525 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2526 irqs)); 2527 } 2528 2529 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2530 int 2531 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2532 { 2533 device_t bus; 2534 2535 bus = device_get_parent(pcib); 2536 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2537 } 2538 2539 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2540 int 2541 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2542 { 2543 struct pcib_softc *sc = device_get_softc(pcib); 2544 device_t bus; 2545 2546 if (sc->flags & PCIB_DISABLE_MSIX) 2547 return (ENXIO); 2548 bus = device_get_parent(pcib); 2549 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2550 } 2551 2552 /* Pass request to release an MSI-X message up to the parent bridge. */ 2553 int 2554 pcib_release_msix(device_t pcib, device_t dev, int irq) 2555 { 2556 device_t bus; 2557 2558 bus = device_get_parent(pcib); 2559 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2560 } 2561 2562 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2563 int 2564 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2565 uint32_t *data) 2566 { 2567 device_t bus; 2568 int error; 2569 2570 bus = device_get_parent(pcib); 2571 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2572 if (error) 2573 return (error); 2574 2575 pci_ht_map_msi(pcib, *addr); 2576 return (0); 2577 } 2578 2579 /* Pass request for device power state up to parent bridge. */ 2580 int 2581 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2582 { 2583 device_t bus; 2584 2585 bus = device_get_parent(pcib); 2586 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2587 } 2588 2589 static int 2590 pcib_ari_enabled(device_t pcib) 2591 { 2592 struct pcib_softc *sc; 2593 2594 sc = device_get_softc(pcib); 2595 2596 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2597 } 2598 2599 static int 2600 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2601 uintptr_t *id) 2602 { 2603 struct pcib_softc *sc; 2604 device_t bus_dev; 2605 uint8_t bus, slot, func; 2606 2607 if (type != PCI_ID_RID) { 2608 bus_dev = device_get_parent(pcib); 2609 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2610 } 2611 2612 sc = device_get_softc(pcib); 2613 2614 if (sc->flags & PCIB_ENABLE_ARI) { 2615 bus = pci_get_bus(dev); 2616 func = pci_get_function(dev); 2617 2618 *id = (PCI_ARI_RID(bus, func)); 2619 } else { 2620 bus = pci_get_bus(dev); 2621 slot = pci_get_slot(dev); 2622 func = pci_get_function(dev); 2623 2624 *id = (PCI_RID(bus, slot, func)); 2625 } 2626 2627 return (0); 2628 } 2629 2630 /* 2631 * Check that the downstream port (pcib) and the endpoint device (dev) both 2632 * support ARI. If so, enable it and return 0, otherwise return an error. 2633 */ 2634 static int 2635 pcib_try_enable_ari(device_t pcib, device_t dev) 2636 { 2637 struct pcib_softc *sc; 2638 int error; 2639 uint32_t cap2; 2640 int ari_cap_off; 2641 uint32_t ari_ver; 2642 uint32_t pcie_pos; 2643 2644 sc = device_get_softc(pcib); 2645 2646 /* 2647 * ARI is controlled in a register in the PCIe capability structure. 2648 * If the downstream port does not have the PCIe capability structure 2649 * then it does not support ARI. 2650 */ 2651 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2652 if (error != 0) 2653 return (ENODEV); 2654 2655 /* Check that the PCIe port advertises ARI support. */ 2656 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2657 if (!(cap2 & PCIEM_CAP2_ARI)) 2658 return (ENODEV); 2659 2660 /* 2661 * Check that the endpoint device advertises ARI support via the ARI 2662 * extended capability structure. 2663 */ 2664 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2665 if (error != 0) 2666 return (ENODEV); 2667 2668 /* 2669 * Finally, check that the endpoint device supports the same version 2670 * of ARI that we do. 2671 */ 2672 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2673 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2674 if (bootverbose) 2675 device_printf(pcib, 2676 "Unsupported version of ARI (%d) detected\n", 2677 PCI_EXTCAP_VER(ari_ver)); 2678 2679 return (ENXIO); 2680 } 2681 2682 pcib_enable_ari(sc, pcie_pos); 2683 2684 return (0); 2685 } 2686 2687 int 2688 pcib_request_feature_allow(device_t pcib, device_t dev, 2689 enum pci_feature feature) 2690 { 2691 /* 2692 * No host firmware we have to negotiate with, so we allow 2693 * every valid feature requested. 2694 */ 2695 switch (feature) { 2696 case PCI_FEATURE_AER: 2697 case PCI_FEATURE_HP: 2698 break; 2699 default: 2700 return (EINVAL); 2701 } 2702 2703 return (0); 2704 } 2705 2706 int 2707 pcib_request_feature(device_t dev, enum pci_feature feature) 2708 { 2709 2710 /* 2711 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2712 * the firmware overrides the method of PCI-PCI bridges. 2713 */ 2714 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2715 } 2716 2717 /* 2718 * Pass the request to use this PCI feature up the tree. Either there's a 2719 * firmware like ACPI that's using this feature that will approve (or deny) the 2720 * request to take it over, or the platform has no such firmware, in which case 2721 * the request will be approved. If the request is approved, the OS is expected 2722 * to make use of the feature or render it harmless. 2723 */ 2724 static int 2725 pcib_request_feature_default(device_t pcib, device_t dev, 2726 enum pci_feature feature) 2727 { 2728 device_t bus; 2729 2730 /* 2731 * Our parent is necessarily a pci bus. Its parent will either be 2732 * another pci bridge (which passes it up) or a host bridge that can 2733 * approve or reject the request. 2734 */ 2735 bus = device_get_parent(pcib); 2736 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2737 } 2738 2739 static int 2740 pcib_reset_child(device_t dev, device_t child, int flags) 2741 { 2742 struct pci_devinfo *pdinfo; 2743 int error; 2744 2745 error = 0; 2746 if (dev == NULL || device_get_parent(child) != dev) 2747 goto out; 2748 error = ENXIO; 2749 if (device_get_devclass(child) != devclass_find("pci")) 2750 goto out; 2751 pdinfo = device_get_ivars(dev); 2752 if (pdinfo->cfg.pcie.pcie_location != 0 && 2753 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT || 2754 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) { 2755 error = bus_helper_reset_prepare(child, flags); 2756 if (error == 0) { 2757 error = pcie_link_reset(dev, 2758 pdinfo->cfg.pcie.pcie_location); 2759 /* XXXKIB call _post even if error != 0 ? */ 2760 bus_helper_reset_post(child, flags); 2761 } 2762 } 2763 out: 2764 return (error); 2765 } 2766