1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "pcib_if.h" 54 55 #ifdef __HAVE_ACPI 56 #include <contrib/dev/acpica/include/acpi.h> 57 #include "acpi_if.h" 58 #else 59 #define ACPI_PWR_FOR_SLEEP(x, y, z) 60 #endif 61 62 extern int pci_do_power_resume; 63 64 static int pcib_probe(device_t dev); 65 static int pcib_suspend(device_t dev); 66 static int pcib_resume(device_t dev); 67 68 static device_method_t pcib_methods[] = { 69 /* Device interface */ 70 DEVMETHOD(device_probe, pcib_probe), 71 DEVMETHOD(device_attach, pcib_attach), 72 DEVMETHOD(device_detach, bus_generic_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD(device_suspend, pcib_suspend), 75 DEVMETHOD(device_resume, pcib_resume), 76 77 /* Bus interface */ 78 DEVMETHOD(bus_print_child, bus_generic_print_child), 79 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 80 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 81 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 82 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 83 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 84 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 85 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 86 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 87 88 /* pcib interface */ 89 DEVMETHOD(pcib_maxslots, pcib_maxslots), 90 DEVMETHOD(pcib_read_config, pcib_read_config), 91 DEVMETHOD(pcib_write_config, pcib_write_config), 92 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 93 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 94 DEVMETHOD(pcib_release_msi, pcib_release_msi), 95 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 96 DEVMETHOD(pcib_release_msix, pcib_release_msix), 97 DEVMETHOD(pcib_map_msi, pcib_map_msi), 98 99 { 0, 0 } 100 }; 101 102 static devclass_t pcib_devclass; 103 104 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 105 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 106 107 /* 108 * Is the prefetch window open (eg, can we allocate memory in it?) 109 */ 110 static int 111 pcib_is_prefetch_open(struct pcib_softc *sc) 112 { 113 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 114 } 115 116 /* 117 * Is the nonprefetch window open (eg, can we allocate memory in it?) 118 */ 119 static int 120 pcib_is_nonprefetch_open(struct pcib_softc *sc) 121 { 122 return (sc->membase > 0 && sc->membase < sc->memlimit); 123 } 124 125 /* 126 * Is the io window open (eg, can we allocate ports in it?) 127 */ 128 static int 129 pcib_is_io_open(struct pcib_softc *sc) 130 { 131 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 132 } 133 134 /* 135 * Get current I/O decode. 136 */ 137 static void 138 pcib_get_io_decode(struct pcib_softc *sc) 139 { 140 device_t dev; 141 uint32_t iolow; 142 143 dev = sc->dev; 144 145 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 146 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 147 sc->iobase = PCI_PPBIOBASE( 148 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 149 else 150 sc->iobase = PCI_PPBIOBASE(0, iolow); 151 152 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 153 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 154 sc->iolimit = PCI_PPBIOLIMIT( 155 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 156 else 157 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 158 } 159 160 /* 161 * Get current memory decode. 162 */ 163 static void 164 pcib_get_mem_decode(struct pcib_softc *sc) 165 { 166 device_t dev; 167 pci_addr_t pmemlow; 168 169 dev = sc->dev; 170 171 sc->membase = PCI_PPBMEMBASE(0, 172 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 173 sc->memlimit = PCI_PPBMEMLIMIT(0, 174 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 175 176 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 177 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 178 sc->pmembase = PCI_PPBMEMBASE( 179 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 180 else 181 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 182 183 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 184 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 185 sc->pmemlimit = PCI_PPBMEMLIMIT( 186 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 187 else 188 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 189 } 190 191 /* 192 * Restore previous I/O decode. 193 */ 194 static void 195 pcib_set_io_decode(struct pcib_softc *sc) 196 { 197 device_t dev; 198 uint32_t iohi; 199 200 dev = sc->dev; 201 202 iohi = sc->iobase >> 16; 203 if (iohi > 0) 204 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 205 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 206 207 iohi = sc->iolimit >> 16; 208 if (iohi > 0) 209 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 210 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 211 } 212 213 /* 214 * Restore previous memory decode. 215 */ 216 static void 217 pcib_set_mem_decode(struct pcib_softc *sc) 218 { 219 device_t dev; 220 pci_addr_t pmemhi; 221 222 dev = sc->dev; 223 224 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 225 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 226 227 pmemhi = sc->pmembase >> 32; 228 if (pmemhi > 0) 229 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 230 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 231 232 pmemhi = sc->pmemlimit >> 32; 233 if (pmemhi > 0) 234 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 235 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 236 } 237 238 /* 239 * Get current bridge configuration. 240 */ 241 static void 242 pcib_cfg_save(struct pcib_softc *sc) 243 { 244 device_t dev; 245 246 dev = sc->dev; 247 248 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 249 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 250 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 251 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 252 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 253 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 254 if (sc->command & PCIM_CMD_PORTEN) 255 pcib_get_io_decode(sc); 256 if (sc->command & PCIM_CMD_MEMEN) 257 pcib_get_mem_decode(sc); 258 } 259 260 /* 261 * Restore previous bridge configuration. 262 */ 263 static void 264 pcib_cfg_restore(struct pcib_softc *sc) 265 { 266 device_t dev; 267 268 dev = sc->dev; 269 270 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 271 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 272 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 273 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 274 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 275 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 276 if (sc->command & PCIM_CMD_PORTEN) 277 pcib_set_io_decode(sc); 278 if (sc->command & PCIM_CMD_MEMEN) 279 pcib_set_mem_decode(sc); 280 } 281 282 /* 283 * Generic device interface 284 */ 285 static int 286 pcib_probe(device_t dev) 287 { 288 if ((pci_get_class(dev) == PCIC_BRIDGE) && 289 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 290 device_set_desc(dev, "PCI-PCI bridge"); 291 return(-10000); 292 } 293 return(ENXIO); 294 } 295 296 void 297 pcib_attach_common(device_t dev) 298 { 299 struct pcib_softc *sc; 300 struct sysctl_ctx_list *sctx; 301 struct sysctl_oid *soid; 302 303 sc = device_get_softc(dev); 304 sc->dev = dev; 305 306 /* 307 * Get current bridge configuration. 308 */ 309 sc->domain = pci_get_domain(dev); 310 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 311 pcib_cfg_save(sc); 312 313 /* 314 * Setup sysctl reporting nodes 315 */ 316 sctx = device_get_sysctl_ctx(dev); 317 soid = device_get_sysctl_tree(dev); 318 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 319 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 320 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 321 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 322 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 323 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 324 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 325 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 326 327 /* 328 * Quirk handling. 329 */ 330 switch (pci_get_devid(dev)) { 331 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 332 { 333 uint8_t supbus; 334 335 supbus = pci_read_config(dev, 0x41, 1); 336 if (supbus != 0xff) { 337 sc->secbus = supbus + 1; 338 sc->subbus = supbus + 1; 339 } 340 break; 341 } 342 343 /* 344 * The i82380FB mobile docking controller is a PCI-PCI bridge, 345 * and it is a subtractive bridge. However, the ProgIf is wrong 346 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 347 * happen. There's also a Toshiba bridge that behaves this 348 * way. 349 */ 350 case 0x124b8086: /* Intel 82380FB Mobile */ 351 case 0x060513d7: /* Toshiba ???? */ 352 sc->flags |= PCIB_SUBTRACTIVE; 353 break; 354 355 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 356 case 0x00dd10de: 357 { 358 char *cp; 359 360 if ((cp = getenv("smbios.planar.maker")) == NULL) 361 break; 362 if (strncmp(cp, "Compal", 6) != 0) { 363 freeenv(cp); 364 break; 365 } 366 freeenv(cp); 367 if ((cp = getenv("smbios.planar.product")) == NULL) 368 break; 369 if (strncmp(cp, "08A0", 4) != 0) { 370 freeenv(cp); 371 break; 372 } 373 freeenv(cp); 374 if (sc->subbus < 0xa) { 375 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 376 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 377 } 378 break; 379 } 380 } 381 382 if (pci_msi_device_blacklisted(dev)) 383 sc->flags |= PCIB_DISABLE_MSI; 384 385 /* 386 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 387 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 388 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 389 * This means they act as if they were subtractively decoding 390 * bridges and pass all transactions. Mark them and real ProgIf 1 391 * parts as subtractive. 392 */ 393 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 394 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 395 sc->flags |= PCIB_SUBTRACTIVE; 396 397 if (bootverbose) { 398 device_printf(dev, " domain %d\n", sc->domain); 399 device_printf(dev, " secondary bus %d\n", sc->secbus); 400 device_printf(dev, " subordinate bus %d\n", sc->subbus); 401 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 402 if (pcib_is_nonprefetch_open(sc)) 403 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 404 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 405 if (pcib_is_prefetch_open(sc)) 406 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 407 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 408 else 409 device_printf(dev, " no prefetched decode\n"); 410 if (sc->flags & PCIB_SUBTRACTIVE) 411 device_printf(dev, " Subtractively decoded bridge.\n"); 412 } 413 414 /* 415 * XXX If the secondary bus number is zero, we should assign a bus number 416 * since the BIOS hasn't, then initialise the bridge. A simple 417 * bus_alloc_resource with the a couple of busses seems like the right 418 * approach, but we don't know what busses the BIOS might have already 419 * assigned to other bridges on this bus that probe later than we do. 420 * 421 * If the subordinate bus number is less than the secondary bus number, 422 * we should pick a better value. One sensible alternative would be to 423 * pick 255; the only tradeoff here is that configuration transactions 424 * would be more widely routed than absolutely necessary. We could 425 * then do a walk of the tree later and fix it. 426 */ 427 } 428 429 int 430 pcib_attach(device_t dev) 431 { 432 struct pcib_softc *sc; 433 device_t child; 434 435 pcib_attach_common(dev); 436 sc = device_get_softc(dev); 437 if (sc->secbus != 0) { 438 child = device_add_child(dev, "pci", sc->secbus); 439 if (child != NULL) 440 return(bus_generic_attach(dev)); 441 } 442 443 /* no secondary bus; we should have fixed this */ 444 return(0); 445 } 446 447 int 448 pcib_suspend(device_t dev) 449 { 450 device_t acpi_dev; 451 int dstate, error; 452 453 pcib_cfg_save(device_get_softc(dev)); 454 error = bus_generic_suspend(dev); 455 if (error == 0 && pci_do_power_resume) { 456 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 457 if (acpi_dev != NULL) { 458 dstate = PCI_POWERSTATE_D3; 459 ACPI_PWR_FOR_SLEEP(acpi_dev, dev, &dstate); 460 pci_set_powerstate(dev, dstate); 461 } 462 } 463 return (error); 464 } 465 466 int 467 pcib_resume(device_t dev) 468 { 469 device_t acpi_dev; 470 471 if (pci_do_power_resume) { 472 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 473 if (acpi_dev != NULL) { 474 ACPI_PWR_FOR_SLEEP(acpi_dev, dev, NULL); 475 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 476 } 477 } 478 pcib_cfg_restore(device_get_softc(dev)); 479 return (bus_generic_resume(dev)); 480 } 481 482 int 483 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 484 { 485 struct pcib_softc *sc = device_get_softc(dev); 486 487 switch (which) { 488 case PCIB_IVAR_DOMAIN: 489 *result = sc->domain; 490 return(0); 491 case PCIB_IVAR_BUS: 492 *result = sc->secbus; 493 return(0); 494 } 495 return(ENOENT); 496 } 497 498 int 499 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 500 { 501 struct pcib_softc *sc = device_get_softc(dev); 502 503 switch (which) { 504 case PCIB_IVAR_DOMAIN: 505 return(EINVAL); 506 case PCIB_IVAR_BUS: 507 sc->secbus = value; 508 return(0); 509 } 510 return(ENOENT); 511 } 512 513 /* 514 * We have to trap resource allocation requests and ensure that the bridge 515 * is set up to, or capable of handling them. 516 */ 517 struct resource * 518 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 519 u_long start, u_long end, u_long count, u_int flags) 520 { 521 struct pcib_softc *sc = device_get_softc(dev); 522 const char *name, *suffix; 523 int ok; 524 525 /* 526 * Fail the allocation for this range if it's not supported. 527 */ 528 name = device_get_nameunit(child); 529 if (name == NULL) { 530 name = ""; 531 suffix = ""; 532 } else 533 suffix = " "; 534 switch (type) { 535 case SYS_RES_IOPORT: 536 ok = 0; 537 if (!pcib_is_io_open(sc)) 538 break; 539 ok = (start >= sc->iobase && end <= sc->iolimit); 540 541 /* 542 * Make sure we allow access to VGA I/O addresses when the 543 * bridge has the "VGA Enable" bit set. 544 */ 545 if (!ok && pci_is_vga_ioport_range(start, end)) 546 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 547 548 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 549 if (!ok) { 550 if (start < sc->iobase) 551 start = sc->iobase; 552 if (end > sc->iolimit) 553 end = sc->iolimit; 554 if (start < end) 555 ok = 1; 556 } 557 } else { 558 ok = 1; 559 #if 0 560 /* 561 * If we overlap with the subtractive range, then 562 * pick the upper range to use. 563 */ 564 if (start < sc->iolimit && end > sc->iobase) 565 start = sc->iolimit + 1; 566 #endif 567 } 568 if (end < start) { 569 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 570 end, start); 571 start = 0; 572 end = 0; 573 ok = 0; 574 } 575 if (!ok) { 576 device_printf(dev, "%s%srequested unsupported I/O " 577 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 578 name, suffix, start, end, sc->iobase, sc->iolimit); 579 return (NULL); 580 } 581 if (bootverbose) 582 device_printf(dev, 583 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 584 name, suffix, start, end); 585 break; 586 587 case SYS_RES_MEMORY: 588 ok = 0; 589 if (pcib_is_nonprefetch_open(sc)) 590 ok = ok || (start >= sc->membase && end <= sc->memlimit); 591 if (pcib_is_prefetch_open(sc)) 592 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 593 594 /* 595 * Make sure we allow access to VGA memory addresses when the 596 * bridge has the "VGA Enable" bit set. 597 */ 598 if (!ok && pci_is_vga_memory_range(start, end)) 599 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 600 601 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 602 if (!ok) { 603 ok = 1; 604 if (flags & RF_PREFETCHABLE) { 605 if (pcib_is_prefetch_open(sc)) { 606 if (start < sc->pmembase) 607 start = sc->pmembase; 608 if (end > sc->pmemlimit) 609 end = sc->pmemlimit; 610 } else { 611 ok = 0; 612 } 613 } else { /* non-prefetchable */ 614 if (pcib_is_nonprefetch_open(sc)) { 615 if (start < sc->membase) 616 start = sc->membase; 617 if (end > sc->memlimit) 618 end = sc->memlimit; 619 } else { 620 ok = 0; 621 } 622 } 623 } 624 } else if (!ok) { 625 ok = 1; /* subtractive bridge: always ok */ 626 #if 0 627 if (pcib_is_nonprefetch_open(sc)) { 628 if (start < sc->memlimit && end > sc->membase) 629 start = sc->memlimit + 1; 630 } 631 if (pcib_is_prefetch_open(sc)) { 632 if (start < sc->pmemlimit && end > sc->pmembase) 633 start = sc->pmemlimit + 1; 634 } 635 #endif 636 } 637 if (end < start) { 638 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 639 end, start); 640 start = 0; 641 end = 0; 642 ok = 0; 643 } 644 if (!ok && bootverbose) 645 device_printf(dev, 646 "%s%srequested unsupported memory range %#lx-%#lx " 647 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 648 name, suffix, start, end, 649 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 650 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 651 if (!ok) 652 return (NULL); 653 if (bootverbose) 654 device_printf(dev,"%s%srequested memory range " 655 "0x%lx-0x%lx: good\n", 656 name, suffix, start, end); 657 break; 658 659 default: 660 break; 661 } 662 /* 663 * Bridge is OK decoding this resource, so pass it up. 664 */ 665 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 666 count, flags)); 667 } 668 669 /* 670 * PCIB interface. 671 */ 672 int 673 pcib_maxslots(device_t dev) 674 { 675 return(PCI_SLOTMAX); 676 } 677 678 /* 679 * Since we are a child of a PCI bus, its parent must support the pcib interface. 680 */ 681 uint32_t 682 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 683 { 684 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 685 } 686 687 void 688 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 689 { 690 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 691 } 692 693 /* 694 * Route an interrupt across a PCI bridge. 695 */ 696 int 697 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 698 { 699 device_t bus; 700 int parent_intpin; 701 int intnum; 702 703 /* 704 * 705 * The PCI standard defines a swizzle of the child-side device/intpin to 706 * the parent-side intpin as follows. 707 * 708 * device = device on child bus 709 * child_intpin = intpin on child bus slot (0-3) 710 * parent_intpin = intpin on parent bus slot (0-3) 711 * 712 * parent_intpin = (device + child_intpin) % 4 713 */ 714 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 715 716 /* 717 * Our parent is a PCI bus. Its parent must export the pcib interface 718 * which includes the ability to route interrupts. 719 */ 720 bus = device_get_parent(pcib); 721 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 722 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 723 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 724 pci_get_slot(dev), 'A' + pin - 1, intnum); 725 } 726 return(intnum); 727 } 728 729 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 730 int 731 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 732 { 733 struct pcib_softc *sc = device_get_softc(pcib); 734 device_t bus; 735 736 if (sc->flags & PCIB_DISABLE_MSI) 737 return (ENXIO); 738 bus = device_get_parent(pcib); 739 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 740 irqs)); 741 } 742 743 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 744 int 745 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 746 { 747 device_t bus; 748 749 bus = device_get_parent(pcib); 750 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 751 } 752 753 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 754 int 755 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 756 { 757 struct pcib_softc *sc = device_get_softc(pcib); 758 device_t bus; 759 760 if (sc->flags & PCIB_DISABLE_MSI) 761 return (ENXIO); 762 bus = device_get_parent(pcib); 763 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 764 } 765 766 /* Pass request to release an MSI-X message up to the parent bridge. */ 767 int 768 pcib_release_msix(device_t pcib, device_t dev, int irq) 769 { 770 device_t bus; 771 772 bus = device_get_parent(pcib); 773 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 774 } 775 776 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 777 int 778 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 779 uint32_t *data) 780 { 781 device_t bus; 782 int error; 783 784 bus = device_get_parent(pcib); 785 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 786 if (error) 787 return (error); 788 789 pci_ht_map_msi(pcib, *addr); 790 return (0); 791 } 792 793 /* 794 * Try to read the bus number of a host-PCI bridge using appropriate config 795 * registers. 796 */ 797 int 798 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 799 uint8_t *busnum) 800 { 801 uint32_t id; 802 803 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 804 if (id == 0xffffffff) 805 return (0); 806 807 switch (id) { 808 case 0x12258086: 809 /* Intel 824?? */ 810 /* XXX This is a guess */ 811 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 812 *busnum = bus; 813 break; 814 case 0x84c48086: 815 /* Intel 82454KX/GX (Orion) */ 816 *busnum = read_config(bus, slot, func, 0x4a, 1); 817 break; 818 case 0x84ca8086: 819 /* 820 * For the 450nx chipset, there is a whole bundle of 821 * things pretending to be host bridges. The MIOC will 822 * be seen first and isn't really a pci bridge (the 823 * actual busses are attached to the PXB's). We need to 824 * read the registers of the MIOC to figure out the 825 * bus numbers for the PXB channels. 826 * 827 * Since the MIOC doesn't have a pci bus attached, we 828 * pretend it wasn't there. 829 */ 830 return (0); 831 case 0x84cb8086: 832 switch (slot) { 833 case 0x12: 834 /* Intel 82454NX PXB#0, Bus#A */ 835 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 836 break; 837 case 0x13: 838 /* Intel 82454NX PXB#0, Bus#B */ 839 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 840 break; 841 case 0x14: 842 /* Intel 82454NX PXB#1, Bus#A */ 843 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 844 break; 845 case 0x15: 846 /* Intel 82454NX PXB#1, Bus#B */ 847 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 848 break; 849 } 850 break; 851 852 /* ServerWorks -- vendor 0x1166 */ 853 case 0x00051166: 854 case 0x00061166: 855 case 0x00081166: 856 case 0x00091166: 857 case 0x00101166: 858 case 0x00111166: 859 case 0x00171166: 860 case 0x01011166: 861 case 0x010f1014: 862 case 0x02011166: 863 case 0x03021014: 864 *busnum = read_config(bus, slot, func, 0x44, 1); 865 break; 866 867 /* Compaq/HP -- vendor 0x0e11 */ 868 case 0x60100e11: 869 *busnum = read_config(bus, slot, func, 0xc8, 1); 870 break; 871 default: 872 /* Don't know how to read bus number. */ 873 return 0; 874 } 875 876 return 1; 877 } 878