1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/pciio.h> 48 #include <sys/rman.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_private.h> 56 #include <dev/pci/pcib_private.h> 57 58 #include "pcib_if.h" 59 60 static int pcib_probe(device_t dev); 61 static int pcib_resume(device_t dev); 62 63 static bus_child_present_t pcib_child_present; 64 static bus_alloc_resource_t pcib_alloc_resource; 65 static bus_adjust_resource_t pcib_adjust_resource; 66 static bus_release_resource_t pcib_release_resource; 67 static bus_activate_resource_t pcib_activate_resource; 68 static bus_deactivate_resource_t pcib_deactivate_resource; 69 static bus_map_resource_t pcib_map_resource; 70 static bus_unmap_resource_t pcib_unmap_resource; 71 static int pcib_reset_child(device_t dev, device_t child, int flags); 72 73 static int pcib_power_for_sleep(device_t pcib, device_t dev, 74 int *pstate); 75 static int pcib_ari_get_id(device_t pcib, device_t dev, 76 enum pci_id_type type, uintptr_t *id); 77 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 78 u_int f, u_int reg, int width); 79 static void pcib_write_config(device_t dev, u_int b, u_int s, 80 u_int f, u_int reg, uint32_t val, int width); 81 static int pcib_ari_maxslots(device_t dev); 82 static int pcib_ari_maxfuncs(device_t dev); 83 static int pcib_try_enable_ari(device_t pcib, device_t dev); 84 static int pcib_ari_enabled(device_t pcib); 85 static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 86 int *bus, int *slot, int *func); 87 #ifdef PCI_HP 88 static void pcib_pcie_ab_timeout(void *arg, int pending); 89 static void pcib_pcie_cc_timeout(void *arg, int pending); 90 static void pcib_pcie_dll_timeout(void *arg, int pending); 91 #endif 92 static int pcib_request_feature_default(device_t pcib, device_t dev, 93 enum pci_feature feature); 94 95 static device_method_t pcib_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pcib_probe), 98 DEVMETHOD(device_attach, pcib_attach), 99 DEVMETHOD(device_detach, pcib_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, bus_generic_suspend), 102 DEVMETHOD(device_resume, pcib_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_child_present, pcib_child_present), 106 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 107 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 108 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 109 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 110 DEVMETHOD(bus_release_resource, pcib_release_resource), 111 DEVMETHOD(bus_activate_resource, pcib_activate_resource), 112 DEVMETHOD(bus_deactivate_resource, pcib_deactivate_resource), 113 DEVMETHOD(bus_map_resource, pcib_map_resource), 114 DEVMETHOD(bus_unmap_resource, pcib_unmap_resource), 115 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 116 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 117 DEVMETHOD(bus_reset_child, pcib_reset_child), 118 119 /* pcib interface */ 120 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 121 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 122 DEVMETHOD(pcib_read_config, pcib_read_config), 123 DEVMETHOD(pcib_write_config, pcib_write_config), 124 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 125 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 126 DEVMETHOD(pcib_release_msi, pcib_release_msi), 127 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 128 DEVMETHOD(pcib_release_msix, pcib_release_msix), 129 DEVMETHOD(pcib_map_msi, pcib_map_msi), 130 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 131 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 132 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 133 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 134 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 135 DEVMETHOD(pcib_request_feature, pcib_request_feature_default), 136 137 DEVMETHOD_END 138 }; 139 140 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 141 EARLY_DRIVER_MODULE(pcib, pci, pcib_driver, NULL, NULL, BUS_PASS_BUS); 142 143 SYSCTL_DECL(_hw_pci); 144 145 static int pci_clear_pcib; 146 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 147 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 148 149 /* 150 * Get the corresponding window if this resource from a child device was 151 * sub-allocated from one of our window resource managers. 152 */ 153 static struct pcib_window * 154 pcib_get_resource_window(struct pcib_softc *sc, struct resource *r) 155 { 156 switch (rman_get_type(r)) { 157 case SYS_RES_IOPORT: 158 if (rman_is_region_manager(r, &sc->io.rman)) 159 return (&sc->io); 160 break; 161 case SYS_RES_MEMORY: 162 /* Prefetchable resources may live in either memory rman. */ 163 if (rman_get_flags(r) & RF_PREFETCHABLE && 164 rman_is_region_manager(r, &sc->pmem.rman)) 165 return (&sc->pmem); 166 if (rman_is_region_manager(r, &sc->mem.rman)) 167 return (&sc->mem); 168 break; 169 } 170 return (NULL); 171 } 172 173 /* 174 * Is a resource from a child device sub-allocated from one of our 175 * resource managers? 176 */ 177 static int 178 pcib_is_resource_managed(struct pcib_softc *sc, struct resource *r) 179 { 180 181 if (rman_get_type(r) == PCI_RES_BUS) 182 return (rman_is_region_manager(r, &sc->bus.rman)); 183 return (pcib_get_resource_window(sc, r) != NULL); 184 } 185 186 static int 187 pcib_is_window_open(struct pcib_window *pw) 188 { 189 190 return (pw->valid && pw->base < pw->limit); 191 } 192 193 /* 194 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 195 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 196 * when allocating the resource windows and rely on the PCI bus driver 197 * to do this for us. 198 */ 199 static void 200 pcib_activate_window(struct pcib_softc *sc, int type) 201 { 202 203 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 204 } 205 206 static void 207 pcib_write_windows(struct pcib_softc *sc, int mask) 208 { 209 device_t dev; 210 uint32_t val; 211 212 dev = sc->dev; 213 if (sc->io.valid && mask & WIN_IO) { 214 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 215 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 216 pci_write_config(dev, PCIR_IOBASEH_1, 217 sc->io.base >> 16, 2); 218 pci_write_config(dev, PCIR_IOLIMITH_1, 219 sc->io.limit >> 16, 2); 220 } 221 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 222 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 223 } 224 225 if (mask & WIN_MEM) { 226 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 227 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 228 } 229 230 if (sc->pmem.valid && mask & WIN_PMEM) { 231 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 232 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 233 pci_write_config(dev, PCIR_PMBASEH_1, 234 sc->pmem.base >> 32, 4); 235 pci_write_config(dev, PCIR_PMLIMITH_1, 236 sc->pmem.limit >> 32, 4); 237 } 238 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 239 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 240 } 241 } 242 243 /* 244 * This is used to reject I/O port allocations that conflict with an 245 * ISA alias range. 246 */ 247 static int 248 pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 249 rman_res_t count) 250 { 251 rman_res_t next_alias; 252 253 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 254 return (0); 255 256 /* Only check fixed ranges for overlap. */ 257 if (start + count - 1 != end) 258 return (0); 259 260 /* ISA aliases are only in the lower 64KB of I/O space. */ 261 if (start >= 65536) 262 return (0); 263 264 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 265 if (start < 0x100) 266 goto alias; 267 268 /* 269 * If the start address is an alias, the range is an alias. 270 * Otherwise, compute the start of the next alias range and 271 * check if it is before the end of the candidate range. 272 */ 273 if ((start & 0x300) != 0) 274 goto alias; 275 next_alias = (start & ~0x3fful) | 0x100; 276 if (next_alias <= end) 277 goto alias; 278 return (0); 279 280 alias: 281 if (bootverbose) 282 device_printf(sc->dev, 283 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 284 end); 285 return (1); 286 } 287 288 static void 289 pcib_add_window_resources(struct pcib_window *w, struct resource **res, 290 int count) 291 { 292 struct resource **newarray; 293 int error, i; 294 295 newarray = malloc(sizeof(struct resource *) * (w->count + count), 296 M_DEVBUF, M_WAITOK); 297 if (w->res != NULL) 298 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 299 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 300 free(w->res, M_DEVBUF); 301 w->res = newarray; 302 w->count += count; 303 304 for (i = 0; i < count; i++) { 305 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 306 rman_get_end(res[i])); 307 if (error) 308 panic("Failed to add resource to rman"); 309 } 310 } 311 312 typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 313 314 static void 315 pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 316 void *arg) 317 { 318 rman_res_t next_end; 319 320 /* 321 * If start is within an ISA alias range, move up to the start 322 * of the next non-alias range. As a special case, addresses 323 * in the range 0x000 - 0x0ff should also be skipped since 324 * those are used for various system I/O devices in ISA 325 * systems. 326 */ 327 if (start <= 65535) { 328 if (start < 0x100 || (start & 0x300) != 0) { 329 start &= ~0x3ff; 330 start += 0x400; 331 } 332 } 333 334 /* ISA aliases are only in the lower 64KB of I/O space. */ 335 while (start <= MIN(end, 65535)) { 336 next_end = MIN(start | 0xff, end); 337 cb(start, next_end, arg); 338 start += 0x400; 339 } 340 341 if (start <= end) 342 cb(start, end, arg); 343 } 344 345 static void 346 count_ranges(rman_res_t start, rman_res_t end, void *arg) 347 { 348 int *countp; 349 350 countp = arg; 351 (*countp)++; 352 } 353 354 struct alloc_state { 355 struct resource **res; 356 struct pcib_softc *sc; 357 int count, error; 358 }; 359 360 static void 361 alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 362 { 363 struct alloc_state *as; 364 struct pcib_window *w; 365 int rid; 366 367 as = arg; 368 if (as->error != 0) 369 return; 370 371 w = &as->sc->io; 372 rid = w->reg; 373 if (bootverbose) 374 device_printf(as->sc->dev, 375 "allocating non-ISA range %#jx-%#jx\n", start, end); 376 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 377 &rid, start, end, end - start + 1, RF_ACTIVE | RF_UNMAPPED); 378 if (as->res[as->count] == NULL) 379 as->error = ENXIO; 380 else 381 as->count++; 382 } 383 384 static int 385 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 386 { 387 struct alloc_state as; 388 int i, new_count; 389 390 /* First, see how many ranges we need. */ 391 new_count = 0; 392 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 393 394 /* Second, allocate the ranges. */ 395 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 396 M_WAITOK); 397 as.sc = sc; 398 as.count = 0; 399 as.error = 0; 400 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 401 if (as.error != 0) { 402 for (i = 0; i < as.count; i++) 403 bus_release_resource(sc->dev, SYS_RES_IOPORT, 404 sc->io.reg, as.res[i]); 405 free(as.res, M_DEVBUF); 406 return (as.error); 407 } 408 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 409 410 /* Third, add the ranges to the window. */ 411 pcib_add_window_resources(&sc->io, as.res, as.count); 412 free(as.res, M_DEVBUF); 413 return (0); 414 } 415 416 static void 417 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 418 int flags, pci_addr_t max_address) 419 { 420 struct resource *res; 421 char buf[64]; 422 int error, rid; 423 424 if (max_address != (rman_res_t)max_address) 425 max_address = ~0; 426 w->rman.rm_start = 0; 427 w->rman.rm_end = max_address; 428 w->rman.rm_type = RMAN_ARRAY; 429 snprintf(buf, sizeof(buf), "%s %s window", 430 device_get_nameunit(sc->dev), w->name); 431 w->rman.rm_descr = strdup(buf, M_DEVBUF); 432 error = rman_init(&w->rman); 433 if (error) 434 panic("Failed to initialize %s %s rman", 435 device_get_nameunit(sc->dev), w->name); 436 437 if (!pcib_is_window_open(w)) 438 return; 439 440 if (w->base > max_address || w->limit > max_address) { 441 device_printf(sc->dev, 442 "initial %s window has too many bits, ignoring\n", w->name); 443 return; 444 } 445 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 446 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 447 else { 448 rid = w->reg; 449 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 450 w->limit - w->base + 1, flags | RF_ACTIVE | RF_UNMAPPED); 451 if (res != NULL) 452 pcib_add_window_resources(w, &res, 1); 453 } 454 if (w->res == NULL) { 455 device_printf(sc->dev, 456 "failed to allocate initial %s window: %#jx-%#jx\n", 457 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 458 w->base = max_address; 459 w->limit = 0; 460 pcib_write_windows(sc, w->mask); 461 return; 462 } 463 pcib_activate_window(sc, type); 464 } 465 466 /* 467 * Initialize I/O windows. 468 */ 469 static void 470 pcib_probe_windows(struct pcib_softc *sc) 471 { 472 pci_addr_t max; 473 device_t dev; 474 uint32_t val; 475 476 dev = sc->dev; 477 478 if (pci_clear_pcib) { 479 pcib_bridge_init(dev); 480 } 481 482 /* Determine if the I/O port window is implemented. */ 483 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 484 if (val == 0) { 485 /* 486 * If 'val' is zero, then only 16-bits of I/O space 487 * are supported. 488 */ 489 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 490 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 491 sc->io.valid = 1; 492 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 493 } 494 } else 495 sc->io.valid = 1; 496 497 /* Read the existing I/O port window. */ 498 if (sc->io.valid) { 499 sc->io.reg = PCIR_IOBASEL_1; 500 sc->io.step = 12; 501 sc->io.mask = WIN_IO; 502 sc->io.name = "I/O port"; 503 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 504 sc->io.base = PCI_PPBIOBASE( 505 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 506 sc->io.limit = PCI_PPBIOLIMIT( 507 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 508 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 509 max = 0xffffffff; 510 } else { 511 sc->io.base = PCI_PPBIOBASE(0, val); 512 sc->io.limit = PCI_PPBIOLIMIT(0, 513 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 514 max = 0xffff; 515 } 516 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 517 } 518 519 /* Read the existing memory window. */ 520 sc->mem.valid = 1; 521 sc->mem.reg = PCIR_MEMBASE_1; 522 sc->mem.step = 20; 523 sc->mem.mask = WIN_MEM; 524 sc->mem.name = "memory"; 525 sc->mem.base = PCI_PPBMEMBASE(0, 526 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 527 sc->mem.limit = PCI_PPBMEMLIMIT(0, 528 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 529 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 530 531 /* Determine if the prefetchable memory window is implemented. */ 532 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 533 if (val == 0) { 534 /* 535 * If 'val' is zero, then only 32-bits of memory space 536 * are supported. 537 */ 538 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 539 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 540 sc->pmem.valid = 1; 541 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 542 } 543 } else 544 sc->pmem.valid = 1; 545 546 /* Read the existing prefetchable memory window. */ 547 if (sc->pmem.valid) { 548 sc->pmem.reg = PCIR_PMBASEL_1; 549 sc->pmem.step = 20; 550 sc->pmem.mask = WIN_PMEM; 551 sc->pmem.name = "prefetch"; 552 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 553 sc->pmem.base = PCI_PPBMEMBASE( 554 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 555 sc->pmem.limit = PCI_PPBMEMLIMIT( 556 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 557 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 558 max = 0xffffffffffffffff; 559 } else { 560 sc->pmem.base = PCI_PPBMEMBASE(0, val); 561 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 562 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 563 max = 0xffffffff; 564 } 565 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 566 RF_PREFETCHABLE, max); 567 } 568 } 569 570 static void 571 pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 572 { 573 device_t dev; 574 int error, i; 575 576 if (!w->valid) 577 return; 578 579 dev = sc->dev; 580 error = rman_fini(&w->rman); 581 if (error) { 582 device_printf(dev, "failed to release %s rman\n", w->name); 583 return; 584 } 585 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 586 587 for (i = 0; i < w->count; i++) { 588 error = bus_free_resource(dev, type, w->res[i]); 589 if (error) 590 device_printf(dev, 591 "failed to release %s resource: %d\n", w->name, 592 error); 593 } 594 free(w->res, M_DEVBUF); 595 } 596 597 static void 598 pcib_free_windows(struct pcib_softc *sc) 599 { 600 601 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 602 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 603 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 604 } 605 606 /* 607 * Allocate a suitable secondary bus for this bridge if needed and 608 * initialize the resource manager for the secondary bus range. Note 609 * that the minimum count is a desired value and this may allocate a 610 * smaller range. 611 */ 612 void 613 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 614 { 615 char buf[64]; 616 int error, rid, sec_reg; 617 618 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 619 case PCIM_HDRTYPE_BRIDGE: 620 sec_reg = PCIR_SECBUS_1; 621 bus->sub_reg = PCIR_SUBBUS_1; 622 break; 623 case PCIM_HDRTYPE_CARDBUS: 624 sec_reg = PCIR_SECBUS_2; 625 bus->sub_reg = PCIR_SUBBUS_2; 626 break; 627 default: 628 panic("not a PCI bridge"); 629 } 630 bus->sec = pci_read_config(dev, sec_reg, 1); 631 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 632 bus->dev = dev; 633 bus->rman.rm_start = 0; 634 bus->rman.rm_end = PCI_BUSMAX; 635 bus->rman.rm_type = RMAN_ARRAY; 636 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 637 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 638 error = rman_init(&bus->rman); 639 if (error) 640 panic("Failed to initialize %s bus number rman", 641 device_get_nameunit(dev)); 642 643 /* 644 * Allocate a bus range. This will return an existing bus range 645 * if one exists, or a new bus range if one does not. 646 */ 647 rid = 0; 648 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 649 min_count, RF_ACTIVE); 650 if (bus->res == NULL) { 651 /* 652 * Fall back to just allocating a range of a single bus 653 * number. 654 */ 655 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 656 1, RF_ACTIVE); 657 } else if (rman_get_size(bus->res) < min_count) 658 /* 659 * Attempt to grow the existing range to satisfy the 660 * minimum desired count. 661 */ 662 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 663 rman_get_start(bus->res), rman_get_start(bus->res) + 664 min_count - 1); 665 666 /* 667 * Add the initial resource to the rman. 668 */ 669 if (bus->res != NULL) { 670 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 671 rman_get_end(bus->res)); 672 if (error) 673 panic("Failed to add resource to rman"); 674 bus->sec = rman_get_start(bus->res); 675 bus->sub = rman_get_end(bus->res); 676 } 677 } 678 679 void 680 pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 681 { 682 int error; 683 684 error = rman_fini(&bus->rman); 685 if (error) { 686 device_printf(dev, "failed to release bus number rman\n"); 687 return; 688 } 689 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 690 691 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 692 if (error) 693 device_printf(dev, 694 "failed to release bus numbers resource: %d\n", error); 695 } 696 697 static struct resource * 698 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 699 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 700 { 701 struct resource *res; 702 703 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 704 child); 705 if (res == NULL) 706 return (NULL); 707 708 if (bootverbose) 709 device_printf(bus->dev, 710 "allocated bus range (%ju-%ju) for rid %d of %s\n", 711 rman_get_start(res), rman_get_end(res), *rid, 712 pcib_child_name(child)); 713 rman_set_rid(res, *rid); 714 rman_set_type(res, PCI_RES_BUS); 715 return (res); 716 } 717 718 /* 719 * Attempt to grow the secondary bus range. This is much simpler than 720 * for I/O windows as the range can only be grown by increasing 721 * subbus. 722 */ 723 static int 724 pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 725 { 726 rman_res_t old_end; 727 int error; 728 729 old_end = rman_get_end(bus->res); 730 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 731 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 732 rman_get_start(bus->res), new_end); 733 if (error) 734 return (error); 735 if (bootverbose) 736 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 737 rman_get_start(bus->res), rman_get_end(bus->res)); 738 error = rman_manage_region(&bus->rman, old_end + 1, 739 rman_get_end(bus->res)); 740 if (error) 741 panic("Failed to add resource to rman"); 742 bus->sub = rman_get_end(bus->res); 743 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 744 return (0); 745 } 746 747 struct resource * 748 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 749 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 750 { 751 struct resource *res; 752 rman_res_t start_free, end_free, new_end; 753 754 /* 755 * First, see if the request can be satisified by the existing 756 * bus range. 757 */ 758 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 759 if (res != NULL) 760 return (res); 761 762 /* 763 * Figure out a range to grow the bus range. First, find the 764 * first bus number after the last allocated bus in the rman and 765 * enforce that as a minimum starting point for the range. 766 */ 767 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 768 end_free != bus->sub) 769 start_free = bus->sub + 1; 770 if (start_free < start) 771 start_free = start; 772 new_end = start_free + count - 1; 773 774 /* 775 * See if this new range would satisfy the request if it 776 * succeeds. 777 */ 778 if (new_end > end) 779 return (NULL); 780 781 /* Finally, attempt to grow the existing resource. */ 782 if (bootverbose) { 783 device_printf(bus->dev, 784 "attempting to grow bus range for %ju buses\n", count); 785 printf("\tback candidate range: %ju-%ju\n", start_free, 786 new_end); 787 } 788 if (pcib_grow_subbus(bus, new_end) == 0) 789 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 790 flags)); 791 return (NULL); 792 } 793 794 #ifdef PCI_HP 795 /* 796 * PCI-express HotPlug support. 797 */ 798 static int pci_enable_pcie_hp = 1; 799 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 800 &pci_enable_pcie_hp, 0, 801 "Enable support for native PCI-express HotPlug."); 802 803 static sbintime_t pcie_hp_detach_timeout = 5 * SBT_1S; 804 SYSCTL_SBINTIME_MSEC(_hw_pci, OID_AUTO, pcie_hp_detach_timeout, CTLFLAG_RWTUN, 805 &pcie_hp_detach_timeout, 806 "Attention Button delay for PCI-express Eject."); 807 808 static void 809 pcib_probe_hotplug(struct pcib_softc *sc) 810 { 811 device_t dev; 812 uint32_t link_cap; 813 uint16_t link_sta, slot_sta; 814 815 if (!pci_enable_pcie_hp) 816 return; 817 818 dev = sc->dev; 819 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 820 return; 821 822 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 823 return; 824 825 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 826 827 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 828 return; 829 link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 830 if ((link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 831 return; 832 833 /* 834 * Some devices report that they have an MRL when they actually 835 * do not. Since they always report that the MRL is open, child 836 * devices would be ignored. Try to detect these devices and 837 * ignore their claim of HotPlug support. 838 * 839 * If there is an open MRL but the Data Link Layer is active, 840 * the MRL is not real. 841 */ 842 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0) { 843 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 844 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 845 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 846 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 847 return; 848 } 849 } 850 851 /* 852 * Now that we're sure we want to do hot plug, ask the 853 * firmware, if any, if that's OK. 854 */ 855 if (pcib_request_feature(dev, PCI_FEATURE_HP) != 0) { 856 if (bootverbose) 857 device_printf(dev, "Unable to activate hot plug feature.\n"); 858 return; 859 } 860 861 sc->flags |= PCIB_HOTPLUG; 862 } 863 864 /* 865 * Send a HotPlug command to the slot control register. If this slot 866 * uses command completion interrupts and a previous command is still 867 * in progress, then the command is dropped. Once the previous 868 * command completes or times out, pcib_pcie_hotplug_update() will be 869 * invoked to post a new command based on the slot's state at that 870 * time. 871 */ 872 static void 873 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 874 { 875 device_t dev; 876 uint16_t ctl, new; 877 878 dev = sc->dev; 879 880 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 881 return; 882 883 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 884 new = (ctl & ~mask) | val; 885 if (new == ctl) 886 return; 887 if (bootverbose) 888 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 889 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 890 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 891 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 892 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 893 if (!cold) 894 taskqueue_enqueue_timeout(taskqueue_bus, 895 &sc->pcie_cc_task, hz); 896 } 897 } 898 899 static void 900 pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 901 { 902 device_t dev; 903 904 dev = sc->dev; 905 906 if (bootverbose) 907 device_printf(dev, "Command Completed\n"); 908 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 909 return; 910 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, NULL); 911 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 912 wakeup(sc); 913 } 914 915 /* 916 * Returns true if a card is fully inserted from the user's 917 * perspective. It may not yet be ready for access, but the driver 918 * can now start enabling access if necessary. 919 */ 920 static bool 921 pcib_hotplug_inserted(struct pcib_softc *sc) 922 { 923 924 /* Pretend the card isn't present if a detach is forced. */ 925 if (sc->flags & PCIB_DETACHING) 926 return (false); 927 928 /* Card must be present in the slot. */ 929 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 930 return (false); 931 932 /* A power fault implicitly turns off power to the slot. */ 933 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 934 return (false); 935 936 /* If the MRL is disengaged, the slot is powered off. */ 937 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 938 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 939 return (false); 940 941 return (true); 942 } 943 944 /* 945 * Returns -1 if the card is fully inserted, powered, and ready for 946 * access. Otherwise, returns 0. 947 */ 948 static int 949 pcib_hotplug_present(struct pcib_softc *sc) 950 { 951 952 /* Card must be inserted. */ 953 if (!pcib_hotplug_inserted(sc)) 954 return (0); 955 956 /* Require the Data Link Layer to be active. */ 957 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 958 return (0); 959 960 return (-1); 961 } 962 963 static int pci_enable_pcie_ei = 0; 964 SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_ei, CTLFLAG_RWTUN, 965 &pci_enable_pcie_ei, 0, 966 "Enable support for PCI-express Electromechanical Interlock."); 967 968 static void 969 pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 970 bool schedule_task) 971 { 972 bool card_inserted, ei_engaged; 973 974 /* Clear DETACHING if Presence Detect has cleared. */ 975 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 976 PCIEM_SLOT_STA_PDC) 977 sc->flags &= ~PCIB_DETACHING; 978 979 card_inserted = pcib_hotplug_inserted(sc); 980 981 /* Turn the power indicator on if a card is inserted. */ 982 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 983 mask |= PCIEM_SLOT_CTL_PIC; 984 if (card_inserted) 985 val |= PCIEM_SLOT_CTL_PI_ON; 986 else if (sc->flags & PCIB_DETACH_PENDING) 987 val |= PCIEM_SLOT_CTL_PI_BLINK; 988 else 989 val |= PCIEM_SLOT_CTL_PI_OFF; 990 } 991 992 /* Turn the power on via the Power Controller if a card is inserted. */ 993 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 994 mask |= PCIEM_SLOT_CTL_PCC; 995 if (card_inserted) 996 val |= PCIEM_SLOT_CTL_PC_ON; 997 else 998 val |= PCIEM_SLOT_CTL_PC_OFF; 999 } 1000 1001 /* 1002 * If a card is inserted, enable the Electromechanical 1003 * Interlock. If a card is not inserted (or we are in the 1004 * process of detaching), disable the Electromechanical 1005 * Interlock. 1006 */ 1007 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) && 1008 pci_enable_pcie_ei) { 1009 mask |= PCIEM_SLOT_CTL_EIC; 1010 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1011 if (card_inserted != ei_engaged) 1012 val |= PCIEM_SLOT_CTL_EIC; 1013 } 1014 1015 /* 1016 * Start a timer to see if the Data Link Layer times out. 1017 * Note that we only start the timer if Presence Detect or MRL Sensor 1018 * changed on this interrupt. Stop any scheduled timer if 1019 * the Data Link Layer is active. 1020 */ 1021 if (card_inserted && 1022 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1023 sc->pcie_slot_sta & 1024 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1025 if (cold) 1026 device_printf(sc->dev, 1027 "Data Link Layer inactive\n"); 1028 else 1029 taskqueue_enqueue_timeout(taskqueue_bus, 1030 &sc->pcie_dll_task, hz); 1031 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1032 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_dll_task, 1033 NULL); 1034 1035 pcib_pcie_hotplug_command(sc, val, mask); 1036 1037 /* 1038 * During attach the child "pci" device is added synchronously; 1039 * otherwise, the task is scheduled to manage the child 1040 * device. 1041 */ 1042 if (schedule_task && 1043 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1044 taskqueue_enqueue(taskqueue_bus, &sc->pcie_hp_task); 1045 } 1046 1047 static void 1048 pcib_pcie_intr_hotplug(void *arg) 1049 { 1050 struct pcib_softc *sc; 1051 device_t dev; 1052 uint16_t old_slot_sta; 1053 1054 sc = arg; 1055 dev = sc->dev; 1056 PCIB_HP_LOCK(sc); 1057 old_slot_sta = sc->pcie_slot_sta; 1058 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1059 1060 /* Clear the events just reported. */ 1061 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1062 1063 if (bootverbose) 1064 device_printf(dev, "HotPlug interrupt: %#x\n", 1065 sc->pcie_slot_sta); 1066 1067 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1068 if (sc->flags & PCIB_DETACH_PENDING) { 1069 device_printf(dev, 1070 "Attention Button Pressed: Detach Cancelled\n"); 1071 sc->flags &= ~PCIB_DETACH_PENDING; 1072 taskqueue_cancel_timeout(taskqueue_bus, 1073 &sc->pcie_ab_task, NULL); 1074 } else if (old_slot_sta & PCIEM_SLOT_STA_PDS) { 1075 /* Only initiate detach sequence if device present. */ 1076 if (pcie_hp_detach_timeout != 0) { 1077 device_printf(dev, 1078 "Attention Button Pressed: Detaching in %ld ms\n", 1079 (long)(pcie_hp_detach_timeout / SBT_1MS)); 1080 sc->flags |= PCIB_DETACH_PENDING; 1081 taskqueue_enqueue_timeout_sbt(taskqueue_bus, 1082 &sc->pcie_ab_task, pcie_hp_detach_timeout, 1083 SBT_1S, 0); 1084 } else { 1085 sc->flags |= PCIB_DETACHING; 1086 } 1087 } 1088 } 1089 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1090 device_printf(dev, "Power Fault Detected\n"); 1091 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1092 device_printf(dev, "MRL Sensor Changed to %s\n", 1093 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1094 "closed"); 1095 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1096 device_printf(dev, "Presence Detect Changed to %s\n", 1097 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1098 "empty"); 1099 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1100 pcib_pcie_hotplug_command_completed(sc); 1101 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1102 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1103 if (bootverbose) 1104 device_printf(dev, 1105 "Data Link Layer State Changed to %s\n", 1106 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1107 "active" : "inactive"); 1108 } 1109 1110 pcib_pcie_hotplug_update(sc, 0, 0, true); 1111 PCIB_HP_UNLOCK(sc); 1112 } 1113 1114 static void 1115 pcib_pcie_hotplug_task(void *context, int pending) 1116 { 1117 struct pcib_softc *sc; 1118 device_t dev; 1119 1120 sc = context; 1121 PCIB_HP_LOCK(sc); 1122 dev = sc->dev; 1123 if (pcib_hotplug_present(sc) != 0) { 1124 if (sc->child == NULL) { 1125 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1126 bus_attach_children(dev); 1127 } 1128 } else { 1129 if (sc->child != NULL) { 1130 if (device_delete_child(dev, sc->child) == 0) 1131 sc->child = NULL; 1132 } 1133 } 1134 PCIB_HP_UNLOCK(sc); 1135 } 1136 1137 static void 1138 pcib_pcie_ab_timeout(void *arg, int pending) 1139 { 1140 struct pcib_softc *sc = arg; 1141 1142 PCIB_HP_LOCK(sc); 1143 if (sc->flags & PCIB_DETACH_PENDING) { 1144 sc->flags |= PCIB_DETACHING; 1145 sc->flags &= ~PCIB_DETACH_PENDING; 1146 pcib_pcie_hotplug_update(sc, 0, 0, true); 1147 } 1148 PCIB_HP_UNLOCK(sc); 1149 } 1150 1151 static void 1152 pcib_pcie_cc_timeout(void *arg, int pending) 1153 { 1154 struct pcib_softc *sc = arg; 1155 device_t dev = sc->dev; 1156 uint16_t sta; 1157 1158 PCIB_HP_LOCK(sc); 1159 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1160 if (!(sta & PCIEM_SLOT_STA_CC)) { 1161 device_printf(dev, "HotPlug Command Timed Out\n"); 1162 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1163 } else { 1164 device_printf(dev, 1165 "Missed HotPlug interrupt waiting for Command Completion\n"); 1166 pcib_pcie_intr_hotplug(sc); 1167 } 1168 PCIB_HP_UNLOCK(sc); 1169 } 1170 1171 static void 1172 pcib_pcie_dll_timeout(void *arg, int pending) 1173 { 1174 struct pcib_softc *sc = arg; 1175 device_t dev = sc->dev; 1176 uint16_t sta; 1177 1178 PCIB_HP_LOCK(sc); 1179 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1180 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1181 device_printf(dev, 1182 "Timed out waiting for Data Link Layer Active\n"); 1183 sc->flags |= PCIB_DETACHING; 1184 pcib_pcie_hotplug_update(sc, 0, 0, true); 1185 } else if (sta != sc->pcie_link_sta) { 1186 device_printf(dev, 1187 "Missed HotPlug interrupt waiting for DLL Active\n"); 1188 pcib_pcie_intr_hotplug(sc); 1189 } 1190 PCIB_HP_UNLOCK(sc); 1191 } 1192 1193 static int 1194 pcib_alloc_pcie_irq(struct pcib_softc *sc) 1195 { 1196 device_t dev; 1197 int count, error, mem_rid, rid; 1198 1199 rid = -1; 1200 dev = sc->dev; 1201 1202 /* 1203 * For simplicity, only use MSI-X if there is a single message. 1204 * To support a device with multiple messages we would have to 1205 * use remap intr if the MSI number is not 0. 1206 */ 1207 count = pci_msix_count(dev); 1208 if (count == 1) { 1209 mem_rid = pci_msix_table_bar(dev); 1210 sc->pcie_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1211 &mem_rid, RF_ACTIVE); 1212 if (sc->pcie_mem == NULL) { 1213 device_printf(dev, 1214 "Failed to allocate BAR for MSI-X table\n"); 1215 } else { 1216 error = pci_alloc_msix(dev, &count); 1217 if (error == 0) 1218 rid = 1; 1219 } 1220 } 1221 1222 if (rid < 0 && pci_msi_count(dev) > 0) { 1223 count = 1; 1224 error = pci_alloc_msi(dev, &count); 1225 if (error == 0) 1226 rid = 1; 1227 } 1228 1229 if (rid < 0) 1230 rid = 0; 1231 1232 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1233 RF_ACTIVE | RF_SHAREABLE); 1234 if (sc->pcie_irq == NULL) { 1235 device_printf(dev, 1236 "Failed to allocate interrupt for PCI-e events\n"); 1237 if (rid > 0) 1238 pci_release_msi(dev); 1239 return (ENXIO); 1240 } 1241 1242 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC|INTR_MPSAFE, 1243 NULL, pcib_pcie_intr_hotplug, sc, &sc->pcie_ihand); 1244 if (error) { 1245 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1246 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1247 if (rid > 0) 1248 pci_release_msi(dev); 1249 return (error); 1250 } 1251 return (0); 1252 } 1253 1254 static int 1255 pcib_release_pcie_irq(struct pcib_softc *sc) 1256 { 1257 device_t dev; 1258 int error; 1259 1260 dev = sc->dev; 1261 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1262 if (error) 1263 return (error); 1264 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1265 if (error) 1266 return (error); 1267 error = pci_release_msi(dev); 1268 if (error) 1269 return (error); 1270 if (sc->pcie_mem != NULL) 1271 error = bus_free_resource(dev, SYS_RES_MEMORY, sc->pcie_mem); 1272 return (error); 1273 } 1274 1275 static void 1276 pcib_setup_hotplug(struct pcib_softc *sc) 1277 { 1278 device_t dev; 1279 uint16_t mask, val; 1280 1281 dev = sc->dev; 1282 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1283 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_ab_task, 0, 1284 pcib_pcie_ab_timeout, sc); 1285 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_cc_task, 0, 1286 pcib_pcie_cc_timeout, sc); 1287 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->pcie_dll_task, 0, 1288 pcib_pcie_dll_timeout, sc); 1289 sc->pcie_hp_lock = bus_topo_mtx(); 1290 1291 /* Allocate IRQ. */ 1292 if (pcib_alloc_pcie_irq(sc) != 0) 1293 return; 1294 1295 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1296 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1297 1298 /* Clear any events previously pending. */ 1299 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1300 1301 /* Enable HotPlug events. */ 1302 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1303 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1304 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1305 val = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | PCIEM_SLOT_CTL_PDCE; 1306 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1307 val |= PCIEM_SLOT_CTL_ABPE; 1308 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1309 val |= PCIEM_SLOT_CTL_PFDE; 1310 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1311 val |= PCIEM_SLOT_CTL_MRLSCE; 1312 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1313 val |= PCIEM_SLOT_CTL_CCIE; 1314 1315 /* Turn the attention indicator off. */ 1316 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1317 mask |= PCIEM_SLOT_CTL_AIC; 1318 val |= PCIEM_SLOT_CTL_AI_OFF; 1319 } 1320 1321 pcib_pcie_hotplug_update(sc, val, mask, false); 1322 } 1323 1324 static int 1325 pcib_detach_hotplug(struct pcib_softc *sc) 1326 { 1327 uint16_t mask, val; 1328 int error; 1329 1330 /* Disable the card in the slot and force it to detach. */ 1331 if (sc->flags & PCIB_DETACH_PENDING) { 1332 sc->flags &= ~PCIB_DETACH_PENDING; 1333 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_ab_task, 1334 NULL); 1335 } 1336 sc->flags |= PCIB_DETACHING; 1337 1338 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1339 taskqueue_cancel_timeout(taskqueue_bus, &sc->pcie_cc_task, 1340 NULL); 1341 tsleep(sc, 0, "hpcmd", hz); 1342 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1343 } 1344 1345 /* Disable HotPlug events. */ 1346 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1347 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1348 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1349 val = 0; 1350 1351 /* Turn the attention indicator off. */ 1352 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1353 mask |= PCIEM_SLOT_CTL_AIC; 1354 val |= PCIEM_SLOT_CTL_AI_OFF; 1355 } 1356 1357 pcib_pcie_hotplug_update(sc, val, mask, false); 1358 1359 error = pcib_release_pcie_irq(sc); 1360 if (error) 1361 return (error); 1362 taskqueue_drain(taskqueue_bus, &sc->pcie_hp_task); 1363 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_ab_task); 1364 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_cc_task); 1365 taskqueue_drain_timeout(taskqueue_bus, &sc->pcie_dll_task); 1366 return (0); 1367 } 1368 #endif 1369 1370 /* 1371 * Restore previous bridge configuration. 1372 */ 1373 static void 1374 pcib_cfg_restore(struct pcib_softc *sc) 1375 { 1376 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1377 } 1378 1379 /* 1380 * Generic device interface 1381 */ 1382 static int 1383 pcib_probe(device_t dev) 1384 { 1385 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1386 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1387 device_set_desc(dev, "PCI-PCI bridge"); 1388 return(-10000); 1389 } 1390 return(ENXIO); 1391 } 1392 1393 void 1394 pcib_attach_common(device_t dev) 1395 { 1396 struct pcib_softc *sc; 1397 struct sysctl_ctx_list *sctx; 1398 struct sysctl_oid *soid; 1399 int comma; 1400 1401 sc = device_get_softc(dev); 1402 sc->dev = dev; 1403 1404 /* 1405 * Get current bridge configuration. 1406 */ 1407 sc->domain = pci_get_domain(dev); 1408 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1409 1410 /* 1411 * The primary bus register should always be the bus of the 1412 * parent. 1413 */ 1414 sc->pribus = pci_get_bus(dev); 1415 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1416 1417 /* 1418 * Setup sysctl reporting nodes 1419 */ 1420 sctx = device_get_sysctl_ctx(dev); 1421 soid = device_get_sysctl_tree(dev); 1422 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1423 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1424 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1425 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1426 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1427 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1428 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1429 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1430 1431 /* 1432 * Quirk handling. 1433 */ 1434 switch (pci_get_devid(dev)) { 1435 /* 1436 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1437 * and it is a subtractive bridge. However, the ProgIf is wrong 1438 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1439 * happen. There are also Toshiba and Cavium ThunderX bridges 1440 * that behave this way. 1441 */ 1442 case 0xa002177d: /* Cavium ThunderX */ 1443 case 0x124b8086: /* Intel 82380FB Mobile */ 1444 case 0x060513d7: /* Toshiba ???? */ 1445 sc->flags |= PCIB_SUBTRACTIVE; 1446 break; 1447 } 1448 1449 if (pci_msi_device_blacklisted(dev)) 1450 sc->flags |= PCIB_DISABLE_MSI; 1451 1452 if (pci_msix_device_blacklisted(dev)) 1453 sc->flags |= PCIB_DISABLE_MSIX; 1454 1455 /* 1456 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1457 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1458 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1459 * This means they act as if they were subtractively decoding 1460 * bridges and pass all transactions. Mark them and real ProgIf 1 1461 * parts as subtractive. 1462 */ 1463 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1464 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1465 sc->flags |= PCIB_SUBTRACTIVE; 1466 1467 #ifdef PCI_HP 1468 pcib_probe_hotplug(sc); 1469 #endif 1470 pcib_setup_secbus(dev, &sc->bus, 1); 1471 pcib_probe_windows(sc); 1472 #ifdef PCI_HP 1473 if (sc->flags & PCIB_HOTPLUG) 1474 pcib_setup_hotplug(sc); 1475 #endif 1476 if (bootverbose) { 1477 device_printf(dev, " domain %d\n", sc->domain); 1478 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1479 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1480 if (pcib_is_window_open(&sc->io)) 1481 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1482 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1483 if (pcib_is_window_open(&sc->mem)) 1484 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1485 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1486 if (pcib_is_window_open(&sc->pmem)) 1487 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1488 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1489 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1490 sc->flags & PCIB_SUBTRACTIVE) { 1491 device_printf(dev, " special decode "); 1492 comma = 0; 1493 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1494 printf("ISA"); 1495 comma = 1; 1496 } 1497 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1498 printf("%sVGA", comma ? ", " : ""); 1499 comma = 1; 1500 } 1501 if (sc->flags & PCIB_SUBTRACTIVE) 1502 printf("%ssubtractive", comma ? ", " : ""); 1503 printf("\n"); 1504 } 1505 } 1506 1507 /* 1508 * Always enable busmastering on bridges so that transactions 1509 * initiated on the secondary bus are passed through to the 1510 * primary bus. 1511 */ 1512 pci_enable_busmaster(dev); 1513 } 1514 1515 #ifdef PCI_HP 1516 static int 1517 pcib_present(struct pcib_softc *sc) 1518 { 1519 1520 if (sc->flags & PCIB_HOTPLUG) 1521 return (pcib_hotplug_present(sc) != 0); 1522 return (1); 1523 } 1524 #endif 1525 1526 int 1527 pcib_attach_child(device_t dev) 1528 { 1529 struct pcib_softc *sc; 1530 1531 sc = device_get_softc(dev); 1532 if (sc->bus.sec == 0) { 1533 /* no secondary bus; we should have fixed this */ 1534 return(0); 1535 } 1536 1537 #ifdef PCI_HP 1538 if (!pcib_present(sc)) { 1539 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1540 return (0); 1541 } 1542 #endif 1543 1544 sc->child = device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1545 bus_attach_children(dev); 1546 return (0); 1547 } 1548 1549 int 1550 pcib_attach(device_t dev) 1551 { 1552 1553 pcib_attach_common(dev); 1554 return (pcib_attach_child(dev)); 1555 } 1556 1557 int 1558 pcib_detach(device_t dev) 1559 { 1560 struct pcib_softc *sc; 1561 int error; 1562 1563 sc = device_get_softc(dev); 1564 error = bus_detach_children(dev); 1565 if (error) 1566 return (error); 1567 #ifdef PCI_HP 1568 if (sc->flags & PCIB_HOTPLUG) { 1569 error = pcib_detach_hotplug(sc); 1570 if (error) 1571 return (error); 1572 } 1573 #endif 1574 error = device_delete_children(dev); 1575 if (error) 1576 return (error); 1577 pcib_free_windows(sc); 1578 pcib_free_secbus(dev, &sc->bus); 1579 return (0); 1580 } 1581 1582 int 1583 pcib_resume(device_t dev) 1584 { 1585 1586 pcib_cfg_restore(device_get_softc(dev)); 1587 1588 /* 1589 * Restore the Command register only after restoring the windows. 1590 * The bridge should not be claiming random windows. 1591 */ 1592 pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2); 1593 return (bus_generic_resume(dev)); 1594 } 1595 1596 void 1597 pcib_bridge_init(device_t dev) 1598 { 1599 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1600 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1601 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1602 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1603 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1604 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1605 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1606 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1607 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1608 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1609 } 1610 1611 int 1612 pcib_child_present(device_t dev, device_t child) 1613 { 1614 #ifdef PCI_HP 1615 struct pcib_softc *sc = device_get_softc(dev); 1616 int retval; 1617 1618 retval = bus_child_present(dev); 1619 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1620 retval = pcib_hotplug_present(sc); 1621 return (retval); 1622 #else 1623 return (bus_child_present(dev)); 1624 #endif 1625 } 1626 1627 int 1628 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1629 { 1630 struct pcib_softc *sc = device_get_softc(dev); 1631 1632 switch (which) { 1633 case PCIB_IVAR_DOMAIN: 1634 *result = sc->domain; 1635 return(0); 1636 case PCIB_IVAR_BUS: 1637 *result = sc->bus.sec; 1638 return(0); 1639 } 1640 return(ENOENT); 1641 } 1642 1643 int 1644 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1645 { 1646 1647 switch (which) { 1648 case PCIB_IVAR_DOMAIN: 1649 return(EINVAL); 1650 case PCIB_IVAR_BUS: 1651 return(EINVAL); 1652 } 1653 return(ENOENT); 1654 } 1655 1656 /* 1657 * Attempt to allocate a resource from the existing resources assigned 1658 * to a window. 1659 */ 1660 static struct resource * 1661 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1662 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1663 rman_res_t count, u_int flags) 1664 { 1665 struct resource *res; 1666 1667 if (!pcib_is_window_open(w)) 1668 return (NULL); 1669 1670 res = rman_reserve_resource(&w->rman, start, end, count, 1671 flags & ~RF_ACTIVE, child); 1672 if (res == NULL) 1673 return (NULL); 1674 1675 if (bootverbose) 1676 device_printf(sc->dev, 1677 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1678 w->name, rman_get_start(res), rman_get_end(res), *rid, 1679 pcib_child_name(child)); 1680 rman_set_rid(res, *rid); 1681 rman_set_type(res, type); 1682 1683 if (flags & RF_ACTIVE) { 1684 if (bus_activate_resource(child, type, *rid, res) != 0) { 1685 rman_release_resource(res); 1686 return (NULL); 1687 } 1688 } 1689 1690 return (res); 1691 } 1692 1693 /* Allocate a fresh resource range for an unconfigured window. */ 1694 static int 1695 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1696 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1697 { 1698 struct resource *res; 1699 rman_res_t base, limit, wmask; 1700 int rid; 1701 1702 /* 1703 * If this is an I/O window on a bridge with ISA enable set 1704 * and the start address is below 64k, then try to allocate an 1705 * initial window of 0x1000 bytes long starting at address 1706 * 0xf000 and walking down. Note that if the original request 1707 * was larger than the non-aliased range size of 0x100 our 1708 * caller would have raised the start address up to 64k 1709 * already. 1710 */ 1711 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1712 start < 65536) { 1713 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1714 limit = base + 0xfff; 1715 1716 /* 1717 * Skip ranges that wouldn't work for the 1718 * original request. Note that the actual 1719 * window that overlaps are the non-alias 1720 * ranges within [base, limit], so this isn't 1721 * quite a simple comparison. 1722 */ 1723 if (start + count > limit - 0x400) 1724 continue; 1725 if (base == 0) { 1726 /* 1727 * The first open region for the window at 1728 * 0 is 0x400-0x4ff. 1729 */ 1730 if (end - count + 1 < 0x400) 1731 continue; 1732 } else { 1733 if (end - count + 1 < base) 1734 continue; 1735 } 1736 1737 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1738 w->base = base; 1739 w->limit = limit; 1740 return (0); 1741 } 1742 } 1743 return (ENOSPC); 1744 } 1745 1746 wmask = ((rman_res_t)1 << w->step) - 1; 1747 if (RF_ALIGNMENT(flags) < w->step) { 1748 flags &= ~RF_ALIGNMENT_MASK; 1749 flags |= RF_ALIGNMENT_LOG2(w->step); 1750 } 1751 start &= ~wmask; 1752 end |= wmask; 1753 count = roundup2(count, (rman_res_t)1 << w->step); 1754 rid = w->reg; 1755 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1756 flags | RF_ACTIVE | RF_UNMAPPED); 1757 if (res == NULL) 1758 return (ENOSPC); 1759 pcib_add_window_resources(w, &res, 1); 1760 pcib_activate_window(sc, type); 1761 w->base = rman_get_start(res); 1762 w->limit = rman_get_end(res); 1763 return (0); 1764 } 1765 1766 /* Try to expand an existing window to the requested base and limit. */ 1767 static int 1768 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1769 rman_res_t base, rman_res_t limit) 1770 { 1771 struct resource *res; 1772 int error, i, force_64k_base; 1773 1774 KASSERT(base <= w->base && limit >= w->limit, 1775 ("attempting to shrink window")); 1776 1777 /* 1778 * XXX: pcib_grow_window() doesn't try to do this anyway and 1779 * the error handling for all the edge cases would be tedious. 1780 */ 1781 KASSERT(limit == w->limit || base == w->base, 1782 ("attempting to grow both ends of a window")); 1783 1784 /* 1785 * Yet more special handling for requests to expand an I/O 1786 * window behind an ISA-enabled bridge. Since I/O windows 1787 * have to grow in 0x1000 increments and the end of the 0xffff 1788 * range is an alias, growing a window below 64k will always 1789 * result in allocating new resources and never adjusting an 1790 * existing resource. 1791 */ 1792 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1793 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1794 KASSERT(limit == w->limit || limit <= 65535, 1795 ("attempting to grow both ends across 64k ISA alias")); 1796 1797 if (base != w->base) 1798 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1799 else 1800 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1801 limit); 1802 if (error == 0) { 1803 w->base = base; 1804 w->limit = limit; 1805 } 1806 return (error); 1807 } 1808 1809 /* 1810 * Find the existing resource to adjust. Usually there is only one, 1811 * but for an ISA-enabled bridge we might be growing the I/O window 1812 * above 64k and need to find the existing resource that maps all 1813 * of the area above 64k. 1814 */ 1815 for (i = 0; i < w->count; i++) { 1816 if (rman_get_end(w->res[i]) == w->limit) 1817 break; 1818 } 1819 KASSERT(i != w->count, ("did not find existing resource")); 1820 res = w->res[i]; 1821 1822 /* 1823 * Usually the resource we found should match the window's 1824 * existing range. The one exception is the ISA-enabled case 1825 * mentioned above in which case the resource should start at 1826 * 64k. 1827 */ 1828 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1829 w->base <= 65535) { 1830 KASSERT(rman_get_start(res) == 65536, 1831 ("existing resource mismatch")); 1832 force_64k_base = 1; 1833 } else { 1834 KASSERT(w->base == rman_get_start(res), 1835 ("existing resource mismatch")); 1836 force_64k_base = 0; 1837 } 1838 1839 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1840 rman_get_start(res) : base, limit); 1841 if (error) 1842 return (error); 1843 1844 /* Add the newly allocated region to the resource manager. */ 1845 if (w->base != base) { 1846 error = rman_manage_region(&w->rman, base, w->base - 1); 1847 w->base = base; 1848 } else { 1849 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1850 w->limit = limit; 1851 } 1852 if (error) { 1853 if (bootverbose) 1854 device_printf(sc->dev, 1855 "failed to expand %s resource manager\n", w->name); 1856 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1857 rman_get_start(res) : w->base, w->limit); 1858 } 1859 return (error); 1860 } 1861 1862 /* 1863 * Attempt to grow a window to make room for a given resource request. 1864 */ 1865 static int 1866 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1867 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1868 { 1869 rman_res_t align, start_free, end_free, front, back, wmask; 1870 int error; 1871 1872 /* 1873 * Clamp the desired resource range to the maximum address 1874 * this window supports. Reject impossible requests. 1875 * 1876 * For I/O port requests behind a bridge with the ISA enable 1877 * bit set, force large allocations to start above 64k. 1878 */ 1879 if (!w->valid) 1880 return (EINVAL); 1881 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1882 start < 65536) 1883 start = 65536; 1884 if (end > w->rman.rm_end) 1885 end = w->rman.rm_end; 1886 if (start + count - 1 > end || start + count < start) 1887 return (EINVAL); 1888 wmask = ((rman_res_t)1 << w->step) - 1; 1889 1890 /* 1891 * If there is no resource at all, just try to allocate enough 1892 * aligned space for this resource. 1893 */ 1894 if (w->res == NULL) { 1895 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1896 flags); 1897 if (error) { 1898 if (bootverbose) 1899 device_printf(sc->dev, 1900 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 1901 w->name, start, end, count); 1902 return (error); 1903 } 1904 if (bootverbose) 1905 device_printf(sc->dev, 1906 "allocated initial %s window of %#jx-%#jx\n", 1907 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1908 goto updatewin; 1909 } 1910 1911 /* 1912 * See if growing the window would help. Compute the minimum 1913 * amount of address space needed on both the front and back 1914 * ends of the existing window to satisfy the allocation. 1915 * 1916 * For each end, build a candidate region adjusting for the 1917 * required alignment, etc. If there is a free region at the 1918 * edge of the window, grow from the inner edge of the free 1919 * region. Otherwise grow from the window boundary. 1920 * 1921 * Growing an I/O window below 64k for a bridge with the ISA 1922 * enable bit doesn't require any special magic as the step 1923 * size of an I/O window (1k) always includes multiple 1924 * non-alias ranges when it is grown in either direction. 1925 * 1926 * XXX: Special case: if w->res is completely empty and the 1927 * request size is larger than w->res, we should find the 1928 * optimal aligned buffer containing w->res and allocate that. 1929 */ 1930 if (bootverbose) 1931 device_printf(sc->dev, 1932 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 1933 w->name, start, end, count); 1934 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 1935 if (start < w->base) { 1936 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1937 0 || start_free != w->base) 1938 end_free = w->base; 1939 if (end_free > end) 1940 end_free = end + 1; 1941 1942 /* Move end_free down until it is properly aligned. */ 1943 end_free &= ~(align - 1); 1944 end_free--; 1945 front = end_free - (count - 1); 1946 1947 /* 1948 * The resource would now be allocated at (front, 1949 * end_free). Ensure that fits in the (start, end) 1950 * bounds. end_free is checked above. If 'front' is 1951 * ok, ensure it is properly aligned for this window. 1952 * Also check for underflow. 1953 */ 1954 if (front >= start && front <= end_free) { 1955 if (bootverbose) 1956 printf("\tfront candidate range: %#jx-%#jx\n", 1957 front, end_free); 1958 front &= ~wmask; 1959 front = w->base - front; 1960 } else 1961 front = 0; 1962 } else 1963 front = 0; 1964 if (end > w->limit) { 1965 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1966 0 || end_free != w->limit) 1967 start_free = w->limit + 1; 1968 if (start_free < start) 1969 start_free = start; 1970 1971 /* Move start_free up until it is properly aligned. */ 1972 start_free = roundup2(start_free, align); 1973 back = start_free + count - 1; 1974 1975 /* 1976 * The resource would now be allocated at (start_free, 1977 * back). Ensure that fits in the (start, end) 1978 * bounds. start_free is checked above. If 'back' is 1979 * ok, ensure it is properly aligned for this window. 1980 * Also check for overflow. 1981 */ 1982 if (back <= end && start_free <= back) { 1983 if (bootverbose) 1984 printf("\tback candidate range: %#jx-%#jx\n", 1985 start_free, back); 1986 back |= wmask; 1987 back -= w->limit; 1988 } else 1989 back = 0; 1990 } else 1991 back = 0; 1992 1993 /* 1994 * Try to allocate the smallest needed region first. 1995 * If that fails, fall back to the other region. 1996 */ 1997 error = ENOSPC; 1998 while (front != 0 || back != 0) { 1999 if (front != 0 && (front <= back || back == 0)) { 2000 error = pcib_expand_window(sc, w, type, w->base - front, 2001 w->limit); 2002 if (error == 0) 2003 break; 2004 front = 0; 2005 } else { 2006 error = pcib_expand_window(sc, w, type, w->base, 2007 w->limit + back); 2008 if (error == 0) 2009 break; 2010 back = 0; 2011 } 2012 } 2013 2014 if (error) 2015 return (error); 2016 if (bootverbose) 2017 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2018 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2019 2020 updatewin: 2021 /* Write the new window. */ 2022 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2023 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2024 pcib_write_windows(sc, w->mask); 2025 return (0); 2026 } 2027 2028 /* 2029 * We have to trap resource allocation requests and ensure that the bridge 2030 * is set up to, or capable of handling them. 2031 */ 2032 static struct resource * 2033 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2034 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2035 { 2036 struct pcib_softc *sc; 2037 struct resource *r; 2038 2039 sc = device_get_softc(dev); 2040 2041 /* 2042 * VGA resources are decoded iff the VGA enable bit is set in 2043 * the bridge control register. VGA resources do not fall into 2044 * the resource windows and are passed up to the parent. 2045 */ 2046 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2047 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2048 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2049 return (bus_generic_alloc_resource(dev, child, type, 2050 rid, start, end, count, flags)); 2051 else 2052 return (NULL); 2053 } 2054 2055 switch (type) { 2056 case PCI_RES_BUS: 2057 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2058 count, flags)); 2059 case SYS_RES_IOPORT: 2060 if (pcib_is_isa_range(sc, start, end, count)) 2061 return (NULL); 2062 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2063 end, count, flags); 2064 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2065 break; 2066 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2067 flags) == 0) 2068 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2069 rid, start, end, count, flags); 2070 break; 2071 case SYS_RES_MEMORY: 2072 /* 2073 * For prefetchable resources, prefer the prefetchable 2074 * memory window, but fall back to the regular memory 2075 * window if that fails. Try both windows before 2076 * attempting to grow a window in case the firmware 2077 * has used a range in the regular memory window to 2078 * map a prefetchable BAR. 2079 */ 2080 if (flags & RF_PREFETCHABLE) { 2081 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2082 rid, start, end, count, flags); 2083 if (r != NULL) 2084 break; 2085 } 2086 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2087 start, end, count, flags); 2088 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2089 break; 2090 if (flags & RF_PREFETCHABLE) { 2091 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2092 count, flags) == 0) { 2093 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2094 type, rid, start, end, count, flags); 2095 if (r != NULL) 2096 break; 2097 } 2098 } 2099 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2100 flags & ~RF_PREFETCHABLE) == 0) 2101 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2102 rid, start, end, count, flags); 2103 break; 2104 default: 2105 return (bus_generic_alloc_resource(dev, child, type, rid, 2106 start, end, count, flags)); 2107 } 2108 2109 /* 2110 * If attempts to suballocate from the window fail but this is a 2111 * subtractive bridge, pass the request up the tree. 2112 */ 2113 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2114 return (bus_generic_alloc_resource(dev, child, type, rid, 2115 start, end, count, flags)); 2116 return (r); 2117 } 2118 2119 static int 2120 pcib_adjust_resource(device_t bus, device_t child, struct resource *r, 2121 rman_res_t start, rman_res_t end) 2122 { 2123 struct pcib_softc *sc; 2124 struct pcib_window *w; 2125 rman_res_t wmask; 2126 int error, type; 2127 2128 sc = device_get_softc(bus); 2129 type = rman_get_type(r); 2130 2131 /* 2132 * If the resource wasn't sub-allocated from one of our region 2133 * managers then just pass the request up. 2134 */ 2135 if (!pcib_is_resource_managed(sc, r)) 2136 return (bus_generic_adjust_resource(bus, child, r, start, end)); 2137 2138 if (type == PCI_RES_BUS) { 2139 /* 2140 * If our bus range isn't big enough to grow the sub-allocation 2141 * then we need to grow our bus range. Any request that would 2142 * require us to decrease the start of our own bus range is 2143 * invalid, we can only extend the end; ignore such requests 2144 * and let rman_adjust_resource fail below. 2145 */ 2146 if (start >= sc->bus.sec && end > sc->bus.sub) { 2147 error = pcib_grow_subbus(&sc->bus, end); 2148 if (error != 0) 2149 return (error); 2150 } 2151 } else { 2152 /* 2153 * Resource is managed and not a secondary bus number, must 2154 * be from one of our windows. 2155 */ 2156 w = pcib_get_resource_window(sc, r); 2157 KASSERT(w != NULL, 2158 ("%s: no window for resource (%#jx-%#jx) type %d", 2159 __func__, rman_get_start(r), rman_get_end(r), type)); 2160 2161 /* 2162 * If our window isn't big enough to grow the sub-allocation 2163 * then we need to expand the window. 2164 */ 2165 if (start < w->base || end > w->limit) { 2166 wmask = ((rman_res_t)1 << w->step) - 1; 2167 error = pcib_expand_window(sc, w, type, 2168 MIN(start & ~wmask, w->base), 2169 MAX(end | wmask, w->limit)); 2170 if (error != 0) 2171 return (error); 2172 if (bootverbose) 2173 device_printf(sc->dev, 2174 "grew %s window to %#jx-%#jx\n", 2175 w->name, (uintmax_t)w->base, 2176 (uintmax_t)w->limit); 2177 pcib_write_windows(sc, w->mask); 2178 } 2179 } 2180 2181 return (rman_adjust_resource(r, start, end)); 2182 } 2183 2184 static int 2185 pcib_release_resource(device_t dev, device_t child, struct resource *r) 2186 { 2187 struct pcib_softc *sc; 2188 int error; 2189 2190 sc = device_get_softc(dev); 2191 if (pcib_is_resource_managed(sc, r)) { 2192 if (rman_get_flags(r) & RF_ACTIVE) { 2193 error = bus_deactivate_resource(child, r); 2194 if (error) 2195 return (error); 2196 } 2197 return (rman_release_resource(r)); 2198 } 2199 return (bus_generic_release_resource(dev, child, r)); 2200 } 2201 2202 static int 2203 pcib_activate_resource(device_t dev, device_t child, struct resource *r) 2204 { 2205 struct pcib_softc *sc = device_get_softc(dev); 2206 struct resource_map map; 2207 int error, type; 2208 2209 if (!pcib_is_resource_managed(sc, r)) 2210 return (bus_generic_activate_resource(dev, child, r)); 2211 2212 error = rman_activate_resource(r); 2213 if (error != 0) 2214 return (error); 2215 2216 type = rman_get_type(r); 2217 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2218 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2219 error = BUS_MAP_RESOURCE(dev, child, r, NULL, &map); 2220 if (error != 0) { 2221 rman_deactivate_resource(r); 2222 return (error); 2223 } 2224 2225 rman_set_mapping(r, &map); 2226 } 2227 return (0); 2228 } 2229 2230 static int 2231 pcib_deactivate_resource(device_t dev, device_t child, struct resource *r) 2232 { 2233 struct pcib_softc *sc = device_get_softc(dev); 2234 struct resource_map map; 2235 int error, type; 2236 2237 if (!pcib_is_resource_managed(sc, r)) 2238 return (bus_generic_deactivate_resource(dev, child, r)); 2239 2240 error = rman_deactivate_resource(r); 2241 if (error != 0) 2242 return (error); 2243 2244 type = rman_get_type(r); 2245 if ((rman_get_flags(r) & RF_UNMAPPED) == 0 && 2246 (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT)) { 2247 rman_get_mapping(r, &map); 2248 BUS_UNMAP_RESOURCE(dev, child, r, &map); 2249 } 2250 return (0); 2251 } 2252 2253 static struct resource * 2254 pcib_find_parent_resource(struct pcib_window *w, struct resource *r) 2255 { 2256 for (int i = 0; i < w->count; i++) { 2257 if (rman_get_start(w->res[i]) <= rman_get_start(r) && 2258 rman_get_end(w->res[i]) >= rman_get_end(r)) 2259 return (w->res[i]); 2260 } 2261 return (NULL); 2262 } 2263 2264 static int 2265 pcib_map_resource(device_t dev, device_t child, struct resource *r, 2266 struct resource_map_request *argsp, struct resource_map *map) 2267 { 2268 struct pcib_softc *sc = device_get_softc(dev); 2269 struct resource_map_request args; 2270 struct pcib_window *w; 2271 struct resource *pres; 2272 rman_res_t length, start; 2273 int error; 2274 2275 w = pcib_get_resource_window(sc, r); 2276 if (w == NULL) 2277 return (bus_generic_map_resource(dev, child, r, argsp, map)); 2278 2279 /* Resources must be active to be mapped. */ 2280 if (!(rman_get_flags(r) & RF_ACTIVE)) 2281 return (ENXIO); 2282 2283 resource_init_map_request(&args); 2284 error = resource_validate_map_request(r, argsp, &args, &start, &length); 2285 if (error) 2286 return (error); 2287 2288 pres = pcib_find_parent_resource(w, r); 2289 if (pres == NULL) 2290 return (ENOENT); 2291 2292 args.offset = start - rman_get_start(pres); 2293 args.length = length; 2294 return (bus_map_resource(dev, pres, &args, map)); 2295 } 2296 2297 static int 2298 pcib_unmap_resource(device_t dev, device_t child, struct resource *r, 2299 struct resource_map *map) 2300 { 2301 struct pcib_softc *sc = device_get_softc(dev); 2302 struct pcib_window *w; 2303 struct resource *pres; 2304 2305 w = pcib_get_resource_window(sc, r); 2306 if (w == NULL) 2307 return (bus_generic_unmap_resource(dev, child, r, map)); 2308 2309 pres = pcib_find_parent_resource(w, r); 2310 if (pres == NULL) 2311 return (ENOENT); 2312 return (bus_unmap_resource(dev, pres, map)); 2313 } 2314 2315 /* 2316 * If ARI is enabled on this downstream port, translate the function number 2317 * to the non-ARI slot/function. The downstream port will convert it back in 2318 * hardware. If ARI is not enabled slot and func are not modified. 2319 */ 2320 static __inline void 2321 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2322 { 2323 struct pcib_softc *sc; 2324 int ari_func; 2325 2326 sc = device_get_softc(pcib); 2327 ari_func = *func; 2328 2329 if (sc->flags & PCIB_ENABLE_ARI) { 2330 KASSERT(*slot == 0, 2331 ("Non-zero slot number with ARI enabled!")); 2332 *slot = PCIE_ARI_SLOT(ari_func); 2333 *func = PCIE_ARI_FUNC(ari_func); 2334 } 2335 } 2336 2337 static void 2338 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2339 { 2340 uint32_t ctl2; 2341 2342 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2343 ctl2 |= PCIEM_CTL2_ARI; 2344 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2345 2346 sc->flags |= PCIB_ENABLE_ARI; 2347 } 2348 2349 /* 2350 * PCIB interface. 2351 */ 2352 int 2353 pcib_maxslots(device_t dev) 2354 { 2355 #if !defined(__amd64__) && !defined(__i386__) 2356 uint32_t pcie_pos; 2357 uint16_t val; 2358 2359 /* 2360 * If this is a PCIe rootport or downstream switch port, there's only 2361 * one slot permitted. 2362 */ 2363 if (pci_find_cap(dev, PCIY_EXPRESS, &pcie_pos) == 0) { 2364 val = pci_read_config(dev, pcie_pos + PCIER_FLAGS, 2); 2365 val &= PCIEM_FLAGS_TYPE; 2366 if (val == PCIEM_TYPE_ROOT_PORT || 2367 val == PCIEM_TYPE_DOWNSTREAM_PORT) 2368 return (0); 2369 } 2370 #endif 2371 return (PCI_SLOTMAX); 2372 } 2373 2374 static int 2375 pcib_ari_maxslots(device_t dev) 2376 { 2377 struct pcib_softc *sc; 2378 2379 sc = device_get_softc(dev); 2380 2381 if (sc->flags & PCIB_ENABLE_ARI) 2382 return (PCIE_ARI_SLOTMAX); 2383 else 2384 return (pcib_maxslots(dev)); 2385 } 2386 2387 static int 2388 pcib_ari_maxfuncs(device_t dev) 2389 { 2390 struct pcib_softc *sc; 2391 2392 sc = device_get_softc(dev); 2393 2394 if (sc->flags & PCIB_ENABLE_ARI) 2395 return (PCIE_ARI_FUNCMAX); 2396 else 2397 return (PCI_FUNCMAX); 2398 } 2399 2400 static void 2401 pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2402 int *func) 2403 { 2404 struct pcib_softc *sc; 2405 2406 sc = device_get_softc(pcib); 2407 2408 *bus = PCI_RID2BUS(rid); 2409 if (sc->flags & PCIB_ENABLE_ARI) { 2410 *slot = PCIE_ARI_RID2SLOT(rid); 2411 *func = PCIE_ARI_RID2FUNC(rid); 2412 } else { 2413 *slot = PCI_RID2SLOT(rid); 2414 *func = PCI_RID2FUNC(rid); 2415 } 2416 } 2417 2418 /* 2419 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2420 */ 2421 static uint32_t 2422 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2423 { 2424 #ifdef PCI_HP 2425 struct pcib_softc *sc; 2426 2427 sc = device_get_softc(dev); 2428 if (!pcib_present(sc)) { 2429 switch (width) { 2430 case 2: 2431 return (0xffff); 2432 case 1: 2433 return (0xff); 2434 default: 2435 return (0xffffffff); 2436 } 2437 } 2438 #endif 2439 pcib_xlate_ari(dev, b, &s, &f); 2440 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2441 f, reg, width)); 2442 } 2443 2444 static void 2445 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2446 { 2447 #ifdef PCI_HP 2448 struct pcib_softc *sc; 2449 2450 sc = device_get_softc(dev); 2451 if (!pcib_present(sc)) 2452 return; 2453 #endif 2454 pcib_xlate_ari(dev, b, &s, &f); 2455 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2456 reg, val, width); 2457 } 2458 2459 /* 2460 * Route an interrupt across a PCI bridge. 2461 */ 2462 int 2463 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2464 { 2465 device_t bus; 2466 int parent_intpin; 2467 int intnum; 2468 2469 /* 2470 * 2471 * The PCI standard defines a swizzle of the child-side device/intpin to 2472 * the parent-side intpin as follows. 2473 * 2474 * device = device on child bus 2475 * child_intpin = intpin on child bus slot (0-3) 2476 * parent_intpin = intpin on parent bus slot (0-3) 2477 * 2478 * parent_intpin = (device + child_intpin) % 4 2479 */ 2480 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2481 2482 /* 2483 * Our parent is a PCI bus. Its parent must export the pcib interface 2484 * which includes the ability to route interrupts. 2485 */ 2486 bus = device_get_parent(pcib); 2487 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2488 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2489 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2490 pci_get_slot(dev), 'A' + pin - 1, intnum); 2491 } 2492 return(intnum); 2493 } 2494 2495 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2496 int 2497 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2498 { 2499 struct pcib_softc *sc = device_get_softc(pcib); 2500 device_t bus; 2501 2502 if (sc->flags & PCIB_DISABLE_MSI) 2503 return (ENXIO); 2504 bus = device_get_parent(pcib); 2505 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2506 irqs)); 2507 } 2508 2509 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2510 int 2511 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2512 { 2513 device_t bus; 2514 2515 bus = device_get_parent(pcib); 2516 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2517 } 2518 2519 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 2520 int 2521 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2522 { 2523 struct pcib_softc *sc = device_get_softc(pcib); 2524 device_t bus; 2525 2526 if (sc->flags & PCIB_DISABLE_MSIX) 2527 return (ENXIO); 2528 bus = device_get_parent(pcib); 2529 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2530 } 2531 2532 /* Pass request to release an MSI-X message up to the parent bridge. */ 2533 int 2534 pcib_release_msix(device_t pcib, device_t dev, int irq) 2535 { 2536 device_t bus; 2537 2538 bus = device_get_parent(pcib); 2539 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2540 } 2541 2542 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 2543 int 2544 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2545 uint32_t *data) 2546 { 2547 device_t bus; 2548 int error; 2549 2550 bus = device_get_parent(pcib); 2551 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2552 if (error) 2553 return (error); 2554 2555 pci_ht_map_msi(pcib, *addr); 2556 return (0); 2557 } 2558 2559 /* Pass request for device power state up to parent bridge. */ 2560 int 2561 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2562 { 2563 device_t bus; 2564 2565 bus = device_get_parent(pcib); 2566 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2567 } 2568 2569 static int 2570 pcib_ari_enabled(device_t pcib) 2571 { 2572 struct pcib_softc *sc; 2573 2574 sc = device_get_softc(pcib); 2575 2576 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2577 } 2578 2579 static int 2580 pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2581 uintptr_t *id) 2582 { 2583 struct pcib_softc *sc; 2584 device_t bus_dev; 2585 uint8_t bus, slot, func; 2586 2587 if (type != PCI_ID_RID) { 2588 bus_dev = device_get_parent(pcib); 2589 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2590 } 2591 2592 sc = device_get_softc(pcib); 2593 2594 if (sc->flags & PCIB_ENABLE_ARI) { 2595 bus = pci_get_bus(dev); 2596 func = pci_get_function(dev); 2597 2598 *id = (PCI_ARI_RID(bus, func)); 2599 } else { 2600 bus = pci_get_bus(dev); 2601 slot = pci_get_slot(dev); 2602 func = pci_get_function(dev); 2603 2604 *id = (PCI_RID(bus, slot, func)); 2605 } 2606 2607 return (0); 2608 } 2609 2610 /* 2611 * Check that the downstream port (pcib) and the endpoint device (dev) both 2612 * support ARI. If so, enable it and return 0, otherwise return an error. 2613 */ 2614 static int 2615 pcib_try_enable_ari(device_t pcib, device_t dev) 2616 { 2617 struct pcib_softc *sc; 2618 int error; 2619 uint32_t cap2; 2620 int ari_cap_off; 2621 uint32_t ari_ver; 2622 uint32_t pcie_pos; 2623 2624 sc = device_get_softc(pcib); 2625 2626 /* 2627 * ARI is controlled in a register in the PCIe capability structure. 2628 * If the downstream port does not have the PCIe capability structure 2629 * then it does not support ARI. 2630 */ 2631 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2632 if (error != 0) 2633 return (ENODEV); 2634 2635 /* Check that the PCIe port advertises ARI support. */ 2636 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2637 if (!(cap2 & PCIEM_CAP2_ARI)) 2638 return (ENODEV); 2639 2640 /* 2641 * Check that the endpoint device advertises ARI support via the ARI 2642 * extended capability structure. 2643 */ 2644 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2645 if (error != 0) 2646 return (ENODEV); 2647 2648 /* 2649 * Finally, check that the endpoint device supports the same version 2650 * of ARI that we do. 2651 */ 2652 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2653 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2654 if (bootverbose) 2655 device_printf(pcib, 2656 "Unsupported version of ARI (%d) detected\n", 2657 PCI_EXTCAP_VER(ari_ver)); 2658 2659 return (ENXIO); 2660 } 2661 2662 pcib_enable_ari(sc, pcie_pos); 2663 2664 return (0); 2665 } 2666 2667 int 2668 pcib_request_feature_allow(device_t pcib, device_t dev, 2669 enum pci_feature feature) 2670 { 2671 /* 2672 * No host firmware we have to negotiate with, so we allow 2673 * every valid feature requested. 2674 */ 2675 switch (feature) { 2676 case PCI_FEATURE_AER: 2677 case PCI_FEATURE_HP: 2678 break; 2679 default: 2680 return (EINVAL); 2681 } 2682 2683 return (0); 2684 } 2685 2686 int 2687 pcib_request_feature(device_t dev, enum pci_feature feature) 2688 { 2689 2690 /* 2691 * Invoke PCIB_REQUEST_FEATURE of this bridge first in case 2692 * the firmware overrides the method of PCI-PCI bridges. 2693 */ 2694 return (PCIB_REQUEST_FEATURE(dev, dev, feature)); 2695 } 2696 2697 /* 2698 * Pass the request to use this PCI feature up the tree. Either there's a 2699 * firmware like ACPI that's using this feature that will approve (or deny) the 2700 * request to take it over, or the platform has no such firmware, in which case 2701 * the request will be approved. If the request is approved, the OS is expected 2702 * to make use of the feature or render it harmless. 2703 */ 2704 static int 2705 pcib_request_feature_default(device_t pcib, device_t dev, 2706 enum pci_feature feature) 2707 { 2708 device_t bus; 2709 2710 /* 2711 * Our parent is necessarily a pci bus. Its parent will either be 2712 * another pci bridge (which passes it up) or a host bridge that can 2713 * approve or reject the request. 2714 */ 2715 bus = device_get_parent(pcib); 2716 return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature)); 2717 } 2718 2719 static int 2720 pcib_reset_child(device_t dev, device_t child, int flags) 2721 { 2722 struct pci_devinfo *pdinfo; 2723 int error; 2724 2725 error = 0; 2726 if (dev == NULL || device_get_parent(child) != dev) 2727 goto out; 2728 error = ENXIO; 2729 if (device_get_devclass(child) != devclass_find("pci")) 2730 goto out; 2731 pdinfo = device_get_ivars(dev); 2732 if (pdinfo->cfg.pcie.pcie_location != 0 && 2733 (pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT || 2734 pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) { 2735 error = bus_helper_reset_prepare(child, flags); 2736 if (error == 0) { 2737 error = pcie_link_reset(dev, 2738 pdinfo->cfg.pcie.pcie_location); 2739 /* XXXKIB call _post even if error != 0 ? */ 2740 bus_helper_reset_post(child, flags); 2741 } 2742 } 2743 out: 2744 return (error); 2745 } 2746