1 /*- 2 * Copyright (c) 2013-2015 Sandvine Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_bus.h" 29 30 #include <sys/param.h> 31 #include <sys/conf.h> 32 #include <sys/kernel.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/fcntl.h> 36 #include <sys/ioccom.h> 37 #include <sys/iov.h> 38 #include <sys/linker.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/pciio.h> 44 #include <sys/queue.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/bus.h> 49 #include <machine/stdarg.h> 50 51 #include <sys/nv.h> 52 #include <sys/iov_schema.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pci_iov.h> 57 #include <dev/pci/pci_private.h> 58 #include <dev/pci/pci_iov_private.h> 59 #include <dev/pci/schema_private.h> 60 61 #include "pcib_if.h" 62 63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations"); 64 65 static d_ioctl_t pci_iov_ioctl; 66 67 static struct cdevsw iov_cdevsw = { 68 .d_version = D_VERSION, 69 .d_name = "iov", 70 .d_ioctl = pci_iov_ioctl 71 }; 72 73 SYSCTL_DECL(_hw_pci); 74 75 /* 76 * The maximum amount of memory we will allocate for user configuration of an 77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this 78 * configurable just in case. 79 */ 80 static u_long pci_iov_max_config = 1024 * 1024; 81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN, 82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration."); 83 84 #define IOV_READ(d, r, w) \ 85 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w) 86 87 #define IOV_WRITE(d, r, v, w) \ 88 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w) 89 90 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema, 91 nvlist_t **vf_schema); 92 static void pci_iov_build_pf_schema(nvlist_t *schema, 93 nvlist_t **driver_schema); 94 static void pci_iov_build_vf_schema(nvlist_t *schema, 95 nvlist_t **driver_schema); 96 static int pci_iov_delete_iov_children(struct pci_devinfo *dinfo); 97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void); 98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void); 99 100 int 101 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema, 102 struct nvlist *vf_schema, const char *fmt, ...) 103 { 104 char buf[NAME_MAX + 1]; 105 va_list ap; 106 107 va_start(ap, fmt); 108 vsnprintf(buf, sizeof(buf), fmt, ap); 109 va_end(ap); 110 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema, 111 vf_schema, buf)); 112 } 113 114 int 115 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema, 116 nvlist_t *vf_schema, const char *name) 117 { 118 struct pci_devinfo *dinfo; 119 struct pcicfg_iov *iov; 120 nvlist_t *schema; 121 uint32_t version; 122 int error; 123 int iov_pos; 124 125 dinfo = device_get_ivars(dev); 126 schema = NULL; 127 128 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 129 130 if (error != 0) 131 return (error); 132 133 version = pci_read_config(dev, iov_pos, 4); 134 if (PCI_EXTCAP_VER(version) != 1) { 135 if (bootverbose) 136 device_printf(dev, 137 "Unsupported version of SR-IOV (%d) detected\n", 138 PCI_EXTCAP_VER(version)); 139 140 return (ENXIO); 141 } 142 143 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO); 144 145 mtx_lock(&Giant); 146 if (dinfo->cfg.iov != NULL) { 147 error = EBUSY; 148 goto cleanup; 149 } 150 iov->iov_pf = dev; 151 iov->iov_pos = iov_pos; 152 153 schema = pci_iov_build_schema(&pf_schema, &vf_schema); 154 if (schema == NULL) { 155 error = ENOMEM; 156 goto cleanup; 157 } 158 159 error = pci_iov_validate_schema(schema); 160 if (error != 0) 161 goto cleanup; 162 iov->iov_schema = schema; 163 164 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev), 165 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name); 166 167 if (iov->iov_cdev == NULL) { 168 error = ENOMEM; 169 goto cleanup; 170 } 171 172 dinfo->cfg.iov = iov; 173 iov->iov_cdev->si_drv1 = dinfo; 174 mtx_unlock(&Giant); 175 176 return (0); 177 178 cleanup: 179 nvlist_destroy(schema); 180 nvlist_destroy(pf_schema); 181 nvlist_destroy(vf_schema); 182 free(iov, M_SRIOV); 183 mtx_unlock(&Giant); 184 return (error); 185 } 186 187 int 188 pci_iov_detach_method(device_t bus, device_t dev) 189 { 190 struct pci_devinfo *dinfo; 191 struct pcicfg_iov *iov; 192 int error; 193 194 mtx_lock(&Giant); 195 dinfo = device_get_ivars(dev); 196 iov = dinfo->cfg.iov; 197 198 if (iov == NULL) { 199 mtx_unlock(&Giant); 200 return (0); 201 } 202 203 if ((iov->iov_flags & IOV_BUSY) != 0) { 204 mtx_unlock(&Giant); 205 return (EBUSY); 206 } 207 208 error = pci_iov_delete_iov_children(dinfo); 209 if (error != 0) { 210 mtx_unlock(&Giant); 211 return (error); 212 } 213 214 dinfo->cfg.iov = NULL; 215 216 if (iov->iov_cdev) { 217 destroy_dev(iov->iov_cdev); 218 iov->iov_cdev = NULL; 219 } 220 nvlist_destroy(iov->iov_schema); 221 222 free(iov, M_SRIOV); 223 mtx_unlock(&Giant); 224 225 return (0); 226 } 227 228 static nvlist_t * 229 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf) 230 { 231 nvlist_t *schema, *pf_driver, *vf_driver; 232 233 /* We always take ownership of the schemas. */ 234 pf_driver = *pf; 235 *pf = NULL; 236 vf_driver = *vf; 237 *vf = NULL; 238 239 schema = pci_iov_schema_alloc_node(); 240 if (schema == NULL) 241 goto cleanup; 242 243 pci_iov_build_pf_schema(schema, &pf_driver); 244 pci_iov_build_vf_schema(schema, &vf_driver); 245 246 if (nvlist_error(schema) != 0) 247 goto cleanup; 248 249 return (schema); 250 251 cleanup: 252 nvlist_destroy(schema); 253 nvlist_destroy(pf_driver); 254 nvlist_destroy(vf_driver); 255 return (NULL); 256 } 257 258 static void 259 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema) 260 { 261 nvlist_t *pf_schema, *iov_schema; 262 263 pf_schema = pci_iov_schema_alloc_node(); 264 if (pf_schema == NULL) { 265 nvlist_set_error(schema, ENOMEM); 266 return; 267 } 268 269 iov_schema = pci_iov_get_pf_subsystem_schema(); 270 271 /* 272 * Note that if either *driver_schema or iov_schema is NULL, then 273 * nvlist_move_nvlist will put the schema in the error state and 274 * SR-IOV will fail to initialize later, so we don't have to explicitly 275 * handle that case. 276 */ 277 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema); 278 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema); 279 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema); 280 *driver_schema = NULL; 281 } 282 283 static void 284 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema) 285 { 286 nvlist_t *vf_schema, *iov_schema; 287 288 vf_schema = pci_iov_schema_alloc_node(); 289 if (vf_schema == NULL) { 290 nvlist_set_error(schema, ENOMEM); 291 return; 292 } 293 294 iov_schema = pci_iov_get_vf_subsystem_schema(); 295 296 /* 297 * Note that if either *driver_schema or iov_schema is NULL, then 298 * nvlist_move_nvlist will put the schema in the error state and 299 * SR-IOV will fail to initialize later, so we don't have to explicitly 300 * handle that case. 301 */ 302 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema); 303 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema); 304 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema); 305 *driver_schema = NULL; 306 } 307 308 static nvlist_t * 309 pci_iov_get_pf_subsystem_schema(void) 310 { 311 nvlist_t *pf; 312 313 pf = pci_iov_schema_alloc_node(); 314 if (pf == NULL) 315 return (NULL); 316 317 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1); 318 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL); 319 320 return (pf); 321 } 322 323 static nvlist_t * 324 pci_iov_get_vf_subsystem_schema(void) 325 { 326 nvlist_t *vf; 327 328 vf = pci_iov_schema_alloc_node(); 329 if (vf == NULL) 330 return (NULL); 331 332 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0); 333 334 return (vf); 335 } 336 337 static int 338 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift) 339 { 340 struct resource *res; 341 struct pcicfg_iov *iov; 342 device_t dev, bus; 343 rman_res_t start, end; 344 pci_addr_t bar_size; 345 int rid; 346 347 iov = dinfo->cfg.iov; 348 dev = dinfo->cfg.dev; 349 bus = device_get_parent(dev); 350 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar); 351 bar_size = 1 << bar_shift; 352 353 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0, 354 ~0, 1, iov->iov_num_vfs, RF_ACTIVE); 355 356 if (res == NULL) 357 return (ENXIO); 358 359 iov->iov_bar[bar].res = res; 360 iov->iov_bar[bar].bar_size = bar_size; 361 iov->iov_bar[bar].bar_shift = bar_shift; 362 363 start = rman_get_start(res); 364 end = rman_get_end(res); 365 return (rman_manage_region(&iov->rman, start, end)); 366 } 367 368 static void 369 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo) 370 { 371 struct pci_iov_bar *bar; 372 uint64_t bar_start; 373 int i; 374 375 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 376 bar = &iov->iov_bar[i]; 377 if (bar->res != NULL) { 378 bar_start = rman_get_start(bar->res) + 379 dinfo->cfg.vf.index * bar->bar_size; 380 381 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start, 382 bar->bar_shift); 383 } 384 } 385 } 386 387 static int 388 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg, 389 nvlist_t **ret) 390 { 391 void *packed_config; 392 nvlist_t *config; 393 int error; 394 395 config = NULL; 396 packed_config = NULL; 397 398 if (arg->len > pci_iov_max_config) { 399 error = EMSGSIZE; 400 goto out; 401 } 402 403 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK); 404 405 error = copyin(arg->config, packed_config, arg->len); 406 if (error != 0) 407 goto out; 408 409 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE); 410 if (config == NULL) { 411 error = EINVAL; 412 goto out; 413 } 414 415 error = pci_iov_schema_validate_config(iov->iov_schema, config); 416 if (error != 0) 417 goto out; 418 419 error = nvlist_error(config); 420 if (error != 0) 421 goto out; 422 423 *ret = config; 424 config = NULL; 425 426 out: 427 nvlist_destroy(config); 428 free(packed_config, M_SRIOV); 429 return (error); 430 } 431 432 /* 433 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV 434 * capability. This bit is only writeable on the lowest-numbered PF but 435 * affects all PFs on the device. 436 */ 437 static int 438 pci_iov_set_ari(device_t bus, bool *ari_enabled) 439 { 440 device_t lowest; 441 device_t *devlist; 442 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func; 443 uint16_t iov_ctl; 444 445 /* If ARI is disabled on the downstream port there is nothing to do. */ 446 if (!PCIB_ARI_ENABLED(device_get_parent(bus))) { 447 *ari_enabled = false; 448 return (0); 449 } 450 451 error = device_get_children(bus, &devlist, &devcount); 452 453 if (error != 0) 454 return (error); 455 456 lowest = NULL; 457 for (i = 0; i < devcount; i++) { 458 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) { 459 dev_func = pci_get_function(devlist[i]); 460 if (lowest == NULL || dev_func < lowest_func) { 461 lowest = devlist[i]; 462 lowest_func = dev_func; 463 lowest_pos = iov_pos; 464 } 465 } 466 } 467 free(devlist, M_TEMP); 468 469 /* 470 * If we called this function some device must have the SR-IOV 471 * capability. 472 */ 473 KASSERT(lowest != NULL, 474 ("Could not find child of %s with SR-IOV capability", 475 device_get_nameunit(bus))); 476 477 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2); 478 iov_ctl |= PCIM_SRIOV_ARI_EN; 479 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2); 480 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) & 481 PCIM_SRIOV_ARI_EN) == 0) { 482 device_printf(lowest, "failed to enable ARI\n"); 483 return (ENXIO); 484 } 485 *ari_enabled = true; 486 return (0); 487 } 488 489 static int 490 pci_iov_config_page_size(struct pci_devinfo *dinfo) 491 { 492 uint32_t page_cap, page_size; 493 494 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4); 495 496 /* 497 * If the system page size is less than the smallest SR-IOV page size 498 * then round up to the smallest SR-IOV page size. 499 */ 500 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT) 501 page_size = (1 << 0); 502 else 503 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT)); 504 505 /* Check that the device supports the system page size. */ 506 if (!(page_size & page_cap)) 507 return (ENXIO); 508 509 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4); 510 return (0); 511 } 512 513 static int 514 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config) 515 { 516 const nvlist_t *device, *driver_config; 517 518 device = nvlist_get_nvlist(config, PF_CONFIG_NAME); 519 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 520 return (PCI_IOV_INIT(dev, num_vfs, driver_config)); 521 } 522 523 static int 524 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov) 525 { 526 int error; 527 528 iov->rman.rm_start = 0; 529 iov->rman.rm_end = ~0; 530 iov->rman.rm_type = RMAN_ARRAY; 531 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory", 532 device_get_nameunit(pf)); 533 iov->rman.rm_descr = iov->rman_name; 534 535 error = rman_init(&iov->rman); 536 if (error != 0) 537 return (error); 538 539 iov->iov_flags |= IOV_RMAN_INITED; 540 return (0); 541 } 542 543 static int 544 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar) 545 { 546 struct pcicfg_iov *iov; 547 rman_res_t start, end; 548 struct resource *res; 549 struct resource_list *rl; 550 struct resource_list_entry *rle; 551 552 rl = &dinfo->resources; 553 iov = dinfo->cfg.iov; 554 555 rle = resource_list_find(rl, SYS_RES_MEMORY, 556 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 557 if (rle == NULL) 558 rle = resource_list_find(rl, SYS_RES_IOPORT, 559 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 560 if (rle == NULL) 561 return (ENXIO); 562 res = rle->res; 563 564 iov->iov_bar[bar].res = res; 565 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs; 566 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size); 567 568 start = rman_get_start(res); 569 end = rman_get_end(res); 570 571 return (rman_manage_region(&iov->rman, start, end)); 572 } 573 574 static int 575 pci_iov_setup_bars(struct pci_devinfo *dinfo) 576 { 577 device_t dev; 578 struct pcicfg_iov *iov; 579 pci_addr_t bar_value, testval; 580 int i, last_64, error; 581 582 iov = dinfo->cfg.iov; 583 dev = dinfo->cfg.dev; 584 last_64 = 0; 585 586 pci_add_resources_ea(device_get_parent(dev), dev, 1); 587 588 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 589 /* First, try to use BARs allocated with EA */ 590 error = pci_iov_alloc_bar_ea(dinfo, i); 591 if (error == 0) 592 continue; 593 594 /* Allocate legacy-BAR only if EA is not enabled */ 595 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i))) 596 continue; 597 598 /* 599 * If a PCI BAR is a 64-bit wide BAR, then it spans two 600 * consecutive registers. Therefore if the last BAR that 601 * we looked at was a 64-bit BAR, we need to skip this 602 * register as it's the second half of the last BAR. 603 */ 604 if (!last_64) { 605 pci_read_bar(dev, 606 iov->iov_pos + PCIR_SRIOV_BAR(i), 607 &bar_value, &testval, &last_64); 608 609 if (testval != 0) { 610 error = pci_iov_alloc_bar(dinfo, i, 611 pci_mapsize(testval)); 612 if (error != 0) 613 return (error); 614 } 615 } else 616 last_64 = 0; 617 } 618 619 return (0); 620 } 621 622 static void 623 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config, 624 uint16_t first_rid, uint16_t rid_stride) 625 { 626 char device_name[VF_MAX_NAME]; 627 const nvlist_t *device, *driver_config, *iov_config; 628 device_t bus, dev, vf; 629 struct pcicfg_iov *iov; 630 struct pci_devinfo *vfinfo; 631 int i, error; 632 uint16_t vid, did, next_rid; 633 634 iov = dinfo->cfg.iov; 635 dev = dinfo->cfg.dev; 636 bus = device_get_parent(dev); 637 next_rid = first_rid; 638 vid = pci_get_vendor(dev); 639 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2); 640 641 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) { 642 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i); 643 device = nvlist_get_nvlist(config, device_name); 644 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME); 645 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 646 647 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did); 648 if (vf == NULL) 649 break; 650 651 /* 652 * If we are creating passthrough devices then force the ppt 653 * driver to attach to prevent a VF driver from claiming the 654 * VFs. 655 */ 656 if (nvlist_get_bool(iov_config, "passthrough")) 657 device_set_devclass_fixed(vf, "ppt"); 658 659 vfinfo = device_get_ivars(vf); 660 661 vfinfo->cfg.iov = iov; 662 vfinfo->cfg.vf.index = i; 663 664 pci_iov_add_bars(iov, vfinfo); 665 666 error = PCI_IOV_ADD_VF(dev, i, driver_config); 667 if (error != 0) { 668 device_printf(dev, "Failed to add VF %d\n", i); 669 device_delete_child(bus, vf); 670 } 671 } 672 673 bus_generic_attach(bus); 674 } 675 676 static int 677 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg) 678 { 679 device_t bus, dev; 680 struct pci_devinfo *dinfo; 681 struct pcicfg_iov *iov; 682 nvlist_t *config; 683 int i, error; 684 uint16_t rid_off, rid_stride; 685 uint16_t first_rid, last_rid; 686 uint16_t iov_ctl; 687 uint16_t num_vfs, total_vfs; 688 int iov_inited; 689 bool ari_enabled; 690 691 mtx_lock(&Giant); 692 dinfo = cdev->si_drv1; 693 iov = dinfo->cfg.iov; 694 dev = dinfo->cfg.dev; 695 bus = device_get_parent(dev); 696 iov_inited = 0; 697 config = NULL; 698 699 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) { 700 mtx_unlock(&Giant); 701 return (EBUSY); 702 } 703 iov->iov_flags |= IOV_BUSY; 704 705 error = pci_iov_parse_config(iov, arg, &config); 706 if (error != 0) 707 goto out; 708 709 num_vfs = pci_iov_config_get_num_vfs(config); 710 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2); 711 if (num_vfs > total_vfs) { 712 error = EINVAL; 713 goto out; 714 } 715 716 error = pci_iov_config_page_size(dinfo); 717 if (error != 0) 718 goto out; 719 720 error = pci_iov_set_ari(bus, &ari_enabled); 721 if (error != 0) 722 goto out; 723 724 error = pci_iov_init(dev, num_vfs, config); 725 if (error != 0) 726 goto out; 727 iov_inited = 1; 728 729 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2); 730 731 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2); 732 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2); 733 734 first_rid = pci_get_rid(dev) + rid_off; 735 last_rid = first_rid + (num_vfs - 1) * rid_stride; 736 737 /* We don't yet support allocating extra bus numbers for VFs. */ 738 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) { 739 error = ENOSPC; 740 goto out; 741 } 742 743 if (!ari_enabled && PCI_RID2SLOT(last_rid) != 0) { 744 error = ENOSPC; 745 goto out; 746 } 747 748 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 749 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 750 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 751 752 error = pci_iov_init_rman(dev, iov); 753 if (error != 0) 754 goto out; 755 756 iov->iov_num_vfs = num_vfs; 757 758 error = pci_iov_setup_bars(dinfo); 759 if (error != 0) 760 goto out; 761 762 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 763 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE; 764 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 765 766 /* Per specification, we must wait 100ms before accessing VFs. */ 767 pause("iov", roundup(hz, 10)); 768 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride); 769 770 nvlist_destroy(config); 771 iov->iov_flags &= ~IOV_BUSY; 772 mtx_unlock(&Giant); 773 774 return (0); 775 out: 776 if (iov_inited) 777 PCI_IOV_UNINIT(dev); 778 779 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 780 if (iov->iov_bar[i].res != NULL) { 781 pci_release_resource(bus, dev, SYS_RES_MEMORY, 782 iov->iov_pos + PCIR_SRIOV_BAR(i), 783 iov->iov_bar[i].res); 784 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 785 iov->iov_pos + PCIR_SRIOV_BAR(i)); 786 iov->iov_bar[i].res = NULL; 787 } 788 } 789 790 if (iov->iov_flags & IOV_RMAN_INITED) { 791 rman_fini(&iov->rman); 792 iov->iov_flags &= ~IOV_RMAN_INITED; 793 } 794 795 nvlist_destroy(config); 796 iov->iov_num_vfs = 0; 797 iov->iov_flags &= ~IOV_BUSY; 798 mtx_unlock(&Giant); 799 return (error); 800 } 801 802 void 803 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 804 { 805 struct pcicfg_iov *iov; 806 807 iov = dinfo->cfg.iov; 808 809 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4); 810 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2); 811 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2); 812 } 813 814 void 815 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo) 816 { 817 struct pcicfg_iov *iov; 818 819 iov = dinfo->cfg.iov; 820 821 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4); 822 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 823 } 824 825 /* Return true if child is a VF of the given PF. */ 826 static int 827 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child) 828 { 829 struct pci_devinfo *vfinfo; 830 831 vfinfo = device_get_ivars(child); 832 833 if (!(vfinfo->cfg.flags & PCICFG_VF)) 834 return (0); 835 836 return (pf == vfinfo->cfg.iov); 837 } 838 839 static int 840 pci_iov_delete_iov_children(struct pci_devinfo *dinfo) 841 { 842 device_t bus, dev, vf, *devlist; 843 struct pcicfg_iov *iov; 844 int i, error, devcount; 845 uint32_t iov_ctl; 846 847 mtx_assert(&Giant, MA_OWNED); 848 849 iov = dinfo->cfg.iov; 850 dev = dinfo->cfg.dev; 851 bus = device_get_parent(dev); 852 devlist = NULL; 853 854 iov->iov_flags |= IOV_BUSY; 855 856 error = device_get_children(bus, &devlist, &devcount); 857 858 if (error != 0) 859 goto out; 860 861 for (i = 0; i < devcount; i++) { 862 vf = devlist[i]; 863 864 if (!pci_iov_is_child_vf(iov, vf)) 865 continue; 866 867 error = device_detach(vf); 868 if (error != 0) { 869 device_printf(dev, 870 "Could not disable SR-IOV: failed to detach VF %s\n", 871 device_get_nameunit(vf)); 872 goto out; 873 } 874 } 875 876 for (i = 0; i < devcount; i++) { 877 vf = devlist[i]; 878 879 if (pci_iov_is_child_vf(iov, vf)) 880 device_delete_child(bus, vf); 881 } 882 PCI_IOV_UNINIT(dev); 883 884 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 885 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 886 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 887 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2); 888 889 iov->iov_num_vfs = 0; 890 891 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 892 if (iov->iov_bar[i].res != NULL) { 893 pci_release_resource(bus, dev, SYS_RES_MEMORY, 894 iov->iov_pos + PCIR_SRIOV_BAR(i), 895 iov->iov_bar[i].res); 896 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 897 iov->iov_pos + PCIR_SRIOV_BAR(i)); 898 iov->iov_bar[i].res = NULL; 899 } 900 } 901 902 if (iov->iov_flags & IOV_RMAN_INITED) { 903 rman_fini(&iov->rman); 904 iov->iov_flags &= ~IOV_RMAN_INITED; 905 } 906 907 error = 0; 908 out: 909 free(devlist, M_TEMP); 910 iov->iov_flags &= ~IOV_BUSY; 911 return (error); 912 } 913 914 static int 915 pci_iov_delete(struct cdev *cdev) 916 { 917 struct pci_devinfo *dinfo; 918 struct pcicfg_iov *iov; 919 int error; 920 921 mtx_lock(&Giant); 922 dinfo = cdev->si_drv1; 923 iov = dinfo->cfg.iov; 924 925 if ((iov->iov_flags & IOV_BUSY) != 0) { 926 error = EBUSY; 927 goto out; 928 } 929 if (iov->iov_num_vfs == 0) { 930 error = ECHILD; 931 goto out; 932 } 933 934 error = pci_iov_delete_iov_children(dinfo); 935 936 out: 937 mtx_unlock(&Giant); 938 return (error); 939 } 940 941 static int 942 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output) 943 { 944 struct pci_devinfo *dinfo; 945 void *packed; 946 size_t output_len, size; 947 int error; 948 949 packed = NULL; 950 951 mtx_lock(&Giant); 952 dinfo = cdev->si_drv1; 953 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size); 954 mtx_unlock(&Giant); 955 956 if (packed == NULL) { 957 error = ENOMEM; 958 goto fail; 959 } 960 961 output_len = output->len; 962 output->len = size; 963 if (size <= output_len) { 964 error = copyout(packed, output->schema, size); 965 966 if (error != 0) 967 goto fail; 968 969 output->error = 0; 970 } else 971 /* 972 * If we return an error then the ioctl code won't copyout 973 * output back to userland, so we flag the error in the struct 974 * instead. 975 */ 976 output->error = EMSGSIZE; 977 978 error = 0; 979 980 fail: 981 free(packed, M_NVLIST); 982 983 return (error); 984 } 985 986 static int 987 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 988 struct thread *td) 989 { 990 991 switch (cmd) { 992 case IOV_CONFIG: 993 return (pci_iov_config(dev, (struct pci_iov_arg *)data)); 994 case IOV_DELETE: 995 return (pci_iov_delete(dev)); 996 case IOV_GET_SCHEMA: 997 return (pci_iov_get_schema_ioctl(dev, 998 (struct pci_iov_schema *)data)); 999 default: 1000 return (EINVAL); 1001 } 1002 } 1003 1004 struct resource * 1005 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, 1006 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1007 { 1008 struct pci_devinfo *dinfo; 1009 struct pcicfg_iov *iov; 1010 struct pci_map *map; 1011 struct resource *res; 1012 struct resource_list_entry *rle; 1013 rman_res_t bar_start, bar_end; 1014 pci_addr_t bar_length; 1015 int error; 1016 1017 dinfo = device_get_ivars(child); 1018 iov = dinfo->cfg.iov; 1019 1020 map = pci_find_bar(child, *rid); 1021 if (map == NULL) 1022 return (NULL); 1023 1024 bar_length = 1 << map->pm_size; 1025 bar_start = map->pm_value; 1026 bar_end = bar_start + bar_length - 1; 1027 1028 /* Make sure that the resource fits the constraints. */ 1029 if (bar_start >= end || bar_end <= bar_start || count != 1) 1030 return (NULL); 1031 1032 /* Clamp the resource to the constraints if necessary. */ 1033 if (bar_start < start) 1034 bar_start = start; 1035 if (bar_end > end) 1036 bar_end = end; 1037 bar_length = bar_end - bar_start + 1; 1038 1039 res = rman_reserve_resource(&iov->rman, bar_start, bar_end, 1040 bar_length, flags, child); 1041 if (res == NULL) 1042 return (NULL); 1043 1044 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid, 1045 bar_start, bar_end, 1); 1046 if (rle == NULL) { 1047 rman_release_resource(res); 1048 return (NULL); 1049 } 1050 1051 rman_set_rid(res, *rid); 1052 1053 if (flags & RF_ACTIVE) { 1054 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res); 1055 if (error != 0) { 1056 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1057 *rid); 1058 rman_release_resource(res); 1059 return (NULL); 1060 } 1061 } 1062 rle->res = res; 1063 1064 return (res); 1065 } 1066 1067 int 1068 pci_vf_release_mem_resource(device_t dev, device_t child, int rid, 1069 struct resource *r) 1070 { 1071 struct pci_devinfo *dinfo; 1072 struct resource_list_entry *rle; 1073 int error; 1074 1075 dinfo = device_get_ivars(child); 1076 1077 if (rman_get_flags(r) & RF_ACTIVE) { 1078 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r); 1079 if (error != 0) 1080 return (error); 1081 } 1082 1083 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid); 1084 if (rle != NULL) { 1085 rle->res = NULL; 1086 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1087 rid); 1088 } 1089 1090 return (rman_release_resource(r)); 1091 } 1092