1 /*- 2 * Copyright (c) 2013-2015 Sandvine Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/fcntl.h> 38 #include <sys/ioccom.h> 39 #include <sys/iov.h> 40 #include <sys/linker.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/pciio.h> 46 #include <sys/queue.h> 47 #include <sys/rman.h> 48 #include <sys/sysctl.h> 49 50 #include <machine/bus.h> 51 #include <machine/stdarg.h> 52 53 #include <sys/nv.h> 54 #include <sys/iov_schema.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_iov.h> 59 #include <dev/pci/pci_private.h> 60 #include <dev/pci/pci_iov_private.h> 61 #include <dev/pci/schema_private.h> 62 63 #include "pcib_if.h" 64 65 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations"); 66 67 static d_ioctl_t pci_iov_ioctl; 68 69 static struct cdevsw iov_cdevsw = { 70 .d_version = D_VERSION, 71 .d_name = "iov", 72 .d_ioctl = pci_iov_ioctl 73 }; 74 75 SYSCTL_DECL(_hw_pci); 76 77 /* 78 * The maximum amount of memory we will allocate for user configuration of an 79 * SR-IOV device. 1MB ought to be enough for anyone, but leave this 80 * configurable just in case. 81 */ 82 static u_long pci_iov_max_config = 1024 * 1024; 83 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN, 84 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration."); 85 86 #define IOV_READ(d, r, w) \ 87 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w) 88 89 #define IOV_WRITE(d, r, v, w) \ 90 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w) 91 92 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema, 93 nvlist_t **vf_schema); 94 static void pci_iov_build_pf_schema(nvlist_t *schema, 95 nvlist_t **driver_schema); 96 static void pci_iov_build_vf_schema(nvlist_t *schema, 97 nvlist_t **driver_schema); 98 static int pci_iov_delete_iov_children(struct pci_devinfo *dinfo); 99 static nvlist_t *pci_iov_get_pf_subsystem_schema(void); 100 static nvlist_t *pci_iov_get_vf_subsystem_schema(void); 101 102 int 103 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema, 104 struct nvlist *vf_schema, const char *fmt, ...) 105 { 106 char buf[NAME_MAX + 1]; 107 va_list ap; 108 109 va_start(ap, fmt); 110 vsnprintf(buf, sizeof(buf), fmt, ap); 111 va_end(ap); 112 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema, 113 vf_schema, buf)); 114 } 115 116 int 117 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema, 118 nvlist_t *vf_schema, const char *name) 119 { 120 device_t pcib; 121 struct pci_devinfo *dinfo; 122 struct pcicfg_iov *iov; 123 nvlist_t *schema; 124 uint32_t version; 125 int error; 126 int iov_pos; 127 128 dinfo = device_get_ivars(dev); 129 pcib = device_get_parent(bus); 130 schema = NULL; 131 132 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 133 134 if (error != 0) 135 return (error); 136 137 version = pci_read_config(dev, iov_pos, 4); 138 if (PCI_EXTCAP_VER(version) != 1) { 139 if (bootverbose) 140 device_printf(dev, 141 "Unsupported version of SR-IOV (%d) detected\n", 142 PCI_EXTCAP_VER(version)); 143 144 return (ENXIO); 145 } 146 147 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO); 148 149 mtx_lock(&Giant); 150 if (dinfo->cfg.iov != NULL) { 151 error = EBUSY; 152 goto cleanup; 153 } 154 iov->iov_pf = dev; 155 iov->iov_pos = iov_pos; 156 157 schema = pci_iov_build_schema(&pf_schema, &vf_schema); 158 if (schema == NULL) { 159 error = ENOMEM; 160 goto cleanup; 161 } 162 163 error = pci_iov_validate_schema(schema); 164 if (error != 0) 165 goto cleanup; 166 iov->iov_schema = schema; 167 168 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev), 169 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name); 170 171 if (iov->iov_cdev == NULL) { 172 error = ENOMEM; 173 goto cleanup; 174 } 175 176 dinfo->cfg.iov = iov; 177 iov->iov_cdev->si_drv1 = dinfo; 178 mtx_unlock(&Giant); 179 180 return (0); 181 182 cleanup: 183 nvlist_destroy(schema); 184 nvlist_destroy(pf_schema); 185 nvlist_destroy(vf_schema); 186 free(iov, M_SRIOV); 187 mtx_unlock(&Giant); 188 return (error); 189 } 190 191 int 192 pci_iov_detach_method(device_t bus, device_t dev) 193 { 194 struct pci_devinfo *dinfo; 195 struct pcicfg_iov *iov; 196 int error; 197 198 mtx_lock(&Giant); 199 dinfo = device_get_ivars(dev); 200 iov = dinfo->cfg.iov; 201 202 if (iov == NULL) { 203 mtx_unlock(&Giant); 204 return (0); 205 } 206 207 if ((iov->iov_flags & IOV_BUSY) != 0) { 208 mtx_unlock(&Giant); 209 return (EBUSY); 210 } 211 212 error = pci_iov_delete_iov_children(dinfo); 213 if (error != 0) { 214 mtx_unlock(&Giant); 215 return (error); 216 } 217 218 dinfo->cfg.iov = NULL; 219 220 if (iov->iov_cdev) { 221 destroy_dev(iov->iov_cdev); 222 iov->iov_cdev = NULL; 223 } 224 nvlist_destroy(iov->iov_schema); 225 226 free(iov, M_SRIOV); 227 mtx_unlock(&Giant); 228 229 return (0); 230 } 231 232 static nvlist_t * 233 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf) 234 { 235 nvlist_t *schema, *pf_driver, *vf_driver; 236 237 /* We always take ownership of the schemas. */ 238 pf_driver = *pf; 239 *pf = NULL; 240 vf_driver = *vf; 241 *vf = NULL; 242 243 schema = pci_iov_schema_alloc_node(); 244 if (schema == NULL) 245 goto cleanup; 246 247 pci_iov_build_pf_schema(schema, &pf_driver); 248 pci_iov_build_vf_schema(schema, &vf_driver); 249 250 if (nvlist_error(schema) != 0) 251 goto cleanup; 252 253 return (schema); 254 255 cleanup: 256 nvlist_destroy(schema); 257 nvlist_destroy(pf_driver); 258 nvlist_destroy(vf_driver); 259 return (NULL); 260 } 261 262 static void 263 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema) 264 { 265 nvlist_t *pf_schema, *iov_schema; 266 267 pf_schema = pci_iov_schema_alloc_node(); 268 if (pf_schema == NULL) { 269 nvlist_set_error(schema, ENOMEM); 270 return; 271 } 272 273 iov_schema = pci_iov_get_pf_subsystem_schema(); 274 275 /* 276 * Note that if either *driver_schema or iov_schema is NULL, then 277 * nvlist_move_nvlist will put the schema in the error state and 278 * SR-IOV will fail to initialize later, so we don't have to explicitly 279 * handle that case. 280 */ 281 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema); 282 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema); 283 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema); 284 *driver_schema = NULL; 285 } 286 287 static void 288 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema) 289 { 290 nvlist_t *vf_schema, *iov_schema; 291 292 vf_schema = pci_iov_schema_alloc_node(); 293 if (vf_schema == NULL) { 294 nvlist_set_error(schema, ENOMEM); 295 return; 296 } 297 298 iov_schema = pci_iov_get_vf_subsystem_schema(); 299 300 /* 301 * Note that if either *driver_schema or iov_schema is NULL, then 302 * nvlist_move_nvlist will put the schema in the error state and 303 * SR-IOV will fail to initialize later, so we don't have to explicitly 304 * handle that case. 305 */ 306 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema); 307 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema); 308 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema); 309 *driver_schema = NULL; 310 } 311 312 static nvlist_t * 313 pci_iov_get_pf_subsystem_schema(void) 314 { 315 nvlist_t *pf; 316 317 pf = pci_iov_schema_alloc_node(); 318 if (pf == NULL) 319 return (NULL); 320 321 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1); 322 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL); 323 324 return (pf); 325 } 326 327 static nvlist_t * 328 pci_iov_get_vf_subsystem_schema(void) 329 { 330 nvlist_t *vf; 331 332 vf = pci_iov_schema_alloc_node(); 333 if (vf == NULL) 334 return (NULL); 335 336 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0); 337 338 return (vf); 339 } 340 341 static int 342 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift) 343 { 344 struct resource *res; 345 struct pcicfg_iov *iov; 346 device_t dev, bus; 347 rman_res_t start, end; 348 pci_addr_t bar_size; 349 int rid; 350 351 iov = dinfo->cfg.iov; 352 dev = dinfo->cfg.dev; 353 bus = device_get_parent(dev); 354 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar); 355 bar_size = 1 << bar_shift; 356 357 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0, 358 ~0, 1, iov->iov_num_vfs, RF_ACTIVE); 359 360 if (res == NULL) 361 return (ENXIO); 362 363 iov->iov_bar[bar].res = res; 364 iov->iov_bar[bar].bar_size = bar_size; 365 iov->iov_bar[bar].bar_shift = bar_shift; 366 367 start = rman_get_start(res); 368 end = rman_get_end(res); 369 return (rman_manage_region(&iov->rman, start, end)); 370 } 371 372 static void 373 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo) 374 { 375 struct pci_iov_bar *bar; 376 uint64_t bar_start; 377 int i; 378 379 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 380 bar = &iov->iov_bar[i]; 381 if (bar->res != NULL) { 382 bar_start = rman_get_start(bar->res) + 383 dinfo->cfg.vf.index * bar->bar_size; 384 385 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start, 386 bar->bar_shift); 387 } 388 } 389 } 390 391 static int 392 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg, 393 nvlist_t **ret) 394 { 395 void *packed_config; 396 nvlist_t *config; 397 int error; 398 399 config = NULL; 400 packed_config = NULL; 401 402 if (arg->len > pci_iov_max_config) { 403 error = EMSGSIZE; 404 goto out; 405 } 406 407 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK); 408 409 error = copyin(arg->config, packed_config, arg->len); 410 if (error != 0) 411 goto out; 412 413 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE); 414 if (config == NULL) { 415 error = EINVAL; 416 goto out; 417 } 418 419 error = pci_iov_schema_validate_config(iov->iov_schema, config); 420 if (error != 0) 421 goto out; 422 423 error = nvlist_error(config); 424 if (error != 0) 425 goto out; 426 427 *ret = config; 428 config = NULL; 429 430 out: 431 nvlist_destroy(config); 432 free(packed_config, M_SRIOV); 433 return (error); 434 } 435 436 /* 437 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV 438 * capability. This bit is only writeable on the lowest-numbered PF but 439 * affects all PFs on the device. 440 */ 441 static int 442 pci_iov_set_ari(device_t bus) 443 { 444 device_t lowest; 445 device_t *devlist; 446 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func; 447 uint16_t iov_ctl; 448 449 /* If ARI is disabled on the downstream port there is nothing to do. */ 450 if (!PCIB_ARI_ENABLED(device_get_parent(bus))) 451 return (0); 452 453 error = device_get_children(bus, &devlist, &devcount); 454 455 if (error != 0) 456 return (error); 457 458 lowest = NULL; 459 for (i = 0; i < devcount; i++) { 460 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) { 461 dev_func = pci_get_function(devlist[i]); 462 if (lowest == NULL || dev_func < lowest_func) { 463 lowest = devlist[i]; 464 lowest_func = dev_func; 465 lowest_pos = iov_pos; 466 } 467 } 468 } 469 free(devlist, M_TEMP); 470 471 /* 472 * If we called this function some device must have the SR-IOV 473 * capability. 474 */ 475 KASSERT(lowest != NULL, 476 ("Could not find child of %s with SR-IOV capability", 477 device_get_nameunit(bus))); 478 479 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2); 480 iov_ctl |= PCIM_SRIOV_ARI_EN; 481 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2); 482 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) & 483 PCIM_SRIOV_ARI_EN) == 0) { 484 device_printf(lowest, "failed to enable ARI\n"); 485 return (ENXIO); 486 } 487 return (0); 488 } 489 490 static int 491 pci_iov_config_page_size(struct pci_devinfo *dinfo) 492 { 493 uint32_t page_cap, page_size; 494 495 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4); 496 497 /* 498 * If the system page size is less than the smallest SR-IOV page size 499 * then round up to the smallest SR-IOV page size. 500 */ 501 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT) 502 page_size = (1 << 0); 503 else 504 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT)); 505 506 /* Check that the device supports the system page size. */ 507 if (!(page_size & page_cap)) 508 return (ENXIO); 509 510 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4); 511 return (0); 512 } 513 514 static int 515 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config) 516 { 517 const nvlist_t *device, *driver_config; 518 519 device = nvlist_get_nvlist(config, PF_CONFIG_NAME); 520 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 521 return (PCI_IOV_INIT(dev, num_vfs, driver_config)); 522 } 523 524 static int 525 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov) 526 { 527 int error; 528 529 iov->rman.rm_start = 0; 530 iov->rman.rm_end = ~0; 531 iov->rman.rm_type = RMAN_ARRAY; 532 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory", 533 device_get_nameunit(pf)); 534 iov->rman.rm_descr = iov->rman_name; 535 536 error = rman_init(&iov->rman); 537 if (error != 0) 538 return (error); 539 540 iov->iov_flags |= IOV_RMAN_INITED; 541 return (0); 542 } 543 544 static int 545 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar) 546 { 547 struct pcicfg_iov *iov; 548 rman_res_t start, end; 549 struct resource *res; 550 struct resource_list *rl; 551 struct resource_list_entry *rle; 552 553 rl = &dinfo->resources; 554 iov = dinfo->cfg.iov; 555 556 rle = resource_list_find(rl, SYS_RES_MEMORY, 557 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 558 if (rle == NULL) 559 rle = resource_list_find(rl, SYS_RES_IOPORT, 560 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 561 if (rle == NULL) 562 return (ENXIO); 563 res = rle->res; 564 565 iov->iov_bar[bar].res = res; 566 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs; 567 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size); 568 569 start = rman_get_start(res); 570 end = rman_get_end(res); 571 572 return (rman_manage_region(&iov->rman, start, end)); 573 } 574 575 static int 576 pci_iov_setup_bars(struct pci_devinfo *dinfo) 577 { 578 device_t dev; 579 struct pcicfg_iov *iov; 580 pci_addr_t bar_value, testval; 581 int i, last_64, error; 582 583 iov = dinfo->cfg.iov; 584 dev = dinfo->cfg.dev; 585 last_64 = 0; 586 587 pci_add_resources_ea(device_get_parent(dev), dev, 1); 588 589 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 590 /* First, try to use BARs allocated with EA */ 591 error = pci_iov_alloc_bar_ea(dinfo, i); 592 if (error == 0) 593 continue; 594 595 /* Allocate legacy-BAR only if EA is not enabled */ 596 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i))) 597 continue; 598 599 /* 600 * If a PCI BAR is a 64-bit wide BAR, then it spans two 601 * consecutive registers. Therefore if the last BAR that 602 * we looked at was a 64-bit BAR, we need to skip this 603 * register as it's the second half of the last BAR. 604 */ 605 if (!last_64) { 606 pci_read_bar(dev, 607 iov->iov_pos + PCIR_SRIOV_BAR(i), 608 &bar_value, &testval, &last_64); 609 610 if (testval != 0) { 611 error = pci_iov_alloc_bar(dinfo, i, 612 pci_mapsize(testval)); 613 if (error != 0) 614 return (error); 615 } 616 } else 617 last_64 = 0; 618 } 619 620 return (0); 621 } 622 623 static void 624 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config, 625 uint16_t first_rid, uint16_t rid_stride) 626 { 627 char device_name[VF_MAX_NAME]; 628 const nvlist_t *device, *driver_config, *iov_config; 629 device_t bus, dev, vf; 630 struct pcicfg_iov *iov; 631 struct pci_devinfo *vfinfo; 632 int i, error; 633 uint16_t vid, did, next_rid; 634 635 iov = dinfo->cfg.iov; 636 dev = dinfo->cfg.dev; 637 bus = device_get_parent(dev); 638 next_rid = first_rid; 639 vid = pci_get_vendor(dev); 640 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2); 641 642 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) { 643 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i); 644 device = nvlist_get_nvlist(config, device_name); 645 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME); 646 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 647 648 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did); 649 if (vf == NULL) 650 break; 651 652 /* 653 * If we are creating passthrough devices then force the ppt 654 * driver to attach to prevent a VF driver from claiming the 655 * VFs. 656 */ 657 if (nvlist_get_bool(iov_config, "passthrough")) 658 device_set_devclass_fixed(vf, "ppt"); 659 660 vfinfo = device_get_ivars(vf); 661 662 vfinfo->cfg.iov = iov; 663 vfinfo->cfg.vf.index = i; 664 665 pci_iov_add_bars(iov, vfinfo); 666 667 error = PCI_IOV_ADD_VF(dev, i, driver_config); 668 if (error != 0) { 669 device_printf(dev, "Failed to add VF %d\n", i); 670 device_delete_child(bus, vf); 671 } 672 } 673 674 bus_generic_attach(bus); 675 } 676 677 static int 678 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg) 679 { 680 device_t bus, dev; 681 struct pci_devinfo *dinfo; 682 struct pcicfg_iov *iov; 683 nvlist_t *config; 684 int i, error; 685 uint16_t rid_off, rid_stride; 686 uint16_t first_rid, last_rid; 687 uint16_t iov_ctl; 688 uint16_t num_vfs, total_vfs; 689 int iov_inited; 690 691 mtx_lock(&Giant); 692 dinfo = cdev->si_drv1; 693 iov = dinfo->cfg.iov; 694 dev = dinfo->cfg.dev; 695 bus = device_get_parent(dev); 696 iov_inited = 0; 697 config = NULL; 698 699 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) { 700 mtx_unlock(&Giant); 701 return (EBUSY); 702 } 703 iov->iov_flags |= IOV_BUSY; 704 705 error = pci_iov_parse_config(iov, arg, &config); 706 if (error != 0) 707 goto out; 708 709 num_vfs = pci_iov_config_get_num_vfs(config); 710 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2); 711 if (num_vfs > total_vfs) { 712 error = EINVAL; 713 goto out; 714 } 715 716 error = pci_iov_config_page_size(dinfo); 717 if (error != 0) 718 goto out; 719 720 error = pci_iov_set_ari(bus); 721 if (error != 0) 722 goto out; 723 724 error = pci_iov_init(dev, num_vfs, config); 725 if (error != 0) 726 goto out; 727 iov_inited = 1; 728 729 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2); 730 731 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2); 732 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2); 733 734 first_rid = pci_get_rid(dev) + rid_off; 735 last_rid = first_rid + (num_vfs - 1) * rid_stride; 736 737 /* We don't yet support allocating extra bus numbers for VFs. */ 738 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) { 739 error = ENOSPC; 740 goto out; 741 } 742 743 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 744 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 745 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 746 747 error = pci_iov_init_rman(dev, iov); 748 if (error != 0) 749 goto out; 750 751 iov->iov_num_vfs = num_vfs; 752 753 error = pci_iov_setup_bars(dinfo); 754 if (error != 0) 755 goto out; 756 757 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 758 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE; 759 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 760 761 /* Per specification, we must wait 100ms before accessing VFs. */ 762 pause("iov", roundup(hz, 10)); 763 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride); 764 765 nvlist_destroy(config); 766 iov->iov_flags &= ~IOV_BUSY; 767 mtx_unlock(&Giant); 768 769 return (0); 770 out: 771 if (iov_inited) 772 PCI_IOV_UNINIT(dev); 773 774 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 775 if (iov->iov_bar[i].res != NULL) { 776 pci_release_resource(bus, dev, SYS_RES_MEMORY, 777 iov->iov_pos + PCIR_SRIOV_BAR(i), 778 iov->iov_bar[i].res); 779 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 780 iov->iov_pos + PCIR_SRIOV_BAR(i)); 781 iov->iov_bar[i].res = NULL; 782 } 783 } 784 785 if (iov->iov_flags & IOV_RMAN_INITED) { 786 rman_fini(&iov->rman); 787 iov->iov_flags &= ~IOV_RMAN_INITED; 788 } 789 790 nvlist_destroy(config); 791 iov->iov_num_vfs = 0; 792 iov->iov_flags &= ~IOV_BUSY; 793 mtx_unlock(&Giant); 794 return (error); 795 } 796 797 void 798 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 799 { 800 struct pcicfg_iov *iov; 801 802 iov = dinfo->cfg.iov; 803 804 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4); 805 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2); 806 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2); 807 } 808 809 void 810 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo) 811 { 812 struct pcicfg_iov *iov; 813 814 iov = dinfo->cfg.iov; 815 816 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4); 817 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 818 } 819 820 /* Return true if child is a VF of the given PF. */ 821 static int 822 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child) 823 { 824 struct pci_devinfo *vfinfo; 825 826 vfinfo = device_get_ivars(child); 827 828 if (!(vfinfo->cfg.flags & PCICFG_VF)) 829 return (0); 830 831 return (pf == vfinfo->cfg.iov); 832 } 833 834 static int 835 pci_iov_delete_iov_children(struct pci_devinfo *dinfo) 836 { 837 device_t bus, dev, vf, *devlist; 838 struct pcicfg_iov *iov; 839 int i, error, devcount; 840 uint32_t iov_ctl; 841 842 mtx_assert(&Giant, MA_OWNED); 843 844 iov = dinfo->cfg.iov; 845 dev = dinfo->cfg.dev; 846 bus = device_get_parent(dev); 847 devlist = NULL; 848 849 iov->iov_flags |= IOV_BUSY; 850 851 error = device_get_children(bus, &devlist, &devcount); 852 853 if (error != 0) 854 goto out; 855 856 for (i = 0; i < devcount; i++) { 857 vf = devlist[i]; 858 859 if (!pci_iov_is_child_vf(iov, vf)) 860 continue; 861 862 error = device_detach(vf); 863 if (error != 0) { 864 device_printf(dev, 865 "Could not disable SR-IOV: failed to detach VF %s\n", 866 device_get_nameunit(vf)); 867 goto out; 868 } 869 } 870 871 for (i = 0; i < devcount; i++) { 872 vf = devlist[i]; 873 874 if (pci_iov_is_child_vf(iov, vf)) 875 device_delete_child(bus, vf); 876 } 877 PCI_IOV_UNINIT(dev); 878 879 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 880 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 881 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 882 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2); 883 884 iov->iov_num_vfs = 0; 885 886 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 887 if (iov->iov_bar[i].res != NULL) { 888 pci_release_resource(bus, dev, SYS_RES_MEMORY, 889 iov->iov_pos + PCIR_SRIOV_BAR(i), 890 iov->iov_bar[i].res); 891 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 892 iov->iov_pos + PCIR_SRIOV_BAR(i)); 893 iov->iov_bar[i].res = NULL; 894 } 895 } 896 897 if (iov->iov_flags & IOV_RMAN_INITED) { 898 rman_fini(&iov->rman); 899 iov->iov_flags &= ~IOV_RMAN_INITED; 900 } 901 902 error = 0; 903 out: 904 free(devlist, M_TEMP); 905 iov->iov_flags &= ~IOV_BUSY; 906 return (error); 907 } 908 909 static int 910 pci_iov_delete(struct cdev *cdev) 911 { 912 struct pci_devinfo *dinfo; 913 struct pcicfg_iov *iov; 914 int error; 915 916 mtx_lock(&Giant); 917 dinfo = cdev->si_drv1; 918 iov = dinfo->cfg.iov; 919 920 if ((iov->iov_flags & IOV_BUSY) != 0) { 921 error = EBUSY; 922 goto out; 923 } 924 if (iov->iov_num_vfs == 0) { 925 error = ECHILD; 926 goto out; 927 } 928 929 error = pci_iov_delete_iov_children(dinfo); 930 931 out: 932 mtx_unlock(&Giant); 933 return (error); 934 } 935 936 static int 937 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output) 938 { 939 struct pci_devinfo *dinfo; 940 void *packed; 941 size_t output_len, size; 942 int error; 943 944 packed = NULL; 945 946 mtx_lock(&Giant); 947 dinfo = cdev->si_drv1; 948 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size); 949 mtx_unlock(&Giant); 950 951 if (packed == NULL) { 952 error = ENOMEM; 953 goto fail; 954 } 955 956 output_len = output->len; 957 output->len = size; 958 if (size <= output_len) { 959 error = copyout(packed, output->schema, size); 960 961 if (error != 0) 962 goto fail; 963 964 output->error = 0; 965 } else 966 /* 967 * If we return an error then the ioctl code won't copyout 968 * output back to userland, so we flag the error in the struct 969 * instead. 970 */ 971 output->error = EMSGSIZE; 972 973 error = 0; 974 975 fail: 976 free(packed, M_NVLIST); 977 978 return (error); 979 } 980 981 static int 982 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 983 struct thread *td) 984 { 985 986 switch (cmd) { 987 case IOV_CONFIG: 988 return (pci_iov_config(dev, (struct pci_iov_arg *)data)); 989 case IOV_DELETE: 990 return (pci_iov_delete(dev)); 991 case IOV_GET_SCHEMA: 992 return (pci_iov_get_schema_ioctl(dev, 993 (struct pci_iov_schema *)data)); 994 default: 995 return (EINVAL); 996 } 997 } 998 999 struct resource * 1000 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, 1001 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1002 { 1003 struct pci_devinfo *dinfo; 1004 struct pcicfg_iov *iov; 1005 struct pci_map *map; 1006 struct resource *res; 1007 struct resource_list_entry *rle; 1008 rman_res_t bar_start, bar_end; 1009 pci_addr_t bar_length; 1010 int error; 1011 1012 dinfo = device_get_ivars(child); 1013 iov = dinfo->cfg.iov; 1014 1015 map = pci_find_bar(child, *rid); 1016 if (map == NULL) 1017 return (NULL); 1018 1019 bar_length = 1 << map->pm_size; 1020 bar_start = map->pm_value; 1021 bar_end = bar_start + bar_length - 1; 1022 1023 /* Make sure that the resource fits the constraints. */ 1024 if (bar_start >= end || bar_end <= bar_start || count != 1) 1025 return (NULL); 1026 1027 /* Clamp the resource to the constraints if necessary. */ 1028 if (bar_start < start) 1029 bar_start = start; 1030 if (bar_end > end) 1031 bar_end = end; 1032 bar_length = bar_end - bar_start + 1; 1033 1034 res = rman_reserve_resource(&iov->rman, bar_start, bar_end, 1035 bar_length, flags, child); 1036 if (res == NULL) 1037 return (NULL); 1038 1039 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid, 1040 bar_start, bar_end, 1); 1041 if (rle == NULL) { 1042 rman_release_resource(res); 1043 return (NULL); 1044 } 1045 1046 rman_set_rid(res, *rid); 1047 1048 if (flags & RF_ACTIVE) { 1049 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res); 1050 if (error != 0) { 1051 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1052 *rid); 1053 rman_release_resource(res); 1054 return (NULL); 1055 } 1056 } 1057 rle->res = res; 1058 1059 return (res); 1060 } 1061 1062 int 1063 pci_vf_release_mem_resource(device_t dev, device_t child, int rid, 1064 struct resource *r) 1065 { 1066 struct pci_devinfo *dinfo; 1067 struct resource_list_entry *rle; 1068 int error; 1069 1070 dinfo = device_get_ivars(child); 1071 1072 if (rman_get_flags(r) & RF_ACTIVE) { 1073 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r); 1074 if (error != 0) 1075 return (error); 1076 } 1077 1078 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid); 1079 if (rle != NULL) { 1080 rle->res = NULL; 1081 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1082 rid); 1083 } 1084 1085 return (rman_release_resource(r)); 1086 } 1087